1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2024, IBM Corporation.. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/log.h" 11 #include "qemu/module.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "system/cpus.h" 15 #include "system/dma.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/ppc/xive.h" 18 #include "hw/ppc/xive2.h" 19 #include "hw/ppc/xive2_regs.h" 20 #include "trace.h" 21 22 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 23 uint32_t end_idx, uint32_t end_data, 24 bool redistribute); 25 26 static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring, 27 uint8_t *nvp_blk, uint32_t *nvp_idx); 28 29 uint32_t xive2_router_get_config(Xive2Router *xrtr) 30 { 31 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 32 33 return xrc->get_config(xrtr); 34 } 35 36 static int xive2_router_get_block_id(Xive2Router *xrtr) 37 { 38 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 39 40 return xrc->get_block_id(xrtr); 41 } 42 43 static uint64_t xive2_nvp_reporting_addr(Xive2Nvp *nvp) 44 { 45 uint64_t cache_addr; 46 47 cache_addr = xive_get_field32(NVP2_W6_REPORTING_LINE, nvp->w6) << 24 | 48 xive_get_field32(NVP2_W7_REPORTING_LINE, nvp->w7); 49 cache_addr <<= 8; /* aligned on a cache line pair */ 50 return cache_addr; 51 } 52 53 static uint32_t xive2_nvgc_get_backlog(Xive2Nvgc *nvgc, uint8_t priority) 54 { 55 uint32_t val = 0; 56 uint8_t *ptr, i; 57 58 if (priority > 7) { 59 return 0; 60 } 61 62 /* 63 * The per-priority backlog counters are 24-bit and the structure 64 * is stored in big endian. NVGC is 32-bytes long, so 24-bytes from 65 * w2, which fits 8 priorities * 24-bits per priority. 66 */ 67 ptr = (uint8_t *)&nvgc->w2 + priority * 3; 68 for (i = 0; i < 3; i++, ptr++) { 69 val = (val << 8) + *ptr; 70 } 71 return val; 72 } 73 74 static void xive2_nvgc_set_backlog(Xive2Nvgc *nvgc, uint8_t priority, 75 uint32_t val) 76 { 77 uint8_t *ptr, i; 78 uint32_t shift; 79 80 if (priority > 7) { 81 return; 82 } 83 84 if (val > 0xFFFFFF) { 85 val = 0xFFFFFF; 86 } 87 /* 88 * The per-priority backlog counters are 24-bit and the structure 89 * is stored in big endian 90 */ 91 ptr = (uint8_t *)&nvgc->w2 + priority * 3; 92 for (i = 0; i < 3; i++, ptr++) { 93 shift = 8 * (2 - i); 94 *ptr = (val >> shift) & 0xFF; 95 } 96 } 97 98 uint64_t xive2_presenter_nvgc_backlog_op(XivePresenter *xptr, 99 bool crowd, 100 uint8_t blk, uint32_t idx, 101 uint16_t offset, uint16_t val) 102 { 103 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 104 uint8_t priority = GETFIELD(NVx_BACKLOG_PRIO, offset); 105 uint8_t op = GETFIELD(NVx_BACKLOG_OP, offset); 106 Xive2Nvgc nvgc; 107 uint32_t count, old_count; 108 109 if (xive2_router_get_nvgc(xrtr, crowd, blk, idx, &nvgc)) { 110 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No %s %x/%x\n", 111 crowd ? "NVC" : "NVG", blk, idx); 112 return -1; 113 } 114 if (!xive2_nvgc_is_valid(&nvgc)) { 115 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n", blk, idx); 116 return -1; 117 } 118 119 old_count = xive2_nvgc_get_backlog(&nvgc, priority); 120 count = old_count; 121 /* 122 * op: 123 * 0b00 => increment 124 * 0b01 => decrement 125 * 0b1- => read 126 */ 127 if (op == 0b00 || op == 0b01) { 128 if (op == 0b00) { 129 count += val; 130 } else { 131 if (count > val) { 132 count -= val; 133 } else { 134 count = 0; 135 } 136 } 137 xive2_nvgc_set_backlog(&nvgc, priority, count); 138 xive2_router_write_nvgc(xrtr, crowd, blk, idx, &nvgc); 139 } 140 trace_xive_nvgc_backlog_op(crowd, blk, idx, op, priority, old_count); 141 return old_count; 142 } 143 144 uint64_t xive2_presenter_nvp_backlog_op(XivePresenter *xptr, 145 uint8_t blk, uint32_t idx, 146 uint16_t offset) 147 { 148 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 149 uint8_t priority = GETFIELD(NVx_BACKLOG_PRIO, offset); 150 uint8_t op = GETFIELD(NVx_BACKLOG_OP, offset); 151 Xive2Nvp nvp; 152 uint8_t ipb, old_ipb, rc; 153 154 if (xive2_router_get_nvp(xrtr, blk, idx, &nvp)) { 155 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", blk, idx); 156 return -1; 157 } 158 if (!xive2_nvp_is_valid(&nvp)) { 159 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVP %x/%x\n", blk, idx); 160 return -1; 161 } 162 163 old_ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2); 164 ipb = old_ipb; 165 /* 166 * op: 167 * 0b00 => set priority bit 168 * 0b01 => reset priority bit 169 * 0b1- => read 170 */ 171 if (op == 0b00 || op == 0b01) { 172 if (op == 0b00) { 173 ipb |= xive_priority_to_ipb(priority); 174 } else { 175 ipb &= ~xive_priority_to_ipb(priority); 176 } 177 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 178 xive2_router_write_nvp(xrtr, blk, idx, &nvp, 2); 179 } 180 rc = !!(old_ipb & xive_priority_to_ipb(priority)); 181 trace_xive_nvp_backlog_op(blk, idx, op, priority, rc); 182 return rc; 183 } 184 185 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf) 186 { 187 if (!xive2_eas_is_valid(eas)) { 188 return; 189 } 190 191 g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n", 192 lisn, xive2_eas_is_masked(eas) ? "M" : " ", 193 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 194 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 195 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 196 } 197 198 #define XIVE2_QSIZE_CHUNK_CL 128 199 #define XIVE2_QSIZE_CHUNK_4k 4096 200 /* Calculate max number of queue entries for an END */ 201 static uint32_t xive2_end_get_qentries(Xive2End *end) 202 { 203 uint32_t w3 = end->w3; 204 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, w3); 205 if (xive_get_field32(END2_W3_CL, w3)) { 206 g_assert(qsize <= 4); 207 return (XIVE2_QSIZE_CHUNK_CL << qsize) / sizeof(uint32_t); 208 } else { 209 g_assert(qsize <= 12); 210 return (XIVE2_QSIZE_CHUNK_4k << qsize) / sizeof(uint32_t); 211 } 212 } 213 214 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString *buf) 215 { 216 uint64_t qaddr_base = xive2_end_qaddr(end); 217 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 218 uint32_t qentries = xive2_end_get_qentries(end); 219 int i; 220 221 /* 222 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 223 */ 224 g_string_append_printf(buf, " [ "); 225 qindex = (qindex - (width - 1)) & (qentries - 1); 226 for (i = 0; i < width; i++) { 227 uint64_t qaddr = qaddr_base + (qindex << 2); 228 uint32_t qdata = -1; 229 230 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 231 sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 232 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 233 HWADDR_PRIx "\n", qaddr); 234 return; 235 } 236 g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "", 237 be32_to_cpu(qdata)); 238 qindex = (qindex + 1) & (qentries - 1); 239 } 240 g_string_append_printf(buf, "]"); 241 } 242 243 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf) 244 { 245 uint64_t qaddr_base = xive2_end_qaddr(end); 246 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 247 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 248 uint32_t qentries = xive2_end_get_qentries(end); 249 250 uint32_t nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); 251 uint32_t nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); 252 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7); 253 uint8_t pq; 254 255 if (!xive2_end_is_valid(end)) { 256 return; 257 } 258 259 pq = xive_get_field32(END2_W1_ESn, end->w1); 260 261 g_string_append_printf(buf, 262 " %08x %c%c %c%c%c%c%c%c%c%c%c%c%c %c%c " 263 "prio:%d nvp:%02x/%04x", 264 end_idx, 265 pq & XIVE_ESB_VAL_P ? 'P' : '-', 266 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 267 xive2_end_is_valid(end) ? 'v' : '-', 268 xive2_end_is_enqueue(end) ? 'q' : '-', 269 xive2_end_is_notify(end) ? 'n' : '-', 270 xive2_end_is_backlog(end) ? 'b' : '-', 271 xive2_end_is_precluded_escalation(end) ? 'p' : '-', 272 xive2_end_is_escalate(end) ? 'e' : '-', 273 xive2_end_is_escalate_end(end) ? 'N' : '-', 274 xive2_end_is_uncond_escalation(end) ? 'u' : '-', 275 xive2_end_is_silent_escalation(end) ? 's' : '-', 276 xive2_end_is_firmware1(end) ? 'f' : '-', 277 xive2_end_is_firmware2(end) ? 'F' : '-', 278 xive2_end_is_ignore(end) ? 'i' : '-', 279 xive2_end_is_crowd(end) ? 'c' : '-', 280 priority, nvx_blk, nvx_idx); 281 282 if (qaddr_base) { 283 g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d", 284 qaddr_base, qindex, qentries, qgen); 285 xive2_end_queue_pic_print_info(end, 6, buf); 286 } 287 g_string_append_c(buf, '\n'); 288 } 289 290 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, 291 GString *buf) 292 { 293 Xive2Eas *eas = (Xive2Eas *) &end->w4; 294 uint8_t pq; 295 296 if (!xive2_end_is_escalate(end)) { 297 return; 298 } 299 300 pq = xive_get_field32(END2_W1_ESe, end->w1); 301 302 g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 303 end_idx, 304 pq & XIVE_ESB_VAL_P ? 'P' : '-', 305 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 306 xive2_eas_is_valid(eas) ? 'v' : ' ', 307 xive2_eas_is_masked(eas) ? 'M' : ' ', 308 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 309 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 310 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 311 } 312 313 void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *buf) 314 { 315 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); 316 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); 317 uint64_t cache_line = xive2_nvp_reporting_addr(nvp); 318 319 if (!xive2_nvp_is_valid(nvp)) { 320 return; 321 } 322 323 g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x PGoFirst:%02x", 324 nvp_idx, eq_blk, eq_idx, 325 xive_get_field32(NVP2_W2_IPB, nvp->w2), 326 xive_get_field32(NVP2_W0_PGOFIRST, nvp->w0)); 327 if (cache_line) { 328 g_string_append_printf(buf, " reporting CL:%016"PRIx64, cache_line); 329 } 330 331 /* 332 * When the NVP is HW controlled, more fields are updated 333 */ 334 if (xive2_nvp_is_hw(nvp)) { 335 g_string_append_printf(buf, " CPPR:%02x", 336 xive_get_field32(NVP2_W2_CPPR, nvp->w2)); 337 if (xive2_nvp_is_co(nvp)) { 338 g_string_append_printf(buf, " CO:%04x", 339 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); 340 } 341 } 342 g_string_append_c(buf, '\n'); 343 } 344 345 void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_t nvgc_idx, GString *buf) 346 { 347 uint8_t i; 348 349 if (!xive2_nvgc_is_valid(nvgc)) { 350 return; 351 } 352 353 g_string_append_printf(buf, " %08x PGoNext:%02x bklog: ", nvgc_idx, 354 xive_get_field32(NVGC2_W0_PGONEXT, nvgc->w0)); 355 for (i = 0; i <= XIVE_PRIORITY_MAX; i++) { 356 g_string_append_printf(buf, "[%d]=0x%x ", 357 i, xive2_nvgc_get_backlog(nvgc, i)); 358 } 359 g_string_append_printf(buf, "\n"); 360 } 361 362 static void xive2_end_enqueue(Xive2End *end, uint32_t data) 363 { 364 uint64_t qaddr_base = xive2_end_qaddr(end); 365 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 366 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 367 368 uint64_t qaddr = qaddr_base + (qindex << 2); 369 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 370 uint32_t qentries = xive2_end_get_qentries(end); 371 372 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata), 373 MEMTXATTRS_UNSPECIFIED)) { 374 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 375 HWADDR_PRIx "\n", qaddr); 376 return; 377 } 378 379 qindex = (qindex + 1) & (qentries - 1); 380 if (qindex == 0) { 381 qgen ^= 1; 382 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); 383 384 /* Set gen flipped to 1, it gets reset on a cache watch operation */ 385 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, 1); 386 } 387 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); 388 } 389 390 static void xive2_pgofnext(uint8_t *nvgc_blk, uint32_t *nvgc_idx, 391 uint8_t next_level) 392 { 393 uint32_t mask, next_idx; 394 uint8_t next_blk; 395 396 /* 397 * Adjust the block and index of a VP for the next group/crowd 398 * size (PGofFirst/PGofNext field in the NVP and NVGC structures). 399 * 400 * The 6-bit group level is split into a 2-bit crowd and 4-bit 401 * group levels. Encoding is similar. However, we don't support 402 * crowd size of 8. So a crowd level of 0b11 is bumped to a crowd 403 * size of 16. 404 */ 405 next_blk = NVx_CROWD_LVL(next_level); 406 if (next_blk == 3) { 407 next_blk = 4; 408 } 409 mask = (1 << next_blk) - 1; 410 *nvgc_blk &= ~mask; 411 *nvgc_blk |= mask >> 1; 412 413 next_idx = NVx_GROUP_LVL(next_level); 414 mask = (1 << next_idx) - 1; 415 *nvgc_idx &= ~mask; 416 *nvgc_idx |= mask >> 1; 417 } 418 419 /* 420 * Scan the group chain and return the highest priority and group 421 * level of pending group interrupts. 422 */ 423 static uint8_t xive2_presenter_backlog_scan(XivePresenter *xptr, 424 uint8_t nvx_blk, uint32_t nvx_idx, 425 uint8_t first_group, 426 uint8_t *out_level) 427 { 428 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 429 uint32_t nvgc_idx; 430 uint32_t current_level, count; 431 uint8_t nvgc_blk, prio; 432 Xive2Nvgc nvgc; 433 434 for (prio = 0; prio <= XIVE_PRIORITY_MAX; prio++) { 435 current_level = first_group & 0x3F; 436 nvgc_blk = nvx_blk; 437 nvgc_idx = nvx_idx; 438 439 while (current_level) { 440 xive2_pgofnext(&nvgc_blk, &nvgc_idx, current_level); 441 442 if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(current_level), 443 nvgc_blk, nvgc_idx, &nvgc)) { 444 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n", 445 nvgc_blk, nvgc_idx); 446 return 0xFF; 447 } 448 if (!xive2_nvgc_is_valid(&nvgc)) { 449 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n", 450 nvgc_blk, nvgc_idx); 451 return 0xFF; 452 } 453 454 count = xive2_nvgc_get_backlog(&nvgc, prio); 455 if (count) { 456 *out_level = current_level; 457 return prio; 458 } 459 current_level = xive_get_field32(NVGC2_W0_PGONEXT, nvgc.w0) & 0x3F; 460 } 461 } 462 return 0xFF; 463 } 464 465 static void xive2_presenter_backlog_decr(XivePresenter *xptr, 466 uint8_t nvx_blk, uint32_t nvx_idx, 467 uint8_t group_prio, 468 uint8_t group_level) 469 { 470 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 471 uint32_t nvgc_idx, count; 472 uint8_t nvgc_blk; 473 Xive2Nvgc nvgc; 474 475 nvgc_blk = nvx_blk; 476 nvgc_idx = nvx_idx; 477 xive2_pgofnext(&nvgc_blk, &nvgc_idx, group_level); 478 479 if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(group_level), 480 nvgc_blk, nvgc_idx, &nvgc)) { 481 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n", 482 nvgc_blk, nvgc_idx); 483 return; 484 } 485 if (!xive2_nvgc_is_valid(&nvgc)) { 486 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n", 487 nvgc_blk, nvgc_idx); 488 return; 489 } 490 count = xive2_nvgc_get_backlog(&nvgc, group_prio); 491 if (!count) { 492 return; 493 } 494 xive2_nvgc_set_backlog(&nvgc, group_prio, count - 1); 495 xive2_router_write_nvgc(xrtr, NVx_CROWD_LVL(group_level), 496 nvgc_blk, nvgc_idx, &nvgc); 497 } 498 499 /* 500 * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode 501 * 502 * TIMA Gen2 VP “save & restore” (S&R) indicated by H bit next to V bit 503 * 504 * - if a context is enabled with the H bit set, the VP context 505 * information is retrieved from the NVP structure (“check out”) 506 * and stored back on a context pull (“check in”), the SW receives 507 * the same context pull information as on P9 508 * 509 * - the H bit cannot be changed while the V bit is set, i.e. a 510 * context cannot be set up in the TIMA and then be “pushed” into 511 * the NVP by changing the H bit while the context is enabled 512 */ 513 514 static void xive2_tctx_save_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 515 uint8_t ring, 516 uint8_t nvp_blk, uint32_t nvp_idx) 517 { 518 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 519 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 520 Xive2Nvp nvp; 521 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); 522 uint8_t *regs = &tctx->regs[ring]; 523 524 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 525 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 526 nvp_blk, nvp_idx); 527 return; 528 } 529 530 if (!xive2_nvp_is_valid(&nvp)) { 531 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 532 nvp_blk, nvp_idx); 533 return; 534 } 535 536 if (!xive2_nvp_is_hw(&nvp)) { 537 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 538 nvp_blk, nvp_idx); 539 return; 540 } 541 542 if (!xive2_nvp_is_co(&nvp)) { 543 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not checkout\n", 544 nvp_blk, nvp_idx); 545 return; 546 } 547 548 if (xive_get_field32(NVP2_W1_CO_THRID_VALID, nvp.w1) && 549 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) { 550 qemu_log_mask(LOG_GUEST_ERROR, 551 "XIVE: NVP %x/%x invalid checkout Thread %x\n", 552 nvp_blk, nvp_idx, pir); 553 return; 554 } 555 556 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]); 557 558 if ((nvp.w0 & NVP2_W0_P) || ring != TM_QW2_HV_POOL) { 559 /* 560 * Non-pool contexts always save CPPR (ignore p bit). XXX: Clarify 561 * whether that is the correct behaviour. 562 */ 563 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, sig_regs[TM_CPPR]); 564 } 565 if (nvp.w0 & NVP2_W0_L) { 566 /* 567 * Typically not used. If LSMFB is restored with 0, it will 568 * force a backlog rescan 569 */ 570 nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]); 571 } 572 if (nvp.w0 & NVP2_W0_G) { 573 nvp.w2 = xive_set_field32(NVP2_W2_LGS, nvp.w2, regs[TM_LGS]); 574 } 575 if (nvp.w0 & NVP2_W0_T) { 576 nvp.w2 = xive_set_field32(NVP2_W2_T, nvp.w2, regs[TM_T]); 577 } 578 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 579 580 nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0); 581 /* NVP2_W1_CO_THRID_VALID only set once */ 582 nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF); 583 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1); 584 } 585 586 static void xive2_cam_decode(uint32_t cam, uint8_t *nvp_blk, 587 uint32_t *nvp_idx, bool *valid, bool *hw) 588 { 589 *nvp_blk = xive2_nvp_blk(cam); 590 *nvp_idx = xive2_nvp_idx(cam); 591 *valid = !!(cam & TM2_W2_VALID); 592 *hw = !!(cam & TM2_W2_HW); 593 } 594 595 /* 596 * Encode the HW CAM line with 7bit or 8bit thread id. The thread id 597 * width and block id width is configurable at the IC level. 598 * 599 * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit) 600 * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit) 601 */ 602 static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 603 { 604 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 605 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 606 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 607 uint8_t blk = xive2_router_get_block_id(xrtr); 608 uint8_t tid_shift = 609 xive2_router_get_config(xrtr) & XIVE2_THREADID_8BITS ? 8 : 7; 610 uint8_t tid_mask = (1 << tid_shift) - 1; 611 612 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); 613 } 614 615 static void xive2_redistribute(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t ring) 616 { 617 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); 618 uint8_t nsr = sig_regs[TM_NSR]; 619 uint8_t pipr = sig_regs[TM_PIPR]; 620 uint8_t crowd = NVx_CROWD_LVL(nsr); 621 uint8_t group = NVx_GROUP_LVL(nsr); 622 uint8_t nvgc_blk, end_blk, nvp_blk; 623 uint32_t nvgc_idx, end_idx, nvp_idx; 624 Xive2Nvgc nvgc; 625 uint8_t prio_limit; 626 uint32_t cfg; 627 628 /* redistribution is only for group/crowd interrupts */ 629 if (!xive_nsr_indicates_group_exception(ring, nsr)) { 630 return; 631 } 632 633 /* Don't check return code since ring is expected to be invalidated */ 634 xive2_tctx_get_nvp_indexes(tctx, ring, &nvp_blk, &nvp_idx); 635 636 trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx); 637 638 trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx); 639 /* convert crowd/group to blk/idx */ 640 if (group > 0) { 641 nvgc_idx = (nvp_idx & (0xffffffff << group)) | 642 ((1 << (group - 1)) - 1); 643 } else { 644 nvgc_idx = nvp_idx; 645 } 646 647 if (crowd > 0) { 648 crowd = (crowd == 3) ? 4 : crowd; 649 nvgc_blk = (nvp_blk & (0xffffffff << crowd)) | 650 ((1 << (crowd - 1)) - 1); 651 } else { 652 nvgc_blk = nvp_blk; 653 } 654 655 /* Use blk/idx to retrieve the NVGC */ 656 if (xive2_router_get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, &nvgc)) { 657 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no %s %x/%x\n", 658 crowd ? "NVC" : "NVG", nvgc_blk, nvgc_idx); 659 return; 660 } 661 662 /* retrieve the END blk/idx from the NVGC */ 663 end_blk = xive_get_field32(NVGC2_W1_END_BLK, nvgc.w1); 664 end_idx = xive_get_field32(NVGC2_W1_END_IDX, nvgc.w1); 665 666 /* determine number of priorities being used */ 667 cfg = xive2_router_get_config(xrtr); 668 if (cfg & XIVE2_EN_VP_GRP_PRIORITY) { 669 prio_limit = 1 << GETFIELD(NVGC2_W1_PSIZE, nvgc.w1); 670 } else { 671 prio_limit = 1 << GETFIELD(XIVE2_VP_INT_PRIO, cfg); 672 } 673 674 /* add priority offset to end index */ 675 end_idx += pipr % prio_limit; 676 677 /* trigger the group END */ 678 xive2_router_end_notify(xrtr, end_blk, end_idx, 0, true); 679 680 /* clear interrupt indication for the context */ 681 sig_regs[TM_NSR] = 0; 682 sig_regs[TM_PIPR] = sig_regs[TM_CPPR]; 683 xive_tctx_reset_signal(tctx, ring); 684 } 685 686 static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, XiveTCTX *tctx, 687 hwaddr offset, unsigned size, uint8_t ring) 688 { 689 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 690 uint32_t target_ringw2 = xive_tctx_word2(&tctx->regs[ring]); 691 uint32_t cam = be32_to_cpu(target_ringw2); 692 uint8_t nvp_blk; 693 uint32_t nvp_idx; 694 uint8_t cur_ring; 695 bool valid; 696 bool do_save; 697 uint8_t nsr; 698 699 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &valid, &do_save); 700 701 if (xive2_tctx_get_nvp_indexes(tctx, ring, &nvp_blk, &nvp_idx)) { 702 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n", 703 nvp_blk, nvp_idx); 704 } 705 706 /* Invalidate CAM line of requested ring and all lower rings */ 707 for (cur_ring = TM_QW0_USER; cur_ring <= ring; 708 cur_ring += XIVE_TM_RING_SIZE) { 709 uint32_t ringw2 = xive_tctx_word2(&tctx->regs[cur_ring]); 710 uint32_t ringw2_new = xive_set_field32(TM2_QW1W2_VO, ringw2, 0); 711 bool is_valid = !!(xive_get_field32(TM2_QW1W2_VO, ringw2)); 712 uint8_t *sig_regs; 713 714 memcpy(&tctx->regs[cur_ring + TM_WORD2], &ringw2_new, 4); 715 716 /* Skip the rest for USER or invalid contexts */ 717 if ((cur_ring == TM_QW0_USER) || !is_valid) { 718 continue; 719 } 720 721 /* Active group/crowd interrupts need to be redistributed */ 722 sig_regs = xive_tctx_signal_regs(tctx, ring); 723 nsr = sig_regs[TM_NSR]; 724 if (xive_nsr_indicates_group_exception(cur_ring, nsr)) { 725 /* Ensure ring matches NSR (for HV NSR POOL vs PHYS rings) */ 726 if (cur_ring == xive_nsr_exception_ring(cur_ring, nsr)) { 727 xive2_redistribute(xrtr, tctx, cur_ring); 728 } 729 } 730 731 /* 732 * Lower external interrupt line of requested ring and below except for 733 * USER, which doesn't exist. 734 */ 735 if (xive_nsr_indicates_exception(cur_ring, nsr)) { 736 if (cur_ring == xive_nsr_exception_ring(cur_ring, nsr)) { 737 xive_tctx_reset_signal(tctx, cur_ring); 738 } 739 } 740 } 741 742 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { 743 xive2_tctx_save_ctx(xrtr, tctx, ring, nvp_blk, nvp_idx); 744 } 745 746 return target_ringw2; 747 } 748 749 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 750 hwaddr offset, unsigned size) 751 { 752 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW1_OS); 753 } 754 755 uint64_t xive2_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 756 hwaddr offset, unsigned size) 757 { 758 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW2_HV_POOL); 759 } 760 761 uint64_t xive2_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, 762 hwaddr offset, unsigned size) 763 { 764 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW3_HV_PHYS); 765 } 766 767 #define REPORT_LINE_GEN1_SIZE 16 768 769 static void xive2_tm_report_line_gen1(XiveTCTX *tctx, uint8_t *data, 770 uint8_t size) 771 { 772 uint8_t *regs = tctx->regs; 773 774 g_assert(size == REPORT_LINE_GEN1_SIZE); 775 memset(data, 0, size); 776 /* 777 * See xive architecture for description of what is saved. It is 778 * hand-picked information to fit in 16 bytes. 779 */ 780 data[0x0] = regs[TM_QW3_HV_PHYS + TM_NSR]; 781 data[0x1] = regs[TM_QW3_HV_PHYS + TM_CPPR]; 782 data[0x2] = regs[TM_QW3_HV_PHYS + TM_IPB]; 783 data[0x3] = regs[TM_QW2_HV_POOL + TM_IPB]; 784 data[0x4] = regs[TM_QW1_OS + TM_ACK_CNT]; 785 data[0x5] = regs[TM_QW3_HV_PHYS + TM_LGS]; 786 data[0x6] = 0xFF; 787 data[0x7] = regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x80; 788 data[0x7] |= (regs[TM_QW2_HV_POOL + TM_WORD2] & 0x80) >> 1; 789 data[0x7] |= (regs[TM_QW1_OS + TM_WORD2] & 0x80) >> 2; 790 data[0x7] |= (regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x3); 791 data[0x8] = regs[TM_QW1_OS + TM_NSR]; 792 data[0x9] = regs[TM_QW1_OS + TM_CPPR]; 793 data[0xA] = regs[TM_QW1_OS + TM_IPB]; 794 data[0xB] = regs[TM_QW1_OS + TM_LGS]; 795 if (regs[TM_QW0_USER + TM_WORD2] & 0x80) { 796 /* 797 * Logical server extension, except VU bit replaced by EB bit 798 * from NSR 799 */ 800 data[0xC] = regs[TM_QW0_USER + TM_WORD2]; 801 data[0xC] &= ~0x80; 802 data[0xC] |= regs[TM_QW0_USER + TM_NSR] & 0x80; 803 data[0xD] = regs[TM_QW0_USER + TM_WORD2 + 1]; 804 data[0xE] = regs[TM_QW0_USER + TM_WORD2 + 2]; 805 data[0xF] = regs[TM_QW0_USER + TM_WORD2 + 3]; 806 } 807 } 808 809 static void xive2_tm_pull_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 810 hwaddr offset, uint64_t value, 811 unsigned size, uint8_t ring) 812 { 813 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 814 uint32_t hw_cam, nvp_idx, xive2_cfg, reserved; 815 uint8_t nvp_blk; 816 Xive2Nvp nvp; 817 uint64_t phys_addr; 818 MemTxResult result; 819 820 hw_cam = xive2_tctx_hw_cam_line(xptr, tctx); 821 nvp_blk = xive2_nvp_blk(hw_cam); 822 nvp_idx = xive2_nvp_idx(hw_cam); 823 824 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 825 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 826 nvp_blk, nvp_idx); 827 return; 828 } 829 830 if (!xive2_nvp_is_valid(&nvp)) { 831 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 832 nvp_blk, nvp_idx); 833 return; 834 } 835 836 xive2_cfg = xive2_router_get_config(xrtr); 837 838 phys_addr = xive2_nvp_reporting_addr(&nvp) + 0x80; /* odd line */ 839 if (xive2_cfg & XIVE2_GEN1_TIMA_OS) { 840 uint8_t pull_ctxt[REPORT_LINE_GEN1_SIZE]; 841 842 xive2_tm_report_line_gen1(tctx, pull_ctxt, REPORT_LINE_GEN1_SIZE); 843 result = dma_memory_write(&address_space_memory, phys_addr, 844 pull_ctxt, REPORT_LINE_GEN1_SIZE, 845 MEMTXATTRS_UNSPECIFIED); 846 assert(result == MEMTX_OK); 847 } else { 848 result = dma_memory_write(&address_space_memory, phys_addr, 849 &tctx->regs, sizeof(tctx->regs), 850 MEMTXATTRS_UNSPECIFIED); 851 assert(result == MEMTX_OK); 852 reserved = 0xFFFFFFFF; 853 result = dma_memory_write(&address_space_memory, phys_addr + 12, 854 &reserved, sizeof(reserved), 855 MEMTXATTRS_UNSPECIFIED); 856 assert(result == MEMTX_OK); 857 } 858 859 /* the rest is similar to pull context to registers */ 860 xive2_tm_pull_ctx(xptr, tctx, offset, size, ring); 861 } 862 863 void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 864 hwaddr offset, uint64_t value, unsigned size) 865 { 866 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW1_OS); 867 } 868 869 870 void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 871 hwaddr offset, uint64_t value, unsigned size) 872 { 873 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW3_HV_PHYS); 874 } 875 876 static uint8_t xive2_tctx_restore_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 877 uint8_t ring, 878 uint8_t nvp_blk, uint32_t nvp_idx, 879 Xive2Nvp *nvp) 880 { 881 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 882 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 883 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); 884 uint8_t *regs = &tctx->regs[ring]; 885 uint8_t cppr; 886 887 if (!xive2_nvp_is_hw(nvp)) { 888 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 889 nvp_blk, nvp_idx); 890 return 0; 891 } 892 893 cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2); 894 nvp->w2 = xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0); 895 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2); 896 897 sig_regs[TM_CPPR] = cppr; 898 regs[TM_LSMFB] = xive_get_field32(NVP2_W2_LSMFB, nvp->w2); 899 regs[TM_LGS] = xive_get_field32(NVP2_W2_LGS, nvp->w2); 900 regs[TM_T] = xive_get_field32(NVP2_W2_T, nvp->w2); 901 902 nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1); 903 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1); 904 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir); 905 906 /* 907 * Checkout privilege: 0:OS, 1:Pool, 2:Hard 908 * 909 * TODO: we don't support hard push/pull 910 */ 911 switch (ring) { 912 case TM_QW1_OS: 913 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0); 914 break; 915 case TM_QW2_HV_POOL: 916 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 1); 917 break; 918 default: 919 g_assert_not_reached(); 920 } 921 922 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 1); 923 924 /* return restored CPPR to generate a CPU exception if needed */ 925 return cppr; 926 } 927 928 static void xive2_tctx_process_pending(XiveTCTX *tctx, uint8_t sig_ring); 929 930 static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, 931 uint8_t nvp_blk, uint32_t nvp_idx, 932 bool do_restore) 933 { 934 uint8_t *regs = &tctx->regs[TM_QW1_OS]; 935 uint8_t ipb; 936 Xive2Nvp nvp; 937 938 /* 939 * Grab the associated thread interrupt context registers in the 940 * associated NVP 941 */ 942 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 943 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 944 nvp_blk, nvp_idx); 945 return; 946 } 947 948 if (!xive2_nvp_is_valid(&nvp)) { 949 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 950 nvp_blk, nvp_idx); 951 return; 952 } 953 954 /* Automatically restore thread context registers */ 955 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_restore) { 956 xive2_tctx_restore_ctx(xrtr, tctx, TM_QW1_OS, nvp_blk, nvp_idx, &nvp); 957 } 958 959 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2); 960 if (ipb) { 961 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0); 962 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 963 } 964 /* IPB bits in the backlog are merged with the TIMA IPB bits */ 965 regs[TM_IPB] |= ipb; 966 967 xive2_tctx_process_pending(tctx, TM_QW1_OS); 968 } 969 970 /* 971 * Updating the OS CAM line can trigger a resend of interrupt 972 */ 973 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 974 hwaddr offset, uint64_t value, unsigned size) 975 { 976 uint32_t cam; 977 uint32_t qw1w2; 978 uint64_t qw1dw1; 979 uint8_t nvp_blk; 980 uint32_t nvp_idx; 981 bool vo; 982 bool do_restore; 983 984 /* First update the thead context */ 985 switch (size) { 986 case 4: 987 cam = value; 988 qw1w2 = cpu_to_be32(cam); 989 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 990 break; 991 case 8: 992 cam = value >> 32; 993 qw1dw1 = cpu_to_be64(value); 994 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1dw1, 8); 995 break; 996 default: 997 g_assert_not_reached(); 998 } 999 1000 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore); 1001 1002 /* Check the interrupt pending bits */ 1003 if (vo) { 1004 xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx, 1005 do_restore); 1006 } 1007 } 1008 1009 /* returns -1 if ring is invalid, but still populates block and index */ 1010 static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring, 1011 uint8_t *nvp_blk, uint32_t *nvp_idx) 1012 { 1013 uint32_t w2; 1014 uint32_t cam = 0; 1015 int rc = 0; 1016 1017 w2 = xive_tctx_word2(&tctx->regs[ring]); 1018 switch (ring) { 1019 case TM_QW1_OS: 1020 if (!(be32_to_cpu(w2) & TM2_QW1W2_VO)) { 1021 rc = -1; 1022 } 1023 cam = xive_get_field32(TM2_QW1W2_OS_CAM, w2); 1024 break; 1025 case TM_QW2_HV_POOL: 1026 if (!(be32_to_cpu(w2) & TM2_QW2W2_VP)) { 1027 rc = -1; 1028 } 1029 cam = xive_get_field32(TM2_QW2W2_POOL_CAM, w2); 1030 break; 1031 case TM_QW3_HV_PHYS: 1032 if (!(be32_to_cpu(w2) & TM2_QW3W2_VT)) { 1033 rc = -1; 1034 } 1035 cam = xive2_tctx_hw_cam_line(tctx->xptr, tctx); 1036 break; 1037 default: 1038 rc = -1; 1039 } 1040 *nvp_blk = xive2_nvp_blk(cam); 1041 *nvp_idx = xive2_nvp_idx(cam); 1042 return rc; 1043 } 1044 1045 static void xive2_tctx_accept_el(XivePresenter *xptr, XiveTCTX *tctx, 1046 uint8_t ring, uint8_t cl_ring) 1047 { 1048 uint64_t rd; 1049 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 1050 uint32_t nvp_idx, xive2_cfg; 1051 uint8_t nvp_blk; 1052 Xive2Nvp nvp; 1053 uint64_t phys_addr; 1054 uint8_t OGen = 0; 1055 1056 xive2_tctx_get_nvp_indexes(tctx, cl_ring, &nvp_blk, &nvp_idx); 1057 1058 if (xive2_router_get_nvp(xrtr, (uint8_t)nvp_blk, nvp_idx, &nvp)) { 1059 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 1060 nvp_blk, nvp_idx); 1061 return; 1062 } 1063 1064 if (!xive2_nvp_is_valid(&nvp)) { 1065 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 1066 nvp_blk, nvp_idx); 1067 return; 1068 } 1069 1070 1071 rd = xive_tctx_accept(tctx, ring); 1072 1073 if (ring == TM_QW1_OS) { 1074 OGen = tctx->regs[ring + TM_OGEN]; 1075 } 1076 xive2_cfg = xive2_router_get_config(xrtr); 1077 phys_addr = xive2_nvp_reporting_addr(&nvp); 1078 uint8_t report_data[REPORT_LINE_GEN1_SIZE]; 1079 memset(report_data, 0xff, sizeof(report_data)); 1080 if ((OGen == 1) || (xive2_cfg & XIVE2_GEN1_TIMA_OS)) { 1081 report_data[8] = (rd >> 8) & 0xff; 1082 report_data[9] = rd & 0xff; 1083 } else { 1084 report_data[0] = (rd >> 8) & 0xff; 1085 report_data[1] = rd & 0xff; 1086 } 1087 cpu_physical_memory_write(phys_addr, report_data, REPORT_LINE_GEN1_SIZE); 1088 } 1089 1090 void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTCTX *tctx, 1091 hwaddr offset, uint64_t value, unsigned size) 1092 { 1093 xive2_tctx_accept_el(xptr, tctx, TM_QW1_OS, TM_QW1_OS); 1094 } 1095 1096 /* Re-calculate and present pending interrupts */ 1097 static void xive2_tctx_process_pending(XiveTCTX *tctx, uint8_t sig_ring) 1098 { 1099 uint8_t *sig_regs = &tctx->regs[sig_ring]; 1100 Xive2Router *xrtr = XIVE2_ROUTER(tctx->xptr); 1101 uint8_t backlog_prio; 1102 uint8_t first_group; 1103 uint8_t group_level; 1104 uint8_t pipr_min; 1105 uint8_t lsmfb_min; 1106 uint8_t ring_min; 1107 uint8_t cppr = sig_regs[TM_CPPR]; 1108 bool group_enabled; 1109 Xive2Nvp nvp; 1110 int rc; 1111 1112 g_assert(sig_ring == TM_QW3_HV_PHYS || sig_ring == TM_QW1_OS); 1113 g_assert(!xive_nsr_indicates_group_exception(sig_ring, sig_regs[TM_NSR])); 1114 1115 /* 1116 * Recompute the PIPR based on local pending interrupts. It will 1117 * be adjusted below if needed in case of pending group interrupts. 1118 */ 1119 again: 1120 pipr_min = xive_ipb_to_pipr(sig_regs[TM_IPB]); 1121 group_enabled = !!sig_regs[TM_LGS]; 1122 lsmfb_min = group_enabled ? sig_regs[TM_LSMFB] : 0xff; 1123 ring_min = sig_ring; 1124 group_level = 0; 1125 1126 /* PHYS updates also depend on POOL values */ 1127 if (sig_ring == TM_QW3_HV_PHYS) { 1128 uint8_t *pool_regs = &tctx->regs[TM_QW2_HV_POOL]; 1129 1130 /* POOL values only matter if POOL ctx is valid */ 1131 if (pool_regs[TM_WORD2] & 0x80) { 1132 uint8_t pool_pipr = xive_ipb_to_pipr(pool_regs[TM_IPB]); 1133 uint8_t pool_lsmfb = pool_regs[TM_LSMFB]; 1134 1135 /* 1136 * Determine highest priority interrupt and 1137 * remember which ring has it. 1138 */ 1139 if (pool_pipr < pipr_min) { 1140 pipr_min = pool_pipr; 1141 if (pool_pipr < lsmfb_min) { 1142 ring_min = TM_QW2_HV_POOL; 1143 } 1144 } 1145 1146 /* Values needed for group priority calculation */ 1147 if (pool_regs[TM_LGS] && (pool_lsmfb < lsmfb_min)) { 1148 group_enabled = true; 1149 lsmfb_min = pool_lsmfb; 1150 if (lsmfb_min < pipr_min) { 1151 ring_min = TM_QW2_HV_POOL; 1152 } 1153 } 1154 } 1155 } 1156 1157 if (group_enabled && 1158 lsmfb_min < cppr && 1159 lsmfb_min < pipr_min) { 1160 1161 uint8_t nvp_blk; 1162 uint32_t nvp_idx; 1163 1164 /* 1165 * Thread has seen a group interrupt with a higher priority 1166 * than the new cppr or pending local interrupt. Check the 1167 * backlog 1168 */ 1169 rc = xive2_tctx_get_nvp_indexes(tctx, ring_min, &nvp_blk, &nvp_idx); 1170 if (rc) { 1171 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: set CPPR on invalid " 1172 "context\n"); 1173 return; 1174 } 1175 1176 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 1177 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 1178 nvp_blk, nvp_idx); 1179 return; 1180 } 1181 1182 if (!xive2_nvp_is_valid(&nvp)) { 1183 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 1184 nvp_blk, nvp_idx); 1185 return; 1186 } 1187 1188 first_group = xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0); 1189 if (!first_group) { 1190 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 1191 nvp_blk, nvp_idx); 1192 return; 1193 } 1194 1195 backlog_prio = xive2_presenter_backlog_scan(tctx->xptr, 1196 nvp_blk, nvp_idx, 1197 first_group, &group_level); 1198 tctx->regs[ring_min + TM_LSMFB] = backlog_prio; 1199 if (backlog_prio != lsmfb_min) { 1200 /* 1201 * If the group backlog scan finds a less favored or no interrupt, 1202 * then re-do the processing which may turn up a more favored 1203 * interrupt from IPB or the other pool. Backlog should not 1204 * find a priority < LSMFB. 1205 */ 1206 g_assert(backlog_prio >= lsmfb_min); 1207 goto again; 1208 } 1209 1210 xive2_presenter_backlog_decr(tctx->xptr, nvp_blk, nvp_idx, 1211 backlog_prio, group_level); 1212 pipr_min = backlog_prio; 1213 } 1214 1215 if (pipr_min > cppr) { 1216 pipr_min = cppr; 1217 } 1218 xive_tctx_pipr_set(tctx, ring_min, pipr_min, group_level); 1219 } 1220 1221 /* NOTE: CPPR only exists for TM_QW1_OS and TM_QW3_HV_PHYS */ 1222 static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t sig_ring, uint8_t cppr) 1223 { 1224 uint8_t *sig_regs = &tctx->regs[sig_ring]; 1225 Xive2Router *xrtr = XIVE2_ROUTER(tctx->xptr); 1226 uint8_t old_cppr; 1227 uint8_t nsr = sig_regs[TM_NSR]; 1228 1229 g_assert(sig_ring == TM_QW1_OS || sig_ring == TM_QW3_HV_PHYS); 1230 1231 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] == 0); 1232 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0); 1233 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); 1234 1235 /* XXX: should show pool IPB for PHYS ring */ 1236 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, sig_ring, 1237 sig_regs[TM_IPB], sig_regs[TM_PIPR], 1238 cppr, nsr); 1239 1240 if (cppr > XIVE_PRIORITY_MAX) { 1241 cppr = 0xff; 1242 } 1243 1244 old_cppr = sig_regs[TM_CPPR]; 1245 sig_regs[TM_CPPR] = cppr; 1246 1247 /* Handle increased CPPR priority (lower value) */ 1248 if (cppr < old_cppr) { 1249 if (cppr <= sig_regs[TM_PIPR]) { 1250 /* CPPR lowered below PIPR, must un-present interrupt */ 1251 if (xive_nsr_indicates_exception(sig_ring, nsr)) { 1252 if (xive_nsr_indicates_group_exception(sig_ring, nsr)) { 1253 /* redistribute precluded active grp interrupt */ 1254 xive2_redistribute(xrtr, tctx, 1255 xive_nsr_exception_ring(sig_ring, nsr)); 1256 return; 1257 } 1258 } 1259 1260 /* interrupt is VP directed, pending in IPB */ 1261 xive_tctx_pipr_set(tctx, sig_ring, cppr, 0); 1262 return; 1263 } else { 1264 /* CPPR was lowered, but still above PIPR. No action needed. */ 1265 return; 1266 } 1267 } 1268 1269 /* CPPR didn't change, nothing needs to be done */ 1270 if (cppr == old_cppr) { 1271 return; 1272 } 1273 1274 /* CPPR priority decreased (higher value) */ 1275 if (!xive_nsr_indicates_exception(sig_ring, nsr)) { 1276 xive2_tctx_process_pending(tctx, sig_ring); 1277 } 1278 } 1279 1280 void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 1281 hwaddr offset, uint64_t value, unsigned size) 1282 { 1283 xive2_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 1284 } 1285 1286 void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 1287 hwaddr offset, uint64_t value, unsigned size) 1288 { 1289 xive2_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 1290 } 1291 1292 static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t target) 1293 { 1294 uint8_t *regs = &tctx->regs[ring]; 1295 1296 regs[TM_T] = target; 1297 } 1298 1299 void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, 1300 hwaddr offset, uint64_t value, unsigned size) 1301 { 1302 xive2_tctx_set_target(tctx, TM_QW3_HV_PHYS, value & 0xff); 1303 } 1304 1305 /* 1306 * XIVE Router (aka. Virtualization Controller or IVRE) 1307 */ 1308 1309 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1310 Xive2Eas *eas) 1311 { 1312 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1313 1314 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1315 } 1316 1317 static 1318 int xive2_router_get_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1319 uint8_t *pq) 1320 { 1321 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1322 1323 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); 1324 } 1325 1326 static 1327 int xive2_router_set_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1328 uint8_t *pq) 1329 { 1330 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1331 1332 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); 1333 } 1334 1335 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 1336 Xive2End *end) 1337 { 1338 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1339 1340 return xrc->get_end(xrtr, end_blk, end_idx, end); 1341 } 1342 1343 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 1344 Xive2End *end, uint8_t word_number) 1345 { 1346 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1347 1348 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1349 } 1350 1351 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 1352 Xive2Nvp *nvp) 1353 { 1354 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1355 1356 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp); 1357 } 1358 1359 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 1360 Xive2Nvp *nvp, uint8_t word_number) 1361 { 1362 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1363 1364 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number); 1365 } 1366 1367 int xive2_router_get_nvgc(Xive2Router *xrtr, bool crowd, 1368 uint8_t nvgc_blk, uint32_t nvgc_idx, 1369 Xive2Nvgc *nvgc) 1370 { 1371 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1372 1373 return xrc->get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); 1374 } 1375 1376 int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd, 1377 uint8_t nvgc_blk, uint32_t nvgc_idx, 1378 Xive2Nvgc *nvgc) 1379 { 1380 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1381 1382 return xrc->write_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); 1383 } 1384 1385 static bool xive2_vp_match_mask(uint32_t cam1, uint32_t cam2, 1386 uint32_t vp_mask) 1387 { 1388 return (cam1 & vp_mask) == (cam2 & vp_mask); 1389 } 1390 1391 static uint8_t xive2_get_vp_block_mask(uint32_t nvt_blk, bool crowd) 1392 { 1393 uint8_t block_mask = 0b1111; 1394 1395 /* 3 supported crowd sizes: 2, 4, 16 */ 1396 if (crowd) { 1397 uint32_t size = xive_get_vpgroup_size(nvt_blk); 1398 1399 if (size != 2 && size != 4 && size != 16) { 1400 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid crowd size of %d", 1401 size); 1402 return block_mask; 1403 } 1404 block_mask &= ~(size - 1); 1405 } 1406 return block_mask; 1407 } 1408 1409 static uint32_t xive2_get_vp_index_mask(uint32_t nvt_index, bool cam_ignore) 1410 { 1411 uint32_t index_mask = 0xFFFFFF; /* 24 bits */ 1412 1413 if (cam_ignore) { 1414 uint32_t size = xive_get_vpgroup_size(nvt_index); 1415 1416 if (size < 2) { 1417 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid group size of %d", 1418 size); 1419 return index_mask; 1420 } 1421 index_mask &= ~(size - 1); 1422 } 1423 return index_mask; 1424 } 1425 1426 /* 1427 * The thread context register words are in big-endian format. 1428 */ 1429 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1430 uint8_t format, 1431 uint8_t nvt_blk, uint32_t nvt_idx, 1432 bool crowd, bool cam_ignore, 1433 uint32_t logic_serv) 1434 { 1435 uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx); 1436 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1437 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1438 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1439 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1440 1441 uint32_t index_mask, vp_mask; 1442 uint8_t block_mask; 1443 1444 if (format == 0) { 1445 /* 1446 * i=0: Specific NVT notification 1447 * i=1: VP-group notification (bits ignored at the end of the 1448 * NVT identifier) 1449 */ 1450 block_mask = xive2_get_vp_block_mask(nvt_blk, crowd); 1451 index_mask = xive2_get_vp_index_mask(nvt_idx, cam_ignore); 1452 vp_mask = xive2_nvp_cam_line(block_mask, index_mask); 1453 1454 /* For VP-group notifications, threads with LGS=0 are excluded */ 1455 1456 /* PHYS ring */ 1457 if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) && 1458 !(cam_ignore && tctx->regs[TM_QW3_HV_PHYS + TM_LGS] == 0) && 1459 xive2_vp_match_mask(cam, 1460 xive2_tctx_hw_cam_line(xptr, tctx), 1461 vp_mask)) { 1462 return TM_QW3_HV_PHYS; 1463 } 1464 1465 /* HV POOL ring */ 1466 if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) && 1467 !(cam_ignore && tctx->regs[TM_QW2_HV_POOL + TM_LGS] == 0) && 1468 xive2_vp_match_mask(cam, 1469 xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2), 1470 vp_mask)) { 1471 return TM_QW2_HV_POOL; 1472 } 1473 1474 /* OS ring */ 1475 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 1476 !(cam_ignore && tctx->regs[TM_QW1_OS + TM_LGS] == 0) && 1477 xive2_vp_match_mask(cam, 1478 xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2), 1479 vp_mask)) { 1480 return TM_QW1_OS; 1481 } 1482 } else { 1483 /* F=1 : User level Event-Based Branch (EBB) notification */ 1484 1485 /* FIXME: what if cam_ignore and LGS = 0 ? */ 1486 /* USER ring */ 1487 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 1488 (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) && 1489 (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) && 1490 (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) { 1491 return TM_QW0_USER; 1492 } 1493 } 1494 return -1; 1495 } 1496 1497 bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority) 1498 { 1499 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); 1500 1501 /* 1502 * The xive2_presenter_tctx_match() above tells if there's a match 1503 * but for VP-group notification, we still need to look at the 1504 * priority to know if the thread can take the interrupt now or if 1505 * it is precluded. 1506 */ 1507 if (priority < sig_regs[TM_PIPR]) { 1508 return false; 1509 } 1510 return true; 1511 } 1512 1513 void xive2_tm_set_lsmfb(XiveTCTX *tctx, int ring, uint8_t priority) 1514 { 1515 uint8_t *regs = &tctx->regs[ring]; 1516 1517 /* 1518 * Called by the router during a VP-group notification when the 1519 * thread matches but can't take the interrupt because it's 1520 * already running at a more favored priority. It then stores the 1521 * new interrupt priority in the LSMFB field. 1522 */ 1523 regs[TM_LSMFB] = priority; 1524 } 1525 1526 static void xive2_router_realize(DeviceState *dev, Error **errp) 1527 { 1528 Xive2Router *xrtr = XIVE2_ROUTER(dev); 1529 1530 assert(xrtr->xfb); 1531 } 1532 1533 /* 1534 * Notification using the END ESe/ESn bit (Event State Buffer for 1535 * escalation and notification). Profide further coalescing in the 1536 * Router. 1537 */ 1538 static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk, 1539 uint32_t end_idx, Xive2End *end, 1540 uint32_t end_esmask) 1541 { 1542 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1543 bool notify = xive_esb_trigger(&pq); 1544 1545 if (pq != xive_get_field32(end_esmask, end->w1)) { 1546 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1547 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1); 1548 } 1549 1550 /* ESe/n[Q]=1 : end of notification */ 1551 return notify; 1552 } 1553 1554 /* 1555 * An END trigger can come from an event trigger (IPI or HW) or from 1556 * another chip. We don't model the PowerBus but the END trigger 1557 * message has the same parameters than in the function below. 1558 */ 1559 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 1560 uint32_t end_idx, uint32_t end_data, 1561 bool redistribute) 1562 { 1563 Xive2End end; 1564 uint8_t priority; 1565 uint8_t format; 1566 XiveTCTXMatch match; 1567 bool crowd, cam_ignore; 1568 uint8_t nvx_blk; 1569 uint32_t nvx_idx; 1570 1571 /* END cache lookup */ 1572 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) { 1573 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1574 end_idx); 1575 return; 1576 } 1577 1578 if (!xive2_end_is_valid(&end)) { 1579 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1580 end_blk, end_idx); 1581 return; 1582 } 1583 1584 if (xive2_end_is_crowd(&end) && !xive2_end_is_ignore(&end)) { 1585 qemu_log_mask(LOG_GUEST_ERROR, 1586 "XIVE: invalid END, 'crowd' bit requires 'ignore' bit\n"); 1587 return; 1588 } 1589 1590 if (!redistribute && xive2_end_is_enqueue(&end)) { 1591 trace_xive_end_enqueue(end_blk, end_idx, end_data); 1592 xive2_end_enqueue(&end, end_data); 1593 /* Enqueuing event data modifies the EQ toggle and index */ 1594 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1595 } 1596 1597 /* 1598 * When the END is silent, we skip the notification part. 1599 */ 1600 if (xive2_end_is_silent_escalation(&end)) { 1601 goto do_escalation; 1602 } 1603 1604 /* 1605 * The W7 format depends on the F bit in W6. It defines the type 1606 * of the notification : 1607 * 1608 * F=0 : single or multiple NVP notification 1609 * F=1 : User level Event-Based Branch (EBB) notification, no 1610 * priority 1611 */ 1612 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6); 1613 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7); 1614 1615 /* The END is masked */ 1616 if (format == 0 && priority == 0xff) { 1617 return; 1618 } 1619 1620 /* 1621 * Check the END ESn (Event State Buffer for notification) for 1622 * even further coalescing in the Router 1623 */ 1624 if (!xive2_end_is_notify(&end)) { 1625 /* ESn[Q]=1 : end of notification */ 1626 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 1627 &end, END2_W1_ESn)) { 1628 return; 1629 } 1630 } 1631 1632 /* 1633 * Follows IVPE notification 1634 */ 1635 nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6); 1636 nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6); 1637 crowd = xive2_end_is_crowd(&end); 1638 cam_ignore = xive2_end_is_ignore(&end); 1639 1640 /* TODO: Auto EOI. */ 1641 if (xive_presenter_match(xrtr->xfb, format, nvx_blk, nvx_idx, 1642 crowd, cam_ignore, priority, 1643 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7), 1644 &match)) { 1645 XiveTCTX *tctx = match.tctx; 1646 uint8_t ring = match.ring; 1647 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); 1648 uint8_t nsr = sig_regs[TM_NSR]; 1649 uint8_t group_level; 1650 1651 if (priority < sig_regs[TM_PIPR] && 1652 xive_nsr_indicates_group_exception(ring, nsr)) { 1653 xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, nsr)); 1654 } 1655 1656 group_level = xive_get_group_level(crowd, cam_ignore, nvx_blk, nvx_idx); 1657 trace_xive_presenter_notify(nvx_blk, nvx_idx, ring, group_level); 1658 xive_tctx_pipr_present(tctx, ring, priority, group_level); 1659 return; 1660 } 1661 1662 /* 1663 * If no matching NVP is dispatched on a HW thread : 1664 * - specific VP: update the NVP structure if backlog is activated 1665 * - VP-group: update the backlog counter for that priority in the NVG 1666 */ 1667 if (xive2_end_is_backlog(&end)) { 1668 1669 if (format == 1) { 1670 qemu_log_mask(LOG_GUEST_ERROR, 1671 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1672 end_blk, end_idx); 1673 return; 1674 } 1675 1676 if (!cam_ignore) { 1677 uint8_t ipb; 1678 Xive2Nvp nvp; 1679 1680 /* NVP cache lookup */ 1681 if (xive2_router_get_nvp(xrtr, nvx_blk, nvx_idx, &nvp)) { 1682 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n", 1683 nvx_blk, nvx_idx); 1684 return; 1685 } 1686 1687 if (!xive2_nvp_is_valid(&nvp)) { 1688 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n", 1689 nvx_blk, nvx_idx); 1690 return; 1691 } 1692 1693 /* 1694 * Record the IPB in the associated NVP structure for later 1695 * use. The presenter will resend the interrupt when the vCPU 1696 * is dispatched again on a HW thread. 1697 */ 1698 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) | 1699 xive_priority_to_ipb(priority); 1700 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 1701 xive2_router_write_nvp(xrtr, nvx_blk, nvx_idx, &nvp, 2); 1702 } else { 1703 Xive2Nvgc nvgc; 1704 uint32_t backlog; 1705 1706 /* 1707 * For groups and crowds, the per-priority backlog 1708 * counters are stored in the NVG/NVC structures 1709 */ 1710 if (xive2_router_get_nvgc(xrtr, crowd, 1711 nvx_blk, nvx_idx, &nvgc)) { 1712 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no %s %x/%x\n", 1713 crowd ? "NVC" : "NVG", nvx_blk, nvx_idx); 1714 return; 1715 } 1716 1717 if (!xive2_nvgc_is_valid(&nvgc)) { 1718 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVG %x/%x is invalid\n", 1719 nvx_blk, nvx_idx); 1720 return; 1721 } 1722 1723 /* 1724 * Increment the backlog counter for that priority. 1725 * We only call broadcast the first time the counter is 1726 * incremented. broadcast will set the LSMFB field of the TIMA of 1727 * relevant threads so that they know an interrupt is pending. 1728 */ 1729 backlog = xive2_nvgc_get_backlog(&nvgc, priority) + 1; 1730 xive2_nvgc_set_backlog(&nvgc, priority, backlog); 1731 xive2_router_write_nvgc(xrtr, crowd, nvx_blk, nvx_idx, &nvgc); 1732 1733 if (backlog == 1) { 1734 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xrtr->xfb); 1735 xfc->broadcast(xrtr->xfb, nvx_blk, nvx_idx, 1736 crowd, cam_ignore, priority); 1737 1738 if (!xive2_end_is_precluded_escalation(&end)) { 1739 /* 1740 * The interrupt will be picked up when the 1741 * matching thread lowers its priority level 1742 */ 1743 return; 1744 } 1745 } 1746 } 1747 } 1748 1749 do_escalation: 1750 /* 1751 * If activated, escalate notification using the ESe PQ bits and 1752 * the EAS in w4-5 1753 */ 1754 if (!xive2_end_is_escalate(&end)) { 1755 return; 1756 } 1757 1758 /* 1759 * Check the END ESe (Event State Buffer for escalation) for even 1760 * further coalescing in the Router 1761 */ 1762 if (!xive2_end_is_uncond_escalation(&end)) { 1763 /* ESe[Q]=1 : end of escalation notification */ 1764 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 1765 &end, END2_W1_ESe)) { 1766 return; 1767 } 1768 } 1769 1770 if (xive2_end_is_escalate_end(&end)) { 1771 /* 1772 * Perform END Adaptive escalation processing 1773 * The END trigger becomes an Escalation trigger 1774 */ 1775 uint8_t esc_blk = xive_get_field32(END2_W4_END_BLOCK, end.w4); 1776 uint32_t esc_idx = xive_get_field32(END2_W4_ESC_END_INDEX, end.w4); 1777 uint32_t esc_data = xive_get_field32(END2_W5_ESC_END_DATA, end.w5); 1778 trace_xive_escalate_end(end_blk, end_idx, esc_blk, esc_idx, esc_data); 1779 xive2_router_end_notify(xrtr, esc_blk, esc_idx, esc_data, false); 1780 } /* end END adaptive escalation */ 1781 1782 else { 1783 uint32_t lisn; /* Logical Interrupt Source Number */ 1784 1785 /* 1786 * Perform ESB escalation processing 1787 * E[N] == 1 --> N 1788 * Req[Block] <- E[ESB_Block] 1789 * Req[Index] <- E[ESB_Index] 1790 * Req[Offset] <- 0x000 1791 * Execute <ESB Store> Req command 1792 */ 1793 lisn = XIVE_EAS(xive_get_field32(END2_W4_END_BLOCK, end.w4), 1794 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4)); 1795 1796 trace_xive_escalate_esb(end_blk, end_idx, lisn); 1797 xive2_notify(xrtr, lisn, true /* pq_checked */); 1798 } 1799 1800 return; 1801 } 1802 1803 void xive2_notify(Xive2Router *xrtr , uint32_t lisn, bool pq_checked) 1804 { 1805 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1806 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1807 Xive2Eas eas; 1808 1809 /* EAS cache lookup */ 1810 if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1811 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1812 return; 1813 } 1814 1815 if (!pq_checked) { 1816 bool notify; 1817 uint8_t pq; 1818 1819 /* PQ cache lookup */ 1820 if (xive2_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) { 1821 /* Set FIR */ 1822 g_assert_not_reached(); 1823 } 1824 1825 notify = xive_esb_trigger(&pq); 1826 1827 if (xive2_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) { 1828 /* Set FIR */ 1829 g_assert_not_reached(); 1830 } 1831 1832 if (!notify) { 1833 return; 1834 } 1835 } 1836 1837 if (!xive2_eas_is_valid(&eas)) { 1838 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn); 1839 return; 1840 } 1841 1842 if (xive2_eas_is_masked(&eas)) { 1843 /* Notification completed */ 1844 return; 1845 } 1846 1847 /* TODO: add support for EAS resume */ 1848 if (xive2_eas_is_resume(&eas)) { 1849 qemu_log_mask(LOG_UNIMP, 1850 "XIVE: EAS resume processing unimplemented - LISN %x\n", 1851 lisn); 1852 return; 1853 } 1854 1855 /* 1856 * The event trigger becomes an END trigger 1857 */ 1858 xive2_router_end_notify(xrtr, 1859 xive_get_field64(EAS2_END_BLOCK, eas.w), 1860 xive_get_field64(EAS2_END_INDEX, eas.w), 1861 xive_get_field64(EAS2_END_DATA, eas.w), 1862 false); 1863 return; 1864 } 1865 1866 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) 1867 { 1868 Xive2Router *xrtr = XIVE2_ROUTER(xn); 1869 1870 xive2_notify(xrtr, lisn, pq_checked); 1871 return; 1872 } 1873 1874 static const Property xive2_router_properties[] = { 1875 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb, 1876 TYPE_XIVE_FABRIC, XiveFabric *), 1877 }; 1878 1879 static void xive2_router_class_init(ObjectClass *klass, const void *data) 1880 { 1881 DeviceClass *dc = DEVICE_CLASS(klass); 1882 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1883 1884 dc->desc = "XIVE2 Router Engine"; 1885 device_class_set_props(dc, xive2_router_properties); 1886 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 1887 dc->realize = xive2_router_realize; 1888 xnc->notify = xive2_router_notify; 1889 } 1890 1891 static const TypeInfo xive2_router_info = { 1892 .name = TYPE_XIVE2_ROUTER, 1893 .parent = TYPE_SYS_BUS_DEVICE, 1894 .abstract = true, 1895 .instance_size = sizeof(Xive2Router), 1896 .class_size = sizeof(Xive2RouterClass), 1897 .class_init = xive2_router_class_init, 1898 .interfaces = (const InterfaceInfo[]) { 1899 { TYPE_XIVE_NOTIFIER }, 1900 { TYPE_XIVE_PRESENTER }, 1901 { } 1902 } 1903 }; 1904 1905 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 1906 { 1907 return !((addr >> shift) & 1); 1908 } 1909 1910 static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size) 1911 { 1912 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 1913 uint32_t offset = addr & 0xFFF; 1914 uint8_t end_blk; 1915 uint32_t end_idx; 1916 Xive2End end; 1917 uint32_t end_esmask; 1918 uint8_t pq; 1919 uint64_t ret; 1920 1921 /* 1922 * The block id should be deduced from the load address on the END 1923 * ESB MMIO but our model only supports a single block per XIVE chip. 1924 */ 1925 end_blk = xive2_router_get_block_id(xsrc->xrtr); 1926 end_idx = addr >> (xsrc->esb_shift + 1); 1927 1928 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1929 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1930 end_idx); 1931 return -1; 1932 } 1933 1934 if (!xive2_end_is_valid(&end)) { 1935 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1936 end_blk, end_idx); 1937 return -1; 1938 } 1939 1940 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 1941 END2_W1_ESe; 1942 pq = xive_get_field32(end_esmask, end.w1); 1943 1944 switch (offset) { 1945 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1946 ret = xive_esb_eoi(&pq); 1947 1948 /* Forward the source event notification for routing ?? */ 1949 break; 1950 1951 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1952 ret = pq; 1953 break; 1954 1955 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1956 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1957 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1958 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1959 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1960 break; 1961 default: 1962 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1963 offset); 1964 return -1; 1965 } 1966 1967 if (pq != xive_get_field32(end_esmask, end.w1)) { 1968 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1969 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1970 } 1971 1972 return ret; 1973 } 1974 1975 static void xive2_end_source_write(void *opaque, hwaddr addr, 1976 uint64_t value, unsigned size) 1977 { 1978 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 1979 uint32_t offset = addr & 0xFFF; 1980 uint8_t end_blk; 1981 uint32_t end_idx; 1982 Xive2End end; 1983 uint32_t end_esmask; 1984 uint8_t pq; 1985 bool notify = false; 1986 1987 /* 1988 * The block id should be deduced from the load address on the END 1989 * ESB MMIO but our model only supports a single block per XIVE chip. 1990 */ 1991 end_blk = xive2_router_get_block_id(xsrc->xrtr); 1992 end_idx = addr >> (xsrc->esb_shift + 1); 1993 1994 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1995 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1996 end_idx); 1997 return; 1998 } 1999 2000 if (!xive2_end_is_valid(&end)) { 2001 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 2002 end_blk, end_idx); 2003 return; 2004 } 2005 2006 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 2007 END2_W1_ESe; 2008 pq = xive_get_field32(end_esmask, end.w1); 2009 2010 switch (offset) { 2011 case 0 ... 0x3FF: 2012 notify = xive_esb_trigger(&pq); 2013 break; 2014 2015 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 2016 /* TODO: can we check StoreEOI availability from the router ? */ 2017 notify = xive_esb_eoi(&pq); 2018 break; 2019 2020 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: 2021 if (end_esmask == END2_W1_ESe) { 2022 qemu_log_mask(LOG_GUEST_ERROR, 2023 "XIVE: END %x/%x can not EQ inject on ESe\n", 2024 end_blk, end_idx); 2025 return; 2026 } 2027 notify = true; 2028 break; 2029 2030 default: 2031 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n", 2032 offset); 2033 return; 2034 } 2035 2036 if (pq != xive_get_field32(end_esmask, end.w1)) { 2037 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 2038 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 2039 } 2040 2041 /* TODO: Forward the source event notification for routing */ 2042 if (notify) { 2043 ; 2044 } 2045 } 2046 2047 static const MemoryRegionOps xive2_end_source_ops = { 2048 .read = xive2_end_source_read, 2049 .write = xive2_end_source_write, 2050 .endianness = DEVICE_BIG_ENDIAN, 2051 .valid = { 2052 .min_access_size = 1, 2053 .max_access_size = 8, 2054 }, 2055 .impl = { 2056 .min_access_size = 1, 2057 .max_access_size = 8, 2058 }, 2059 }; 2060 2061 static void xive2_end_source_realize(DeviceState *dev, Error **errp) 2062 { 2063 Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev); 2064 2065 assert(xsrc->xrtr); 2066 2067 if (!xsrc->nr_ends) { 2068 error_setg(errp, "Number of interrupt needs to be greater than 0"); 2069 return; 2070 } 2071 2072 if (xsrc->esb_shift != XIVE_ESB_4K && 2073 xsrc->esb_shift != XIVE_ESB_64K) { 2074 error_setg(errp, "Invalid ESB shift setting"); 2075 return; 2076 } 2077 2078 /* 2079 * Each END is assigned an even/odd pair of MMIO pages, the even page 2080 * manages the ESn field while the odd page manages the ESe field. 2081 */ 2082 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 2083 &xive2_end_source_ops, xsrc, "xive.end", 2084 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 2085 } 2086 2087 static const Property xive2_end_source_properties[] = { 2088 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0), 2089 DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K), 2090 DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER, 2091 Xive2Router *), 2092 }; 2093 2094 static void xive2_end_source_class_init(ObjectClass *klass, const void *data) 2095 { 2096 DeviceClass *dc = DEVICE_CLASS(klass); 2097 2098 dc->desc = "XIVE END Source"; 2099 device_class_set_props(dc, xive2_end_source_properties); 2100 dc->realize = xive2_end_source_realize; 2101 dc->user_creatable = false; 2102 } 2103 2104 static const TypeInfo xive2_end_source_info = { 2105 .name = TYPE_XIVE2_END_SOURCE, 2106 .parent = TYPE_DEVICE, 2107 .instance_size = sizeof(Xive2EndSource), 2108 .class_init = xive2_end_source_class_init, 2109 }; 2110 2111 static void xive2_register_types(void) 2112 { 2113 type_register_static(&xive2_router_info); 2114 type_register_static(&xive2_end_source_info); 2115 } 2116 2117 type_init(xive2_register_types) 2118