1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2024, IBM Corporation.. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/log.h" 11 #include "qemu/module.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "system/cpus.h" 15 #include "system/dma.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/ppc/xive.h" 18 #include "hw/ppc/xive2.h" 19 #include "hw/ppc/xive2_regs.h" 20 #include "trace.h" 21 22 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 23 uint32_t end_idx, uint32_t end_data, 24 bool redistribute); 25 26 static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring, 27 uint8_t *nvp_blk, uint32_t *nvp_idx); 28 29 uint32_t xive2_router_get_config(Xive2Router *xrtr) 30 { 31 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 32 33 return xrc->get_config(xrtr); 34 } 35 36 static int xive2_router_get_block_id(Xive2Router *xrtr) 37 { 38 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 39 40 return xrc->get_block_id(xrtr); 41 } 42 43 static uint64_t xive2_nvp_reporting_addr(Xive2Nvp *nvp) 44 { 45 uint64_t cache_addr; 46 47 cache_addr = xive_get_field32(NVP2_W6_REPORTING_LINE, nvp->w6) << 24 | 48 xive_get_field32(NVP2_W7_REPORTING_LINE, nvp->w7); 49 cache_addr <<= 8; /* aligned on a cache line pair */ 50 return cache_addr; 51 } 52 53 static uint32_t xive2_nvgc_get_backlog(Xive2Nvgc *nvgc, uint8_t priority) 54 { 55 uint32_t val = 0; 56 uint8_t *ptr, i; 57 58 if (priority > 7) { 59 return 0; 60 } 61 62 /* 63 * The per-priority backlog counters are 24-bit and the structure 64 * is stored in big endian. NVGC is 32-bytes long, so 24-bytes from 65 * w2, which fits 8 priorities * 24-bits per priority. 66 */ 67 ptr = (uint8_t *)&nvgc->w2 + priority * 3; 68 for (i = 0; i < 3; i++, ptr++) { 69 val = (val << 8) + *ptr; 70 } 71 return val; 72 } 73 74 static void xive2_nvgc_set_backlog(Xive2Nvgc *nvgc, uint8_t priority, 75 uint32_t val) 76 { 77 uint8_t *ptr, i; 78 uint32_t shift; 79 80 if (priority > 7) { 81 return; 82 } 83 84 if (val > 0xFFFFFF) { 85 val = 0xFFFFFF; 86 } 87 /* 88 * The per-priority backlog counters are 24-bit and the structure 89 * is stored in big endian 90 */ 91 ptr = (uint8_t *)&nvgc->w2 + priority * 3; 92 for (i = 0; i < 3; i++, ptr++) { 93 shift = 8 * (2 - i); 94 *ptr = (val >> shift) & 0xFF; 95 } 96 } 97 98 uint64_t xive2_presenter_nvgc_backlog_op(XivePresenter *xptr, 99 bool crowd, 100 uint8_t blk, uint32_t idx, 101 uint16_t offset, uint16_t val) 102 { 103 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 104 uint8_t priority = GETFIELD(NVx_BACKLOG_PRIO, offset); 105 uint8_t op = GETFIELD(NVx_BACKLOG_OP, offset); 106 Xive2Nvgc nvgc; 107 uint32_t count, old_count; 108 109 if (xive2_router_get_nvgc(xrtr, crowd, blk, idx, &nvgc)) { 110 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No %s %x/%x\n", 111 crowd ? "NVC" : "NVG", blk, idx); 112 return -1; 113 } 114 if (!xive2_nvgc_is_valid(&nvgc)) { 115 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n", blk, idx); 116 return -1; 117 } 118 119 old_count = xive2_nvgc_get_backlog(&nvgc, priority); 120 count = old_count; 121 /* 122 * op: 123 * 0b00 => increment 124 * 0b01 => decrement 125 * 0b1- => read 126 */ 127 if (op == 0b00 || op == 0b01) { 128 if (op == 0b00) { 129 count += val; 130 } else { 131 if (count > val) { 132 count -= val; 133 } else { 134 count = 0; 135 } 136 } 137 xive2_nvgc_set_backlog(&nvgc, priority, count); 138 xive2_router_write_nvgc(xrtr, crowd, blk, idx, &nvgc); 139 } 140 trace_xive_nvgc_backlog_op(crowd, blk, idx, op, priority, old_count); 141 return old_count; 142 } 143 144 uint64_t xive2_presenter_nvp_backlog_op(XivePresenter *xptr, 145 uint8_t blk, uint32_t idx, 146 uint16_t offset) 147 { 148 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 149 uint8_t priority = GETFIELD(NVx_BACKLOG_PRIO, offset); 150 uint8_t op = GETFIELD(NVx_BACKLOG_OP, offset); 151 Xive2Nvp nvp; 152 uint8_t ipb, old_ipb, rc; 153 154 if (xive2_router_get_nvp(xrtr, blk, idx, &nvp)) { 155 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", blk, idx); 156 return -1; 157 } 158 if (!xive2_nvp_is_valid(&nvp)) { 159 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVP %x/%x\n", blk, idx); 160 return -1; 161 } 162 163 old_ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2); 164 ipb = old_ipb; 165 /* 166 * op: 167 * 0b00 => set priority bit 168 * 0b01 => reset priority bit 169 * 0b1- => read 170 */ 171 if (op == 0b00 || op == 0b01) { 172 if (op == 0b00) { 173 ipb |= xive_priority_to_ipb(priority); 174 } else { 175 ipb &= ~xive_priority_to_ipb(priority); 176 } 177 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 178 xive2_router_write_nvp(xrtr, blk, idx, &nvp, 2); 179 } 180 rc = !!(old_ipb & xive_priority_to_ipb(priority)); 181 trace_xive_nvp_backlog_op(blk, idx, op, priority, rc); 182 return rc; 183 } 184 185 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf) 186 { 187 if (!xive2_eas_is_valid(eas)) { 188 return; 189 } 190 191 g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n", 192 lisn, xive2_eas_is_masked(eas) ? "M" : " ", 193 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 194 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 195 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 196 } 197 198 #define XIVE2_QSIZE_CHUNK_CL 128 199 #define XIVE2_QSIZE_CHUNK_4k 4096 200 /* Calculate max number of queue entries for an END */ 201 static uint32_t xive2_end_get_qentries(Xive2End *end) 202 { 203 uint32_t w3 = end->w3; 204 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, w3); 205 if (xive_get_field32(END2_W3_CL, w3)) { 206 g_assert(qsize <= 4); 207 return (XIVE2_QSIZE_CHUNK_CL << qsize) / sizeof(uint32_t); 208 } else { 209 g_assert(qsize <= 12); 210 return (XIVE2_QSIZE_CHUNK_4k << qsize) / sizeof(uint32_t); 211 } 212 } 213 214 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString *buf) 215 { 216 uint64_t qaddr_base = xive2_end_qaddr(end); 217 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 218 uint32_t qentries = xive2_end_get_qentries(end); 219 int i; 220 221 /* 222 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 223 */ 224 g_string_append_printf(buf, " [ "); 225 qindex = (qindex - (width - 1)) & (qentries - 1); 226 for (i = 0; i < width; i++) { 227 uint64_t qaddr = qaddr_base + (qindex << 2); 228 uint32_t qdata = -1; 229 230 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 231 sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 232 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 233 HWADDR_PRIx "\n", qaddr); 234 return; 235 } 236 g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "", 237 be32_to_cpu(qdata)); 238 qindex = (qindex + 1) & (qentries - 1); 239 } 240 g_string_append_printf(buf, "]"); 241 } 242 243 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf) 244 { 245 uint64_t qaddr_base = xive2_end_qaddr(end); 246 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 247 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 248 uint32_t qentries = xive2_end_get_qentries(end); 249 250 uint32_t nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); 251 uint32_t nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); 252 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7); 253 uint8_t pq; 254 255 if (!xive2_end_is_valid(end)) { 256 return; 257 } 258 259 pq = xive_get_field32(END2_W1_ESn, end->w1); 260 261 g_string_append_printf(buf, 262 " %08x %c%c %c%c%c%c%c%c%c%c%c%c%c %c%c " 263 "prio:%d nvp:%02x/%04x", 264 end_idx, 265 pq & XIVE_ESB_VAL_P ? 'P' : '-', 266 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 267 xive2_end_is_valid(end) ? 'v' : '-', 268 xive2_end_is_enqueue(end) ? 'q' : '-', 269 xive2_end_is_notify(end) ? 'n' : '-', 270 xive2_end_is_backlog(end) ? 'b' : '-', 271 xive2_end_is_precluded_escalation(end) ? 'p' : '-', 272 xive2_end_is_escalate(end) ? 'e' : '-', 273 xive2_end_is_escalate_end(end) ? 'N' : '-', 274 xive2_end_is_uncond_escalation(end) ? 'u' : '-', 275 xive2_end_is_silent_escalation(end) ? 's' : '-', 276 xive2_end_is_firmware1(end) ? 'f' : '-', 277 xive2_end_is_firmware2(end) ? 'F' : '-', 278 xive2_end_is_ignore(end) ? 'i' : '-', 279 xive2_end_is_crowd(end) ? 'c' : '-', 280 priority, nvx_blk, nvx_idx); 281 282 if (qaddr_base) { 283 g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d", 284 qaddr_base, qindex, qentries, qgen); 285 xive2_end_queue_pic_print_info(end, 6, buf); 286 } 287 g_string_append_c(buf, '\n'); 288 } 289 290 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, 291 GString *buf) 292 { 293 Xive2Eas *eas = (Xive2Eas *) &end->w4; 294 uint8_t pq; 295 296 if (!xive2_end_is_escalate(end)) { 297 return; 298 } 299 300 pq = xive_get_field32(END2_W1_ESe, end->w1); 301 302 g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 303 end_idx, 304 pq & XIVE_ESB_VAL_P ? 'P' : '-', 305 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 306 xive2_eas_is_valid(eas) ? 'v' : ' ', 307 xive2_eas_is_masked(eas) ? 'M' : ' ', 308 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 309 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 310 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 311 } 312 313 void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *buf) 314 { 315 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); 316 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); 317 uint64_t cache_line = xive2_nvp_reporting_addr(nvp); 318 319 if (!xive2_nvp_is_valid(nvp)) { 320 return; 321 } 322 323 g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x PGoFirst:%02x", 324 nvp_idx, eq_blk, eq_idx, 325 xive_get_field32(NVP2_W2_IPB, nvp->w2), 326 xive_get_field32(NVP2_W0_PGOFIRST, nvp->w0)); 327 if (cache_line) { 328 g_string_append_printf(buf, " reporting CL:%016"PRIx64, cache_line); 329 } 330 331 /* 332 * When the NVP is HW controlled, more fields are updated 333 */ 334 if (xive2_nvp_is_hw(nvp)) { 335 g_string_append_printf(buf, " CPPR:%02x", 336 xive_get_field32(NVP2_W2_CPPR, nvp->w2)); 337 if (xive2_nvp_is_co(nvp)) { 338 g_string_append_printf(buf, " CO:%04x", 339 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); 340 } 341 } 342 g_string_append_c(buf, '\n'); 343 } 344 345 void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_t nvgc_idx, GString *buf) 346 { 347 uint8_t i; 348 349 if (!xive2_nvgc_is_valid(nvgc)) { 350 return; 351 } 352 353 g_string_append_printf(buf, " %08x PGoNext:%02x bklog: ", nvgc_idx, 354 xive_get_field32(NVGC2_W0_PGONEXT, nvgc->w0)); 355 for (i = 0; i <= XIVE_PRIORITY_MAX; i++) { 356 g_string_append_printf(buf, "[%d]=0x%x ", 357 i, xive2_nvgc_get_backlog(nvgc, i)); 358 } 359 g_string_append_printf(buf, "\n"); 360 } 361 362 static void xive2_end_enqueue(Xive2End *end, uint32_t data) 363 { 364 uint64_t qaddr_base = xive2_end_qaddr(end); 365 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 366 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 367 368 uint64_t qaddr = qaddr_base + (qindex << 2); 369 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 370 uint32_t qentries = xive2_end_get_qentries(end); 371 372 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata), 373 MEMTXATTRS_UNSPECIFIED)) { 374 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 375 HWADDR_PRIx "\n", qaddr); 376 return; 377 } 378 379 qindex = (qindex + 1) & (qentries - 1); 380 if (qindex == 0) { 381 qgen ^= 1; 382 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); 383 384 /* Set gen flipped to 1, it gets reset on a cache watch operation */ 385 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, 1); 386 } 387 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); 388 } 389 390 static void xive2_pgofnext(uint8_t *nvgc_blk, uint32_t *nvgc_idx, 391 uint8_t next_level) 392 { 393 uint32_t mask, next_idx; 394 uint8_t next_blk; 395 396 /* 397 * Adjust the block and index of a VP for the next group/crowd 398 * size (PGofFirst/PGofNext field in the NVP and NVGC structures). 399 * 400 * The 6-bit group level is split into a 2-bit crowd and 4-bit 401 * group levels. Encoding is similar. However, we don't support 402 * crowd size of 8. So a crowd level of 0b11 is bumped to a crowd 403 * size of 16. 404 */ 405 next_blk = NVx_CROWD_LVL(next_level); 406 if (next_blk == 3) { 407 next_blk = 4; 408 } 409 mask = (1 << next_blk) - 1; 410 *nvgc_blk &= ~mask; 411 *nvgc_blk |= mask >> 1; 412 413 next_idx = NVx_GROUP_LVL(next_level); 414 mask = (1 << next_idx) - 1; 415 *nvgc_idx &= ~mask; 416 *nvgc_idx |= mask >> 1; 417 } 418 419 /* 420 * Scan the group chain and return the highest priority and group 421 * level of pending group interrupts. 422 */ 423 static uint8_t xive2_presenter_backlog_scan(XivePresenter *xptr, 424 uint8_t nvx_blk, uint32_t nvx_idx, 425 uint8_t first_group, 426 uint8_t *out_level) 427 { 428 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 429 uint32_t nvgc_idx; 430 uint32_t current_level, count; 431 uint8_t nvgc_blk, prio; 432 Xive2Nvgc nvgc; 433 434 for (prio = 0; prio <= XIVE_PRIORITY_MAX; prio++) { 435 current_level = first_group & 0x3F; 436 nvgc_blk = nvx_blk; 437 nvgc_idx = nvx_idx; 438 439 while (current_level) { 440 xive2_pgofnext(&nvgc_blk, &nvgc_idx, current_level); 441 442 if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(current_level), 443 nvgc_blk, nvgc_idx, &nvgc)) { 444 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n", 445 nvgc_blk, nvgc_idx); 446 return 0xFF; 447 } 448 if (!xive2_nvgc_is_valid(&nvgc)) { 449 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n", 450 nvgc_blk, nvgc_idx); 451 return 0xFF; 452 } 453 454 count = xive2_nvgc_get_backlog(&nvgc, prio); 455 if (count) { 456 *out_level = current_level; 457 return prio; 458 } 459 current_level = xive_get_field32(NVGC2_W0_PGONEXT, nvgc.w0) & 0x3F; 460 } 461 } 462 return 0xFF; 463 } 464 465 static void xive2_presenter_backlog_decr(XivePresenter *xptr, 466 uint8_t nvx_blk, uint32_t nvx_idx, 467 uint8_t group_prio, 468 uint8_t group_level) 469 { 470 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 471 uint32_t nvgc_idx, count; 472 uint8_t nvgc_blk; 473 Xive2Nvgc nvgc; 474 475 nvgc_blk = nvx_blk; 476 nvgc_idx = nvx_idx; 477 xive2_pgofnext(&nvgc_blk, &nvgc_idx, group_level); 478 479 if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(group_level), 480 nvgc_blk, nvgc_idx, &nvgc)) { 481 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n", 482 nvgc_blk, nvgc_idx); 483 return; 484 } 485 if (!xive2_nvgc_is_valid(&nvgc)) { 486 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n", 487 nvgc_blk, nvgc_idx); 488 return; 489 } 490 count = xive2_nvgc_get_backlog(&nvgc, group_prio); 491 if (!count) { 492 return; 493 } 494 xive2_nvgc_set_backlog(&nvgc, group_prio, count - 1); 495 xive2_router_write_nvgc(xrtr, NVx_CROWD_LVL(group_level), 496 nvgc_blk, nvgc_idx, &nvgc); 497 } 498 499 /* 500 * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode 501 * 502 * TIMA Gen2 VP “save & restore” (S&R) indicated by H bit next to V bit 503 * 504 * - if a context is enabled with the H bit set, the VP context 505 * information is retrieved from the NVP structure (“check out”) 506 * and stored back on a context pull (“check in”), the SW receives 507 * the same context pull information as on P9 508 * 509 * - the H bit cannot be changed while the V bit is set, i.e. a 510 * context cannot be set up in the TIMA and then be “pushed” into 511 * the NVP by changing the H bit while the context is enabled 512 */ 513 514 static void xive2_tctx_save_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 515 uint8_t nvp_blk, uint32_t nvp_idx, 516 uint8_t ring) 517 { 518 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 519 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 520 Xive2Nvp nvp; 521 uint8_t *regs = &tctx->regs[ring]; 522 523 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 524 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 525 nvp_blk, nvp_idx); 526 return; 527 } 528 529 if (!xive2_nvp_is_valid(&nvp)) { 530 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 531 nvp_blk, nvp_idx); 532 return; 533 } 534 535 if (!xive2_nvp_is_hw(&nvp)) { 536 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 537 nvp_blk, nvp_idx); 538 return; 539 } 540 541 if (!xive2_nvp_is_co(&nvp)) { 542 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not checkout\n", 543 nvp_blk, nvp_idx); 544 return; 545 } 546 547 if (xive_get_field32(NVP2_W1_CO_THRID_VALID, nvp.w1) && 548 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) { 549 qemu_log_mask(LOG_GUEST_ERROR, 550 "XIVE: NVP %x/%x invalid checkout Thread %x\n", 551 nvp_blk, nvp_idx, pir); 552 return; 553 } 554 555 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]); 556 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]); 557 if (nvp.w0 & NVP2_W0_L) { 558 /* 559 * Typically not used. If LSMFB is restored with 0, it will 560 * force a backlog rescan 561 */ 562 nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]); 563 } 564 if (nvp.w0 & NVP2_W0_G) { 565 nvp.w2 = xive_set_field32(NVP2_W2_LGS, nvp.w2, regs[TM_LGS]); 566 } 567 if (nvp.w0 & NVP2_W0_T) { 568 nvp.w2 = xive_set_field32(NVP2_W2_T, nvp.w2, regs[TM_T]); 569 } 570 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 571 572 nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0); 573 /* NVP2_W1_CO_THRID_VALID only set once */ 574 nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF); 575 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1); 576 } 577 578 static void xive2_cam_decode(uint32_t cam, uint8_t *nvp_blk, 579 uint32_t *nvp_idx, bool *valid, bool *hw) 580 { 581 *nvp_blk = xive2_nvp_blk(cam); 582 *nvp_idx = xive2_nvp_idx(cam); 583 *valid = !!(cam & TM2_W2_VALID); 584 *hw = !!(cam & TM2_W2_HW); 585 } 586 587 /* 588 * Encode the HW CAM line with 7bit or 8bit thread id. The thread id 589 * width and block id width is configurable at the IC level. 590 * 591 * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit) 592 * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit) 593 */ 594 static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 595 { 596 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 597 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 598 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 599 uint8_t blk = xive2_router_get_block_id(xrtr); 600 uint8_t tid_shift = 601 xive2_router_get_config(xrtr) & XIVE2_THREADID_8BITS ? 8 : 7; 602 uint8_t tid_mask = (1 << tid_shift) - 1; 603 604 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); 605 } 606 607 static void xive2_redistribute(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t ring) 608 { 609 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); 610 uint8_t nsr = sig_regs[TM_NSR]; 611 uint8_t pipr = sig_regs[TM_PIPR]; 612 uint8_t crowd = NVx_CROWD_LVL(nsr); 613 uint8_t group = NVx_GROUP_LVL(nsr); 614 uint8_t nvgc_blk, end_blk, nvp_blk; 615 uint32_t nvgc_idx, end_idx, nvp_idx; 616 Xive2Nvgc nvgc; 617 uint8_t prio_limit; 618 uint32_t cfg; 619 620 /* redistribution is only for group/crowd interrupts */ 621 if (!xive_nsr_indicates_group_exception(ring, nsr)) { 622 return; 623 } 624 625 /* Don't check return code since ring is expected to be invalidated */ 626 xive2_tctx_get_nvp_indexes(tctx, ring, &nvp_blk, &nvp_idx); 627 628 trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx); 629 630 trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx); 631 /* convert crowd/group to blk/idx */ 632 if (group > 0) { 633 nvgc_idx = (nvp_idx & (0xffffffff << group)) | 634 ((1 << (group - 1)) - 1); 635 } else { 636 nvgc_idx = nvp_idx; 637 } 638 639 if (crowd > 0) { 640 crowd = (crowd == 3) ? 4 : crowd; 641 nvgc_blk = (nvp_blk & (0xffffffff << crowd)) | 642 ((1 << (crowd - 1)) - 1); 643 } else { 644 nvgc_blk = nvp_blk; 645 } 646 647 /* Use blk/idx to retrieve the NVGC */ 648 if (xive2_router_get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, &nvgc)) { 649 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no %s %x/%x\n", 650 crowd ? "NVC" : "NVG", nvgc_blk, nvgc_idx); 651 return; 652 } 653 654 /* retrieve the END blk/idx from the NVGC */ 655 end_blk = xive_get_field32(NVGC2_W1_END_BLK, nvgc.w1); 656 end_idx = xive_get_field32(NVGC2_W1_END_IDX, nvgc.w1); 657 658 /* determine number of priorities being used */ 659 cfg = xive2_router_get_config(xrtr); 660 if (cfg & XIVE2_EN_VP_GRP_PRIORITY) { 661 prio_limit = 1 << GETFIELD(NVGC2_W1_PSIZE, nvgc.w1); 662 } else { 663 prio_limit = 1 << GETFIELD(XIVE2_VP_INT_PRIO, cfg); 664 } 665 666 /* add priority offset to end index */ 667 end_idx += pipr % prio_limit; 668 669 /* trigger the group END */ 670 xive2_router_end_notify(xrtr, end_blk, end_idx, 0, true); 671 672 /* clear interrupt indication for the context */ 673 sig_regs[TM_NSR] = 0; 674 sig_regs[TM_PIPR] = sig_regs[TM_CPPR]; 675 xive_tctx_reset_signal(tctx, ring); 676 } 677 678 static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, XiveTCTX *tctx, 679 hwaddr offset, unsigned size, uint8_t ring) 680 { 681 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 682 uint32_t target_ringw2 = xive_tctx_word2(&tctx->regs[ring]); 683 uint32_t cam = be32_to_cpu(target_ringw2); 684 uint8_t nvp_blk; 685 uint32_t nvp_idx; 686 uint8_t cur_ring; 687 bool valid; 688 bool do_save; 689 uint8_t nsr; 690 691 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &valid, &do_save); 692 693 if (xive2_tctx_get_nvp_indexes(tctx, ring, &nvp_blk, &nvp_idx)) { 694 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n", 695 nvp_blk, nvp_idx); 696 } 697 698 /* Invalidate CAM line of requested ring and all lower rings */ 699 for (cur_ring = TM_QW0_USER; cur_ring <= ring; 700 cur_ring += XIVE_TM_RING_SIZE) { 701 uint32_t ringw2 = xive_tctx_word2(&tctx->regs[cur_ring]); 702 uint32_t ringw2_new = xive_set_field32(TM2_QW1W2_VO, ringw2, 0); 703 bool is_valid = !!(xive_get_field32(TM2_QW1W2_VO, ringw2)); 704 uint8_t *sig_regs; 705 706 memcpy(&tctx->regs[cur_ring + TM_WORD2], &ringw2_new, 4); 707 708 /* Skip the rest for USER or invalid contexts */ 709 if ((cur_ring == TM_QW0_USER) || !is_valid) { 710 continue; 711 } 712 713 /* Active group/crowd interrupts need to be redistributed */ 714 sig_regs = xive_tctx_signal_regs(tctx, ring); 715 nsr = sig_regs[TM_NSR]; 716 if (xive_nsr_indicates_group_exception(cur_ring, nsr)) { 717 /* Ensure ring matches NSR (for HV NSR POOL vs PHYS rings) */ 718 if (cur_ring == xive_nsr_exception_ring(cur_ring, nsr)) { 719 xive2_redistribute(xrtr, tctx, cur_ring); 720 } 721 } 722 } 723 724 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { 725 xive2_tctx_save_ctx(xrtr, tctx, nvp_blk, nvp_idx, ring); 726 } 727 728 /* 729 * Lower external interrupt line of requested ring and below except for 730 * USER, which doesn't exist. 731 */ 732 for (cur_ring = TM_QW1_OS; cur_ring <= ring; 733 cur_ring += XIVE_TM_RING_SIZE) { 734 xive_tctx_reset_signal(tctx, cur_ring); 735 } 736 return target_ringw2; 737 } 738 739 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 740 hwaddr offset, unsigned size) 741 { 742 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW1_OS); 743 } 744 745 uint64_t xive2_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 746 hwaddr offset, unsigned size) 747 { 748 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW2_HV_POOL); 749 } 750 751 uint64_t xive2_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, 752 hwaddr offset, unsigned size) 753 { 754 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW3_HV_PHYS); 755 } 756 757 #define REPORT_LINE_GEN1_SIZE 16 758 759 static void xive2_tm_report_line_gen1(XiveTCTX *tctx, uint8_t *data, 760 uint8_t size) 761 { 762 uint8_t *regs = tctx->regs; 763 764 g_assert(size == REPORT_LINE_GEN1_SIZE); 765 memset(data, 0, size); 766 /* 767 * See xive architecture for description of what is saved. It is 768 * hand-picked information to fit in 16 bytes. 769 */ 770 data[0x0] = regs[TM_QW3_HV_PHYS + TM_NSR]; 771 data[0x1] = regs[TM_QW3_HV_PHYS + TM_CPPR]; 772 data[0x2] = regs[TM_QW3_HV_PHYS + TM_IPB]; 773 data[0x3] = regs[TM_QW2_HV_POOL + TM_IPB]; 774 data[0x4] = regs[TM_QW1_OS + TM_ACK_CNT]; 775 data[0x5] = regs[TM_QW3_HV_PHYS + TM_LGS]; 776 data[0x6] = 0xFF; 777 data[0x7] = regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x80; 778 data[0x7] |= (regs[TM_QW2_HV_POOL + TM_WORD2] & 0x80) >> 1; 779 data[0x7] |= (regs[TM_QW1_OS + TM_WORD2] & 0x80) >> 2; 780 data[0x7] |= (regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x3); 781 data[0x8] = regs[TM_QW1_OS + TM_NSR]; 782 data[0x9] = regs[TM_QW1_OS + TM_CPPR]; 783 data[0xA] = regs[TM_QW1_OS + TM_IPB]; 784 data[0xB] = regs[TM_QW1_OS + TM_LGS]; 785 if (regs[TM_QW0_USER + TM_WORD2] & 0x80) { 786 /* 787 * Logical server extension, except VU bit replaced by EB bit 788 * from NSR 789 */ 790 data[0xC] = regs[TM_QW0_USER + TM_WORD2]; 791 data[0xC] &= ~0x80; 792 data[0xC] |= regs[TM_QW0_USER + TM_NSR] & 0x80; 793 data[0xD] = regs[TM_QW0_USER + TM_WORD2 + 1]; 794 data[0xE] = regs[TM_QW0_USER + TM_WORD2 + 2]; 795 data[0xF] = regs[TM_QW0_USER + TM_WORD2 + 3]; 796 } 797 } 798 799 static void xive2_tm_pull_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 800 hwaddr offset, uint64_t value, 801 unsigned size, uint8_t ring) 802 { 803 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 804 uint32_t hw_cam, nvp_idx, xive2_cfg, reserved; 805 uint8_t nvp_blk; 806 Xive2Nvp nvp; 807 uint64_t phys_addr; 808 MemTxResult result; 809 810 hw_cam = xive2_tctx_hw_cam_line(xptr, tctx); 811 nvp_blk = xive2_nvp_blk(hw_cam); 812 nvp_idx = xive2_nvp_idx(hw_cam); 813 814 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 815 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 816 nvp_blk, nvp_idx); 817 return; 818 } 819 820 if (!xive2_nvp_is_valid(&nvp)) { 821 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 822 nvp_blk, nvp_idx); 823 return; 824 } 825 826 xive2_cfg = xive2_router_get_config(xrtr); 827 828 phys_addr = xive2_nvp_reporting_addr(&nvp) + 0x80; /* odd line */ 829 if (xive2_cfg & XIVE2_GEN1_TIMA_OS) { 830 uint8_t pull_ctxt[REPORT_LINE_GEN1_SIZE]; 831 832 xive2_tm_report_line_gen1(tctx, pull_ctxt, REPORT_LINE_GEN1_SIZE); 833 result = dma_memory_write(&address_space_memory, phys_addr, 834 pull_ctxt, REPORT_LINE_GEN1_SIZE, 835 MEMTXATTRS_UNSPECIFIED); 836 assert(result == MEMTX_OK); 837 } else { 838 result = dma_memory_write(&address_space_memory, phys_addr, 839 &tctx->regs, sizeof(tctx->regs), 840 MEMTXATTRS_UNSPECIFIED); 841 assert(result == MEMTX_OK); 842 reserved = 0xFFFFFFFF; 843 result = dma_memory_write(&address_space_memory, phys_addr + 12, 844 &reserved, sizeof(reserved), 845 MEMTXATTRS_UNSPECIFIED); 846 assert(result == MEMTX_OK); 847 } 848 849 /* the rest is similar to pull context to registers */ 850 xive2_tm_pull_ctx(xptr, tctx, offset, size, ring); 851 } 852 853 void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 854 hwaddr offset, uint64_t value, unsigned size) 855 { 856 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW1_OS); 857 } 858 859 860 void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 861 hwaddr offset, uint64_t value, unsigned size) 862 { 863 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW3_HV_PHYS); 864 } 865 866 static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 867 uint8_t nvp_blk, uint32_t nvp_idx, 868 Xive2Nvp *nvp) 869 { 870 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 871 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 872 uint8_t cppr; 873 874 if (!xive2_nvp_is_hw(nvp)) { 875 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 876 nvp_blk, nvp_idx); 877 return 0; 878 } 879 880 cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2); 881 nvp->w2 = xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0); 882 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2); 883 884 tctx->regs[TM_QW1_OS + TM_CPPR] = cppr; 885 tctx->regs[TM_QW1_OS + TM_LSMFB] = xive_get_field32(NVP2_W2_LSMFB, nvp->w2); 886 tctx->regs[TM_QW1_OS + TM_LGS] = xive_get_field32(NVP2_W2_LGS, nvp->w2); 887 tctx->regs[TM_QW1_OS + TM_T] = xive_get_field32(NVP2_W2_T, nvp->w2); 888 889 nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1); 890 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1); 891 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir); 892 893 /* 894 * Checkout privilege: 0:OS, 1:Pool, 2:Hard 895 * 896 * TODO: we only support OS push/pull 897 */ 898 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0); 899 900 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 1); 901 902 /* return restored CPPR to generate a CPU exception if needed */ 903 return cppr; 904 } 905 906 static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, 907 uint8_t nvp_blk, uint32_t nvp_idx, 908 bool do_restore) 909 { 910 XivePresenter *xptr = XIVE_PRESENTER(xrtr); 911 uint8_t ipb; 912 uint8_t backlog_level; 913 uint8_t group_level; 914 uint8_t first_group; 915 uint8_t backlog_prio; 916 uint8_t group_prio; 917 uint8_t *regs = &tctx->regs[TM_QW1_OS]; 918 Xive2Nvp nvp; 919 920 /* 921 * Grab the associated thread interrupt context registers in the 922 * associated NVP 923 */ 924 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 925 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 926 nvp_blk, nvp_idx); 927 return; 928 } 929 930 if (!xive2_nvp_is_valid(&nvp)) { 931 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 932 nvp_blk, nvp_idx); 933 return; 934 } 935 936 /* Automatically restore thread context registers */ 937 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && 938 do_restore) { 939 xive2_tctx_restore_os_ctx(xrtr, tctx, nvp_blk, nvp_idx, &nvp); 940 } 941 942 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2); 943 if (ipb) { 944 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0); 945 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 946 } 947 /* IPB bits in the backlog are merged with the TIMA IPB bits */ 948 regs[TM_IPB] |= ipb; 949 backlog_prio = xive_ipb_to_pipr(regs[TM_IPB]); 950 backlog_level = 0; 951 952 first_group = xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0); 953 if (first_group && regs[TM_LSMFB] < backlog_prio) { 954 group_prio = xive2_presenter_backlog_scan(xptr, nvp_blk, nvp_idx, 955 first_group, &group_level); 956 regs[TM_LSMFB] = group_prio; 957 if (regs[TM_LGS] && group_prio < backlog_prio && 958 group_prio < regs[TM_CPPR]) { 959 960 /* VP can take a group interrupt */ 961 xive2_presenter_backlog_decr(xptr, nvp_blk, nvp_idx, 962 group_prio, group_level); 963 backlog_prio = group_prio; 964 backlog_level = group_level; 965 } 966 } 967 968 /* 969 * Compute the PIPR based on the restored state. 970 * It will raise the External interrupt signal if needed. 971 */ 972 xive_tctx_pipr_update(tctx, TM_QW1_OS, backlog_prio, backlog_level); 973 } 974 975 /* 976 * Updating the OS CAM line can trigger a resend of interrupt 977 */ 978 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 979 hwaddr offset, uint64_t value, unsigned size) 980 { 981 uint32_t cam; 982 uint32_t qw1w2; 983 uint64_t qw1dw1; 984 uint8_t nvp_blk; 985 uint32_t nvp_idx; 986 bool vo; 987 bool do_restore; 988 989 /* First update the thead context */ 990 switch (size) { 991 case 4: 992 cam = value; 993 qw1w2 = cpu_to_be32(cam); 994 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 995 break; 996 case 8: 997 cam = value >> 32; 998 qw1dw1 = cpu_to_be64(value); 999 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1dw1, 8); 1000 break; 1001 default: 1002 g_assert_not_reached(); 1003 } 1004 1005 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore); 1006 1007 /* Check the interrupt pending bits */ 1008 if (vo) { 1009 xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx, 1010 do_restore); 1011 } 1012 } 1013 1014 /* returns -1 if ring is invalid, but still populates block and index */ 1015 static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring, 1016 uint8_t *nvp_blk, uint32_t *nvp_idx) 1017 { 1018 uint32_t w2; 1019 uint32_t cam = 0; 1020 int rc = 0; 1021 1022 w2 = xive_tctx_word2(&tctx->regs[ring]); 1023 switch (ring) { 1024 case TM_QW1_OS: 1025 if (!(be32_to_cpu(w2) & TM2_QW1W2_VO)) { 1026 rc = -1; 1027 } 1028 cam = xive_get_field32(TM2_QW1W2_OS_CAM, w2); 1029 break; 1030 case TM_QW2_HV_POOL: 1031 if (!(be32_to_cpu(w2) & TM2_QW2W2_VP)) { 1032 rc = -1; 1033 } 1034 cam = xive_get_field32(TM2_QW2W2_POOL_CAM, w2); 1035 break; 1036 case TM_QW3_HV_PHYS: 1037 if (!(be32_to_cpu(w2) & TM2_QW3W2_VT)) { 1038 rc = -1; 1039 } 1040 cam = xive2_tctx_hw_cam_line(tctx->xptr, tctx); 1041 break; 1042 default: 1043 rc = -1; 1044 } 1045 *nvp_blk = xive2_nvp_blk(cam); 1046 *nvp_idx = xive2_nvp_idx(cam); 1047 return rc; 1048 } 1049 1050 static void xive2_tctx_accept_el(XivePresenter *xptr, XiveTCTX *tctx, 1051 uint8_t ring, uint8_t cl_ring) 1052 { 1053 uint64_t rd; 1054 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 1055 uint32_t nvp_idx, xive2_cfg; 1056 uint8_t nvp_blk; 1057 Xive2Nvp nvp; 1058 uint64_t phys_addr; 1059 uint8_t OGen = 0; 1060 1061 xive2_tctx_get_nvp_indexes(tctx, cl_ring, &nvp_blk, &nvp_idx); 1062 1063 if (xive2_router_get_nvp(xrtr, (uint8_t)nvp_blk, nvp_idx, &nvp)) { 1064 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 1065 nvp_blk, nvp_idx); 1066 return; 1067 } 1068 1069 if (!xive2_nvp_is_valid(&nvp)) { 1070 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 1071 nvp_blk, nvp_idx); 1072 return; 1073 } 1074 1075 1076 rd = xive_tctx_accept(tctx, ring); 1077 1078 if (ring == TM_QW1_OS) { 1079 OGen = tctx->regs[ring + TM_OGEN]; 1080 } 1081 xive2_cfg = xive2_router_get_config(xrtr); 1082 phys_addr = xive2_nvp_reporting_addr(&nvp); 1083 uint8_t report_data[REPORT_LINE_GEN1_SIZE]; 1084 memset(report_data, 0xff, sizeof(report_data)); 1085 if ((OGen == 1) || (xive2_cfg & XIVE2_GEN1_TIMA_OS)) { 1086 report_data[8] = (rd >> 8) & 0xff; 1087 report_data[9] = rd & 0xff; 1088 } else { 1089 report_data[0] = (rd >> 8) & 0xff; 1090 report_data[1] = rd & 0xff; 1091 } 1092 cpu_physical_memory_write(phys_addr, report_data, REPORT_LINE_GEN1_SIZE); 1093 } 1094 1095 void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTCTX *tctx, 1096 hwaddr offset, uint64_t value, unsigned size) 1097 { 1098 xive2_tctx_accept_el(xptr, tctx, TM_QW1_OS, TM_QW1_OS); 1099 } 1100 1101 /* NOTE: CPPR only exists for TM_QW1_OS and TM_QW3_HV_PHYS */ 1102 static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 1103 { 1104 uint8_t *sig_regs = &tctx->regs[ring]; 1105 Xive2Router *xrtr = XIVE2_ROUTER(tctx->xptr); 1106 uint8_t old_cppr, backlog_prio, first_group, group_level; 1107 uint8_t pipr_min, lsmfb_min, ring_min; 1108 bool group_enabled; 1109 uint8_t nvp_blk; 1110 uint32_t nvp_idx; 1111 Xive2Nvp nvp; 1112 int rc; 1113 uint8_t nsr = sig_regs[TM_NSR]; 1114 1115 g_assert(ring == TM_QW1_OS || ring == TM_QW3_HV_PHYS); 1116 1117 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] == 0); 1118 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0); 1119 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); 1120 1121 /* XXX: should show pool IPB for PHYS ring */ 1122 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, 1123 sig_regs[TM_IPB], sig_regs[TM_PIPR], 1124 cppr, nsr); 1125 1126 if (cppr > XIVE_PRIORITY_MAX) { 1127 cppr = 0xff; 1128 } 1129 1130 old_cppr = sig_regs[TM_CPPR]; 1131 sig_regs[TM_CPPR] = cppr; 1132 1133 /* Handle increased CPPR priority (lower value) */ 1134 if (cppr < old_cppr) { 1135 if (cppr <= sig_regs[TM_PIPR]) { 1136 /* CPPR lowered below PIPR, must un-present interrupt */ 1137 if (xive_nsr_indicates_exception(ring, nsr)) { 1138 if (xive_nsr_indicates_group_exception(ring, nsr)) { 1139 /* redistribute precluded active grp interrupt */ 1140 xive2_redistribute(xrtr, tctx, 1141 xive_nsr_exception_ring(ring, nsr)); 1142 return; 1143 } 1144 } 1145 1146 /* interrupt is VP directed, pending in IPB */ 1147 sig_regs[TM_PIPR] = cppr; 1148 xive_tctx_notify(tctx, ring, 0); /* Ensure interrupt is cleared */ 1149 return; 1150 } else { 1151 /* CPPR was lowered, but still above PIPR. No action needed. */ 1152 return; 1153 } 1154 } 1155 1156 /* CPPR didn't change, nothing needs to be done */ 1157 if (cppr == old_cppr) { 1158 return; 1159 } 1160 1161 /* CPPR priority decreased (higher value) */ 1162 1163 /* 1164 * Recompute the PIPR based on local pending interrupts. It will 1165 * be adjusted below if needed in case of pending group interrupts. 1166 */ 1167 again: 1168 pipr_min = xive_ipb_to_pipr(sig_regs[TM_IPB]); 1169 group_enabled = !!sig_regs[TM_LGS]; 1170 lsmfb_min = group_enabled ? sig_regs[TM_LSMFB] : 0xff; 1171 ring_min = ring; 1172 group_level = 0; 1173 1174 /* PHYS updates also depend on POOL values */ 1175 if (ring == TM_QW3_HV_PHYS) { 1176 uint8_t *pool_regs = &tctx->regs[TM_QW2_HV_POOL]; 1177 1178 /* POOL values only matter if POOL ctx is valid */ 1179 if (pool_regs[TM_WORD2] & 0x80) { 1180 uint8_t pool_pipr = xive_ipb_to_pipr(pool_regs[TM_IPB]); 1181 uint8_t pool_lsmfb = pool_regs[TM_LSMFB]; 1182 1183 /* 1184 * Determine highest priority interrupt and 1185 * remember which ring has it. 1186 */ 1187 if (pool_pipr < pipr_min) { 1188 pipr_min = pool_pipr; 1189 if (pool_pipr < lsmfb_min) { 1190 ring_min = TM_QW2_HV_POOL; 1191 } 1192 } 1193 1194 /* Values needed for group priority calculation */ 1195 if (pool_regs[TM_LGS] && (pool_lsmfb < lsmfb_min)) { 1196 group_enabled = true; 1197 lsmfb_min = pool_lsmfb; 1198 if (lsmfb_min < pipr_min) { 1199 ring_min = TM_QW2_HV_POOL; 1200 } 1201 } 1202 } 1203 } 1204 1205 rc = xive2_tctx_get_nvp_indexes(tctx, ring_min, &nvp_blk, &nvp_idx); 1206 if (rc) { 1207 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: set CPPR on invalid context\n"); 1208 return; 1209 } 1210 1211 if (group_enabled && 1212 lsmfb_min < cppr && 1213 lsmfb_min < pipr_min) { 1214 /* 1215 * Thread has seen a group interrupt with a higher priority 1216 * than the new cppr or pending local interrupt. Check the 1217 * backlog 1218 */ 1219 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 1220 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 1221 nvp_blk, nvp_idx); 1222 return; 1223 } 1224 1225 if (!xive2_nvp_is_valid(&nvp)) { 1226 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 1227 nvp_blk, nvp_idx); 1228 return; 1229 } 1230 1231 first_group = xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0); 1232 if (!first_group) { 1233 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 1234 nvp_blk, nvp_idx); 1235 return; 1236 } 1237 1238 backlog_prio = xive2_presenter_backlog_scan(tctx->xptr, 1239 nvp_blk, nvp_idx, 1240 first_group, &group_level); 1241 tctx->regs[ring_min + TM_LSMFB] = backlog_prio; 1242 if (backlog_prio != lsmfb_min) { 1243 /* 1244 * If the group backlog scan finds a less favored or no interrupt, 1245 * then re-do the processing which may turn up a more favored 1246 * interrupt from IPB or the other pool. Backlog should not 1247 * find a priority < LSMFB. 1248 */ 1249 g_assert(backlog_prio >= lsmfb_min); 1250 goto again; 1251 } 1252 1253 xive2_presenter_backlog_decr(tctx->xptr, nvp_blk, nvp_idx, 1254 backlog_prio, group_level); 1255 pipr_min = backlog_prio; 1256 } 1257 1258 /* PIPR should not be set to a value greater than CPPR */ 1259 sig_regs[TM_PIPR] = (pipr_min > cppr) ? cppr : pipr_min; 1260 1261 /* CPPR has changed, check if we need to raise a pending exception */ 1262 xive_tctx_notify(tctx, ring_min, group_level); 1263 } 1264 1265 void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 1266 hwaddr offset, uint64_t value, unsigned size) 1267 { 1268 xive2_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 1269 } 1270 1271 void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 1272 hwaddr offset, uint64_t value, unsigned size) 1273 { 1274 xive2_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 1275 } 1276 1277 static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t target) 1278 { 1279 uint8_t *regs = &tctx->regs[ring]; 1280 1281 regs[TM_T] = target; 1282 } 1283 1284 void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, 1285 hwaddr offset, uint64_t value, unsigned size) 1286 { 1287 xive2_tctx_set_target(tctx, TM_QW3_HV_PHYS, value & 0xff); 1288 } 1289 1290 /* 1291 * XIVE Router (aka. Virtualization Controller or IVRE) 1292 */ 1293 1294 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1295 Xive2Eas *eas) 1296 { 1297 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1298 1299 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1300 } 1301 1302 static 1303 int xive2_router_get_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1304 uint8_t *pq) 1305 { 1306 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1307 1308 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); 1309 } 1310 1311 static 1312 int xive2_router_set_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1313 uint8_t *pq) 1314 { 1315 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1316 1317 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); 1318 } 1319 1320 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 1321 Xive2End *end) 1322 { 1323 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1324 1325 return xrc->get_end(xrtr, end_blk, end_idx, end); 1326 } 1327 1328 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 1329 Xive2End *end, uint8_t word_number) 1330 { 1331 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1332 1333 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1334 } 1335 1336 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 1337 Xive2Nvp *nvp) 1338 { 1339 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1340 1341 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp); 1342 } 1343 1344 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 1345 Xive2Nvp *nvp, uint8_t word_number) 1346 { 1347 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1348 1349 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number); 1350 } 1351 1352 int xive2_router_get_nvgc(Xive2Router *xrtr, bool crowd, 1353 uint8_t nvgc_blk, uint32_t nvgc_idx, 1354 Xive2Nvgc *nvgc) 1355 { 1356 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1357 1358 return xrc->get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); 1359 } 1360 1361 int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd, 1362 uint8_t nvgc_blk, uint32_t nvgc_idx, 1363 Xive2Nvgc *nvgc) 1364 { 1365 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1366 1367 return xrc->write_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); 1368 } 1369 1370 static bool xive2_vp_match_mask(uint32_t cam1, uint32_t cam2, 1371 uint32_t vp_mask) 1372 { 1373 return (cam1 & vp_mask) == (cam2 & vp_mask); 1374 } 1375 1376 static uint8_t xive2_get_vp_block_mask(uint32_t nvt_blk, bool crowd) 1377 { 1378 uint8_t block_mask = 0b1111; 1379 1380 /* 3 supported crowd sizes: 2, 4, 16 */ 1381 if (crowd) { 1382 uint32_t size = xive_get_vpgroup_size(nvt_blk); 1383 1384 if (size != 2 && size != 4 && size != 16) { 1385 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid crowd size of %d", 1386 size); 1387 return block_mask; 1388 } 1389 block_mask &= ~(size - 1); 1390 } 1391 return block_mask; 1392 } 1393 1394 static uint32_t xive2_get_vp_index_mask(uint32_t nvt_index, bool cam_ignore) 1395 { 1396 uint32_t index_mask = 0xFFFFFF; /* 24 bits */ 1397 1398 if (cam_ignore) { 1399 uint32_t size = xive_get_vpgroup_size(nvt_index); 1400 1401 if (size < 2) { 1402 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid group size of %d", 1403 size); 1404 return index_mask; 1405 } 1406 index_mask &= ~(size - 1); 1407 } 1408 return index_mask; 1409 } 1410 1411 /* 1412 * The thread context register words are in big-endian format. 1413 */ 1414 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1415 uint8_t format, 1416 uint8_t nvt_blk, uint32_t nvt_idx, 1417 bool crowd, bool cam_ignore, 1418 uint32_t logic_serv) 1419 { 1420 uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx); 1421 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1422 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1423 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1424 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1425 1426 uint32_t index_mask, vp_mask; 1427 uint8_t block_mask; 1428 1429 if (format == 0) { 1430 /* 1431 * i=0: Specific NVT notification 1432 * i=1: VP-group notification (bits ignored at the end of the 1433 * NVT identifier) 1434 */ 1435 block_mask = xive2_get_vp_block_mask(nvt_blk, crowd); 1436 index_mask = xive2_get_vp_index_mask(nvt_idx, cam_ignore); 1437 vp_mask = xive2_nvp_cam_line(block_mask, index_mask); 1438 1439 /* For VP-group notifications, threads with LGS=0 are excluded */ 1440 1441 /* PHYS ring */ 1442 if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) && 1443 !(cam_ignore && tctx->regs[TM_QW3_HV_PHYS + TM_LGS] == 0) && 1444 xive2_vp_match_mask(cam, 1445 xive2_tctx_hw_cam_line(xptr, tctx), 1446 vp_mask)) { 1447 return TM_QW3_HV_PHYS; 1448 } 1449 1450 /* HV POOL ring */ 1451 if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) && 1452 !(cam_ignore && tctx->regs[TM_QW2_HV_POOL + TM_LGS] == 0) && 1453 xive2_vp_match_mask(cam, 1454 xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2), 1455 vp_mask)) { 1456 return TM_QW2_HV_POOL; 1457 } 1458 1459 /* OS ring */ 1460 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 1461 !(cam_ignore && tctx->regs[TM_QW1_OS + TM_LGS] == 0) && 1462 xive2_vp_match_mask(cam, 1463 xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2), 1464 vp_mask)) { 1465 return TM_QW1_OS; 1466 } 1467 } else { 1468 /* F=1 : User level Event-Based Branch (EBB) notification */ 1469 1470 /* FIXME: what if cam_ignore and LGS = 0 ? */ 1471 /* USER ring */ 1472 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 1473 (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) && 1474 (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) && 1475 (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) { 1476 return TM_QW0_USER; 1477 } 1478 } 1479 return -1; 1480 } 1481 1482 bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority) 1483 { 1484 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); 1485 1486 /* 1487 * The xive2_presenter_tctx_match() above tells if there's a match 1488 * but for VP-group notification, we still need to look at the 1489 * priority to know if the thread can take the interrupt now or if 1490 * it is precluded. 1491 */ 1492 if (priority < sig_regs[TM_PIPR]) { 1493 return false; 1494 } 1495 return true; 1496 } 1497 1498 void xive2_tm_set_lsmfb(XiveTCTX *tctx, int ring, uint8_t priority) 1499 { 1500 uint8_t *regs = &tctx->regs[ring]; 1501 1502 /* 1503 * Called by the router during a VP-group notification when the 1504 * thread matches but can't take the interrupt because it's 1505 * already running at a more favored priority. It then stores the 1506 * new interrupt priority in the LSMFB field. 1507 */ 1508 regs[TM_LSMFB] = priority; 1509 } 1510 1511 static void xive2_router_realize(DeviceState *dev, Error **errp) 1512 { 1513 Xive2Router *xrtr = XIVE2_ROUTER(dev); 1514 1515 assert(xrtr->xfb); 1516 } 1517 1518 /* 1519 * Notification using the END ESe/ESn bit (Event State Buffer for 1520 * escalation and notification). Profide further coalescing in the 1521 * Router. 1522 */ 1523 static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk, 1524 uint32_t end_idx, Xive2End *end, 1525 uint32_t end_esmask) 1526 { 1527 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1528 bool notify = xive_esb_trigger(&pq); 1529 1530 if (pq != xive_get_field32(end_esmask, end->w1)) { 1531 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1532 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1); 1533 } 1534 1535 /* ESe/n[Q]=1 : end of notification */ 1536 return notify; 1537 } 1538 1539 /* 1540 * An END trigger can come from an event trigger (IPI or HW) or from 1541 * another chip. We don't model the PowerBus but the END trigger 1542 * message has the same parameters than in the function below. 1543 */ 1544 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 1545 uint32_t end_idx, uint32_t end_data, 1546 bool redistribute) 1547 { 1548 Xive2End end; 1549 uint8_t priority; 1550 uint8_t format; 1551 XiveTCTXMatch match; 1552 bool crowd, cam_ignore; 1553 uint8_t nvx_blk; 1554 uint32_t nvx_idx; 1555 1556 /* END cache lookup */ 1557 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) { 1558 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1559 end_idx); 1560 return; 1561 } 1562 1563 if (!xive2_end_is_valid(&end)) { 1564 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1565 end_blk, end_idx); 1566 return; 1567 } 1568 1569 if (xive2_end_is_crowd(&end) && !xive2_end_is_ignore(&end)) { 1570 qemu_log_mask(LOG_GUEST_ERROR, 1571 "XIVE: invalid END, 'crowd' bit requires 'ignore' bit\n"); 1572 return; 1573 } 1574 1575 if (!redistribute && xive2_end_is_enqueue(&end)) { 1576 trace_xive_end_enqueue(end_blk, end_idx, end_data); 1577 xive2_end_enqueue(&end, end_data); 1578 /* Enqueuing event data modifies the EQ toggle and index */ 1579 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1580 } 1581 1582 /* 1583 * When the END is silent, we skip the notification part. 1584 */ 1585 if (xive2_end_is_silent_escalation(&end)) { 1586 goto do_escalation; 1587 } 1588 1589 /* 1590 * The W7 format depends on the F bit in W6. It defines the type 1591 * of the notification : 1592 * 1593 * F=0 : single or multiple NVP notification 1594 * F=1 : User level Event-Based Branch (EBB) notification, no 1595 * priority 1596 */ 1597 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6); 1598 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7); 1599 1600 /* The END is masked */ 1601 if (format == 0 && priority == 0xff) { 1602 return; 1603 } 1604 1605 /* 1606 * Check the END ESn (Event State Buffer for notification) for 1607 * even further coalescing in the Router 1608 */ 1609 if (!xive2_end_is_notify(&end)) { 1610 /* ESn[Q]=1 : end of notification */ 1611 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 1612 &end, END2_W1_ESn)) { 1613 return; 1614 } 1615 } 1616 1617 /* 1618 * Follows IVPE notification 1619 */ 1620 nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6); 1621 nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6); 1622 crowd = xive2_end_is_crowd(&end); 1623 cam_ignore = xive2_end_is_ignore(&end); 1624 1625 /* TODO: Auto EOI. */ 1626 if (xive_presenter_match(xrtr->xfb, format, nvx_blk, nvx_idx, 1627 crowd, cam_ignore, priority, 1628 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7), 1629 &match)) { 1630 XiveTCTX *tctx = match.tctx; 1631 uint8_t ring = match.ring; 1632 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); 1633 uint8_t nsr = sig_regs[TM_NSR]; 1634 uint8_t group_level; 1635 1636 if (priority < sig_regs[TM_PIPR] && 1637 xive_nsr_indicates_group_exception(ring, nsr)) { 1638 xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, nsr)); 1639 } 1640 1641 group_level = xive_get_group_level(crowd, cam_ignore, nvx_blk, nvx_idx); 1642 trace_xive_presenter_notify(nvx_blk, nvx_idx, ring, group_level); 1643 xive_tctx_pipr_present(tctx, ring, priority, group_level); 1644 return; 1645 } 1646 1647 /* 1648 * If no matching NVP is dispatched on a HW thread : 1649 * - specific VP: update the NVP structure if backlog is activated 1650 * - VP-group: update the backlog counter for that priority in the NVG 1651 */ 1652 if (xive2_end_is_backlog(&end)) { 1653 1654 if (format == 1) { 1655 qemu_log_mask(LOG_GUEST_ERROR, 1656 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1657 end_blk, end_idx); 1658 return; 1659 } 1660 1661 if (!cam_ignore) { 1662 uint8_t ipb; 1663 Xive2Nvp nvp; 1664 1665 /* NVP cache lookup */ 1666 if (xive2_router_get_nvp(xrtr, nvx_blk, nvx_idx, &nvp)) { 1667 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n", 1668 nvx_blk, nvx_idx); 1669 return; 1670 } 1671 1672 if (!xive2_nvp_is_valid(&nvp)) { 1673 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n", 1674 nvx_blk, nvx_idx); 1675 return; 1676 } 1677 1678 /* 1679 * Record the IPB in the associated NVP structure for later 1680 * use. The presenter will resend the interrupt when the vCPU 1681 * is dispatched again on a HW thread. 1682 */ 1683 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) | 1684 xive_priority_to_ipb(priority); 1685 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 1686 xive2_router_write_nvp(xrtr, nvx_blk, nvx_idx, &nvp, 2); 1687 } else { 1688 Xive2Nvgc nvgc; 1689 uint32_t backlog; 1690 1691 /* 1692 * For groups and crowds, the per-priority backlog 1693 * counters are stored in the NVG/NVC structures 1694 */ 1695 if (xive2_router_get_nvgc(xrtr, crowd, 1696 nvx_blk, nvx_idx, &nvgc)) { 1697 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no %s %x/%x\n", 1698 crowd ? "NVC" : "NVG", nvx_blk, nvx_idx); 1699 return; 1700 } 1701 1702 if (!xive2_nvgc_is_valid(&nvgc)) { 1703 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVG %x/%x is invalid\n", 1704 nvx_blk, nvx_idx); 1705 return; 1706 } 1707 1708 /* 1709 * Increment the backlog counter for that priority. 1710 * We only call broadcast the first time the counter is 1711 * incremented. broadcast will set the LSMFB field of the TIMA of 1712 * relevant threads so that they know an interrupt is pending. 1713 */ 1714 backlog = xive2_nvgc_get_backlog(&nvgc, priority) + 1; 1715 xive2_nvgc_set_backlog(&nvgc, priority, backlog); 1716 xive2_router_write_nvgc(xrtr, crowd, nvx_blk, nvx_idx, &nvgc); 1717 1718 if (backlog == 1) { 1719 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xrtr->xfb); 1720 xfc->broadcast(xrtr->xfb, nvx_blk, nvx_idx, 1721 crowd, cam_ignore, priority); 1722 1723 if (!xive2_end_is_precluded_escalation(&end)) { 1724 /* 1725 * The interrupt will be picked up when the 1726 * matching thread lowers its priority level 1727 */ 1728 return; 1729 } 1730 } 1731 } 1732 } 1733 1734 do_escalation: 1735 /* 1736 * If activated, escalate notification using the ESe PQ bits and 1737 * the EAS in w4-5 1738 */ 1739 if (!xive2_end_is_escalate(&end)) { 1740 return; 1741 } 1742 1743 /* 1744 * Check the END ESe (Event State Buffer for escalation) for even 1745 * further coalescing in the Router 1746 */ 1747 if (!xive2_end_is_uncond_escalation(&end)) { 1748 /* ESe[Q]=1 : end of escalation notification */ 1749 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 1750 &end, END2_W1_ESe)) { 1751 return; 1752 } 1753 } 1754 1755 if (xive2_end_is_escalate_end(&end)) { 1756 /* 1757 * Perform END Adaptive escalation processing 1758 * The END trigger becomes an Escalation trigger 1759 */ 1760 uint8_t esc_blk = xive_get_field32(END2_W4_END_BLOCK, end.w4); 1761 uint32_t esc_idx = xive_get_field32(END2_W4_ESC_END_INDEX, end.w4); 1762 uint32_t esc_data = xive_get_field32(END2_W5_ESC_END_DATA, end.w5); 1763 trace_xive_escalate_end(end_blk, end_idx, esc_blk, esc_idx, esc_data); 1764 xive2_router_end_notify(xrtr, esc_blk, esc_idx, esc_data, false); 1765 } /* end END adaptive escalation */ 1766 1767 else { 1768 uint32_t lisn; /* Logical Interrupt Source Number */ 1769 1770 /* 1771 * Perform ESB escalation processing 1772 * E[N] == 1 --> N 1773 * Req[Block] <- E[ESB_Block] 1774 * Req[Index] <- E[ESB_Index] 1775 * Req[Offset] <- 0x000 1776 * Execute <ESB Store> Req command 1777 */ 1778 lisn = XIVE_EAS(xive_get_field32(END2_W4_END_BLOCK, end.w4), 1779 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4)); 1780 1781 trace_xive_escalate_esb(end_blk, end_idx, lisn); 1782 xive2_notify(xrtr, lisn, true /* pq_checked */); 1783 } 1784 1785 return; 1786 } 1787 1788 void xive2_notify(Xive2Router *xrtr , uint32_t lisn, bool pq_checked) 1789 { 1790 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1791 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1792 Xive2Eas eas; 1793 1794 /* EAS cache lookup */ 1795 if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1796 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1797 return; 1798 } 1799 1800 if (!pq_checked) { 1801 bool notify; 1802 uint8_t pq; 1803 1804 /* PQ cache lookup */ 1805 if (xive2_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) { 1806 /* Set FIR */ 1807 g_assert_not_reached(); 1808 } 1809 1810 notify = xive_esb_trigger(&pq); 1811 1812 if (xive2_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) { 1813 /* Set FIR */ 1814 g_assert_not_reached(); 1815 } 1816 1817 if (!notify) { 1818 return; 1819 } 1820 } 1821 1822 if (!xive2_eas_is_valid(&eas)) { 1823 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn); 1824 return; 1825 } 1826 1827 if (xive2_eas_is_masked(&eas)) { 1828 /* Notification completed */ 1829 return; 1830 } 1831 1832 /* TODO: add support for EAS resume */ 1833 if (xive2_eas_is_resume(&eas)) { 1834 qemu_log_mask(LOG_UNIMP, 1835 "XIVE: EAS resume processing unimplemented - LISN %x\n", 1836 lisn); 1837 return; 1838 } 1839 1840 /* 1841 * The event trigger becomes an END trigger 1842 */ 1843 xive2_router_end_notify(xrtr, 1844 xive_get_field64(EAS2_END_BLOCK, eas.w), 1845 xive_get_field64(EAS2_END_INDEX, eas.w), 1846 xive_get_field64(EAS2_END_DATA, eas.w), 1847 false); 1848 return; 1849 } 1850 1851 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) 1852 { 1853 Xive2Router *xrtr = XIVE2_ROUTER(xn); 1854 1855 xive2_notify(xrtr, lisn, pq_checked); 1856 return; 1857 } 1858 1859 static const Property xive2_router_properties[] = { 1860 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb, 1861 TYPE_XIVE_FABRIC, XiveFabric *), 1862 }; 1863 1864 static void xive2_router_class_init(ObjectClass *klass, const void *data) 1865 { 1866 DeviceClass *dc = DEVICE_CLASS(klass); 1867 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1868 1869 dc->desc = "XIVE2 Router Engine"; 1870 device_class_set_props(dc, xive2_router_properties); 1871 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 1872 dc->realize = xive2_router_realize; 1873 xnc->notify = xive2_router_notify; 1874 } 1875 1876 static const TypeInfo xive2_router_info = { 1877 .name = TYPE_XIVE2_ROUTER, 1878 .parent = TYPE_SYS_BUS_DEVICE, 1879 .abstract = true, 1880 .instance_size = sizeof(Xive2Router), 1881 .class_size = sizeof(Xive2RouterClass), 1882 .class_init = xive2_router_class_init, 1883 .interfaces = (const InterfaceInfo[]) { 1884 { TYPE_XIVE_NOTIFIER }, 1885 { TYPE_XIVE_PRESENTER }, 1886 { } 1887 } 1888 }; 1889 1890 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 1891 { 1892 return !((addr >> shift) & 1); 1893 } 1894 1895 static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size) 1896 { 1897 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 1898 uint32_t offset = addr & 0xFFF; 1899 uint8_t end_blk; 1900 uint32_t end_idx; 1901 Xive2End end; 1902 uint32_t end_esmask; 1903 uint8_t pq; 1904 uint64_t ret; 1905 1906 /* 1907 * The block id should be deduced from the load address on the END 1908 * ESB MMIO but our model only supports a single block per XIVE chip. 1909 */ 1910 end_blk = xive2_router_get_block_id(xsrc->xrtr); 1911 end_idx = addr >> (xsrc->esb_shift + 1); 1912 1913 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1914 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1915 end_idx); 1916 return -1; 1917 } 1918 1919 if (!xive2_end_is_valid(&end)) { 1920 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1921 end_blk, end_idx); 1922 return -1; 1923 } 1924 1925 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 1926 END2_W1_ESe; 1927 pq = xive_get_field32(end_esmask, end.w1); 1928 1929 switch (offset) { 1930 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1931 ret = xive_esb_eoi(&pq); 1932 1933 /* Forward the source event notification for routing ?? */ 1934 break; 1935 1936 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1937 ret = pq; 1938 break; 1939 1940 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1941 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1942 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1943 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1944 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1945 break; 1946 default: 1947 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1948 offset); 1949 return -1; 1950 } 1951 1952 if (pq != xive_get_field32(end_esmask, end.w1)) { 1953 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1954 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1955 } 1956 1957 return ret; 1958 } 1959 1960 static void xive2_end_source_write(void *opaque, hwaddr addr, 1961 uint64_t value, unsigned size) 1962 { 1963 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 1964 uint32_t offset = addr & 0xFFF; 1965 uint8_t end_blk; 1966 uint32_t end_idx; 1967 Xive2End end; 1968 uint32_t end_esmask; 1969 uint8_t pq; 1970 bool notify = false; 1971 1972 /* 1973 * The block id should be deduced from the load address on the END 1974 * ESB MMIO but our model only supports a single block per XIVE chip. 1975 */ 1976 end_blk = xive2_router_get_block_id(xsrc->xrtr); 1977 end_idx = addr >> (xsrc->esb_shift + 1); 1978 1979 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1980 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1981 end_idx); 1982 return; 1983 } 1984 1985 if (!xive2_end_is_valid(&end)) { 1986 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1987 end_blk, end_idx); 1988 return; 1989 } 1990 1991 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 1992 END2_W1_ESe; 1993 pq = xive_get_field32(end_esmask, end.w1); 1994 1995 switch (offset) { 1996 case 0 ... 0x3FF: 1997 notify = xive_esb_trigger(&pq); 1998 break; 1999 2000 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 2001 /* TODO: can we check StoreEOI availability from the router ? */ 2002 notify = xive_esb_eoi(&pq); 2003 break; 2004 2005 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: 2006 if (end_esmask == END2_W1_ESe) { 2007 qemu_log_mask(LOG_GUEST_ERROR, 2008 "XIVE: END %x/%x can not EQ inject on ESe\n", 2009 end_blk, end_idx); 2010 return; 2011 } 2012 notify = true; 2013 break; 2014 2015 default: 2016 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n", 2017 offset); 2018 return; 2019 } 2020 2021 if (pq != xive_get_field32(end_esmask, end.w1)) { 2022 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 2023 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 2024 } 2025 2026 /* TODO: Forward the source event notification for routing */ 2027 if (notify) { 2028 ; 2029 } 2030 } 2031 2032 static const MemoryRegionOps xive2_end_source_ops = { 2033 .read = xive2_end_source_read, 2034 .write = xive2_end_source_write, 2035 .endianness = DEVICE_BIG_ENDIAN, 2036 .valid = { 2037 .min_access_size = 1, 2038 .max_access_size = 8, 2039 }, 2040 .impl = { 2041 .min_access_size = 1, 2042 .max_access_size = 8, 2043 }, 2044 }; 2045 2046 static void xive2_end_source_realize(DeviceState *dev, Error **errp) 2047 { 2048 Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev); 2049 2050 assert(xsrc->xrtr); 2051 2052 if (!xsrc->nr_ends) { 2053 error_setg(errp, "Number of interrupt needs to be greater than 0"); 2054 return; 2055 } 2056 2057 if (xsrc->esb_shift != XIVE_ESB_4K && 2058 xsrc->esb_shift != XIVE_ESB_64K) { 2059 error_setg(errp, "Invalid ESB shift setting"); 2060 return; 2061 } 2062 2063 /* 2064 * Each END is assigned an even/odd pair of MMIO pages, the even page 2065 * manages the ESn field while the odd page manages the ESe field. 2066 */ 2067 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 2068 &xive2_end_source_ops, xsrc, "xive.end", 2069 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 2070 } 2071 2072 static const Property xive2_end_source_properties[] = { 2073 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0), 2074 DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K), 2075 DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER, 2076 Xive2Router *), 2077 }; 2078 2079 static void xive2_end_source_class_init(ObjectClass *klass, const void *data) 2080 { 2081 DeviceClass *dc = DEVICE_CLASS(klass); 2082 2083 dc->desc = "XIVE END Source"; 2084 device_class_set_props(dc, xive2_end_source_properties); 2085 dc->realize = xive2_end_source_realize; 2086 dc->user_creatable = false; 2087 } 2088 2089 static const TypeInfo xive2_end_source_info = { 2090 .name = TYPE_XIVE2_END_SOURCE, 2091 .parent = TYPE_DEVICE, 2092 .instance_size = sizeof(Xive2EndSource), 2093 .class_init = xive2_end_source_class_init, 2094 }; 2095 2096 static void xive2_register_types(void) 2097 { 2098 type_register_static(&xive2_router_info); 2099 type_register_static(&xive2_end_source_info); 2100 } 2101 2102 type_init(xive2_register_types) 2103