1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2024, IBM Corporation.. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/log.h" 11 #include "qemu/module.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "system/cpus.h" 15 #include "system/dma.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/ppc/xive.h" 18 #include "hw/ppc/xive2.h" 19 #include "hw/ppc/xive2_regs.h" 20 #include "trace.h" 21 22 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 23 uint32_t end_idx, uint32_t end_data, 24 bool redistribute); 25 26 static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring, 27 uint8_t *nvp_blk, uint32_t *nvp_idx); 28 29 uint32_t xive2_router_get_config(Xive2Router *xrtr) 30 { 31 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 32 33 return xrc->get_config(xrtr); 34 } 35 36 static int xive2_router_get_block_id(Xive2Router *xrtr) 37 { 38 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 39 40 return xrc->get_block_id(xrtr); 41 } 42 43 static uint64_t xive2_nvp_reporting_addr(Xive2Nvp *nvp) 44 { 45 uint64_t cache_addr; 46 47 cache_addr = xive_get_field32(NVP2_W6_REPORTING_LINE, nvp->w6) << 24 | 48 xive_get_field32(NVP2_W7_REPORTING_LINE, nvp->w7); 49 cache_addr <<= 8; /* aligned on a cache line pair */ 50 return cache_addr; 51 } 52 53 static uint32_t xive2_nvgc_get_backlog(Xive2Nvgc *nvgc, uint8_t priority) 54 { 55 uint32_t val = 0; 56 uint8_t *ptr, i; 57 58 if (priority > 7) { 59 return 0; 60 } 61 62 /* 63 * The per-priority backlog counters are 24-bit and the structure 64 * is stored in big endian. NVGC is 32-bytes long, so 24-bytes from 65 * w2, which fits 8 priorities * 24-bits per priority. 66 */ 67 ptr = (uint8_t *)&nvgc->w2 + priority * 3; 68 for (i = 0; i < 3; i++, ptr++) { 69 val = (val << 8) + *ptr; 70 } 71 return val; 72 } 73 74 static void xive2_nvgc_set_backlog(Xive2Nvgc *nvgc, uint8_t priority, 75 uint32_t val) 76 { 77 uint8_t *ptr, i; 78 uint32_t shift; 79 80 if (priority > 7) { 81 return; 82 } 83 84 if (val > 0xFFFFFF) { 85 val = 0xFFFFFF; 86 } 87 /* 88 * The per-priority backlog counters are 24-bit and the structure 89 * is stored in big endian 90 */ 91 ptr = (uint8_t *)&nvgc->w2 + priority * 3; 92 for (i = 0; i < 3; i++, ptr++) { 93 shift = 8 * (2 - i); 94 *ptr = (val >> shift) & 0xFF; 95 } 96 } 97 98 uint64_t xive2_presenter_nvgc_backlog_op(XivePresenter *xptr, 99 bool crowd, 100 uint8_t blk, uint32_t idx, 101 uint16_t offset, uint16_t val) 102 { 103 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 104 uint8_t priority = GETFIELD(NVx_BACKLOG_PRIO, offset); 105 uint8_t op = GETFIELD(NVx_BACKLOG_OP, offset); 106 Xive2Nvgc nvgc; 107 uint32_t count, old_count; 108 109 if (xive2_router_get_nvgc(xrtr, crowd, blk, idx, &nvgc)) { 110 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No %s %x/%x\n", 111 crowd ? "NVC" : "NVG", blk, idx); 112 return -1; 113 } 114 if (!xive2_nvgc_is_valid(&nvgc)) { 115 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n", blk, idx); 116 return -1; 117 } 118 119 old_count = xive2_nvgc_get_backlog(&nvgc, priority); 120 count = old_count; 121 /* 122 * op: 123 * 0b00 => increment 124 * 0b01 => decrement 125 * 0b1- => read 126 */ 127 if (op == 0b00 || op == 0b01) { 128 if (op == 0b00) { 129 count += val; 130 } else { 131 if (count > val) { 132 count -= val; 133 } else { 134 count = 0; 135 } 136 } 137 xive2_nvgc_set_backlog(&nvgc, priority, count); 138 xive2_router_write_nvgc(xrtr, crowd, blk, idx, &nvgc); 139 } 140 trace_xive_nvgc_backlog_op(crowd, blk, idx, op, priority, old_count); 141 return old_count; 142 } 143 144 uint64_t xive2_presenter_nvp_backlog_op(XivePresenter *xptr, 145 uint8_t blk, uint32_t idx, 146 uint16_t offset) 147 { 148 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 149 uint8_t priority = GETFIELD(NVx_BACKLOG_PRIO, offset); 150 uint8_t op = GETFIELD(NVx_BACKLOG_OP, offset); 151 Xive2Nvp nvp; 152 uint8_t ipb, old_ipb, rc; 153 154 if (xive2_router_get_nvp(xrtr, blk, idx, &nvp)) { 155 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", blk, idx); 156 return -1; 157 } 158 if (!xive2_nvp_is_valid(&nvp)) { 159 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVP %x/%x\n", blk, idx); 160 return -1; 161 } 162 163 old_ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2); 164 ipb = old_ipb; 165 /* 166 * op: 167 * 0b00 => set priority bit 168 * 0b01 => reset priority bit 169 * 0b1- => read 170 */ 171 if (op == 0b00 || op == 0b01) { 172 if (op == 0b00) { 173 ipb |= xive_priority_to_ipb(priority); 174 } else { 175 ipb &= ~xive_priority_to_ipb(priority); 176 } 177 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 178 xive2_router_write_nvp(xrtr, blk, idx, &nvp, 2); 179 } 180 rc = !!(old_ipb & xive_priority_to_ipb(priority)); 181 trace_xive_nvp_backlog_op(blk, idx, op, priority, rc); 182 return rc; 183 } 184 185 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf) 186 { 187 if (!xive2_eas_is_valid(eas)) { 188 return; 189 } 190 191 g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n", 192 lisn, xive2_eas_is_masked(eas) ? "M" : " ", 193 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 194 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 195 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 196 } 197 198 #define XIVE2_QSIZE_CHUNK_CL 128 199 #define XIVE2_QSIZE_CHUNK_4k 4096 200 /* Calculate max number of queue entries for an END */ 201 static uint32_t xive2_end_get_qentries(Xive2End *end) 202 { 203 uint32_t w3 = end->w3; 204 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, w3); 205 if (xive_get_field32(END2_W3_CL, w3)) { 206 g_assert(qsize <= 4); 207 return (XIVE2_QSIZE_CHUNK_CL << qsize) / sizeof(uint32_t); 208 } else { 209 g_assert(qsize <= 12); 210 return (XIVE2_QSIZE_CHUNK_4k << qsize) / sizeof(uint32_t); 211 } 212 } 213 214 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString *buf) 215 { 216 uint64_t qaddr_base = xive2_end_qaddr(end); 217 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 218 uint32_t qentries = xive2_end_get_qentries(end); 219 int i; 220 221 /* 222 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 223 */ 224 g_string_append_printf(buf, " [ "); 225 qindex = (qindex - (width - 1)) & (qentries - 1); 226 for (i = 0; i < width; i++) { 227 uint64_t qaddr = qaddr_base + (qindex << 2); 228 uint32_t qdata = -1; 229 230 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 231 sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 232 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 233 HWADDR_PRIx "\n", qaddr); 234 return; 235 } 236 g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "", 237 be32_to_cpu(qdata)); 238 qindex = (qindex + 1) & (qentries - 1); 239 } 240 g_string_append_printf(buf, "]"); 241 } 242 243 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf) 244 { 245 uint64_t qaddr_base = xive2_end_qaddr(end); 246 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 247 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 248 uint32_t qentries = xive2_end_get_qentries(end); 249 250 uint32_t nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); 251 uint32_t nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); 252 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7); 253 uint8_t pq; 254 255 if (!xive2_end_is_valid(end)) { 256 return; 257 } 258 259 pq = xive_get_field32(END2_W1_ESn, end->w1); 260 261 g_string_append_printf(buf, 262 " %08x %c%c %c%c%c%c%c%c%c%c%c%c%c %c%c " 263 "prio:%d nvp:%02x/%04x", 264 end_idx, 265 pq & XIVE_ESB_VAL_P ? 'P' : '-', 266 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 267 xive2_end_is_valid(end) ? 'v' : '-', 268 xive2_end_is_enqueue(end) ? 'q' : '-', 269 xive2_end_is_notify(end) ? 'n' : '-', 270 xive2_end_is_backlog(end) ? 'b' : '-', 271 xive2_end_is_precluded_escalation(end) ? 'p' : '-', 272 xive2_end_is_escalate(end) ? 'e' : '-', 273 xive2_end_is_escalate_end(end) ? 'N' : '-', 274 xive2_end_is_uncond_escalation(end) ? 'u' : '-', 275 xive2_end_is_silent_escalation(end) ? 's' : '-', 276 xive2_end_is_firmware1(end) ? 'f' : '-', 277 xive2_end_is_firmware2(end) ? 'F' : '-', 278 xive2_end_is_ignore(end) ? 'i' : '-', 279 xive2_end_is_crowd(end) ? 'c' : '-', 280 priority, nvx_blk, nvx_idx); 281 282 if (qaddr_base) { 283 g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d", 284 qaddr_base, qindex, qentries, qgen); 285 xive2_end_queue_pic_print_info(end, 6, buf); 286 } 287 g_string_append_c(buf, '\n'); 288 } 289 290 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, 291 GString *buf) 292 { 293 Xive2Eas *eas = (Xive2Eas *) &end->w4; 294 uint8_t pq; 295 296 if (!xive2_end_is_escalate(end)) { 297 return; 298 } 299 300 pq = xive_get_field32(END2_W1_ESe, end->w1); 301 302 g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 303 end_idx, 304 pq & XIVE_ESB_VAL_P ? 'P' : '-', 305 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 306 xive2_eas_is_valid(eas) ? 'v' : ' ', 307 xive2_eas_is_masked(eas) ? 'M' : ' ', 308 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 309 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 310 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 311 } 312 313 void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *buf) 314 { 315 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); 316 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); 317 uint64_t cache_line = xive2_nvp_reporting_addr(nvp); 318 319 if (!xive2_nvp_is_valid(nvp)) { 320 return; 321 } 322 323 g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x PGoFirst:%02x", 324 nvp_idx, eq_blk, eq_idx, 325 xive_get_field32(NVP2_W2_IPB, nvp->w2), 326 xive_get_field32(NVP2_W0_PGOFIRST, nvp->w0)); 327 if (cache_line) { 328 g_string_append_printf(buf, " reporting CL:%016"PRIx64, cache_line); 329 } 330 331 /* 332 * When the NVP is HW controlled, more fields are updated 333 */ 334 if (xive2_nvp_is_hw(nvp)) { 335 g_string_append_printf(buf, " CPPR:%02x", 336 xive_get_field32(NVP2_W2_CPPR, nvp->w2)); 337 if (xive2_nvp_is_co(nvp)) { 338 g_string_append_printf(buf, " CO:%04x", 339 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); 340 } 341 } 342 g_string_append_c(buf, '\n'); 343 } 344 345 void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_t nvgc_idx, GString *buf) 346 { 347 uint8_t i; 348 349 if (!xive2_nvgc_is_valid(nvgc)) { 350 return; 351 } 352 353 g_string_append_printf(buf, " %08x PGoNext:%02x bklog: ", nvgc_idx, 354 xive_get_field32(NVGC2_W0_PGONEXT, nvgc->w0)); 355 for (i = 0; i <= XIVE_PRIORITY_MAX; i++) { 356 g_string_append_printf(buf, "[%d]=0x%x ", 357 i, xive2_nvgc_get_backlog(nvgc, i)); 358 } 359 g_string_append_printf(buf, "\n"); 360 } 361 362 static void xive2_end_enqueue(Xive2End *end, uint32_t data) 363 { 364 uint64_t qaddr_base = xive2_end_qaddr(end); 365 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 366 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 367 368 uint64_t qaddr = qaddr_base + (qindex << 2); 369 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 370 uint32_t qentries = xive2_end_get_qentries(end); 371 372 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata), 373 MEMTXATTRS_UNSPECIFIED)) { 374 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 375 HWADDR_PRIx "\n", qaddr); 376 return; 377 } 378 379 qindex = (qindex + 1) & (qentries - 1); 380 if (qindex == 0) { 381 qgen ^= 1; 382 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); 383 384 /* Set gen flipped to 1, it gets reset on a cache watch operation */ 385 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, 1); 386 } 387 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); 388 } 389 390 static void xive2_pgofnext(uint8_t *nvgc_blk, uint32_t *nvgc_idx, 391 uint8_t next_level) 392 { 393 uint32_t mask, next_idx; 394 uint8_t next_blk; 395 396 /* 397 * Adjust the block and index of a VP for the next group/crowd 398 * size (PGofFirst/PGofNext field in the NVP and NVGC structures). 399 * 400 * The 6-bit group level is split into a 2-bit crowd and 4-bit 401 * group levels. Encoding is similar. However, we don't support 402 * crowd size of 8. So a crowd level of 0b11 is bumped to a crowd 403 * size of 16. 404 */ 405 next_blk = NVx_CROWD_LVL(next_level); 406 if (next_blk == 3) { 407 next_blk = 4; 408 } 409 mask = (1 << next_blk) - 1; 410 *nvgc_blk &= ~mask; 411 *nvgc_blk |= mask >> 1; 412 413 next_idx = NVx_GROUP_LVL(next_level); 414 mask = (1 << next_idx) - 1; 415 *nvgc_idx &= ~mask; 416 *nvgc_idx |= mask >> 1; 417 } 418 419 /* 420 * Scan the group chain and return the highest priority and group 421 * level of pending group interrupts. 422 */ 423 static uint8_t xive2_presenter_backlog_scan(XivePresenter *xptr, 424 uint8_t nvx_blk, uint32_t nvx_idx, 425 uint8_t first_group, 426 uint8_t *out_level) 427 { 428 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 429 uint32_t nvgc_idx; 430 uint32_t current_level, count; 431 uint8_t nvgc_blk, prio; 432 Xive2Nvgc nvgc; 433 434 for (prio = 0; prio <= XIVE_PRIORITY_MAX; prio++) { 435 current_level = first_group & 0x3F; 436 nvgc_blk = nvx_blk; 437 nvgc_idx = nvx_idx; 438 439 while (current_level) { 440 xive2_pgofnext(&nvgc_blk, &nvgc_idx, current_level); 441 442 if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(current_level), 443 nvgc_blk, nvgc_idx, &nvgc)) { 444 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n", 445 nvgc_blk, nvgc_idx); 446 return 0xFF; 447 } 448 if (!xive2_nvgc_is_valid(&nvgc)) { 449 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n", 450 nvgc_blk, nvgc_idx); 451 return 0xFF; 452 } 453 454 count = xive2_nvgc_get_backlog(&nvgc, prio); 455 if (count) { 456 *out_level = current_level; 457 return prio; 458 } 459 current_level = xive_get_field32(NVGC2_W0_PGONEXT, nvgc.w0) & 0x3F; 460 } 461 } 462 return 0xFF; 463 } 464 465 static void xive2_presenter_backlog_decr(XivePresenter *xptr, 466 uint8_t nvx_blk, uint32_t nvx_idx, 467 uint8_t group_prio, 468 uint8_t group_level) 469 { 470 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 471 uint32_t nvgc_idx, count; 472 uint8_t nvgc_blk; 473 Xive2Nvgc nvgc; 474 475 nvgc_blk = nvx_blk; 476 nvgc_idx = nvx_idx; 477 xive2_pgofnext(&nvgc_blk, &nvgc_idx, group_level); 478 479 if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(group_level), 480 nvgc_blk, nvgc_idx, &nvgc)) { 481 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n", 482 nvgc_blk, nvgc_idx); 483 return; 484 } 485 if (!xive2_nvgc_is_valid(&nvgc)) { 486 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n", 487 nvgc_blk, nvgc_idx); 488 return; 489 } 490 count = xive2_nvgc_get_backlog(&nvgc, group_prio); 491 if (!count) { 492 return; 493 } 494 xive2_nvgc_set_backlog(&nvgc, group_prio, count - 1); 495 xive2_router_write_nvgc(xrtr, NVx_CROWD_LVL(group_level), 496 nvgc_blk, nvgc_idx, &nvgc); 497 } 498 499 /* 500 * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode 501 * 502 * TIMA Gen2 VP “save & restore” (S&R) indicated by H bit next to V bit 503 * 504 * - if a context is enabled with the H bit set, the VP context 505 * information is retrieved from the NVP structure (“check out”) 506 * and stored back on a context pull (“check in”), the SW receives 507 * the same context pull information as on P9 508 * 509 * - the H bit cannot be changed while the V bit is set, i.e. a 510 * context cannot be set up in the TIMA and then be “pushed” into 511 * the NVP by changing the H bit while the context is enabled 512 */ 513 514 static void xive2_tctx_save_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 515 uint8_t ring, 516 uint8_t nvp_blk, uint32_t nvp_idx) 517 { 518 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 519 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 520 Xive2Nvp nvp; 521 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); 522 uint8_t *regs = &tctx->regs[ring]; 523 524 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 525 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 526 nvp_blk, nvp_idx); 527 return; 528 } 529 530 if (!xive2_nvp_is_valid(&nvp)) { 531 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 532 nvp_blk, nvp_idx); 533 return; 534 } 535 536 if (!xive2_nvp_is_hw(&nvp)) { 537 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 538 nvp_blk, nvp_idx); 539 return; 540 } 541 542 if (!xive2_nvp_is_co(&nvp)) { 543 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not checkout\n", 544 nvp_blk, nvp_idx); 545 return; 546 } 547 548 if (xive_get_field32(NVP2_W1_CO_THRID_VALID, nvp.w1) && 549 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) { 550 qemu_log_mask(LOG_GUEST_ERROR, 551 "XIVE: NVP %x/%x invalid checkout Thread %x\n", 552 nvp_blk, nvp_idx, pir); 553 return; 554 } 555 556 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]); 557 558 if ((nvp.w0 & NVP2_W0_P) || ring != TM_QW2_HV_POOL) { 559 /* 560 * Non-pool contexts always save CPPR (ignore p bit). XXX: Clarify 561 * whether that is the correct behaviour. 562 */ 563 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, sig_regs[TM_CPPR]); 564 } 565 if (nvp.w0 & NVP2_W0_L) { 566 /* 567 * Typically not used. If LSMFB is restored with 0, it will 568 * force a backlog rescan 569 */ 570 nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]); 571 } 572 if (nvp.w0 & NVP2_W0_G) { 573 nvp.w2 = xive_set_field32(NVP2_W2_LGS, nvp.w2, regs[TM_LGS]); 574 } 575 if (nvp.w0 & NVP2_W0_T) { 576 nvp.w2 = xive_set_field32(NVP2_W2_T, nvp.w2, regs[TM_T]); 577 } 578 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 579 580 nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0); 581 /* NVP2_W1_CO_THRID_VALID only set once */ 582 nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF); 583 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1); 584 } 585 586 static void xive2_cam_decode(uint32_t cam, uint8_t *nvp_blk, 587 uint32_t *nvp_idx, bool *valid, bool *hw) 588 { 589 *nvp_blk = xive2_nvp_blk(cam); 590 *nvp_idx = xive2_nvp_idx(cam); 591 *valid = !!(cam & TM2_W2_VALID); 592 *hw = !!(cam & TM2_W2_HW); 593 } 594 595 /* 596 * Encode the HW CAM line with 7bit or 8bit thread id. The thread id 597 * width and block id width is configurable at the IC level. 598 * 599 * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit) 600 * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit) 601 */ 602 static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 603 { 604 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 605 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 606 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 607 uint8_t blk = xive2_router_get_block_id(xrtr); 608 uint8_t tid_shift = 609 xive2_router_get_config(xrtr) & XIVE2_THREADID_8BITS ? 8 : 7; 610 uint8_t tid_mask = (1 << tid_shift) - 1; 611 612 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); 613 } 614 615 static void xive2_redistribute(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t ring) 616 { 617 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); 618 uint8_t nsr = sig_regs[TM_NSR]; 619 uint8_t pipr = sig_regs[TM_PIPR]; 620 uint8_t crowd = NVx_CROWD_LVL(nsr); 621 uint8_t group = NVx_GROUP_LVL(nsr); 622 uint8_t nvgc_blk, end_blk, nvp_blk; 623 uint32_t nvgc_idx, end_idx, nvp_idx; 624 Xive2Nvgc nvgc; 625 uint8_t prio_limit; 626 uint32_t cfg; 627 628 /* redistribution is only for group/crowd interrupts */ 629 if (!xive_nsr_indicates_group_exception(ring, nsr)) { 630 return; 631 } 632 633 /* Don't check return code since ring is expected to be invalidated */ 634 xive2_tctx_get_nvp_indexes(tctx, ring, &nvp_blk, &nvp_idx); 635 636 trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx); 637 638 trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx); 639 /* convert crowd/group to blk/idx */ 640 if (group > 0) { 641 nvgc_idx = (nvp_idx & (0xffffffff << group)) | 642 ((1 << (group - 1)) - 1); 643 } else { 644 nvgc_idx = nvp_idx; 645 } 646 647 if (crowd > 0) { 648 crowd = (crowd == 3) ? 4 : crowd; 649 nvgc_blk = (nvp_blk & (0xffffffff << crowd)) | 650 ((1 << (crowd - 1)) - 1); 651 } else { 652 nvgc_blk = nvp_blk; 653 } 654 655 /* Use blk/idx to retrieve the NVGC */ 656 if (xive2_router_get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, &nvgc)) { 657 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no %s %x/%x\n", 658 crowd ? "NVC" : "NVG", nvgc_blk, nvgc_idx); 659 return; 660 } 661 662 /* retrieve the END blk/idx from the NVGC */ 663 end_blk = xive_get_field32(NVGC2_W1_END_BLK, nvgc.w1); 664 end_idx = xive_get_field32(NVGC2_W1_END_IDX, nvgc.w1); 665 666 /* determine number of priorities being used */ 667 cfg = xive2_router_get_config(xrtr); 668 if (cfg & XIVE2_EN_VP_GRP_PRIORITY) { 669 prio_limit = 1 << GETFIELD(NVGC2_W1_PSIZE, nvgc.w1); 670 } else { 671 prio_limit = 1 << GETFIELD(XIVE2_VP_INT_PRIO, cfg); 672 } 673 674 /* add priority offset to end index */ 675 end_idx += pipr % prio_limit; 676 677 /* trigger the group END */ 678 xive2_router_end_notify(xrtr, end_blk, end_idx, 0, true); 679 680 /* clear interrupt indication for the context */ 681 sig_regs[TM_NSR] = 0; 682 sig_regs[TM_PIPR] = sig_regs[TM_CPPR]; 683 xive_tctx_reset_signal(tctx, ring); 684 } 685 686 static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, XiveTCTX *tctx, 687 hwaddr offset, unsigned size, uint8_t ring) 688 { 689 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 690 uint32_t target_ringw2 = xive_tctx_word2(&tctx->regs[ring]); 691 uint32_t cam = be32_to_cpu(target_ringw2); 692 uint8_t nvp_blk; 693 uint32_t nvp_idx; 694 uint8_t cur_ring; 695 bool valid; 696 bool do_save; 697 uint8_t nsr; 698 699 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &valid, &do_save); 700 701 if (xive2_tctx_get_nvp_indexes(tctx, ring, &nvp_blk, &nvp_idx)) { 702 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n", 703 nvp_blk, nvp_idx); 704 } 705 706 /* Invalidate CAM line of requested ring and all lower rings */ 707 for (cur_ring = TM_QW0_USER; cur_ring <= ring; 708 cur_ring += XIVE_TM_RING_SIZE) { 709 uint32_t ringw2 = xive_tctx_word2(&tctx->regs[cur_ring]); 710 uint32_t ringw2_new = xive_set_field32(TM2_QW1W2_VO, ringw2, 0); 711 bool is_valid = !!(xive_get_field32(TM2_QW1W2_VO, ringw2)); 712 uint8_t *sig_regs; 713 714 memcpy(&tctx->regs[cur_ring + TM_WORD2], &ringw2_new, 4); 715 716 /* Skip the rest for USER or invalid contexts */ 717 if ((cur_ring == TM_QW0_USER) || !is_valid) { 718 continue; 719 } 720 721 /* Active group/crowd interrupts need to be redistributed */ 722 sig_regs = xive_tctx_signal_regs(tctx, ring); 723 nsr = sig_regs[TM_NSR]; 724 if (xive_nsr_indicates_group_exception(cur_ring, nsr)) { 725 /* Ensure ring matches NSR (for HV NSR POOL vs PHYS rings) */ 726 if (cur_ring == xive_nsr_exception_ring(cur_ring, nsr)) { 727 xive2_redistribute(xrtr, tctx, cur_ring); 728 } 729 } 730 } 731 732 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { 733 xive2_tctx_save_ctx(xrtr, tctx, ring, nvp_blk, nvp_idx); 734 } 735 736 /* 737 * Lower external interrupt line of requested ring and below except for 738 * USER, which doesn't exist. 739 */ 740 for (cur_ring = TM_QW1_OS; cur_ring <= ring; 741 cur_ring += XIVE_TM_RING_SIZE) { 742 xive_tctx_reset_signal(tctx, cur_ring); 743 } 744 return target_ringw2; 745 } 746 747 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 748 hwaddr offset, unsigned size) 749 { 750 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW1_OS); 751 } 752 753 uint64_t xive2_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 754 hwaddr offset, unsigned size) 755 { 756 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW2_HV_POOL); 757 } 758 759 uint64_t xive2_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, 760 hwaddr offset, unsigned size) 761 { 762 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW3_HV_PHYS); 763 } 764 765 #define REPORT_LINE_GEN1_SIZE 16 766 767 static void xive2_tm_report_line_gen1(XiveTCTX *tctx, uint8_t *data, 768 uint8_t size) 769 { 770 uint8_t *regs = tctx->regs; 771 772 g_assert(size == REPORT_LINE_GEN1_SIZE); 773 memset(data, 0, size); 774 /* 775 * See xive architecture for description of what is saved. It is 776 * hand-picked information to fit in 16 bytes. 777 */ 778 data[0x0] = regs[TM_QW3_HV_PHYS + TM_NSR]; 779 data[0x1] = regs[TM_QW3_HV_PHYS + TM_CPPR]; 780 data[0x2] = regs[TM_QW3_HV_PHYS + TM_IPB]; 781 data[0x3] = regs[TM_QW2_HV_POOL + TM_IPB]; 782 data[0x4] = regs[TM_QW1_OS + TM_ACK_CNT]; 783 data[0x5] = regs[TM_QW3_HV_PHYS + TM_LGS]; 784 data[0x6] = 0xFF; 785 data[0x7] = regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x80; 786 data[0x7] |= (regs[TM_QW2_HV_POOL + TM_WORD2] & 0x80) >> 1; 787 data[0x7] |= (regs[TM_QW1_OS + TM_WORD2] & 0x80) >> 2; 788 data[0x7] |= (regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x3); 789 data[0x8] = regs[TM_QW1_OS + TM_NSR]; 790 data[0x9] = regs[TM_QW1_OS + TM_CPPR]; 791 data[0xA] = regs[TM_QW1_OS + TM_IPB]; 792 data[0xB] = regs[TM_QW1_OS + TM_LGS]; 793 if (regs[TM_QW0_USER + TM_WORD2] & 0x80) { 794 /* 795 * Logical server extension, except VU bit replaced by EB bit 796 * from NSR 797 */ 798 data[0xC] = regs[TM_QW0_USER + TM_WORD2]; 799 data[0xC] &= ~0x80; 800 data[0xC] |= regs[TM_QW0_USER + TM_NSR] & 0x80; 801 data[0xD] = regs[TM_QW0_USER + TM_WORD2 + 1]; 802 data[0xE] = regs[TM_QW0_USER + TM_WORD2 + 2]; 803 data[0xF] = regs[TM_QW0_USER + TM_WORD2 + 3]; 804 } 805 } 806 807 static void xive2_tm_pull_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 808 hwaddr offset, uint64_t value, 809 unsigned size, uint8_t ring) 810 { 811 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 812 uint32_t hw_cam, nvp_idx, xive2_cfg, reserved; 813 uint8_t nvp_blk; 814 Xive2Nvp nvp; 815 uint64_t phys_addr; 816 MemTxResult result; 817 818 hw_cam = xive2_tctx_hw_cam_line(xptr, tctx); 819 nvp_blk = xive2_nvp_blk(hw_cam); 820 nvp_idx = xive2_nvp_idx(hw_cam); 821 822 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 823 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 824 nvp_blk, nvp_idx); 825 return; 826 } 827 828 if (!xive2_nvp_is_valid(&nvp)) { 829 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 830 nvp_blk, nvp_idx); 831 return; 832 } 833 834 xive2_cfg = xive2_router_get_config(xrtr); 835 836 phys_addr = xive2_nvp_reporting_addr(&nvp) + 0x80; /* odd line */ 837 if (xive2_cfg & XIVE2_GEN1_TIMA_OS) { 838 uint8_t pull_ctxt[REPORT_LINE_GEN1_SIZE]; 839 840 xive2_tm_report_line_gen1(tctx, pull_ctxt, REPORT_LINE_GEN1_SIZE); 841 result = dma_memory_write(&address_space_memory, phys_addr, 842 pull_ctxt, REPORT_LINE_GEN1_SIZE, 843 MEMTXATTRS_UNSPECIFIED); 844 assert(result == MEMTX_OK); 845 } else { 846 result = dma_memory_write(&address_space_memory, phys_addr, 847 &tctx->regs, sizeof(tctx->regs), 848 MEMTXATTRS_UNSPECIFIED); 849 assert(result == MEMTX_OK); 850 reserved = 0xFFFFFFFF; 851 result = dma_memory_write(&address_space_memory, phys_addr + 12, 852 &reserved, sizeof(reserved), 853 MEMTXATTRS_UNSPECIFIED); 854 assert(result == MEMTX_OK); 855 } 856 857 /* the rest is similar to pull context to registers */ 858 xive2_tm_pull_ctx(xptr, tctx, offset, size, ring); 859 } 860 861 void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 862 hwaddr offset, uint64_t value, unsigned size) 863 { 864 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW1_OS); 865 } 866 867 868 void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 869 hwaddr offset, uint64_t value, unsigned size) 870 { 871 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW3_HV_PHYS); 872 } 873 874 static uint8_t xive2_tctx_restore_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 875 uint8_t ring, 876 uint8_t nvp_blk, uint32_t nvp_idx, 877 Xive2Nvp *nvp) 878 { 879 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 880 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 881 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); 882 uint8_t *regs = &tctx->regs[ring]; 883 uint8_t cppr; 884 885 if (!xive2_nvp_is_hw(nvp)) { 886 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 887 nvp_blk, nvp_idx); 888 return 0; 889 } 890 891 cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2); 892 nvp->w2 = xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0); 893 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2); 894 895 sig_regs[TM_CPPR] = cppr; 896 regs[TM_LSMFB] = xive_get_field32(NVP2_W2_LSMFB, nvp->w2); 897 regs[TM_LGS] = xive_get_field32(NVP2_W2_LGS, nvp->w2); 898 regs[TM_T] = xive_get_field32(NVP2_W2_T, nvp->w2); 899 900 nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1); 901 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1); 902 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir); 903 904 /* 905 * Checkout privilege: 0:OS, 1:Pool, 2:Hard 906 * 907 * TODO: we don't support hard push/pull 908 */ 909 switch (ring) { 910 case TM_QW1_OS: 911 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0); 912 break; 913 case TM_QW2_HV_POOL: 914 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 1); 915 break; 916 default: 917 g_assert_not_reached(); 918 } 919 920 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 1); 921 922 /* return restored CPPR to generate a CPU exception if needed */ 923 return cppr; 924 } 925 926 static void xive2_tctx_process_pending(XiveTCTX *tctx, uint8_t sig_ring); 927 928 static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, 929 uint8_t nvp_blk, uint32_t nvp_idx, 930 bool do_restore) 931 { 932 uint8_t *regs = &tctx->regs[TM_QW1_OS]; 933 uint8_t ipb; 934 Xive2Nvp nvp; 935 936 /* 937 * Grab the associated thread interrupt context registers in the 938 * associated NVP 939 */ 940 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 941 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 942 nvp_blk, nvp_idx); 943 return; 944 } 945 946 if (!xive2_nvp_is_valid(&nvp)) { 947 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 948 nvp_blk, nvp_idx); 949 return; 950 } 951 952 /* Automatically restore thread context registers */ 953 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_restore) { 954 xive2_tctx_restore_ctx(xrtr, tctx, TM_QW1_OS, nvp_blk, nvp_idx, &nvp); 955 } 956 957 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2); 958 if (ipb) { 959 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0); 960 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 961 } 962 /* IPB bits in the backlog are merged with the TIMA IPB bits */ 963 regs[TM_IPB] |= ipb; 964 965 xive2_tctx_process_pending(tctx, TM_QW1_OS); 966 } 967 968 /* 969 * Updating the OS CAM line can trigger a resend of interrupt 970 */ 971 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 972 hwaddr offset, uint64_t value, unsigned size) 973 { 974 uint32_t cam; 975 uint32_t qw1w2; 976 uint64_t qw1dw1; 977 uint8_t nvp_blk; 978 uint32_t nvp_idx; 979 bool vo; 980 bool do_restore; 981 982 /* First update the thead context */ 983 switch (size) { 984 case 4: 985 cam = value; 986 qw1w2 = cpu_to_be32(cam); 987 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 988 break; 989 case 8: 990 cam = value >> 32; 991 qw1dw1 = cpu_to_be64(value); 992 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1dw1, 8); 993 break; 994 default: 995 g_assert_not_reached(); 996 } 997 998 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore); 999 1000 /* Check the interrupt pending bits */ 1001 if (vo) { 1002 xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx, 1003 do_restore); 1004 } 1005 } 1006 1007 /* returns -1 if ring is invalid, but still populates block and index */ 1008 static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring, 1009 uint8_t *nvp_blk, uint32_t *nvp_idx) 1010 { 1011 uint32_t w2; 1012 uint32_t cam = 0; 1013 int rc = 0; 1014 1015 w2 = xive_tctx_word2(&tctx->regs[ring]); 1016 switch (ring) { 1017 case TM_QW1_OS: 1018 if (!(be32_to_cpu(w2) & TM2_QW1W2_VO)) { 1019 rc = -1; 1020 } 1021 cam = xive_get_field32(TM2_QW1W2_OS_CAM, w2); 1022 break; 1023 case TM_QW2_HV_POOL: 1024 if (!(be32_to_cpu(w2) & TM2_QW2W2_VP)) { 1025 rc = -1; 1026 } 1027 cam = xive_get_field32(TM2_QW2W2_POOL_CAM, w2); 1028 break; 1029 case TM_QW3_HV_PHYS: 1030 if (!(be32_to_cpu(w2) & TM2_QW3W2_VT)) { 1031 rc = -1; 1032 } 1033 cam = xive2_tctx_hw_cam_line(tctx->xptr, tctx); 1034 break; 1035 default: 1036 rc = -1; 1037 } 1038 *nvp_blk = xive2_nvp_blk(cam); 1039 *nvp_idx = xive2_nvp_idx(cam); 1040 return rc; 1041 } 1042 1043 static void xive2_tctx_accept_el(XivePresenter *xptr, XiveTCTX *tctx, 1044 uint8_t ring, uint8_t cl_ring) 1045 { 1046 uint64_t rd; 1047 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 1048 uint32_t nvp_idx, xive2_cfg; 1049 uint8_t nvp_blk; 1050 Xive2Nvp nvp; 1051 uint64_t phys_addr; 1052 uint8_t OGen = 0; 1053 1054 xive2_tctx_get_nvp_indexes(tctx, cl_ring, &nvp_blk, &nvp_idx); 1055 1056 if (xive2_router_get_nvp(xrtr, (uint8_t)nvp_blk, nvp_idx, &nvp)) { 1057 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 1058 nvp_blk, nvp_idx); 1059 return; 1060 } 1061 1062 if (!xive2_nvp_is_valid(&nvp)) { 1063 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 1064 nvp_blk, nvp_idx); 1065 return; 1066 } 1067 1068 1069 rd = xive_tctx_accept(tctx, ring); 1070 1071 if (ring == TM_QW1_OS) { 1072 OGen = tctx->regs[ring + TM_OGEN]; 1073 } 1074 xive2_cfg = xive2_router_get_config(xrtr); 1075 phys_addr = xive2_nvp_reporting_addr(&nvp); 1076 uint8_t report_data[REPORT_LINE_GEN1_SIZE]; 1077 memset(report_data, 0xff, sizeof(report_data)); 1078 if ((OGen == 1) || (xive2_cfg & XIVE2_GEN1_TIMA_OS)) { 1079 report_data[8] = (rd >> 8) & 0xff; 1080 report_data[9] = rd & 0xff; 1081 } else { 1082 report_data[0] = (rd >> 8) & 0xff; 1083 report_data[1] = rd & 0xff; 1084 } 1085 cpu_physical_memory_write(phys_addr, report_data, REPORT_LINE_GEN1_SIZE); 1086 } 1087 1088 void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTCTX *tctx, 1089 hwaddr offset, uint64_t value, unsigned size) 1090 { 1091 xive2_tctx_accept_el(xptr, tctx, TM_QW1_OS, TM_QW1_OS); 1092 } 1093 1094 /* Re-calculate and present pending interrupts */ 1095 static void xive2_tctx_process_pending(XiveTCTX *tctx, uint8_t sig_ring) 1096 { 1097 uint8_t *sig_regs = &tctx->regs[sig_ring]; 1098 Xive2Router *xrtr = XIVE2_ROUTER(tctx->xptr); 1099 uint8_t backlog_prio; 1100 uint8_t first_group; 1101 uint8_t group_level; 1102 uint8_t pipr_min; 1103 uint8_t lsmfb_min; 1104 uint8_t ring_min; 1105 uint8_t cppr = sig_regs[TM_CPPR]; 1106 bool group_enabled; 1107 Xive2Nvp nvp; 1108 int rc; 1109 1110 g_assert(sig_ring == TM_QW3_HV_PHYS || sig_ring == TM_QW1_OS); 1111 g_assert(!xive_nsr_indicates_group_exception(sig_ring, sig_regs[TM_NSR])); 1112 1113 /* 1114 * Recompute the PIPR based on local pending interrupts. It will 1115 * be adjusted below if needed in case of pending group interrupts. 1116 */ 1117 again: 1118 pipr_min = xive_ipb_to_pipr(sig_regs[TM_IPB]); 1119 group_enabled = !!sig_regs[TM_LGS]; 1120 lsmfb_min = group_enabled ? sig_regs[TM_LSMFB] : 0xff; 1121 ring_min = sig_ring; 1122 group_level = 0; 1123 1124 /* PHYS updates also depend on POOL values */ 1125 if (sig_ring == TM_QW3_HV_PHYS) { 1126 uint8_t *pool_regs = &tctx->regs[TM_QW2_HV_POOL]; 1127 1128 /* POOL values only matter if POOL ctx is valid */ 1129 if (pool_regs[TM_WORD2] & 0x80) { 1130 uint8_t pool_pipr = xive_ipb_to_pipr(pool_regs[TM_IPB]); 1131 uint8_t pool_lsmfb = pool_regs[TM_LSMFB]; 1132 1133 /* 1134 * Determine highest priority interrupt and 1135 * remember which ring has it. 1136 */ 1137 if (pool_pipr < pipr_min) { 1138 pipr_min = pool_pipr; 1139 if (pool_pipr < lsmfb_min) { 1140 ring_min = TM_QW2_HV_POOL; 1141 } 1142 } 1143 1144 /* Values needed for group priority calculation */ 1145 if (pool_regs[TM_LGS] && (pool_lsmfb < lsmfb_min)) { 1146 group_enabled = true; 1147 lsmfb_min = pool_lsmfb; 1148 if (lsmfb_min < pipr_min) { 1149 ring_min = TM_QW2_HV_POOL; 1150 } 1151 } 1152 } 1153 } 1154 1155 if (group_enabled && 1156 lsmfb_min < cppr && 1157 lsmfb_min < pipr_min) { 1158 1159 uint8_t nvp_blk; 1160 uint32_t nvp_idx; 1161 1162 /* 1163 * Thread has seen a group interrupt with a higher priority 1164 * than the new cppr or pending local interrupt. Check the 1165 * backlog 1166 */ 1167 rc = xive2_tctx_get_nvp_indexes(tctx, ring_min, &nvp_blk, &nvp_idx); 1168 if (rc) { 1169 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: set CPPR on invalid " 1170 "context\n"); 1171 return; 1172 } 1173 1174 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 1175 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 1176 nvp_blk, nvp_idx); 1177 return; 1178 } 1179 1180 if (!xive2_nvp_is_valid(&nvp)) { 1181 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 1182 nvp_blk, nvp_idx); 1183 return; 1184 } 1185 1186 first_group = xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0); 1187 if (!first_group) { 1188 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 1189 nvp_blk, nvp_idx); 1190 return; 1191 } 1192 1193 backlog_prio = xive2_presenter_backlog_scan(tctx->xptr, 1194 nvp_blk, nvp_idx, 1195 first_group, &group_level); 1196 tctx->regs[ring_min + TM_LSMFB] = backlog_prio; 1197 if (backlog_prio != lsmfb_min) { 1198 /* 1199 * If the group backlog scan finds a less favored or no interrupt, 1200 * then re-do the processing which may turn up a more favored 1201 * interrupt from IPB or the other pool. Backlog should not 1202 * find a priority < LSMFB. 1203 */ 1204 g_assert(backlog_prio >= lsmfb_min); 1205 goto again; 1206 } 1207 1208 xive2_presenter_backlog_decr(tctx->xptr, nvp_blk, nvp_idx, 1209 backlog_prio, group_level); 1210 pipr_min = backlog_prio; 1211 } 1212 1213 if (pipr_min > cppr) { 1214 pipr_min = cppr; 1215 } 1216 xive_tctx_pipr_set(tctx, ring_min, pipr_min, group_level); 1217 } 1218 1219 /* NOTE: CPPR only exists for TM_QW1_OS and TM_QW3_HV_PHYS */ 1220 static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t sig_ring, uint8_t cppr) 1221 { 1222 uint8_t *sig_regs = &tctx->regs[sig_ring]; 1223 Xive2Router *xrtr = XIVE2_ROUTER(tctx->xptr); 1224 uint8_t old_cppr; 1225 uint8_t nsr = sig_regs[TM_NSR]; 1226 1227 g_assert(sig_ring == TM_QW1_OS || sig_ring == TM_QW3_HV_PHYS); 1228 1229 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] == 0); 1230 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0); 1231 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); 1232 1233 /* XXX: should show pool IPB for PHYS ring */ 1234 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, sig_ring, 1235 sig_regs[TM_IPB], sig_regs[TM_PIPR], 1236 cppr, nsr); 1237 1238 if (cppr > XIVE_PRIORITY_MAX) { 1239 cppr = 0xff; 1240 } 1241 1242 old_cppr = sig_regs[TM_CPPR]; 1243 sig_regs[TM_CPPR] = cppr; 1244 1245 /* Handle increased CPPR priority (lower value) */ 1246 if (cppr < old_cppr) { 1247 if (cppr <= sig_regs[TM_PIPR]) { 1248 /* CPPR lowered below PIPR, must un-present interrupt */ 1249 if (xive_nsr_indicates_exception(sig_ring, nsr)) { 1250 if (xive_nsr_indicates_group_exception(sig_ring, nsr)) { 1251 /* redistribute precluded active grp interrupt */ 1252 xive2_redistribute(xrtr, tctx, 1253 xive_nsr_exception_ring(sig_ring, nsr)); 1254 return; 1255 } 1256 } 1257 1258 /* interrupt is VP directed, pending in IPB */ 1259 xive_tctx_pipr_set(tctx, sig_ring, cppr, 0); 1260 return; 1261 } else { 1262 /* CPPR was lowered, but still above PIPR. No action needed. */ 1263 return; 1264 } 1265 } 1266 1267 /* CPPR didn't change, nothing needs to be done */ 1268 if (cppr == old_cppr) { 1269 return; 1270 } 1271 1272 /* CPPR priority decreased (higher value) */ 1273 if (!xive_nsr_indicates_exception(sig_ring, nsr)) { 1274 xive2_tctx_process_pending(tctx, sig_ring); 1275 } 1276 } 1277 1278 void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 1279 hwaddr offset, uint64_t value, unsigned size) 1280 { 1281 xive2_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 1282 } 1283 1284 void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 1285 hwaddr offset, uint64_t value, unsigned size) 1286 { 1287 xive2_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 1288 } 1289 1290 static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t target) 1291 { 1292 uint8_t *regs = &tctx->regs[ring]; 1293 1294 regs[TM_T] = target; 1295 } 1296 1297 void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, 1298 hwaddr offset, uint64_t value, unsigned size) 1299 { 1300 xive2_tctx_set_target(tctx, TM_QW3_HV_PHYS, value & 0xff); 1301 } 1302 1303 /* 1304 * XIVE Router (aka. Virtualization Controller or IVRE) 1305 */ 1306 1307 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1308 Xive2Eas *eas) 1309 { 1310 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1311 1312 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1313 } 1314 1315 static 1316 int xive2_router_get_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1317 uint8_t *pq) 1318 { 1319 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1320 1321 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); 1322 } 1323 1324 static 1325 int xive2_router_set_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1326 uint8_t *pq) 1327 { 1328 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1329 1330 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); 1331 } 1332 1333 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 1334 Xive2End *end) 1335 { 1336 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1337 1338 return xrc->get_end(xrtr, end_blk, end_idx, end); 1339 } 1340 1341 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 1342 Xive2End *end, uint8_t word_number) 1343 { 1344 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1345 1346 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1347 } 1348 1349 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 1350 Xive2Nvp *nvp) 1351 { 1352 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1353 1354 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp); 1355 } 1356 1357 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 1358 Xive2Nvp *nvp, uint8_t word_number) 1359 { 1360 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1361 1362 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number); 1363 } 1364 1365 int xive2_router_get_nvgc(Xive2Router *xrtr, bool crowd, 1366 uint8_t nvgc_blk, uint32_t nvgc_idx, 1367 Xive2Nvgc *nvgc) 1368 { 1369 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1370 1371 return xrc->get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); 1372 } 1373 1374 int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd, 1375 uint8_t nvgc_blk, uint32_t nvgc_idx, 1376 Xive2Nvgc *nvgc) 1377 { 1378 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1379 1380 return xrc->write_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); 1381 } 1382 1383 static bool xive2_vp_match_mask(uint32_t cam1, uint32_t cam2, 1384 uint32_t vp_mask) 1385 { 1386 return (cam1 & vp_mask) == (cam2 & vp_mask); 1387 } 1388 1389 static uint8_t xive2_get_vp_block_mask(uint32_t nvt_blk, bool crowd) 1390 { 1391 uint8_t block_mask = 0b1111; 1392 1393 /* 3 supported crowd sizes: 2, 4, 16 */ 1394 if (crowd) { 1395 uint32_t size = xive_get_vpgroup_size(nvt_blk); 1396 1397 if (size != 2 && size != 4 && size != 16) { 1398 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid crowd size of %d", 1399 size); 1400 return block_mask; 1401 } 1402 block_mask &= ~(size - 1); 1403 } 1404 return block_mask; 1405 } 1406 1407 static uint32_t xive2_get_vp_index_mask(uint32_t nvt_index, bool cam_ignore) 1408 { 1409 uint32_t index_mask = 0xFFFFFF; /* 24 bits */ 1410 1411 if (cam_ignore) { 1412 uint32_t size = xive_get_vpgroup_size(nvt_index); 1413 1414 if (size < 2) { 1415 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid group size of %d", 1416 size); 1417 return index_mask; 1418 } 1419 index_mask &= ~(size - 1); 1420 } 1421 return index_mask; 1422 } 1423 1424 /* 1425 * The thread context register words are in big-endian format. 1426 */ 1427 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1428 uint8_t format, 1429 uint8_t nvt_blk, uint32_t nvt_idx, 1430 bool crowd, bool cam_ignore, 1431 uint32_t logic_serv) 1432 { 1433 uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx); 1434 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1435 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1436 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1437 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1438 1439 uint32_t index_mask, vp_mask; 1440 uint8_t block_mask; 1441 1442 if (format == 0) { 1443 /* 1444 * i=0: Specific NVT notification 1445 * i=1: VP-group notification (bits ignored at the end of the 1446 * NVT identifier) 1447 */ 1448 block_mask = xive2_get_vp_block_mask(nvt_blk, crowd); 1449 index_mask = xive2_get_vp_index_mask(nvt_idx, cam_ignore); 1450 vp_mask = xive2_nvp_cam_line(block_mask, index_mask); 1451 1452 /* For VP-group notifications, threads with LGS=0 are excluded */ 1453 1454 /* PHYS ring */ 1455 if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) && 1456 !(cam_ignore && tctx->regs[TM_QW3_HV_PHYS + TM_LGS] == 0) && 1457 xive2_vp_match_mask(cam, 1458 xive2_tctx_hw_cam_line(xptr, tctx), 1459 vp_mask)) { 1460 return TM_QW3_HV_PHYS; 1461 } 1462 1463 /* HV POOL ring */ 1464 if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) && 1465 !(cam_ignore && tctx->regs[TM_QW2_HV_POOL + TM_LGS] == 0) && 1466 xive2_vp_match_mask(cam, 1467 xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2), 1468 vp_mask)) { 1469 return TM_QW2_HV_POOL; 1470 } 1471 1472 /* OS ring */ 1473 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 1474 !(cam_ignore && tctx->regs[TM_QW1_OS + TM_LGS] == 0) && 1475 xive2_vp_match_mask(cam, 1476 xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2), 1477 vp_mask)) { 1478 return TM_QW1_OS; 1479 } 1480 } else { 1481 /* F=1 : User level Event-Based Branch (EBB) notification */ 1482 1483 /* FIXME: what if cam_ignore and LGS = 0 ? */ 1484 /* USER ring */ 1485 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 1486 (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) && 1487 (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) && 1488 (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) { 1489 return TM_QW0_USER; 1490 } 1491 } 1492 return -1; 1493 } 1494 1495 bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority) 1496 { 1497 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); 1498 1499 /* 1500 * The xive2_presenter_tctx_match() above tells if there's a match 1501 * but for VP-group notification, we still need to look at the 1502 * priority to know if the thread can take the interrupt now or if 1503 * it is precluded. 1504 */ 1505 if (priority < sig_regs[TM_PIPR]) { 1506 return false; 1507 } 1508 return true; 1509 } 1510 1511 void xive2_tm_set_lsmfb(XiveTCTX *tctx, int ring, uint8_t priority) 1512 { 1513 uint8_t *regs = &tctx->regs[ring]; 1514 1515 /* 1516 * Called by the router during a VP-group notification when the 1517 * thread matches but can't take the interrupt because it's 1518 * already running at a more favored priority. It then stores the 1519 * new interrupt priority in the LSMFB field. 1520 */ 1521 regs[TM_LSMFB] = priority; 1522 } 1523 1524 static void xive2_router_realize(DeviceState *dev, Error **errp) 1525 { 1526 Xive2Router *xrtr = XIVE2_ROUTER(dev); 1527 1528 assert(xrtr->xfb); 1529 } 1530 1531 /* 1532 * Notification using the END ESe/ESn bit (Event State Buffer for 1533 * escalation and notification). Profide further coalescing in the 1534 * Router. 1535 */ 1536 static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk, 1537 uint32_t end_idx, Xive2End *end, 1538 uint32_t end_esmask) 1539 { 1540 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1541 bool notify = xive_esb_trigger(&pq); 1542 1543 if (pq != xive_get_field32(end_esmask, end->w1)) { 1544 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1545 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1); 1546 } 1547 1548 /* ESe/n[Q]=1 : end of notification */ 1549 return notify; 1550 } 1551 1552 /* 1553 * An END trigger can come from an event trigger (IPI or HW) or from 1554 * another chip. We don't model the PowerBus but the END trigger 1555 * message has the same parameters than in the function below. 1556 */ 1557 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 1558 uint32_t end_idx, uint32_t end_data, 1559 bool redistribute) 1560 { 1561 Xive2End end; 1562 uint8_t priority; 1563 uint8_t format; 1564 XiveTCTXMatch match; 1565 bool crowd, cam_ignore; 1566 uint8_t nvx_blk; 1567 uint32_t nvx_idx; 1568 1569 /* END cache lookup */ 1570 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) { 1571 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1572 end_idx); 1573 return; 1574 } 1575 1576 if (!xive2_end_is_valid(&end)) { 1577 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1578 end_blk, end_idx); 1579 return; 1580 } 1581 1582 if (xive2_end_is_crowd(&end) && !xive2_end_is_ignore(&end)) { 1583 qemu_log_mask(LOG_GUEST_ERROR, 1584 "XIVE: invalid END, 'crowd' bit requires 'ignore' bit\n"); 1585 return; 1586 } 1587 1588 if (!redistribute && xive2_end_is_enqueue(&end)) { 1589 trace_xive_end_enqueue(end_blk, end_idx, end_data); 1590 xive2_end_enqueue(&end, end_data); 1591 /* Enqueuing event data modifies the EQ toggle and index */ 1592 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1593 } 1594 1595 /* 1596 * When the END is silent, we skip the notification part. 1597 */ 1598 if (xive2_end_is_silent_escalation(&end)) { 1599 goto do_escalation; 1600 } 1601 1602 /* 1603 * The W7 format depends on the F bit in W6. It defines the type 1604 * of the notification : 1605 * 1606 * F=0 : single or multiple NVP notification 1607 * F=1 : User level Event-Based Branch (EBB) notification, no 1608 * priority 1609 */ 1610 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6); 1611 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7); 1612 1613 /* The END is masked */ 1614 if (format == 0 && priority == 0xff) { 1615 return; 1616 } 1617 1618 /* 1619 * Check the END ESn (Event State Buffer for notification) for 1620 * even further coalescing in the Router 1621 */ 1622 if (!xive2_end_is_notify(&end)) { 1623 /* ESn[Q]=1 : end of notification */ 1624 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 1625 &end, END2_W1_ESn)) { 1626 return; 1627 } 1628 } 1629 1630 /* 1631 * Follows IVPE notification 1632 */ 1633 nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6); 1634 nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6); 1635 crowd = xive2_end_is_crowd(&end); 1636 cam_ignore = xive2_end_is_ignore(&end); 1637 1638 /* TODO: Auto EOI. */ 1639 if (xive_presenter_match(xrtr->xfb, format, nvx_blk, nvx_idx, 1640 crowd, cam_ignore, priority, 1641 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7), 1642 &match)) { 1643 XiveTCTX *tctx = match.tctx; 1644 uint8_t ring = match.ring; 1645 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); 1646 uint8_t nsr = sig_regs[TM_NSR]; 1647 uint8_t group_level; 1648 1649 if (priority < sig_regs[TM_PIPR] && 1650 xive_nsr_indicates_group_exception(ring, nsr)) { 1651 xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, nsr)); 1652 } 1653 1654 group_level = xive_get_group_level(crowd, cam_ignore, nvx_blk, nvx_idx); 1655 trace_xive_presenter_notify(nvx_blk, nvx_idx, ring, group_level); 1656 xive_tctx_pipr_present(tctx, ring, priority, group_level); 1657 return; 1658 } 1659 1660 /* 1661 * If no matching NVP is dispatched on a HW thread : 1662 * - specific VP: update the NVP structure if backlog is activated 1663 * - VP-group: update the backlog counter for that priority in the NVG 1664 */ 1665 if (xive2_end_is_backlog(&end)) { 1666 1667 if (format == 1) { 1668 qemu_log_mask(LOG_GUEST_ERROR, 1669 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1670 end_blk, end_idx); 1671 return; 1672 } 1673 1674 if (!cam_ignore) { 1675 uint8_t ipb; 1676 Xive2Nvp nvp; 1677 1678 /* NVP cache lookup */ 1679 if (xive2_router_get_nvp(xrtr, nvx_blk, nvx_idx, &nvp)) { 1680 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n", 1681 nvx_blk, nvx_idx); 1682 return; 1683 } 1684 1685 if (!xive2_nvp_is_valid(&nvp)) { 1686 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n", 1687 nvx_blk, nvx_idx); 1688 return; 1689 } 1690 1691 /* 1692 * Record the IPB in the associated NVP structure for later 1693 * use. The presenter will resend the interrupt when the vCPU 1694 * is dispatched again on a HW thread. 1695 */ 1696 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) | 1697 xive_priority_to_ipb(priority); 1698 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 1699 xive2_router_write_nvp(xrtr, nvx_blk, nvx_idx, &nvp, 2); 1700 } else { 1701 Xive2Nvgc nvgc; 1702 uint32_t backlog; 1703 1704 /* 1705 * For groups and crowds, the per-priority backlog 1706 * counters are stored in the NVG/NVC structures 1707 */ 1708 if (xive2_router_get_nvgc(xrtr, crowd, 1709 nvx_blk, nvx_idx, &nvgc)) { 1710 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no %s %x/%x\n", 1711 crowd ? "NVC" : "NVG", nvx_blk, nvx_idx); 1712 return; 1713 } 1714 1715 if (!xive2_nvgc_is_valid(&nvgc)) { 1716 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVG %x/%x is invalid\n", 1717 nvx_blk, nvx_idx); 1718 return; 1719 } 1720 1721 /* 1722 * Increment the backlog counter for that priority. 1723 * We only call broadcast the first time the counter is 1724 * incremented. broadcast will set the LSMFB field of the TIMA of 1725 * relevant threads so that they know an interrupt is pending. 1726 */ 1727 backlog = xive2_nvgc_get_backlog(&nvgc, priority) + 1; 1728 xive2_nvgc_set_backlog(&nvgc, priority, backlog); 1729 xive2_router_write_nvgc(xrtr, crowd, nvx_blk, nvx_idx, &nvgc); 1730 1731 if (backlog == 1) { 1732 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xrtr->xfb); 1733 xfc->broadcast(xrtr->xfb, nvx_blk, nvx_idx, 1734 crowd, cam_ignore, priority); 1735 1736 if (!xive2_end_is_precluded_escalation(&end)) { 1737 /* 1738 * The interrupt will be picked up when the 1739 * matching thread lowers its priority level 1740 */ 1741 return; 1742 } 1743 } 1744 } 1745 } 1746 1747 do_escalation: 1748 /* 1749 * If activated, escalate notification using the ESe PQ bits and 1750 * the EAS in w4-5 1751 */ 1752 if (!xive2_end_is_escalate(&end)) { 1753 return; 1754 } 1755 1756 /* 1757 * Check the END ESe (Event State Buffer for escalation) for even 1758 * further coalescing in the Router 1759 */ 1760 if (!xive2_end_is_uncond_escalation(&end)) { 1761 /* ESe[Q]=1 : end of escalation notification */ 1762 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 1763 &end, END2_W1_ESe)) { 1764 return; 1765 } 1766 } 1767 1768 if (xive2_end_is_escalate_end(&end)) { 1769 /* 1770 * Perform END Adaptive escalation processing 1771 * The END trigger becomes an Escalation trigger 1772 */ 1773 uint8_t esc_blk = xive_get_field32(END2_W4_END_BLOCK, end.w4); 1774 uint32_t esc_idx = xive_get_field32(END2_W4_ESC_END_INDEX, end.w4); 1775 uint32_t esc_data = xive_get_field32(END2_W5_ESC_END_DATA, end.w5); 1776 trace_xive_escalate_end(end_blk, end_idx, esc_blk, esc_idx, esc_data); 1777 xive2_router_end_notify(xrtr, esc_blk, esc_idx, esc_data, false); 1778 } /* end END adaptive escalation */ 1779 1780 else { 1781 uint32_t lisn; /* Logical Interrupt Source Number */ 1782 1783 /* 1784 * Perform ESB escalation processing 1785 * E[N] == 1 --> N 1786 * Req[Block] <- E[ESB_Block] 1787 * Req[Index] <- E[ESB_Index] 1788 * Req[Offset] <- 0x000 1789 * Execute <ESB Store> Req command 1790 */ 1791 lisn = XIVE_EAS(xive_get_field32(END2_W4_END_BLOCK, end.w4), 1792 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4)); 1793 1794 trace_xive_escalate_esb(end_blk, end_idx, lisn); 1795 xive2_notify(xrtr, lisn, true /* pq_checked */); 1796 } 1797 1798 return; 1799 } 1800 1801 void xive2_notify(Xive2Router *xrtr , uint32_t lisn, bool pq_checked) 1802 { 1803 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1804 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1805 Xive2Eas eas; 1806 1807 /* EAS cache lookup */ 1808 if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1809 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1810 return; 1811 } 1812 1813 if (!pq_checked) { 1814 bool notify; 1815 uint8_t pq; 1816 1817 /* PQ cache lookup */ 1818 if (xive2_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) { 1819 /* Set FIR */ 1820 g_assert_not_reached(); 1821 } 1822 1823 notify = xive_esb_trigger(&pq); 1824 1825 if (xive2_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) { 1826 /* Set FIR */ 1827 g_assert_not_reached(); 1828 } 1829 1830 if (!notify) { 1831 return; 1832 } 1833 } 1834 1835 if (!xive2_eas_is_valid(&eas)) { 1836 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn); 1837 return; 1838 } 1839 1840 if (xive2_eas_is_masked(&eas)) { 1841 /* Notification completed */ 1842 return; 1843 } 1844 1845 /* TODO: add support for EAS resume */ 1846 if (xive2_eas_is_resume(&eas)) { 1847 qemu_log_mask(LOG_UNIMP, 1848 "XIVE: EAS resume processing unimplemented - LISN %x\n", 1849 lisn); 1850 return; 1851 } 1852 1853 /* 1854 * The event trigger becomes an END trigger 1855 */ 1856 xive2_router_end_notify(xrtr, 1857 xive_get_field64(EAS2_END_BLOCK, eas.w), 1858 xive_get_field64(EAS2_END_INDEX, eas.w), 1859 xive_get_field64(EAS2_END_DATA, eas.w), 1860 false); 1861 return; 1862 } 1863 1864 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) 1865 { 1866 Xive2Router *xrtr = XIVE2_ROUTER(xn); 1867 1868 xive2_notify(xrtr, lisn, pq_checked); 1869 return; 1870 } 1871 1872 static const Property xive2_router_properties[] = { 1873 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb, 1874 TYPE_XIVE_FABRIC, XiveFabric *), 1875 }; 1876 1877 static void xive2_router_class_init(ObjectClass *klass, const void *data) 1878 { 1879 DeviceClass *dc = DEVICE_CLASS(klass); 1880 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1881 1882 dc->desc = "XIVE2 Router Engine"; 1883 device_class_set_props(dc, xive2_router_properties); 1884 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 1885 dc->realize = xive2_router_realize; 1886 xnc->notify = xive2_router_notify; 1887 } 1888 1889 static const TypeInfo xive2_router_info = { 1890 .name = TYPE_XIVE2_ROUTER, 1891 .parent = TYPE_SYS_BUS_DEVICE, 1892 .abstract = true, 1893 .instance_size = sizeof(Xive2Router), 1894 .class_size = sizeof(Xive2RouterClass), 1895 .class_init = xive2_router_class_init, 1896 .interfaces = (const InterfaceInfo[]) { 1897 { TYPE_XIVE_NOTIFIER }, 1898 { TYPE_XIVE_PRESENTER }, 1899 { } 1900 } 1901 }; 1902 1903 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 1904 { 1905 return !((addr >> shift) & 1); 1906 } 1907 1908 static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size) 1909 { 1910 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 1911 uint32_t offset = addr & 0xFFF; 1912 uint8_t end_blk; 1913 uint32_t end_idx; 1914 Xive2End end; 1915 uint32_t end_esmask; 1916 uint8_t pq; 1917 uint64_t ret; 1918 1919 /* 1920 * The block id should be deduced from the load address on the END 1921 * ESB MMIO but our model only supports a single block per XIVE chip. 1922 */ 1923 end_blk = xive2_router_get_block_id(xsrc->xrtr); 1924 end_idx = addr >> (xsrc->esb_shift + 1); 1925 1926 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1927 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1928 end_idx); 1929 return -1; 1930 } 1931 1932 if (!xive2_end_is_valid(&end)) { 1933 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1934 end_blk, end_idx); 1935 return -1; 1936 } 1937 1938 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 1939 END2_W1_ESe; 1940 pq = xive_get_field32(end_esmask, end.w1); 1941 1942 switch (offset) { 1943 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1944 ret = xive_esb_eoi(&pq); 1945 1946 /* Forward the source event notification for routing ?? */ 1947 break; 1948 1949 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1950 ret = pq; 1951 break; 1952 1953 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1954 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1955 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1956 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1957 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1958 break; 1959 default: 1960 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1961 offset); 1962 return -1; 1963 } 1964 1965 if (pq != xive_get_field32(end_esmask, end.w1)) { 1966 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1967 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1968 } 1969 1970 return ret; 1971 } 1972 1973 static void xive2_end_source_write(void *opaque, hwaddr addr, 1974 uint64_t value, unsigned size) 1975 { 1976 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 1977 uint32_t offset = addr & 0xFFF; 1978 uint8_t end_blk; 1979 uint32_t end_idx; 1980 Xive2End end; 1981 uint32_t end_esmask; 1982 uint8_t pq; 1983 bool notify = false; 1984 1985 /* 1986 * The block id should be deduced from the load address on the END 1987 * ESB MMIO but our model only supports a single block per XIVE chip. 1988 */ 1989 end_blk = xive2_router_get_block_id(xsrc->xrtr); 1990 end_idx = addr >> (xsrc->esb_shift + 1); 1991 1992 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1993 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1994 end_idx); 1995 return; 1996 } 1997 1998 if (!xive2_end_is_valid(&end)) { 1999 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 2000 end_blk, end_idx); 2001 return; 2002 } 2003 2004 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 2005 END2_W1_ESe; 2006 pq = xive_get_field32(end_esmask, end.w1); 2007 2008 switch (offset) { 2009 case 0 ... 0x3FF: 2010 notify = xive_esb_trigger(&pq); 2011 break; 2012 2013 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 2014 /* TODO: can we check StoreEOI availability from the router ? */ 2015 notify = xive_esb_eoi(&pq); 2016 break; 2017 2018 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: 2019 if (end_esmask == END2_W1_ESe) { 2020 qemu_log_mask(LOG_GUEST_ERROR, 2021 "XIVE: END %x/%x can not EQ inject on ESe\n", 2022 end_blk, end_idx); 2023 return; 2024 } 2025 notify = true; 2026 break; 2027 2028 default: 2029 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n", 2030 offset); 2031 return; 2032 } 2033 2034 if (pq != xive_get_field32(end_esmask, end.w1)) { 2035 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 2036 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 2037 } 2038 2039 /* TODO: Forward the source event notification for routing */ 2040 if (notify) { 2041 ; 2042 } 2043 } 2044 2045 static const MemoryRegionOps xive2_end_source_ops = { 2046 .read = xive2_end_source_read, 2047 .write = xive2_end_source_write, 2048 .endianness = DEVICE_BIG_ENDIAN, 2049 .valid = { 2050 .min_access_size = 1, 2051 .max_access_size = 8, 2052 }, 2053 .impl = { 2054 .min_access_size = 1, 2055 .max_access_size = 8, 2056 }, 2057 }; 2058 2059 static void xive2_end_source_realize(DeviceState *dev, Error **errp) 2060 { 2061 Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev); 2062 2063 assert(xsrc->xrtr); 2064 2065 if (!xsrc->nr_ends) { 2066 error_setg(errp, "Number of interrupt needs to be greater than 0"); 2067 return; 2068 } 2069 2070 if (xsrc->esb_shift != XIVE_ESB_4K && 2071 xsrc->esb_shift != XIVE_ESB_64K) { 2072 error_setg(errp, "Invalid ESB shift setting"); 2073 return; 2074 } 2075 2076 /* 2077 * Each END is assigned an even/odd pair of MMIO pages, the even page 2078 * manages the ESn field while the odd page manages the ESe field. 2079 */ 2080 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 2081 &xive2_end_source_ops, xsrc, "xive.end", 2082 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 2083 } 2084 2085 static const Property xive2_end_source_properties[] = { 2086 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0), 2087 DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K), 2088 DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER, 2089 Xive2Router *), 2090 }; 2091 2092 static void xive2_end_source_class_init(ObjectClass *klass, const void *data) 2093 { 2094 DeviceClass *dc = DEVICE_CLASS(klass); 2095 2096 dc->desc = "XIVE END Source"; 2097 device_class_set_props(dc, xive2_end_source_properties); 2098 dc->realize = xive2_end_source_realize; 2099 dc->user_creatable = false; 2100 } 2101 2102 static const TypeInfo xive2_end_source_info = { 2103 .name = TYPE_XIVE2_END_SOURCE, 2104 .parent = TYPE_DEVICE, 2105 .instance_size = sizeof(Xive2EndSource), 2106 .class_init = xive2_end_source_class_init, 2107 }; 2108 2109 static void xive2_register_types(void) 2110 { 2111 type_register_static(&xive2_router_info); 2112 type_register_static(&xive2_end_source_info); 2113 } 2114 2115 type_init(xive2_register_types) 2116