1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation.. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "hw/qdev-properties.h" 18 #include "hw/ppc/xive.h" 19 #include "hw/ppc/xive2.h" 20 #include "hw/ppc/xive2_regs.h" 21 22 uint32_t xive2_router_get_config(Xive2Router *xrtr) 23 { 24 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 25 26 return xrc->get_config(xrtr); 27 } 28 29 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf) 30 { 31 if (!xive2_eas_is_valid(eas)) { 32 return; 33 } 34 35 g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n", 36 lisn, xive2_eas_is_masked(eas) ? "M" : " ", 37 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 38 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 39 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 40 } 41 42 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString *buf) 43 { 44 uint64_t qaddr_base = xive2_end_qaddr(end); 45 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 46 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 47 uint32_t qentries = 1 << (qsize + 10); 48 int i; 49 50 /* 51 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 52 */ 53 g_string_append_printf(buf, " [ "); 54 qindex = (qindex - (width - 1)) & (qentries - 1); 55 for (i = 0; i < width; i++) { 56 uint64_t qaddr = qaddr_base + (qindex << 2); 57 uint32_t qdata = -1; 58 59 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 60 sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 61 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 62 HWADDR_PRIx "\n", qaddr); 63 return; 64 } 65 g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "", 66 be32_to_cpu(qdata)); 67 qindex = (qindex + 1) & (qentries - 1); 68 } 69 g_string_append_printf(buf, "]"); 70 } 71 72 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf) 73 { 74 uint64_t qaddr_base = xive2_end_qaddr(end); 75 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 76 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 77 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 78 uint32_t qentries = 1 << (qsize + 10); 79 80 uint32_t nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); 81 uint32_t nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); 82 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7); 83 uint8_t pq; 84 85 if (!xive2_end_is_valid(end)) { 86 return; 87 } 88 89 pq = xive_get_field32(END2_W1_ESn, end->w1); 90 91 g_string_append_printf(buf, 92 " %08x %c%c %c%c%c%c%c%c%c%c%c%c " 93 "prio:%d nvp:%02x/%04x", 94 end_idx, 95 pq & XIVE_ESB_VAL_P ? 'P' : '-', 96 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 97 xive2_end_is_valid(end) ? 'v' : '-', 98 xive2_end_is_enqueue(end) ? 'q' : '-', 99 xive2_end_is_notify(end) ? 'n' : '-', 100 xive2_end_is_backlog(end) ? 'b' : '-', 101 xive2_end_is_escalate(end) ? 'e' : '-', 102 xive2_end_is_escalate_end(end) ? 'N' : '-', 103 xive2_end_is_uncond_escalation(end) ? 'u' : '-', 104 xive2_end_is_silent_escalation(end) ? 's' : '-', 105 xive2_end_is_firmware1(end) ? 'f' : '-', 106 xive2_end_is_firmware2(end) ? 'F' : '-', 107 priority, nvp_blk, nvp_idx); 108 109 if (qaddr_base) { 110 g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d", 111 qaddr_base, qindex, qentries, qgen); 112 xive2_end_queue_pic_print_info(end, 6, buf); 113 } 114 g_string_append_c(buf, '\n'); 115 } 116 117 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, 118 GString *buf) 119 { 120 Xive2Eas *eas = (Xive2Eas *) &end->w4; 121 uint8_t pq; 122 123 if (!xive2_end_is_escalate(end)) { 124 return; 125 } 126 127 pq = xive_get_field32(END2_W1_ESe, end->w1); 128 129 g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 130 end_idx, 131 pq & XIVE_ESB_VAL_P ? 'P' : '-', 132 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 133 xive2_eas_is_valid(eas) ? 'v' : ' ', 134 xive2_eas_is_masked(eas) ? 'M' : ' ', 135 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 136 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 137 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 138 } 139 140 static void xive2_end_enqueue(Xive2End *end, uint32_t data) 141 { 142 uint64_t qaddr_base = xive2_end_qaddr(end); 143 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 144 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 145 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 146 147 uint64_t qaddr = qaddr_base + (qindex << 2); 148 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 149 uint32_t qentries = 1 << (qsize + 10); 150 151 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata), 152 MEMTXATTRS_UNSPECIFIED)) { 153 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 154 HWADDR_PRIx "\n", qaddr); 155 return; 156 } 157 158 qindex = (qindex + 1) & (qentries - 1); 159 if (qindex == 0) { 160 qgen ^= 1; 161 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); 162 163 /* TODO(PowerNV): reset GF bit on a cache watch operation */ 164 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen); 165 } 166 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); 167 } 168 169 /* 170 * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode 171 * 172 * TIMA Gen2 VP “save & restore” (S&R) indicated by H bit next to V bit 173 * 174 * - if a context is enabled with the H bit set, the VP context 175 * information is retrieved from the NVP structure (“check out”) 176 * and stored back on a context pull (“check in”), the SW receives 177 * the same context pull information as on P9 178 * 179 * - the H bit cannot be changed while the V bit is set, i.e. a 180 * context cannot be set up in the TIMA and then be “pushed” into 181 * the NVP by changing the H bit while the context is enabled 182 */ 183 184 static void xive2_tctx_save_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 185 uint8_t nvp_blk, uint32_t nvp_idx) 186 { 187 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 188 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 189 Xive2Nvp nvp; 190 uint8_t *regs = &tctx->regs[TM_QW1_OS]; 191 192 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 193 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 194 nvp_blk, nvp_idx); 195 return; 196 } 197 198 if (!xive2_nvp_is_valid(&nvp)) { 199 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 200 nvp_blk, nvp_idx); 201 return; 202 } 203 204 if (!xive2_nvp_is_hw(&nvp)) { 205 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 206 nvp_blk, nvp_idx); 207 return; 208 } 209 210 if (!xive2_nvp_is_co(&nvp)) { 211 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not checkout\n", 212 nvp_blk, nvp_idx); 213 return; 214 } 215 216 if (xive_get_field32(NVP2_W1_CO_THRID_VALID, nvp.w1) && 217 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) { 218 qemu_log_mask(LOG_GUEST_ERROR, 219 "XIVE: NVP %x/%x invalid checkout Thread %x\n", 220 nvp_blk, nvp_idx, pir); 221 return; 222 } 223 224 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]); 225 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]); 226 nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]); 227 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 228 229 nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0); 230 /* NVP2_W1_CO_THRID_VALID only set once */ 231 nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF); 232 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1); 233 } 234 235 static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk, 236 uint32_t *nvp_idx, bool *vo, bool *ho) 237 { 238 *nvp_blk = xive2_nvp_blk(cam); 239 *nvp_idx = xive2_nvp_idx(cam); 240 *vo = !!(cam & TM2_QW1W2_VO); 241 *ho = !!(cam & TM2_QW1W2_HO); 242 } 243 244 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 245 hwaddr offset, unsigned size) 246 { 247 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 248 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 249 uint32_t qw1w2_new; 250 uint32_t cam = be32_to_cpu(qw1w2); 251 uint8_t nvp_blk; 252 uint32_t nvp_idx; 253 bool vo; 254 bool do_save; 255 256 xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_save); 257 258 if (!vo) { 259 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n", 260 nvp_blk, nvp_idx); 261 } 262 263 /* Invalidate CAM line */ 264 qw1w2_new = xive_set_field32(TM2_QW1W2_VO, qw1w2, 0); 265 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4); 266 267 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { 268 xive2_tctx_save_os_ctx(xrtr, tctx, nvp_blk, nvp_idx); 269 } 270 271 xive_tctx_reset_os_signal(tctx); 272 return qw1w2; 273 } 274 275 static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 276 uint8_t nvp_blk, uint32_t nvp_idx, 277 Xive2Nvp *nvp) 278 { 279 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 280 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 281 uint8_t cppr; 282 283 if (!xive2_nvp_is_hw(nvp)) { 284 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 285 nvp_blk, nvp_idx); 286 return 0; 287 } 288 289 cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2); 290 nvp->w2 = xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0); 291 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2); 292 293 tctx->regs[TM_QW1_OS + TM_CPPR] = cppr; 294 /* we don't model LSMFB */ 295 296 nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1); 297 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1); 298 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir); 299 300 /* 301 * Checkout privilege: 0:OS, 1:Pool, 2:Hard 302 * 303 * TODO: we only support OS push/pull 304 */ 305 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0); 306 307 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 1); 308 309 /* return restored CPPR to generate a CPU exception if needed */ 310 return cppr; 311 } 312 313 static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, 314 uint8_t nvp_blk, uint32_t nvp_idx, 315 bool do_restore) 316 { 317 Xive2Nvp nvp; 318 uint8_t ipb; 319 320 /* 321 * Grab the associated thread interrupt context registers in the 322 * associated NVP 323 */ 324 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 325 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 326 nvp_blk, nvp_idx); 327 return; 328 } 329 330 if (!xive2_nvp_is_valid(&nvp)) { 331 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 332 nvp_blk, nvp_idx); 333 return; 334 } 335 336 /* Automatically restore thread context registers */ 337 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && 338 do_restore) { 339 xive2_tctx_restore_os_ctx(xrtr, tctx, nvp_blk, nvp_idx, &nvp); 340 } 341 342 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2); 343 if (ipb) { 344 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0); 345 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 346 } 347 /* 348 * Always call xive_tctx_ipb_update(). Even if there were no 349 * escalation triggered, there could be a pending interrupt which 350 * was saved when the context was pulled and that we need to take 351 * into account by recalculating the PIPR (which is not 352 * saved/restored). 353 * It will also raise the External interrupt signal if needed. 354 */ 355 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); 356 } 357 358 /* 359 * Updating the OS CAM line can trigger a resend of interrupt 360 */ 361 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 362 hwaddr offset, uint64_t value, unsigned size) 363 { 364 uint32_t cam = value; 365 uint32_t qw1w2 = cpu_to_be32(cam); 366 uint8_t nvp_blk; 367 uint32_t nvp_idx; 368 bool vo; 369 bool do_restore; 370 371 xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore); 372 373 /* First update the thead context */ 374 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 375 376 /* Check the interrupt pending bits */ 377 if (vo) { 378 xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx, 379 do_restore); 380 } 381 } 382 383 /* 384 * XIVE Router (aka. Virtualization Controller or IVRE) 385 */ 386 387 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 388 Xive2Eas *eas) 389 { 390 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 391 392 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 393 } 394 395 static 396 int xive2_router_get_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 397 uint8_t *pq) 398 { 399 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 400 401 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); 402 } 403 404 static 405 int xive2_router_set_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 406 uint8_t *pq) 407 { 408 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 409 410 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); 411 } 412 413 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 414 Xive2End *end) 415 { 416 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 417 418 return xrc->get_end(xrtr, end_blk, end_idx, end); 419 } 420 421 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 422 Xive2End *end, uint8_t word_number) 423 { 424 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 425 426 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 427 } 428 429 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 430 Xive2Nvp *nvp) 431 { 432 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 433 434 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp); 435 } 436 437 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 438 Xive2Nvp *nvp, uint8_t word_number) 439 { 440 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 441 442 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number); 443 } 444 445 static int xive2_router_get_block_id(Xive2Router *xrtr) 446 { 447 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 448 449 return xrc->get_block_id(xrtr); 450 } 451 452 /* 453 * Encode the HW CAM line with 7bit or 8bit thread id. The thread id 454 * width and block id width is configurable at the IC level. 455 * 456 * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit) 457 * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit) 458 */ 459 static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 460 { 461 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 462 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 463 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 464 uint8_t blk = xive2_router_get_block_id(xrtr); 465 uint8_t tid_shift = 466 xive2_router_get_config(xrtr) & XIVE2_THREADID_8BITS ? 8 : 7; 467 uint8_t tid_mask = (1 << tid_shift) - 1; 468 469 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); 470 } 471 472 /* 473 * The thread context register words are in big-endian format. 474 */ 475 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 476 uint8_t format, 477 uint8_t nvt_blk, uint32_t nvt_idx, 478 bool cam_ignore, uint32_t logic_serv) 479 { 480 uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx); 481 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 482 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 483 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 484 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 485 486 /* 487 * TODO (PowerNV): ignore mode. The low order bits of the NVT 488 * identifier are ignored in the "CAM" match. 489 */ 490 491 if (format == 0) { 492 if (cam_ignore == true) { 493 /* 494 * F=0 & i=1: Logical server notification (bits ignored at 495 * the end of the NVT identifier) 496 */ 497 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 498 nvt_blk, nvt_idx); 499 return -1; 500 } 501 502 /* F=0 & i=0: Specific NVT notification */ 503 504 /* PHYS ring */ 505 if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) && 506 cam == xive2_tctx_hw_cam_line(xptr, tctx)) { 507 return TM_QW3_HV_PHYS; 508 } 509 510 /* HV POOL ring */ 511 if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) && 512 cam == xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2)) { 513 return TM_QW2_HV_POOL; 514 } 515 516 /* OS ring */ 517 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 518 cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) { 519 return TM_QW1_OS; 520 } 521 } else { 522 /* F=1 : User level Event-Based Branch (EBB) notification */ 523 524 /* USER ring */ 525 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 526 (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) && 527 (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) && 528 (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) { 529 return TM_QW0_USER; 530 } 531 } 532 return -1; 533 } 534 535 static void xive2_router_realize(DeviceState *dev, Error **errp) 536 { 537 Xive2Router *xrtr = XIVE2_ROUTER(dev); 538 539 assert(xrtr->xfb); 540 } 541 542 /* 543 * Notification using the END ESe/ESn bit (Event State Buffer for 544 * escalation and notification). Profide further coalescing in the 545 * Router. 546 */ 547 static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk, 548 uint32_t end_idx, Xive2End *end, 549 uint32_t end_esmask) 550 { 551 uint8_t pq = xive_get_field32(end_esmask, end->w1); 552 bool notify = xive_esb_trigger(&pq); 553 554 if (pq != xive_get_field32(end_esmask, end->w1)) { 555 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 556 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1); 557 } 558 559 /* ESe/n[Q]=1 : end of notification */ 560 return notify; 561 } 562 563 /* 564 * An END trigger can come from an event trigger (IPI or HW) or from 565 * another chip. We don't model the PowerBus but the END trigger 566 * message has the same parameters than in the function below. 567 */ 568 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 569 uint32_t end_idx, uint32_t end_data) 570 { 571 Xive2End end; 572 uint8_t priority; 573 uint8_t format; 574 bool found; 575 Xive2Nvp nvp; 576 uint8_t nvp_blk; 577 uint32_t nvp_idx; 578 579 /* END cache lookup */ 580 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) { 581 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 582 end_idx); 583 return; 584 } 585 586 if (!xive2_end_is_valid(&end)) { 587 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 588 end_blk, end_idx); 589 return; 590 } 591 592 if (xive2_end_is_enqueue(&end)) { 593 xive2_end_enqueue(&end, end_data); 594 /* Enqueuing event data modifies the EQ toggle and index */ 595 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1); 596 } 597 598 /* 599 * When the END is silent, we skip the notification part. 600 */ 601 if (xive2_end_is_silent_escalation(&end)) { 602 goto do_escalation; 603 } 604 605 /* 606 * The W7 format depends on the F bit in W6. It defines the type 607 * of the notification : 608 * 609 * F=0 : single or multiple NVP notification 610 * F=1 : User level Event-Based Branch (EBB) notification, no 611 * priority 612 */ 613 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6); 614 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7); 615 616 /* The END is masked */ 617 if (format == 0 && priority == 0xff) { 618 return; 619 } 620 621 /* 622 * Check the END ESn (Event State Buffer for notification) for 623 * even further coalescing in the Router 624 */ 625 if (!xive2_end_is_notify(&end)) { 626 /* ESn[Q]=1 : end of notification */ 627 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 628 &end, END2_W1_ESn)) { 629 return; 630 } 631 } 632 633 /* 634 * Follows IVPE notification 635 */ 636 nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6); 637 nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6); 638 639 /* NVP cache lookup */ 640 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 641 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n", 642 nvp_blk, nvp_idx); 643 return; 644 } 645 646 if (!xive2_nvp_is_valid(&nvp)) { 647 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n", 648 nvp_blk, nvp_idx); 649 return; 650 } 651 652 found = xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx, 653 xive_get_field32(END2_W6_IGNORE, end.w7), 654 priority, 655 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7)); 656 657 /* TODO: Auto EOI. */ 658 659 if (found) { 660 return; 661 } 662 663 /* 664 * If no matching NVP is dispatched on a HW thread : 665 * - specific VP: update the NVP structure if backlog is activated 666 * - logical server : forward request to IVPE (not supported) 667 */ 668 if (xive2_end_is_backlog(&end)) { 669 uint8_t ipb; 670 671 if (format == 1) { 672 qemu_log_mask(LOG_GUEST_ERROR, 673 "XIVE: END %x/%x invalid config: F1 & backlog\n", 674 end_blk, end_idx); 675 return; 676 } 677 678 /* 679 * Record the IPB in the associated NVP structure for later 680 * use. The presenter will resend the interrupt when the vCPU 681 * is dispatched again on a HW thread. 682 */ 683 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) | 684 xive_priority_to_ipb(priority); 685 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 686 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 687 688 /* 689 * On HW, follows a "Broadcast Backlog" to IVPEs 690 */ 691 } 692 693 do_escalation: 694 /* 695 * If activated, escalate notification using the ESe PQ bits and 696 * the EAS in w4-5 697 */ 698 if (!xive2_end_is_escalate(&end)) { 699 return; 700 } 701 702 /* 703 * Check the END ESe (Event State Buffer for escalation) for even 704 * further coalescing in the Router 705 */ 706 if (!xive2_end_is_uncond_escalation(&end)) { 707 /* ESe[Q]=1 : end of escalation notification */ 708 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 709 &end, END2_W1_ESe)) { 710 return; 711 } 712 } 713 714 /* 715 * The END trigger becomes an Escalation trigger 716 */ 717 xive2_router_end_notify(xrtr, 718 xive_get_field32(END2_W4_END_BLOCK, end.w4), 719 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4), 720 xive_get_field32(END2_W5_ESC_END_DATA, end.w5)); 721 } 722 723 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) 724 { 725 Xive2Router *xrtr = XIVE2_ROUTER(xn); 726 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 727 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 728 Xive2Eas eas; 729 730 /* EAS cache lookup */ 731 if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 732 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 733 return; 734 } 735 736 if (!pq_checked) { 737 bool notify; 738 uint8_t pq; 739 740 /* PQ cache lookup */ 741 if (xive2_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) { 742 /* Set FIR */ 743 g_assert_not_reached(); 744 } 745 746 notify = xive_esb_trigger(&pq); 747 748 if (xive2_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) { 749 /* Set FIR */ 750 g_assert_not_reached(); 751 } 752 753 if (!notify) { 754 return; 755 } 756 } 757 758 if (!xive2_eas_is_valid(&eas)) { 759 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn); 760 return; 761 } 762 763 if (xive2_eas_is_masked(&eas)) { 764 /* Notification completed */ 765 return; 766 } 767 768 /* 769 * The event trigger becomes an END trigger 770 */ 771 xive2_router_end_notify(xrtr, 772 xive_get_field64(EAS2_END_BLOCK, eas.w), 773 xive_get_field64(EAS2_END_INDEX, eas.w), 774 xive_get_field64(EAS2_END_DATA, eas.w)); 775 } 776 777 static Property xive2_router_properties[] = { 778 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb, 779 TYPE_XIVE_FABRIC, XiveFabric *), 780 DEFINE_PROP_END_OF_LIST(), 781 }; 782 783 static void xive2_router_class_init(ObjectClass *klass, void *data) 784 { 785 DeviceClass *dc = DEVICE_CLASS(klass); 786 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 787 788 dc->desc = "XIVE2 Router Engine"; 789 device_class_set_props(dc, xive2_router_properties); 790 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 791 dc->realize = xive2_router_realize; 792 xnc->notify = xive2_router_notify; 793 } 794 795 static const TypeInfo xive2_router_info = { 796 .name = TYPE_XIVE2_ROUTER, 797 .parent = TYPE_SYS_BUS_DEVICE, 798 .abstract = true, 799 .instance_size = sizeof(Xive2Router), 800 .class_size = sizeof(Xive2RouterClass), 801 .class_init = xive2_router_class_init, 802 .interfaces = (InterfaceInfo[]) { 803 { TYPE_XIVE_NOTIFIER }, 804 { TYPE_XIVE_PRESENTER }, 805 { } 806 } 807 }; 808 809 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 810 { 811 return !((addr >> shift) & 1); 812 } 813 814 static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size) 815 { 816 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 817 uint32_t offset = addr & 0xFFF; 818 uint8_t end_blk; 819 uint32_t end_idx; 820 Xive2End end; 821 uint32_t end_esmask; 822 uint8_t pq; 823 uint64_t ret; 824 825 /* 826 * The block id should be deduced from the load address on the END 827 * ESB MMIO but our model only supports a single block per XIVE chip. 828 */ 829 end_blk = xive2_router_get_block_id(xsrc->xrtr); 830 end_idx = addr >> (xsrc->esb_shift + 1); 831 832 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 833 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 834 end_idx); 835 return -1; 836 } 837 838 if (!xive2_end_is_valid(&end)) { 839 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 840 end_blk, end_idx); 841 return -1; 842 } 843 844 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 845 END2_W1_ESe; 846 pq = xive_get_field32(end_esmask, end.w1); 847 848 switch (offset) { 849 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 850 ret = xive_esb_eoi(&pq); 851 852 /* Forward the source event notification for routing ?? */ 853 break; 854 855 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 856 ret = pq; 857 break; 858 859 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 860 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 861 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 862 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 863 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 864 break; 865 default: 866 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 867 offset); 868 return -1; 869 } 870 871 if (pq != xive_get_field32(end_esmask, end.w1)) { 872 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 873 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 874 } 875 876 return ret; 877 } 878 879 static void xive2_end_source_write(void *opaque, hwaddr addr, 880 uint64_t value, unsigned size) 881 { 882 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 883 uint32_t offset = addr & 0xFFF; 884 uint8_t end_blk; 885 uint32_t end_idx; 886 Xive2End end; 887 uint32_t end_esmask; 888 uint8_t pq; 889 bool notify = false; 890 891 /* 892 * The block id should be deduced from the load address on the END 893 * ESB MMIO but our model only supports a single block per XIVE chip. 894 */ 895 end_blk = xive2_router_get_block_id(xsrc->xrtr); 896 end_idx = addr >> (xsrc->esb_shift + 1); 897 898 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 899 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 900 end_idx); 901 return; 902 } 903 904 if (!xive2_end_is_valid(&end)) { 905 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 906 end_blk, end_idx); 907 return; 908 } 909 910 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 911 END2_W1_ESe; 912 pq = xive_get_field32(end_esmask, end.w1); 913 914 switch (offset) { 915 case 0 ... 0x3FF: 916 notify = xive_esb_trigger(&pq); 917 break; 918 919 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 920 /* TODO: can we check StoreEOI availability from the router ? */ 921 notify = xive_esb_eoi(&pq); 922 break; 923 924 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: 925 if (end_esmask == END2_W1_ESe) { 926 qemu_log_mask(LOG_GUEST_ERROR, 927 "XIVE: END %x/%x can not EQ inject on ESe\n", 928 end_blk, end_idx); 929 return; 930 } 931 notify = true; 932 break; 933 934 default: 935 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n", 936 offset); 937 return; 938 } 939 940 if (pq != xive_get_field32(end_esmask, end.w1)) { 941 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 942 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 943 } 944 945 /* TODO: Forward the source event notification for routing */ 946 if (notify) { 947 ; 948 } 949 } 950 951 static const MemoryRegionOps xive2_end_source_ops = { 952 .read = xive2_end_source_read, 953 .write = xive2_end_source_write, 954 .endianness = DEVICE_BIG_ENDIAN, 955 .valid = { 956 .min_access_size = 1, 957 .max_access_size = 8, 958 }, 959 .impl = { 960 .min_access_size = 1, 961 .max_access_size = 8, 962 }, 963 }; 964 965 static void xive2_end_source_realize(DeviceState *dev, Error **errp) 966 { 967 Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev); 968 969 assert(xsrc->xrtr); 970 971 if (!xsrc->nr_ends) { 972 error_setg(errp, "Number of interrupt needs to be greater than 0"); 973 return; 974 } 975 976 if (xsrc->esb_shift != XIVE_ESB_4K && 977 xsrc->esb_shift != XIVE_ESB_64K) { 978 error_setg(errp, "Invalid ESB shift setting"); 979 return; 980 } 981 982 /* 983 * Each END is assigned an even/odd pair of MMIO pages, the even page 984 * manages the ESn field while the odd page manages the ESe field. 985 */ 986 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 987 &xive2_end_source_ops, xsrc, "xive.end", 988 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 989 } 990 991 static Property xive2_end_source_properties[] = { 992 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0), 993 DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K), 994 DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER, 995 Xive2Router *), 996 DEFINE_PROP_END_OF_LIST(), 997 }; 998 999 static void xive2_end_source_class_init(ObjectClass *klass, void *data) 1000 { 1001 DeviceClass *dc = DEVICE_CLASS(klass); 1002 1003 dc->desc = "XIVE END Source"; 1004 device_class_set_props(dc, xive2_end_source_properties); 1005 dc->realize = xive2_end_source_realize; 1006 dc->user_creatable = false; 1007 } 1008 1009 static const TypeInfo xive2_end_source_info = { 1010 .name = TYPE_XIVE2_END_SOURCE, 1011 .parent = TYPE_DEVICE, 1012 .instance_size = sizeof(Xive2EndSource), 1013 .class_init = xive2_end_source_class_init, 1014 }; 1015 1016 static void xive2_register_types(void) 1017 { 1018 type_register_static(&xive2_router_info); 1019 type_register_static(&xive2_end_source_info); 1020 } 1021 1022 type_init(xive2_register_types) 1023