1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "monitor/monitor.h" 21 #include "hw/irq.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive2.h" 24 #include "hw/ppc/xive_regs.h" 25 #include "trace.h" 26 27 /* 28 * XIVE Thread Interrupt Management context 29 */ 30 31 /* 32 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 33 * Interrupt Priority Register (PIPR), which contains the priority of 34 * the most favored pending notification. 35 */ 36 static uint8_t ipb_to_pipr(uint8_t ibp) 37 { 38 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 39 } 40 41 static uint8_t exception_mask(uint8_t ring) 42 { 43 switch (ring) { 44 case TM_QW1_OS: 45 return TM_QW1_NSR_EO; 46 case TM_QW3_HV_PHYS: 47 return TM_QW3_NSR_HE; 48 default: 49 g_assert_not_reached(); 50 } 51 } 52 53 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 54 { 55 switch (ring) { 56 case TM_QW0_USER: 57 return 0; /* Not supported */ 58 case TM_QW1_OS: 59 return tctx->os_output; 60 case TM_QW2_HV_POOL: 61 case TM_QW3_HV_PHYS: 62 return tctx->hv_output; 63 default: 64 return 0; 65 } 66 } 67 68 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 69 { 70 uint8_t *regs = &tctx->regs[ring]; 71 uint8_t nsr = regs[TM_NSR]; 72 uint8_t mask = exception_mask(ring); 73 74 qemu_irq_lower(xive_tctx_output(tctx, ring)); 75 76 if (regs[TM_NSR] & mask) { 77 uint8_t cppr = regs[TM_PIPR]; 78 79 regs[TM_CPPR] = cppr; 80 81 /* Reset the pending buffer bit */ 82 regs[TM_IPB] &= ~xive_priority_to_ipb(cppr); 83 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 84 85 /* Drop Exception bit */ 86 regs[TM_NSR] &= ~mask; 87 88 trace_xive_tctx_accept(tctx->cs->cpu_index, ring, 89 regs[TM_IPB], regs[TM_PIPR], 90 regs[TM_CPPR], regs[TM_NSR]); 91 } 92 93 return (nsr << 8) | regs[TM_CPPR]; 94 } 95 96 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 97 { 98 uint8_t *regs = &tctx->regs[ring]; 99 100 if (regs[TM_PIPR] < regs[TM_CPPR]) { 101 switch (ring) { 102 case TM_QW1_OS: 103 regs[TM_NSR] |= TM_QW1_NSR_EO; 104 break; 105 case TM_QW3_HV_PHYS: 106 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 107 break; 108 default: 109 g_assert_not_reached(); 110 } 111 trace_xive_tctx_notify(tctx->cs->cpu_index, ring, 112 regs[TM_IPB], regs[TM_PIPR], 113 regs[TM_CPPR], regs[TM_NSR]); 114 qemu_irq_raise(xive_tctx_output(tctx, ring)); 115 } 116 } 117 118 void xive_tctx_reset_os_signal(XiveTCTX *tctx) 119 { 120 /* 121 * Lower the External interrupt. Used when pulling an OS 122 * context. It is necessary to avoid catching it in the hypervisor 123 * context. It should be raised again when re-pushing the OS 124 * context. 125 */ 126 qemu_irq_lower(xive_tctx_output(tctx, TM_QW1_OS)); 127 } 128 129 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 130 { 131 uint8_t *regs = &tctx->regs[ring]; 132 133 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, 134 regs[TM_IPB], regs[TM_PIPR], 135 cppr, regs[TM_NSR]); 136 137 if (cppr > XIVE_PRIORITY_MAX) { 138 cppr = 0xff; 139 } 140 141 tctx->regs[ring + TM_CPPR] = cppr; 142 143 /* CPPR has changed, check if we need to raise a pending exception */ 144 xive_tctx_notify(tctx, ring); 145 } 146 147 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) 148 { 149 uint8_t *regs = &tctx->regs[ring]; 150 151 regs[TM_IPB] |= ipb; 152 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 153 xive_tctx_notify(tctx, ring); 154 } 155 156 /* 157 * XIVE Thread Interrupt Management Area (TIMA) 158 */ 159 160 static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 161 hwaddr offset, uint64_t value, unsigned size) 162 { 163 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 164 } 165 166 static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx, 167 hwaddr offset, unsigned size) 168 { 169 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 170 } 171 172 static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 173 hwaddr offset, unsigned size) 174 { 175 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 176 uint32_t qw2w2; 177 178 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 179 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 180 return qw2w2; 181 } 182 183 static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 184 uint64_t value, unsigned size) 185 { 186 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 187 } 188 189 static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, 190 hwaddr offset, unsigned size) 191 { 192 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 193 } 194 195 /* 196 * Define an access map for each page of the TIMA that we will use in 197 * the memory region ops to filter values when doing loads and stores 198 * of raw registers values 199 * 200 * Registers accessibility bits : 201 * 202 * 0x0 - no access 203 * 0x1 - write only 204 * 0x2 - read only 205 * 0x3 - read/write 206 */ 207 208 static const uint8_t xive_tm_hw_view[] = { 209 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 210 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 211 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 212 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 213 }; 214 215 static const uint8_t xive_tm_hv_view[] = { 216 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 217 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 218 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 219 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 220 }; 221 222 static const uint8_t xive_tm_os_view[] = { 223 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 224 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 225 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 226 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 227 }; 228 229 static const uint8_t xive_tm_user_view[] = { 230 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 233 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 234 }; 235 236 /* 237 * Overall TIMA access map for the thread interrupt management context 238 * registers 239 */ 240 static const uint8_t *xive_tm_views[] = { 241 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 242 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 243 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 244 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 245 }; 246 247 /* 248 * Computes a register access mask for a given offset in the TIMA 249 */ 250 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 251 { 252 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 253 uint8_t reg_offset = offset & TM_REG_OFFSET; 254 uint8_t reg_mask = write ? 0x1 : 0x2; 255 uint64_t mask = 0x0; 256 int i; 257 258 for (i = 0; i < size; i++) { 259 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 260 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 261 } 262 } 263 264 return mask; 265 } 266 267 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 268 unsigned size) 269 { 270 uint8_t ring_offset = offset & TM_RING_OFFSET; 271 uint8_t reg_offset = offset & TM_REG_OFFSET; 272 uint64_t mask = xive_tm_mask(offset, size, true); 273 int i; 274 275 /* 276 * Only 4 or 8 bytes stores are allowed and the User ring is 277 * excluded 278 */ 279 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 280 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 281 HWADDR_PRIx"\n", offset); 282 return; 283 } 284 285 /* 286 * Use the register offset for the raw values and filter out 287 * reserved values 288 */ 289 for (i = 0; i < size; i++) { 290 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 291 if (byte_mask) { 292 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 293 byte_mask; 294 } 295 } 296 } 297 298 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 299 { 300 uint8_t ring_offset = offset & TM_RING_OFFSET; 301 uint8_t reg_offset = offset & TM_REG_OFFSET; 302 uint64_t mask = xive_tm_mask(offset, size, false); 303 uint64_t ret; 304 int i; 305 306 /* 307 * Only 4 or 8 bytes loads are allowed and the User ring is 308 * excluded 309 */ 310 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 311 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 312 HWADDR_PRIx"\n", offset); 313 return -1; 314 } 315 316 /* Use the register offset for the raw values */ 317 ret = 0; 318 for (i = 0; i < size; i++) { 319 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 320 } 321 322 /* filter out reserved values */ 323 return ret & mask; 324 } 325 326 /* 327 * The TM context is mapped twice within each page. Stores and loads 328 * to the first mapping below 2K write and read the specified values 329 * without modification. The second mapping above 2K performs specific 330 * state changes (side effects) in addition to setting/returning the 331 * interrupt management area context of the processor thread. 332 */ 333 static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx, 334 hwaddr offset, unsigned size) 335 { 336 return xive_tctx_accept(tctx, TM_QW1_OS); 337 } 338 339 static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 340 hwaddr offset, uint64_t value, unsigned size) 341 { 342 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 343 } 344 345 /* 346 * Adjust the IPB to allow a CPU to process event queues of other 347 * priorities during one physical interrupt cycle. 348 */ 349 static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, 350 hwaddr offset, uint64_t value, unsigned size) 351 { 352 xive_tctx_ipb_update(tctx, TM_QW1_OS, xive_priority_to_ipb(value & 0xff)); 353 } 354 355 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, 356 uint32_t *nvt_idx, bool *vo) 357 { 358 if (nvt_blk) { 359 *nvt_blk = xive_nvt_blk(cam); 360 } 361 if (nvt_idx) { 362 *nvt_idx = xive_nvt_idx(cam); 363 } 364 if (vo) { 365 *vo = !!(cam & TM_QW1W2_VO); 366 } 367 } 368 369 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk, 370 uint32_t *nvt_idx, bool *vo) 371 { 372 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 373 uint32_t cam = be32_to_cpu(qw1w2); 374 375 xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo); 376 return qw1w2; 377 } 378 379 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) 380 { 381 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 382 } 383 384 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 385 hwaddr offset, unsigned size) 386 { 387 uint32_t qw1w2; 388 uint32_t qw1w2_new; 389 uint8_t nvt_blk; 390 uint32_t nvt_idx; 391 bool vo; 392 393 qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); 394 395 if (!vo) { 396 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n", 397 nvt_blk, nvt_idx); 398 } 399 400 /* Invalidate CAM line */ 401 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); 402 xive_tctx_set_os_cam(tctx, qw1w2_new); 403 404 xive_tctx_reset_os_signal(tctx); 405 return qw1w2; 406 } 407 408 static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx, 409 uint8_t nvt_blk, uint32_t nvt_idx) 410 { 411 XiveNVT nvt; 412 uint8_t ipb; 413 414 /* 415 * Grab the associated NVT to pull the pending bits, and merge 416 * them with the IPB of the thread interrupt context registers 417 */ 418 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 419 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n", 420 nvt_blk, nvt_idx); 421 return; 422 } 423 424 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4); 425 426 if (ipb) { 427 /* Reset the NVT value */ 428 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0); 429 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 430 } 431 /* 432 * Always call xive_tctx_ipb_update(). Even if there were no 433 * escalation triggered, there could be a pending interrupt which 434 * was saved when the context was pulled and that we need to take 435 * into account by recalculating the PIPR (which is not 436 * saved/restored). 437 * It will also raise the External interrupt signal if needed. 438 */ 439 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); 440 } 441 442 /* 443 * Updating the OS CAM line can trigger a resend of interrupt 444 */ 445 static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 446 hwaddr offset, uint64_t value, unsigned size) 447 { 448 uint32_t cam = value; 449 uint32_t qw1w2 = cpu_to_be32(cam); 450 uint8_t nvt_blk; 451 uint32_t nvt_idx; 452 bool vo; 453 454 xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); 455 456 /* First update the registers */ 457 xive_tctx_set_os_cam(tctx, qw1w2); 458 459 /* Check the interrupt pending bits */ 460 if (vo) { 461 xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); 462 } 463 } 464 465 static uint32_t xive_presenter_get_config(XivePresenter *xptr) 466 { 467 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 468 469 return xpc->get_config(xptr); 470 } 471 472 /* 473 * Define a mapping of "special" operations depending on the TIMA page 474 * offset and the size of the operation. 475 */ 476 typedef struct XiveTmOp { 477 uint8_t page_offset; 478 uint32_t op_offset; 479 unsigned size; 480 void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, 481 hwaddr offset, 482 uint64_t value, unsigned size); 483 uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 484 unsigned size); 485 } XiveTmOp; 486 487 static const XiveTmOp xive_tm_operations[] = { 488 /* 489 * MMIOs below 2K : raw values and special operations without side 490 * effects 491 */ 492 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 493 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, NULL }, 494 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 495 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 496 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 497 498 /* MMIOs above 2K : special operations with side effects */ 499 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 500 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 501 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, 502 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, 503 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 504 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 505 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 506 }; 507 508 static const XiveTmOp xive2_tm_operations[] = { 509 /* 510 * MMIOs below 2K : raw values and special operations without side 511 * effects 512 */ 513 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 514 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx, NULL }, 515 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 516 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 517 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 518 519 /* MMIOs above 2K : special operations with side effects */ 520 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 521 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 522 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive2_tm_pull_os_ctx }, 523 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive2_tm_pull_os_ctx }, 524 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 525 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 526 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 527 }; 528 529 static const XiveTmOp *xive_tm_find_op(XivePresenter *xptr, hwaddr offset, 530 unsigned size, bool write) 531 { 532 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 533 uint32_t op_offset = offset & TM_ADDRESS_MASK; 534 const XiveTmOp *tm_ops; 535 int i, tm_ops_count; 536 uint32_t cfg; 537 538 cfg = xive_presenter_get_config(xptr); 539 if (cfg & XIVE_PRESENTER_GEN1_TIMA_OS) { 540 tm_ops = xive_tm_operations; 541 tm_ops_count = ARRAY_SIZE(xive_tm_operations); 542 } else { 543 tm_ops = xive2_tm_operations; 544 tm_ops_count = ARRAY_SIZE(xive2_tm_operations); 545 } 546 547 for (i = 0; i < tm_ops_count; i++) { 548 const XiveTmOp *xto = &tm_ops[i]; 549 550 /* Accesses done from a more privileged TIMA page is allowed */ 551 if (xto->page_offset >= page_offset && 552 xto->op_offset == op_offset && 553 xto->size == size && 554 ((write && xto->write_handler) || (!write && xto->read_handler))) { 555 return xto; 556 } 557 } 558 return NULL; 559 } 560 561 /* 562 * TIMA MMIO handlers 563 */ 564 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 565 uint64_t value, unsigned size) 566 { 567 const XiveTmOp *xto; 568 569 trace_xive_tctx_tm_write(tctx->cs->cpu_index, offset, size, value); 570 571 /* 572 * TODO: check V bit in Q[0-3]W2 573 */ 574 575 /* 576 * First, check for special operations in the 2K region 577 */ 578 if (offset & TM_SPECIAL_OP) { 579 xto = xive_tm_find_op(tctx->xptr, offset, size, true); 580 if (!xto) { 581 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 582 "@%"HWADDR_PRIx"\n", offset); 583 } else { 584 xto->write_handler(xptr, tctx, offset, value, size); 585 } 586 return; 587 } 588 589 /* 590 * Then, for special operations in the region below 2K. 591 */ 592 xto = xive_tm_find_op(tctx->xptr, offset, size, true); 593 if (xto) { 594 xto->write_handler(xptr, tctx, offset, value, size); 595 return; 596 } 597 598 /* 599 * Finish with raw access to the register values 600 */ 601 xive_tm_raw_write(tctx, offset, value, size); 602 } 603 604 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 605 unsigned size) 606 { 607 const XiveTmOp *xto; 608 uint64_t ret; 609 610 /* 611 * TODO: check V bit in Q[0-3]W2 612 */ 613 614 /* 615 * First, check for special operations in the 2K region 616 */ 617 if (offset & TM_SPECIAL_OP) { 618 xto = xive_tm_find_op(tctx->xptr, offset, size, false); 619 if (!xto) { 620 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 621 "@%"HWADDR_PRIx"\n", offset); 622 return -1; 623 } 624 ret = xto->read_handler(xptr, tctx, offset, size); 625 goto out; 626 } 627 628 /* 629 * Then, for special operations in the region below 2K. 630 */ 631 xto = xive_tm_find_op(tctx->xptr, offset, size, false); 632 if (xto) { 633 ret = xto->read_handler(xptr, tctx, offset, size); 634 goto out; 635 } 636 637 /* 638 * Finish with raw access to the register values 639 */ 640 ret = xive_tm_raw_read(tctx, offset, size); 641 out: 642 trace_xive_tctx_tm_read(tctx->cs->cpu_index, offset, size, ret); 643 return ret; 644 } 645 646 static char *xive_tctx_ring_print(uint8_t *ring) 647 { 648 uint32_t w2 = xive_tctx_word2(ring); 649 650 return g_strdup_printf("%02x %02x %02x %02x %02x " 651 "%02x %02x %02x %08x", 652 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 653 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 654 be32_to_cpu(w2)); 655 } 656 657 static const char * const xive_tctx_ring_names[] = { 658 "USER", "OS", "POOL", "PHYS", 659 }; 660 661 /* 662 * kvm_irqchip_in_kernel() will cause the compiler to turn this 663 * info a nop if CONFIG_KVM isn't defined. 664 */ 665 #define xive_in_kernel(xptr) \ 666 (kvm_irqchip_in_kernel() && \ 667 ({ \ 668 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); \ 669 xpc->in_kernel ? xpc->in_kernel(xptr) : false; \ 670 })) 671 672 void xive_tctx_pic_print_info(XiveTCTX *tctx, GString *buf) 673 { 674 int cpu_index; 675 int i; 676 677 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs 678 * are hot plugged or unplugged. 679 */ 680 if (!tctx) { 681 return; 682 } 683 684 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 685 686 if (xive_in_kernel(tctx->xptr)) { 687 Error *local_err = NULL; 688 689 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 690 if (local_err) { 691 error_report_err(local_err); 692 return; 693 } 694 } 695 696 g_string_append_printf(buf, "CPU[%04x]: " 697 "QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR W2\n", 698 cpu_index); 699 700 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 701 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 702 g_string_append_printf(buf, "CPU[%04x]: %4s %s\n", 703 cpu_index, xive_tctx_ring_names[i], s); 704 g_free(s); 705 } 706 } 707 708 void xive_tctx_reset(XiveTCTX *tctx) 709 { 710 memset(tctx->regs, 0, sizeof(tctx->regs)); 711 712 /* Set some defaults */ 713 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 714 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 715 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 716 717 /* 718 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 719 * CPPR is first set. 720 */ 721 tctx->regs[TM_QW1_OS + TM_PIPR] = 722 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 723 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 724 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 725 } 726 727 static void xive_tctx_realize(DeviceState *dev, Error **errp) 728 { 729 XiveTCTX *tctx = XIVE_TCTX(dev); 730 PowerPCCPU *cpu; 731 CPUPPCState *env; 732 733 assert(tctx->cs); 734 assert(tctx->xptr); 735 736 cpu = POWERPC_CPU(tctx->cs); 737 env = &cpu->env; 738 switch (PPC_INPUT(env)) { 739 case PPC_FLAGS_INPUT_POWER9: 740 tctx->hv_output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_HINT); 741 tctx->os_output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_INT); 742 break; 743 744 default: 745 error_setg(errp, "XIVE interrupt controller does not support " 746 "this CPU bus model"); 747 return; 748 } 749 750 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 751 if (xive_in_kernel(tctx->xptr)) { 752 if (kvmppc_xive_cpu_connect(tctx, errp) < 0) { 753 return; 754 } 755 } 756 } 757 758 static int vmstate_xive_tctx_pre_save(void *opaque) 759 { 760 XiveTCTX *tctx = XIVE_TCTX(opaque); 761 Error *local_err = NULL; 762 int ret; 763 764 if (xive_in_kernel(tctx->xptr)) { 765 ret = kvmppc_xive_cpu_get_state(tctx, &local_err); 766 if (ret < 0) { 767 error_report_err(local_err); 768 return ret; 769 } 770 } 771 772 return 0; 773 } 774 775 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 776 { 777 XiveTCTX *tctx = XIVE_TCTX(opaque); 778 Error *local_err = NULL; 779 int ret; 780 781 if (xive_in_kernel(tctx->xptr)) { 782 /* 783 * Required for hotplugged CPU, for which the state comes 784 * after all states of the machine. 785 */ 786 ret = kvmppc_xive_cpu_set_state(tctx, &local_err); 787 if (ret < 0) { 788 error_report_err(local_err); 789 return ret; 790 } 791 } 792 793 return 0; 794 } 795 796 static const VMStateDescription vmstate_xive_tctx = { 797 .name = TYPE_XIVE_TCTX, 798 .version_id = 1, 799 .minimum_version_id = 1, 800 .pre_save = vmstate_xive_tctx_pre_save, 801 .post_load = vmstate_xive_tctx_post_load, 802 .fields = (const VMStateField[]) { 803 VMSTATE_BUFFER(regs, XiveTCTX), 804 VMSTATE_END_OF_LIST() 805 }, 806 }; 807 808 static Property xive_tctx_properties[] = { 809 DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), 810 DEFINE_PROP_LINK("presenter", XiveTCTX, xptr, TYPE_XIVE_PRESENTER, 811 XivePresenter *), 812 DEFINE_PROP_END_OF_LIST(), 813 }; 814 815 static void xive_tctx_class_init(ObjectClass *klass, void *data) 816 { 817 DeviceClass *dc = DEVICE_CLASS(klass); 818 819 dc->desc = "XIVE Interrupt Thread Context"; 820 dc->realize = xive_tctx_realize; 821 dc->vmsd = &vmstate_xive_tctx; 822 device_class_set_props(dc, xive_tctx_properties); 823 /* 824 * Reason: part of XIVE interrupt controller, needs to be wired up 825 * by xive_tctx_create(). 826 */ 827 dc->user_creatable = false; 828 } 829 830 static const TypeInfo xive_tctx_info = { 831 .name = TYPE_XIVE_TCTX, 832 .parent = TYPE_DEVICE, 833 .instance_size = sizeof(XiveTCTX), 834 .class_init = xive_tctx_class_init, 835 }; 836 837 Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp) 838 { 839 Object *obj; 840 841 obj = object_new(TYPE_XIVE_TCTX); 842 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj); 843 object_unref(obj); 844 object_property_set_link(obj, "cpu", cpu, &error_abort); 845 object_property_set_link(obj, "presenter", OBJECT(xptr), &error_abort); 846 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 847 object_unparent(obj); 848 return NULL; 849 } 850 return obj; 851 } 852 853 void xive_tctx_destroy(XiveTCTX *tctx) 854 { 855 Object *obj = OBJECT(tctx); 856 857 object_unparent(obj); 858 } 859 860 /* 861 * XIVE ESB helpers 862 */ 863 864 uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 865 { 866 uint8_t old_pq = *pq & 0x3; 867 868 *pq &= ~0x3; 869 *pq |= value & 0x3; 870 871 return old_pq; 872 } 873 874 bool xive_esb_trigger(uint8_t *pq) 875 { 876 uint8_t old_pq = *pq & 0x3; 877 878 switch (old_pq) { 879 case XIVE_ESB_RESET: 880 xive_esb_set(pq, XIVE_ESB_PENDING); 881 return true; 882 case XIVE_ESB_PENDING: 883 case XIVE_ESB_QUEUED: 884 xive_esb_set(pq, XIVE_ESB_QUEUED); 885 return false; 886 case XIVE_ESB_OFF: 887 xive_esb_set(pq, XIVE_ESB_OFF); 888 return false; 889 default: 890 g_assert_not_reached(); 891 } 892 } 893 894 bool xive_esb_eoi(uint8_t *pq) 895 { 896 uint8_t old_pq = *pq & 0x3; 897 898 switch (old_pq) { 899 case XIVE_ESB_RESET: 900 case XIVE_ESB_PENDING: 901 xive_esb_set(pq, XIVE_ESB_RESET); 902 return false; 903 case XIVE_ESB_QUEUED: 904 xive_esb_set(pq, XIVE_ESB_PENDING); 905 return true; 906 case XIVE_ESB_OFF: 907 xive_esb_set(pq, XIVE_ESB_OFF); 908 return false; 909 default: 910 g_assert_not_reached(); 911 } 912 } 913 914 /* 915 * XIVE Interrupt Source (or IVSE) 916 */ 917 918 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 919 { 920 assert(srcno < xsrc->nr_irqs); 921 922 return xsrc->status[srcno] & 0x3; 923 } 924 925 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 926 { 927 assert(srcno < xsrc->nr_irqs); 928 929 return xive_esb_set(&xsrc->status[srcno], pq); 930 } 931 932 /* 933 * Returns whether the event notification should be forwarded. 934 */ 935 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 936 { 937 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 938 939 xive_source_set_asserted(xsrc, srcno, true); 940 941 switch (old_pq) { 942 case XIVE_ESB_RESET: 943 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 944 return true; 945 default: 946 return false; 947 } 948 } 949 950 /* 951 * Sources can be configured with PQ offloading in which case the check 952 * on the PQ state bits of MSIs is disabled 953 */ 954 static bool xive_source_esb_disabled(XiveSource *xsrc, uint32_t srcno) 955 { 956 return (xsrc->esb_flags & XIVE_SRC_PQ_DISABLE) && 957 !xive_source_irq_is_lsi(xsrc, srcno); 958 } 959 960 /* 961 * Returns whether the event notification should be forwarded. 962 */ 963 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 964 { 965 bool ret; 966 967 assert(srcno < xsrc->nr_irqs); 968 969 if (xive_source_esb_disabled(xsrc, srcno)) { 970 return true; 971 } 972 973 ret = xive_esb_trigger(&xsrc->status[srcno]); 974 975 if (xive_source_irq_is_lsi(xsrc, srcno) && 976 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 977 qemu_log_mask(LOG_GUEST_ERROR, 978 "XIVE: queued an event on LSI IRQ %d\n", srcno); 979 } 980 981 return ret; 982 } 983 984 /* 985 * Returns whether the event notification should be forwarded. 986 */ 987 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 988 { 989 bool ret; 990 991 assert(srcno < xsrc->nr_irqs); 992 993 if (xive_source_esb_disabled(xsrc, srcno)) { 994 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EOI for IRQ %d\n", srcno); 995 return false; 996 } 997 998 ret = xive_esb_eoi(&xsrc->status[srcno]); 999 1000 /* 1001 * LSI sources do not set the Q bit but they can still be 1002 * asserted, in which case we should forward a new event 1003 * notification 1004 */ 1005 if (xive_source_irq_is_lsi(xsrc, srcno) && 1006 xive_source_is_asserted(xsrc, srcno)) { 1007 ret = xive_source_lsi_trigger(xsrc, srcno); 1008 } 1009 1010 return ret; 1011 } 1012 1013 /* 1014 * Forward the source event notification to the Router 1015 */ 1016 static void xive_source_notify(XiveSource *xsrc, int srcno) 1017 { 1018 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 1019 bool pq_checked = !xive_source_esb_disabled(xsrc, srcno); 1020 1021 if (xnc->notify) { 1022 xnc->notify(xsrc->xive, srcno, pq_checked); 1023 } 1024 } 1025 1026 /* 1027 * In a two pages ESB MMIO setting, even page is the trigger page, odd 1028 * page is for management 1029 */ 1030 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 1031 { 1032 return !((addr >> shift) & 1); 1033 } 1034 1035 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 1036 { 1037 return xive_source_esb_has_2page(xsrc) && 1038 addr_is_even(addr, xsrc->esb_shift - 1); 1039 } 1040 1041 /* 1042 * ESB MMIO loads 1043 * Trigger page Management/EOI page 1044 * 1045 * ESB MMIO setting 2 pages 1 or 2 pages 1046 * 1047 * 0x000 .. 0x3FF -1 EOI and return 0|1 1048 * 0x400 .. 0x7FF -1 EOI and return 0|1 1049 * 0x800 .. 0xBFF -1 return PQ 1050 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 1051 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 1052 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 1053 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 1054 */ 1055 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 1056 { 1057 XiveSource *xsrc = XIVE_SOURCE(opaque); 1058 uint32_t offset = addr & 0xFFF; 1059 uint32_t srcno = addr >> xsrc->esb_shift; 1060 uint64_t ret = -1; 1061 1062 /* In a two pages ESB MMIO setting, trigger page should not be read */ 1063 if (xive_source_is_trigger_page(xsrc, addr)) { 1064 qemu_log_mask(LOG_GUEST_ERROR, 1065 "XIVE: invalid load on IRQ %d trigger page at " 1066 "0x%"HWADDR_PRIx"\n", srcno, addr); 1067 return -1; 1068 } 1069 1070 switch (offset) { 1071 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1072 ret = xive_source_esb_eoi(xsrc, srcno); 1073 1074 /* Forward the source event notification for routing */ 1075 if (ret) { 1076 xive_source_notify(xsrc, srcno); 1077 } 1078 break; 1079 1080 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1081 ret = xive_source_esb_get(xsrc, srcno); 1082 break; 1083 1084 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1085 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1086 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1087 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1088 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1089 break; 1090 default: 1091 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 1092 offset); 1093 } 1094 1095 trace_xive_source_esb_read(addr, srcno, ret); 1096 1097 return ret; 1098 } 1099 1100 /* 1101 * ESB MMIO stores 1102 * Trigger page Management/EOI page 1103 * 1104 * ESB MMIO setting 2 pages 1 or 2 pages 1105 * 1106 * 0x000 .. 0x3FF Trigger Trigger 1107 * 0x400 .. 0x7FF Trigger EOI 1108 * 0x800 .. 0xBFF Trigger undefined 1109 * 0xC00 .. 0xCFF Trigger PQ=00 1110 * 0xD00 .. 0xDFF Trigger PQ=01 1111 * 0xE00 .. 0xDFF Trigger PQ=10 1112 * 0xF00 .. 0xDFF Trigger PQ=11 1113 */ 1114 static void xive_source_esb_write(void *opaque, hwaddr addr, 1115 uint64_t value, unsigned size) 1116 { 1117 XiveSource *xsrc = XIVE_SOURCE(opaque); 1118 uint32_t offset = addr & 0xFFF; 1119 uint32_t srcno = addr >> xsrc->esb_shift; 1120 bool notify = false; 1121 1122 trace_xive_source_esb_write(addr, srcno, value); 1123 1124 /* In a two pages ESB MMIO setting, trigger page only triggers */ 1125 if (xive_source_is_trigger_page(xsrc, addr)) { 1126 notify = xive_source_esb_trigger(xsrc, srcno); 1127 goto out; 1128 } 1129 1130 switch (offset) { 1131 case 0 ... 0x3FF: 1132 notify = xive_source_esb_trigger(xsrc, srcno); 1133 break; 1134 1135 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 1136 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 1137 qemu_log_mask(LOG_GUEST_ERROR, 1138 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 1139 return; 1140 } 1141 1142 notify = xive_source_esb_eoi(xsrc, srcno); 1143 break; 1144 1145 /* 1146 * This is an internal offset used to inject triggers when the PQ 1147 * state bits are not controlled locally. Such as for LSIs when 1148 * under ABT mode. 1149 */ 1150 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: 1151 notify = true; 1152 break; 1153 1154 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1155 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1156 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1157 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1158 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1159 break; 1160 1161 default: 1162 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 1163 offset); 1164 return; 1165 } 1166 1167 out: 1168 /* Forward the source event notification for routing */ 1169 if (notify) { 1170 xive_source_notify(xsrc, srcno); 1171 } 1172 } 1173 1174 static const MemoryRegionOps xive_source_esb_ops = { 1175 .read = xive_source_esb_read, 1176 .write = xive_source_esb_write, 1177 .endianness = DEVICE_BIG_ENDIAN, 1178 .valid = { 1179 .min_access_size = 1, 1180 .max_access_size = 8, 1181 }, 1182 .impl = { 1183 .min_access_size = 1, 1184 .max_access_size = 8, 1185 }, 1186 }; 1187 1188 void xive_source_set_irq(void *opaque, int srcno, int val) 1189 { 1190 XiveSource *xsrc = XIVE_SOURCE(opaque); 1191 bool notify = false; 1192 1193 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1194 if (val) { 1195 notify = xive_source_lsi_trigger(xsrc, srcno); 1196 } else { 1197 xive_source_set_asserted(xsrc, srcno, false); 1198 } 1199 } else { 1200 if (val) { 1201 notify = xive_source_esb_trigger(xsrc, srcno); 1202 } 1203 } 1204 1205 /* Forward the source event notification for routing */ 1206 if (notify) { 1207 xive_source_notify(xsrc, srcno); 1208 } 1209 } 1210 1211 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 1212 { 1213 int i; 1214 1215 for (i = 0; i < xsrc->nr_irqs; i++) { 1216 uint8_t pq = xive_source_esb_get(xsrc, i); 1217 1218 if (pq == XIVE_ESB_OFF) { 1219 continue; 1220 } 1221 1222 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 1223 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1224 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1225 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1226 xive_source_is_asserted(xsrc, i) ? 'A' : ' '); 1227 } 1228 } 1229 1230 static void xive_source_reset(void *dev) 1231 { 1232 XiveSource *xsrc = XIVE_SOURCE(dev); 1233 1234 /* Do not clear the LSI bitmap */ 1235 1236 memset(xsrc->status, xsrc->reset_pq, xsrc->nr_irqs); 1237 } 1238 1239 static void xive_source_realize(DeviceState *dev, Error **errp) 1240 { 1241 XiveSource *xsrc = XIVE_SOURCE(dev); 1242 size_t esb_len = xive_source_esb_len(xsrc); 1243 1244 assert(xsrc->xive); 1245 1246 if (!xsrc->nr_irqs) { 1247 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1248 return; 1249 } 1250 1251 if (xsrc->esb_shift != XIVE_ESB_4K && 1252 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1253 xsrc->esb_shift != XIVE_ESB_64K && 1254 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1255 error_setg(errp, "Invalid ESB shift setting"); 1256 return; 1257 } 1258 1259 xsrc->status = g_malloc0(xsrc->nr_irqs); 1260 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1261 1262 memory_region_init(&xsrc->esb_mmio, OBJECT(xsrc), "xive.esb", esb_len); 1263 memory_region_init_io(&xsrc->esb_mmio_emulated, OBJECT(xsrc), 1264 &xive_source_esb_ops, xsrc, "xive.esb-emulated", 1265 esb_len); 1266 memory_region_add_subregion(&xsrc->esb_mmio, 0, &xsrc->esb_mmio_emulated); 1267 1268 qemu_register_reset(xive_source_reset, dev); 1269 } 1270 1271 static const VMStateDescription vmstate_xive_source = { 1272 .name = TYPE_XIVE_SOURCE, 1273 .version_id = 1, 1274 .minimum_version_id = 1, 1275 .fields = (const VMStateField[]) { 1276 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1277 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1278 VMSTATE_END_OF_LIST() 1279 }, 1280 }; 1281 1282 /* 1283 * The default XIVE interrupt source setting for the ESB MMIOs is two 1284 * 64k pages without Store EOI, to be in sync with KVM. 1285 */ 1286 static Property xive_source_properties[] = { 1287 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1288 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1289 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1290 /* 1291 * By default, PQs are initialized to 0b01 (Q=1) which corresponds 1292 * to "ints off" 1293 */ 1294 DEFINE_PROP_UINT8("reset-pq", XiveSource, reset_pq, XIVE_ESB_OFF), 1295 DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, 1296 XiveNotifier *), 1297 DEFINE_PROP_END_OF_LIST(), 1298 }; 1299 1300 static void xive_source_class_init(ObjectClass *klass, void *data) 1301 { 1302 DeviceClass *dc = DEVICE_CLASS(klass); 1303 1304 dc->desc = "XIVE Interrupt Source"; 1305 device_class_set_props(dc, xive_source_properties); 1306 dc->realize = xive_source_realize; 1307 dc->vmsd = &vmstate_xive_source; 1308 /* 1309 * Reason: part of XIVE interrupt controller, needs to be wired up, 1310 * e.g. by spapr_xive_instance_init(). 1311 */ 1312 dc->user_creatable = false; 1313 } 1314 1315 static const TypeInfo xive_source_info = { 1316 .name = TYPE_XIVE_SOURCE, 1317 .parent = TYPE_DEVICE, 1318 .instance_size = sizeof(XiveSource), 1319 .class_init = xive_source_class_init, 1320 }; 1321 1322 /* 1323 * XiveEND helpers 1324 */ 1325 1326 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1327 { 1328 uint64_t qaddr_base = xive_end_qaddr(end); 1329 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1330 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1331 uint32_t qentries = 1 << (qsize + 10); 1332 int i; 1333 1334 /* 1335 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1336 */ 1337 monitor_printf(mon, " [ "); 1338 qindex = (qindex - (width - 1)) & (qentries - 1); 1339 for (i = 0; i < width; i++) { 1340 uint64_t qaddr = qaddr_base + (qindex << 2); 1341 uint32_t qdata = -1; 1342 1343 if (dma_memory_read(&address_space_memory, qaddr, 1344 &qdata, sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 1345 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1346 HWADDR_PRIx "\n", qaddr); 1347 return; 1348 } 1349 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1350 be32_to_cpu(qdata)); 1351 qindex = (qindex + 1) & (qentries - 1); 1352 } 1353 monitor_printf(mon, "]"); 1354 } 1355 1356 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1357 { 1358 uint64_t qaddr_base = xive_end_qaddr(end); 1359 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1360 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1361 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1362 uint32_t qentries = 1 << (qsize + 10); 1363 1364 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1365 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1366 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1367 uint8_t pq; 1368 1369 if (!xive_end_is_valid(end)) { 1370 return; 1371 } 1372 1373 pq = xive_get_field32(END_W1_ESn, end->w1); 1374 1375 monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1376 end_idx, 1377 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1378 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1379 xive_end_is_valid(end) ? 'v' : '-', 1380 xive_end_is_enqueue(end) ? 'q' : '-', 1381 xive_end_is_notify(end) ? 'n' : '-', 1382 xive_end_is_backlog(end) ? 'b' : '-', 1383 xive_end_is_escalate(end) ? 'e' : '-', 1384 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1385 xive_end_is_silent_escalation(end) ? 's' : '-', 1386 xive_end_is_firmware(end) ? 'f' : '-', 1387 priority, nvt_blk, nvt_idx); 1388 1389 if (qaddr_base) { 1390 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1391 qaddr_base, qindex, qentries, qgen); 1392 xive_end_queue_pic_print_info(end, 6, mon); 1393 } 1394 monitor_printf(mon, "\n"); 1395 } 1396 1397 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1398 { 1399 uint64_t qaddr_base = xive_end_qaddr(end); 1400 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1401 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1402 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1403 1404 uint64_t qaddr = qaddr_base + (qindex << 2); 1405 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1406 uint32_t qentries = 1 << (qsize + 10); 1407 1408 if (dma_memory_write(&address_space_memory, qaddr, 1409 &qdata, sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 1410 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1411 HWADDR_PRIx "\n", qaddr); 1412 return; 1413 } 1414 1415 qindex = (qindex + 1) & (qentries - 1); 1416 if (qindex == 0) { 1417 qgen ^= 1; 1418 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1419 } 1420 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1421 } 1422 1423 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, 1424 Monitor *mon) 1425 { 1426 XiveEAS *eas = (XiveEAS *) &end->w4; 1427 uint8_t pq; 1428 1429 if (!xive_end_is_escalate(end)) { 1430 return; 1431 } 1432 1433 pq = xive_get_field32(END_W1_ESe, end->w1); 1434 1435 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1436 end_idx, 1437 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1438 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1439 xive_eas_is_valid(eas) ? 'V' : ' ', 1440 xive_eas_is_masked(eas) ? 'M' : ' ', 1441 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1442 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1443 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1444 } 1445 1446 /* 1447 * XIVE Router (aka. Virtualization Controller or IVRE) 1448 */ 1449 1450 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1451 XiveEAS *eas) 1452 { 1453 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1454 1455 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1456 } 1457 1458 static 1459 int xive_router_get_pq(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1460 uint8_t *pq) 1461 { 1462 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1463 1464 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); 1465 } 1466 1467 static 1468 int xive_router_set_pq(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1469 uint8_t *pq) 1470 { 1471 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1472 1473 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); 1474 } 1475 1476 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1477 XiveEND *end) 1478 { 1479 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1480 1481 return xrc->get_end(xrtr, end_blk, end_idx, end); 1482 } 1483 1484 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1485 XiveEND *end, uint8_t word_number) 1486 { 1487 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1488 1489 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1490 } 1491 1492 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1493 XiveNVT *nvt) 1494 { 1495 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1496 1497 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1498 } 1499 1500 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1501 XiveNVT *nvt, uint8_t word_number) 1502 { 1503 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1504 1505 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1506 } 1507 1508 static int xive_router_get_block_id(XiveRouter *xrtr) 1509 { 1510 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1511 1512 return xrc->get_block_id(xrtr); 1513 } 1514 1515 static void xive_router_realize(DeviceState *dev, Error **errp) 1516 { 1517 XiveRouter *xrtr = XIVE_ROUTER(dev); 1518 1519 assert(xrtr->xfb); 1520 } 1521 1522 static void xive_router_end_notify_handler(XiveRouter *xrtr, XiveEAS *eas) 1523 { 1524 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1525 1526 return xrc->end_notify(xrtr, eas); 1527 } 1528 1529 /* 1530 * Encode the HW CAM line in the block group mode format : 1531 * 1532 * chip << 19 | 0000000 0 0001 thread (7Bit) 1533 */ 1534 static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 1535 { 1536 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1537 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1538 uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr)); 1539 1540 return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); 1541 } 1542 1543 /* 1544 * The thread context register words are in big-endian format. 1545 */ 1546 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1547 uint8_t format, 1548 uint8_t nvt_blk, uint32_t nvt_idx, 1549 bool cam_ignore, uint32_t logic_serv) 1550 { 1551 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1552 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1553 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1554 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1555 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1556 1557 /* 1558 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1559 * identifier are ignored in the "CAM" match. 1560 */ 1561 1562 if (format == 0) { 1563 if (cam_ignore == true) { 1564 /* 1565 * F=0 & i=1: Logical server notification (bits ignored at 1566 * the end of the NVT identifier) 1567 */ 1568 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1569 nvt_blk, nvt_idx); 1570 return -1; 1571 } 1572 1573 /* F=0 & i=0: Specific NVT notification */ 1574 1575 /* PHYS ring */ 1576 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1577 cam == xive_tctx_hw_cam_line(xptr, tctx)) { 1578 return TM_QW3_HV_PHYS; 1579 } 1580 1581 /* HV POOL ring */ 1582 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1583 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1584 return TM_QW2_HV_POOL; 1585 } 1586 1587 /* OS ring */ 1588 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1589 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1590 return TM_QW1_OS; 1591 } 1592 } else { 1593 /* F=1 : User level Event-Based Branch (EBB) notification */ 1594 1595 /* USER ring */ 1596 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1597 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1598 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1599 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1600 return TM_QW0_USER; 1601 } 1602 } 1603 return -1; 1604 } 1605 1606 /* 1607 * This is our simple Xive Presenter Engine model. It is merged in the 1608 * Router as it does not require an extra object. 1609 * 1610 * It receives notification requests sent by the IVRE to find one 1611 * matching NVT (or more) dispatched on the processor threads. In case 1612 * of a single NVT notification, the process is abbreviated and the 1613 * thread is signaled if a match is found. In case of a logical server 1614 * notification (bits ignored at the end of the NVT identifier), the 1615 * IVPE and IVRE select a winning thread using different filters. This 1616 * involves 2 or 3 exchanges on the PowerBus that the model does not 1617 * support. 1618 * 1619 * The parameters represent what is sent on the PowerBus 1620 */ 1621 bool xive_presenter_notify(XiveFabric *xfb, uint8_t format, 1622 uint8_t nvt_blk, uint32_t nvt_idx, 1623 bool cam_ignore, uint8_t priority, 1624 uint32_t logic_serv) 1625 { 1626 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb); 1627 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1628 int count; 1629 1630 /* 1631 * Ask the machine to scan the interrupt controllers for a match 1632 */ 1633 count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore, 1634 priority, logic_serv, &match); 1635 if (count < 0) { 1636 return false; 1637 } 1638 1639 /* handle CPU exception delivery */ 1640 if (count) { 1641 trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring); 1642 xive_tctx_ipb_update(match.tctx, match.ring, 1643 xive_priority_to_ipb(priority)); 1644 } 1645 1646 return !!count; 1647 } 1648 1649 /* 1650 * Notification using the END ESe/ESn bit (Event State Buffer for 1651 * escalation and notification). Provide further coalescing in the 1652 * Router. 1653 */ 1654 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1655 uint32_t end_idx, XiveEND *end, 1656 uint32_t end_esmask) 1657 { 1658 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1659 bool notify = xive_esb_trigger(&pq); 1660 1661 if (pq != xive_get_field32(end_esmask, end->w1)) { 1662 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1663 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1664 } 1665 1666 /* ESe/n[Q]=1 : end of notification */ 1667 return notify; 1668 } 1669 1670 /* 1671 * An END trigger can come from an event trigger (IPI or HW) or from 1672 * another chip. We don't model the PowerBus but the END trigger 1673 * message has the same parameters than in the function below. 1674 */ 1675 void xive_router_end_notify(XiveRouter *xrtr, XiveEAS *eas) 1676 { 1677 XiveEND end; 1678 uint8_t priority; 1679 uint8_t format; 1680 uint8_t nvt_blk; 1681 uint32_t nvt_idx; 1682 XiveNVT nvt; 1683 bool found; 1684 1685 uint8_t end_blk = xive_get_field64(EAS_END_BLOCK, eas->w); 1686 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 1687 uint32_t end_data = xive_get_field64(EAS_END_DATA, eas->w); 1688 1689 /* END cache lookup */ 1690 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1691 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1692 end_idx); 1693 return; 1694 } 1695 1696 if (!xive_end_is_valid(&end)) { 1697 trace_xive_router_end_notify(end_blk, end_idx, end_data); 1698 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1699 end_blk, end_idx); 1700 return; 1701 } 1702 1703 if (xive_end_is_enqueue(&end)) { 1704 xive_end_enqueue(&end, end_data); 1705 /* Enqueuing event data modifies the EQ toggle and index */ 1706 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1707 } 1708 1709 /* 1710 * When the END is silent, we skip the notification part. 1711 */ 1712 if (xive_end_is_silent_escalation(&end)) { 1713 goto do_escalation; 1714 } 1715 1716 /* 1717 * The W7 format depends on the F bit in W6. It defines the type 1718 * of the notification : 1719 * 1720 * F=0 : single or multiple NVT notification 1721 * F=1 : User level Event-Based Branch (EBB) notification, no 1722 * priority 1723 */ 1724 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1725 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1726 1727 /* The END is masked */ 1728 if (format == 0 && priority == 0xff) { 1729 return; 1730 } 1731 1732 /* 1733 * Check the END ESn (Event State Buffer for notification) for 1734 * even further coalescing in the Router 1735 */ 1736 if (!xive_end_is_notify(&end)) { 1737 /* ESn[Q]=1 : end of notification */ 1738 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1739 &end, END_W1_ESn)) { 1740 return; 1741 } 1742 } 1743 1744 /* 1745 * Follows IVPE notification 1746 */ 1747 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1748 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1749 1750 /* NVT cache lookup */ 1751 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1752 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1753 nvt_blk, nvt_idx); 1754 return; 1755 } 1756 1757 if (!xive_nvt_is_valid(&nvt)) { 1758 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1759 nvt_blk, nvt_idx); 1760 return; 1761 } 1762 1763 found = xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx, 1764 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1765 priority, 1766 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1767 1768 /* TODO: Auto EOI. */ 1769 1770 if (found) { 1771 return; 1772 } 1773 1774 /* 1775 * If no matching NVT is dispatched on a HW thread : 1776 * - specific VP: update the NVT structure if backlog is activated 1777 * - logical server : forward request to IVPE (not supported) 1778 */ 1779 if (xive_end_is_backlog(&end)) { 1780 uint8_t ipb; 1781 1782 if (format == 1) { 1783 qemu_log_mask(LOG_GUEST_ERROR, 1784 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1785 end_blk, end_idx); 1786 return; 1787 } 1788 /* 1789 * Record the IPB in the associated NVT structure for later 1790 * use. The presenter will resend the interrupt when the vCPU 1791 * is dispatched again on a HW thread. 1792 */ 1793 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | 1794 xive_priority_to_ipb(priority); 1795 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); 1796 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1797 1798 /* 1799 * On HW, follows a "Broadcast Backlog" to IVPEs 1800 */ 1801 } 1802 1803 do_escalation: 1804 /* 1805 * If activated, escalate notification using the ESe PQ bits and 1806 * the EAS in w4-5 1807 */ 1808 if (!xive_end_is_escalate(&end)) { 1809 return; 1810 } 1811 1812 /* 1813 * Check the END ESe (Event State Buffer for escalation) for even 1814 * further coalescing in the Router 1815 */ 1816 if (!xive_end_is_uncond_escalation(&end)) { 1817 /* ESe[Q]=1 : end of notification */ 1818 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1819 &end, END_W1_ESe)) { 1820 return; 1821 } 1822 } 1823 1824 trace_xive_router_end_escalate(end_blk, end_idx, 1825 (uint8_t) xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1826 (uint32_t) xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1827 (uint32_t) xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1828 /* 1829 * The END trigger becomes an Escalation trigger 1830 */ 1831 xive_router_end_notify_handler(xrtr, (XiveEAS *) &end.w4); 1832 } 1833 1834 void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) 1835 { 1836 XiveRouter *xrtr = XIVE_ROUTER(xn); 1837 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1838 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1839 XiveEAS eas; 1840 1841 /* EAS cache lookup */ 1842 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1843 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1844 return; 1845 } 1846 1847 if (!pq_checked) { 1848 bool notify; 1849 uint8_t pq; 1850 1851 /* PQ cache lookup */ 1852 if (xive_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) { 1853 /* Set FIR */ 1854 g_assert_not_reached(); 1855 } 1856 1857 notify = xive_esb_trigger(&pq); 1858 1859 if (xive_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) { 1860 /* Set FIR */ 1861 g_assert_not_reached(); 1862 } 1863 1864 if (!notify) { 1865 return; 1866 } 1867 } 1868 1869 if (!xive_eas_is_valid(&eas)) { 1870 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1871 return; 1872 } 1873 1874 if (xive_eas_is_masked(&eas)) { 1875 /* Notification completed */ 1876 return; 1877 } 1878 1879 /* 1880 * The event trigger becomes an END trigger 1881 */ 1882 xive_router_end_notify_handler(xrtr, &eas); 1883 } 1884 1885 static Property xive_router_properties[] = { 1886 DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb, 1887 TYPE_XIVE_FABRIC, XiveFabric *), 1888 DEFINE_PROP_END_OF_LIST(), 1889 }; 1890 1891 static void xive_router_class_init(ObjectClass *klass, void *data) 1892 { 1893 DeviceClass *dc = DEVICE_CLASS(klass); 1894 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1895 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 1896 1897 dc->desc = "XIVE Router Engine"; 1898 device_class_set_props(dc, xive_router_properties); 1899 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 1900 dc->realize = xive_router_realize; 1901 xnc->notify = xive_router_notify; 1902 1903 /* By default, the router handles END triggers locally */ 1904 xrc->end_notify = xive_router_end_notify; 1905 } 1906 1907 static const TypeInfo xive_router_info = { 1908 .name = TYPE_XIVE_ROUTER, 1909 .parent = TYPE_SYS_BUS_DEVICE, 1910 .abstract = true, 1911 .instance_size = sizeof(XiveRouter), 1912 .class_size = sizeof(XiveRouterClass), 1913 .class_init = xive_router_class_init, 1914 .interfaces = (InterfaceInfo[]) { 1915 { TYPE_XIVE_NOTIFIER }, 1916 { TYPE_XIVE_PRESENTER }, 1917 { } 1918 } 1919 }; 1920 1921 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1922 { 1923 if (!xive_eas_is_valid(eas)) { 1924 return; 1925 } 1926 1927 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1928 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1929 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1930 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1931 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1932 } 1933 1934 /* 1935 * END ESB MMIO loads 1936 */ 1937 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1938 { 1939 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1940 uint32_t offset = addr & 0xFFF; 1941 uint8_t end_blk; 1942 uint32_t end_idx; 1943 XiveEND end; 1944 uint32_t end_esmask; 1945 uint8_t pq; 1946 uint64_t ret = -1; 1947 1948 /* 1949 * The block id should be deduced from the load address on the END 1950 * ESB MMIO but our model only supports a single block per XIVE chip. 1951 */ 1952 end_blk = xive_router_get_block_id(xsrc->xrtr); 1953 end_idx = addr >> (xsrc->esb_shift + 1); 1954 1955 trace_xive_end_source_read(end_blk, end_idx, addr); 1956 1957 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1958 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1959 end_idx); 1960 return -1; 1961 } 1962 1963 if (!xive_end_is_valid(&end)) { 1964 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1965 end_blk, end_idx); 1966 return -1; 1967 } 1968 1969 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1970 pq = xive_get_field32(end_esmask, end.w1); 1971 1972 switch (offset) { 1973 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1974 ret = xive_esb_eoi(&pq); 1975 1976 /* Forward the source event notification for routing ?? */ 1977 break; 1978 1979 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1980 ret = pq; 1981 break; 1982 1983 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1984 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1985 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1986 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1987 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1988 break; 1989 default: 1990 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1991 offset); 1992 return -1; 1993 } 1994 1995 if (pq != xive_get_field32(end_esmask, end.w1)) { 1996 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1997 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1998 } 1999 2000 return ret; 2001 } 2002 2003 /* 2004 * END ESB MMIO stores are invalid 2005 */ 2006 static void xive_end_source_write(void *opaque, hwaddr addr, 2007 uint64_t value, unsigned size) 2008 { 2009 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 2010 HWADDR_PRIx"\n", addr); 2011 } 2012 2013 static const MemoryRegionOps xive_end_source_ops = { 2014 .read = xive_end_source_read, 2015 .write = xive_end_source_write, 2016 .endianness = DEVICE_BIG_ENDIAN, 2017 .valid = { 2018 .min_access_size = 1, 2019 .max_access_size = 8, 2020 }, 2021 .impl = { 2022 .min_access_size = 1, 2023 .max_access_size = 8, 2024 }, 2025 }; 2026 2027 static void xive_end_source_realize(DeviceState *dev, Error **errp) 2028 { 2029 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 2030 2031 assert(xsrc->xrtr); 2032 2033 if (!xsrc->nr_ends) { 2034 error_setg(errp, "Number of interrupt needs to be greater than 0"); 2035 return; 2036 } 2037 2038 if (xsrc->esb_shift != XIVE_ESB_4K && 2039 xsrc->esb_shift != XIVE_ESB_64K) { 2040 error_setg(errp, "Invalid ESB shift setting"); 2041 return; 2042 } 2043 2044 /* 2045 * Each END is assigned an even/odd pair of MMIO pages, the even page 2046 * manages the ESn field while the odd page manages the ESe field. 2047 */ 2048 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 2049 &xive_end_source_ops, xsrc, "xive.end", 2050 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 2051 } 2052 2053 static Property xive_end_source_properties[] = { 2054 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 2055 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 2056 DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, 2057 XiveRouter *), 2058 DEFINE_PROP_END_OF_LIST(), 2059 }; 2060 2061 static void xive_end_source_class_init(ObjectClass *klass, void *data) 2062 { 2063 DeviceClass *dc = DEVICE_CLASS(klass); 2064 2065 dc->desc = "XIVE END Source"; 2066 device_class_set_props(dc, xive_end_source_properties); 2067 dc->realize = xive_end_source_realize; 2068 /* 2069 * Reason: part of XIVE interrupt controller, needs to be wired up, 2070 * e.g. by spapr_xive_instance_init(). 2071 */ 2072 dc->user_creatable = false; 2073 } 2074 2075 static const TypeInfo xive_end_source_info = { 2076 .name = TYPE_XIVE_END_SOURCE, 2077 .parent = TYPE_DEVICE, 2078 .instance_size = sizeof(XiveENDSource), 2079 .class_init = xive_end_source_class_init, 2080 }; 2081 2082 /* 2083 * XIVE Notifier 2084 */ 2085 static const TypeInfo xive_notifier_info = { 2086 .name = TYPE_XIVE_NOTIFIER, 2087 .parent = TYPE_INTERFACE, 2088 .class_size = sizeof(XiveNotifierClass), 2089 }; 2090 2091 /* 2092 * XIVE Presenter 2093 */ 2094 static const TypeInfo xive_presenter_info = { 2095 .name = TYPE_XIVE_PRESENTER, 2096 .parent = TYPE_INTERFACE, 2097 .class_size = sizeof(XivePresenterClass), 2098 }; 2099 2100 /* 2101 * XIVE Fabric 2102 */ 2103 static const TypeInfo xive_fabric_info = { 2104 .name = TYPE_XIVE_FABRIC, 2105 .parent = TYPE_INTERFACE, 2106 .class_size = sizeof(XiveFabricClass), 2107 }; 2108 2109 static void xive_register_types(void) 2110 { 2111 type_register_static(&xive_fabric_info); 2112 type_register_static(&xive_source_info); 2113 type_register_static(&xive_notifier_info); 2114 type_register_static(&xive_presenter_info); 2115 type_register_static(&xive_router_info); 2116 type_register_static(&xive_end_source_info); 2117 type_register_static(&xive_tctx_info); 2118 } 2119 2120 type_init(xive_register_types) 2121