1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "monitor/monitor.h" 21 #include "hw/irq.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive_regs.h" 24 25 /* 26 * XIVE Thread Interrupt Management context 27 */ 28 29 /* 30 * Convert a priority number to an Interrupt Pending Buffer (IPB) 31 * register, which indicates a pending interrupt at the priority 32 * corresponding to the bit number 33 */ 34 static uint8_t priority_to_ipb(uint8_t priority) 35 { 36 return priority > XIVE_PRIORITY_MAX ? 37 0 : 1 << (XIVE_PRIORITY_MAX - priority); 38 } 39 40 /* 41 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 42 * Interrupt Priority Register (PIPR), which contains the priority of 43 * the most favored pending notification. 44 */ 45 static uint8_t ipb_to_pipr(uint8_t ibp) 46 { 47 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 48 } 49 50 static uint8_t exception_mask(uint8_t ring) 51 { 52 switch (ring) { 53 case TM_QW1_OS: 54 return TM_QW1_NSR_EO; 55 case TM_QW3_HV_PHYS: 56 return TM_QW3_NSR_HE; 57 default: 58 g_assert_not_reached(); 59 } 60 } 61 62 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 63 { 64 switch (ring) { 65 case TM_QW0_USER: 66 return 0; /* Not supported */ 67 case TM_QW1_OS: 68 return tctx->os_output; 69 case TM_QW2_HV_POOL: 70 case TM_QW3_HV_PHYS: 71 return tctx->hv_output; 72 default: 73 return 0; 74 } 75 } 76 77 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 78 { 79 uint8_t *regs = &tctx->regs[ring]; 80 uint8_t nsr = regs[TM_NSR]; 81 uint8_t mask = exception_mask(ring); 82 83 qemu_irq_lower(xive_tctx_output(tctx, ring)); 84 85 if (regs[TM_NSR] & mask) { 86 uint8_t cppr = regs[TM_PIPR]; 87 88 regs[TM_CPPR] = cppr; 89 90 /* Reset the pending buffer bit */ 91 regs[TM_IPB] &= ~priority_to_ipb(cppr); 92 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 93 94 /* Drop Exception bit */ 95 regs[TM_NSR] &= ~mask; 96 } 97 98 return (nsr << 8) | regs[TM_CPPR]; 99 } 100 101 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 102 { 103 uint8_t *regs = &tctx->regs[ring]; 104 105 if (regs[TM_PIPR] < regs[TM_CPPR]) { 106 switch (ring) { 107 case TM_QW1_OS: 108 regs[TM_NSR] |= TM_QW1_NSR_EO; 109 break; 110 case TM_QW3_HV_PHYS: 111 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 112 break; 113 default: 114 g_assert_not_reached(); 115 } 116 qemu_irq_raise(xive_tctx_output(tctx, ring)); 117 } 118 } 119 120 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 121 { 122 if (cppr > XIVE_PRIORITY_MAX) { 123 cppr = 0xff; 124 } 125 126 tctx->regs[ring + TM_CPPR] = cppr; 127 128 /* CPPR has changed, check if we need to raise a pending exception */ 129 xive_tctx_notify(tctx, ring); 130 } 131 132 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) 133 { 134 uint8_t *regs = &tctx->regs[ring]; 135 136 regs[TM_IPB] |= ipb; 137 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 138 xive_tctx_notify(tctx, ring); 139 } 140 141 static inline uint32_t xive_tctx_word2(uint8_t *ring) 142 { 143 return *((uint32_t *) &ring[TM_WORD2]); 144 } 145 146 /* 147 * XIVE Thread Interrupt Management Area (TIMA) 148 */ 149 150 static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 151 hwaddr offset, uint64_t value, unsigned size) 152 { 153 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 154 } 155 156 static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx, 157 hwaddr offset, unsigned size) 158 { 159 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 160 } 161 162 static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 163 hwaddr offset, unsigned size) 164 { 165 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 166 uint32_t qw2w2; 167 168 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 169 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 170 return qw2w2; 171 } 172 173 static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 174 uint64_t value, unsigned size) 175 { 176 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 177 } 178 179 static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, 180 hwaddr offset, unsigned size) 181 { 182 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 183 } 184 185 /* 186 * Define an access map for each page of the TIMA that we will use in 187 * the memory region ops to filter values when doing loads and stores 188 * of raw registers values 189 * 190 * Registers accessibility bits : 191 * 192 * 0x0 - no access 193 * 0x1 - write only 194 * 0x2 - read only 195 * 0x3 - read/write 196 */ 197 198 static const uint8_t xive_tm_hw_view[] = { 199 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 200 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 201 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 202 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 203 }; 204 205 static const uint8_t xive_tm_hv_view[] = { 206 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 207 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 208 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 209 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 210 }; 211 212 static const uint8_t xive_tm_os_view[] = { 213 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 214 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 215 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 217 }; 218 219 static const uint8_t xive_tm_user_view[] = { 220 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 223 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 224 }; 225 226 /* 227 * Overall TIMA access map for the thread interrupt management context 228 * registers 229 */ 230 static const uint8_t *xive_tm_views[] = { 231 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 232 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 233 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 234 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 235 }; 236 237 /* 238 * Computes a register access mask for a given offset in the TIMA 239 */ 240 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 241 { 242 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 243 uint8_t reg_offset = offset & 0x3F; 244 uint8_t reg_mask = write ? 0x1 : 0x2; 245 uint64_t mask = 0x0; 246 int i; 247 248 for (i = 0; i < size; i++) { 249 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 250 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 251 } 252 } 253 254 return mask; 255 } 256 257 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 258 unsigned size) 259 { 260 uint8_t ring_offset = offset & 0x30; 261 uint8_t reg_offset = offset & 0x3F; 262 uint64_t mask = xive_tm_mask(offset, size, true); 263 int i; 264 265 /* 266 * Only 4 or 8 bytes stores are allowed and the User ring is 267 * excluded 268 */ 269 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 270 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 271 HWADDR_PRIx"\n", offset); 272 return; 273 } 274 275 /* 276 * Use the register offset for the raw values and filter out 277 * reserved values 278 */ 279 for (i = 0; i < size; i++) { 280 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 281 if (byte_mask) { 282 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 283 byte_mask; 284 } 285 } 286 } 287 288 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 289 { 290 uint8_t ring_offset = offset & 0x30; 291 uint8_t reg_offset = offset & 0x3F; 292 uint64_t mask = xive_tm_mask(offset, size, false); 293 uint64_t ret; 294 int i; 295 296 /* 297 * Only 4 or 8 bytes loads are allowed and the User ring is 298 * excluded 299 */ 300 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 301 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 302 HWADDR_PRIx"\n", offset); 303 return -1; 304 } 305 306 /* Use the register offset for the raw values */ 307 ret = 0; 308 for (i = 0; i < size; i++) { 309 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 310 } 311 312 /* filter out reserved values */ 313 return ret & mask; 314 } 315 316 /* 317 * The TM context is mapped twice within each page. Stores and loads 318 * to the first mapping below 2K write and read the specified values 319 * without modification. The second mapping above 2K performs specific 320 * state changes (side effects) in addition to setting/returning the 321 * interrupt management area context of the processor thread. 322 */ 323 static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx, 324 hwaddr offset, unsigned size) 325 { 326 return xive_tctx_accept(tctx, TM_QW1_OS); 327 } 328 329 static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 330 hwaddr offset, uint64_t value, unsigned size) 331 { 332 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 333 } 334 335 /* 336 * Adjust the IPB to allow a CPU to process event queues of other 337 * priorities during one physical interrupt cycle. 338 */ 339 static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, 340 hwaddr offset, uint64_t value, unsigned size) 341 { 342 xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff)); 343 } 344 345 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, 346 uint32_t *nvt_idx, bool *vo) 347 { 348 if (nvt_blk) { 349 *nvt_blk = xive_nvt_blk(cam); 350 } 351 if (nvt_idx) { 352 *nvt_idx = xive_nvt_idx(cam); 353 } 354 if (vo) { 355 *vo = !!(cam & TM_QW1W2_VO); 356 } 357 } 358 359 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk, 360 uint32_t *nvt_idx, bool *vo) 361 { 362 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 363 uint32_t cam = be32_to_cpu(qw1w2); 364 365 xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo); 366 return qw1w2; 367 } 368 369 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) 370 { 371 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 372 } 373 374 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 375 hwaddr offset, unsigned size) 376 { 377 uint32_t qw1w2; 378 uint32_t qw1w2_new; 379 uint8_t nvt_blk; 380 uint32_t nvt_idx; 381 bool vo; 382 383 qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); 384 385 if (!vo) { 386 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n", 387 nvt_blk, nvt_idx); 388 } 389 390 /* Invalidate CAM line */ 391 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); 392 xive_tctx_set_os_cam(tctx, qw1w2_new); 393 return qw1w2; 394 } 395 396 static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx, 397 uint8_t nvt_blk, uint32_t nvt_idx) 398 { 399 XiveNVT nvt; 400 uint8_t ipb; 401 402 /* 403 * Grab the associated NVT to pull the pending bits, and merge 404 * them with the IPB of the thread interrupt context registers 405 */ 406 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 407 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n", 408 nvt_blk, nvt_idx); 409 return; 410 } 411 412 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4); 413 414 if (ipb) { 415 /* Reset the NVT value */ 416 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0); 417 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 418 419 /* Merge in current context */ 420 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); 421 } 422 } 423 424 /* 425 * Updating the OS CAM line can trigger a resend of interrupt 426 */ 427 static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 428 hwaddr offset, uint64_t value, unsigned size) 429 { 430 uint32_t cam = value; 431 uint32_t qw1w2 = cpu_to_be32(cam); 432 uint8_t nvt_blk; 433 uint32_t nvt_idx; 434 bool vo; 435 436 xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); 437 438 /* First update the registers */ 439 xive_tctx_set_os_cam(tctx, qw1w2); 440 441 /* Check the interrupt pending bits */ 442 if (vo) { 443 xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); 444 } 445 } 446 447 /* 448 * Define a mapping of "special" operations depending on the TIMA page 449 * offset and the size of the operation. 450 */ 451 typedef struct XiveTmOp { 452 uint8_t page_offset; 453 uint32_t op_offset; 454 unsigned size; 455 void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, 456 hwaddr offset, 457 uint64_t value, unsigned size); 458 uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 459 unsigned size); 460 } XiveTmOp; 461 462 static const XiveTmOp xive_tm_operations[] = { 463 /* 464 * MMIOs below 2K : raw values and special operations without side 465 * effects 466 */ 467 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 468 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, NULL }, 469 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 470 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 471 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 472 473 /* MMIOs above 2K : special operations with side effects */ 474 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 475 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 476 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, 477 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, 478 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 479 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 480 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 481 }; 482 483 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 484 { 485 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 486 uint32_t op_offset = offset & 0xFFF; 487 int i; 488 489 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 490 const XiveTmOp *xto = &xive_tm_operations[i]; 491 492 /* Accesses done from a more privileged TIMA page is allowed */ 493 if (xto->page_offset >= page_offset && 494 xto->op_offset == op_offset && 495 xto->size == size && 496 ((write && xto->write_handler) || (!write && xto->read_handler))) { 497 return xto; 498 } 499 } 500 return NULL; 501 } 502 503 /* 504 * TIMA MMIO handlers 505 */ 506 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 507 uint64_t value, unsigned size) 508 { 509 const XiveTmOp *xto; 510 511 /* 512 * TODO: check V bit in Q[0-3]W2 513 */ 514 515 /* 516 * First, check for special operations in the 2K region 517 */ 518 if (offset & 0x800) { 519 xto = xive_tm_find_op(offset, size, true); 520 if (!xto) { 521 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 522 "@%"HWADDR_PRIx"\n", offset); 523 } else { 524 xto->write_handler(xptr, tctx, offset, value, size); 525 } 526 return; 527 } 528 529 /* 530 * Then, for special operations in the region below 2K. 531 */ 532 xto = xive_tm_find_op(offset, size, true); 533 if (xto) { 534 xto->write_handler(xptr, tctx, offset, value, size); 535 return; 536 } 537 538 /* 539 * Finish with raw access to the register values 540 */ 541 xive_tm_raw_write(tctx, offset, value, size); 542 } 543 544 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 545 unsigned size) 546 { 547 const XiveTmOp *xto; 548 549 /* 550 * TODO: check V bit in Q[0-3]W2 551 */ 552 553 /* 554 * First, check for special operations in the 2K region 555 */ 556 if (offset & 0x800) { 557 xto = xive_tm_find_op(offset, size, false); 558 if (!xto) { 559 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 560 "@%"HWADDR_PRIx"\n", offset); 561 return -1; 562 } 563 return xto->read_handler(xptr, tctx, offset, size); 564 } 565 566 /* 567 * Then, for special operations in the region below 2K. 568 */ 569 xto = xive_tm_find_op(offset, size, false); 570 if (xto) { 571 return xto->read_handler(xptr, tctx, offset, size); 572 } 573 574 /* 575 * Finish with raw access to the register values 576 */ 577 return xive_tm_raw_read(tctx, offset, size); 578 } 579 580 static char *xive_tctx_ring_print(uint8_t *ring) 581 { 582 uint32_t w2 = xive_tctx_word2(ring); 583 584 return g_strdup_printf("%02x %02x %02x %02x %02x " 585 "%02x %02x %02x %08x", 586 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 587 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 588 be32_to_cpu(w2)); 589 } 590 591 static const char * const xive_tctx_ring_names[] = { 592 "USER", "OS", "POOL", "PHYS", 593 }; 594 595 /* 596 * kvm_irqchip_in_kernel() will cause the compiler to turn this 597 * info a nop if CONFIG_KVM isn't defined. 598 */ 599 #define xive_in_kernel(xptr) \ 600 (kvm_irqchip_in_kernel() && \ 601 ({ \ 602 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); \ 603 xpc->in_kernel ? xpc->in_kernel(xptr) : false; \ 604 })) 605 606 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 607 { 608 int cpu_index; 609 int i; 610 611 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs 612 * are hot plugged or unplugged. 613 */ 614 if (!tctx) { 615 return; 616 } 617 618 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 619 620 if (xive_in_kernel(tctx->xptr)) { 621 Error *local_err = NULL; 622 623 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 624 if (local_err) { 625 error_report_err(local_err); 626 return; 627 } 628 } 629 630 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 631 " W2\n", cpu_index); 632 633 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 634 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 635 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 636 xive_tctx_ring_names[i], s); 637 g_free(s); 638 } 639 } 640 641 void xive_tctx_reset(XiveTCTX *tctx) 642 { 643 memset(tctx->regs, 0, sizeof(tctx->regs)); 644 645 /* Set some defaults */ 646 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 647 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 648 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 649 650 /* 651 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 652 * CPPR is first set. 653 */ 654 tctx->regs[TM_QW1_OS + TM_PIPR] = 655 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 656 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 657 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 658 } 659 660 static void xive_tctx_realize(DeviceState *dev, Error **errp) 661 { 662 XiveTCTX *tctx = XIVE_TCTX(dev); 663 PowerPCCPU *cpu; 664 CPUPPCState *env; 665 666 assert(tctx->cs); 667 assert(tctx->xptr); 668 669 cpu = POWERPC_CPU(tctx->cs); 670 env = &cpu->env; 671 switch (PPC_INPUT(env)) { 672 case PPC_FLAGS_INPUT_POWER9: 673 tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT]; 674 tctx->os_output = env->irq_inputs[POWER9_INPUT_INT]; 675 break; 676 677 default: 678 error_setg(errp, "XIVE interrupt controller does not support " 679 "this CPU bus model"); 680 return; 681 } 682 683 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 684 if (xive_in_kernel(tctx->xptr)) { 685 if (kvmppc_xive_cpu_connect(tctx, errp) < 0) { 686 return; 687 } 688 } 689 } 690 691 static int vmstate_xive_tctx_pre_save(void *opaque) 692 { 693 XiveTCTX *tctx = XIVE_TCTX(opaque); 694 Error *local_err = NULL; 695 int ret; 696 697 if (xive_in_kernel(tctx->xptr)) { 698 ret = kvmppc_xive_cpu_get_state(tctx, &local_err); 699 if (ret < 0) { 700 error_report_err(local_err); 701 return ret; 702 } 703 } 704 705 return 0; 706 } 707 708 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 709 { 710 XiveTCTX *tctx = XIVE_TCTX(opaque); 711 Error *local_err = NULL; 712 int ret; 713 714 if (xive_in_kernel(tctx->xptr)) { 715 /* 716 * Required for hotplugged CPU, for which the state comes 717 * after all states of the machine. 718 */ 719 ret = kvmppc_xive_cpu_set_state(tctx, &local_err); 720 if (ret < 0) { 721 error_report_err(local_err); 722 return ret; 723 } 724 } 725 726 return 0; 727 } 728 729 static const VMStateDescription vmstate_xive_tctx = { 730 .name = TYPE_XIVE_TCTX, 731 .version_id = 1, 732 .minimum_version_id = 1, 733 .pre_save = vmstate_xive_tctx_pre_save, 734 .post_load = vmstate_xive_tctx_post_load, 735 .fields = (VMStateField[]) { 736 VMSTATE_BUFFER(regs, XiveTCTX), 737 VMSTATE_END_OF_LIST() 738 }, 739 }; 740 741 static Property xive_tctx_properties[] = { 742 DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), 743 DEFINE_PROP_LINK("presenter", XiveTCTX, xptr, TYPE_XIVE_PRESENTER, 744 XivePresenter *), 745 DEFINE_PROP_END_OF_LIST(), 746 }; 747 748 static void xive_tctx_class_init(ObjectClass *klass, void *data) 749 { 750 DeviceClass *dc = DEVICE_CLASS(klass); 751 752 dc->desc = "XIVE Interrupt Thread Context"; 753 dc->realize = xive_tctx_realize; 754 dc->vmsd = &vmstate_xive_tctx; 755 device_class_set_props(dc, xive_tctx_properties); 756 /* 757 * Reason: part of XIVE interrupt controller, needs to be wired up 758 * by xive_tctx_create(). 759 */ 760 dc->user_creatable = false; 761 } 762 763 static const TypeInfo xive_tctx_info = { 764 .name = TYPE_XIVE_TCTX, 765 .parent = TYPE_DEVICE, 766 .instance_size = sizeof(XiveTCTX), 767 .class_init = xive_tctx_class_init, 768 }; 769 770 Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp) 771 { 772 Object *obj; 773 774 obj = object_new(TYPE_XIVE_TCTX); 775 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj); 776 object_unref(obj); 777 object_property_set_link(obj, "cpu", cpu, &error_abort); 778 object_property_set_link(obj, "presenter", OBJECT(xptr), &error_abort); 779 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 780 object_unparent(obj); 781 return NULL; 782 } 783 return obj; 784 } 785 786 void xive_tctx_destroy(XiveTCTX *tctx) 787 { 788 Object *obj = OBJECT(tctx); 789 790 object_unparent(obj); 791 } 792 793 /* 794 * XIVE ESB helpers 795 */ 796 797 static uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 798 { 799 uint8_t old_pq = *pq & 0x3; 800 801 *pq &= ~0x3; 802 *pq |= value & 0x3; 803 804 return old_pq; 805 } 806 807 static bool xive_esb_trigger(uint8_t *pq) 808 { 809 uint8_t old_pq = *pq & 0x3; 810 811 switch (old_pq) { 812 case XIVE_ESB_RESET: 813 xive_esb_set(pq, XIVE_ESB_PENDING); 814 return true; 815 case XIVE_ESB_PENDING: 816 case XIVE_ESB_QUEUED: 817 xive_esb_set(pq, XIVE_ESB_QUEUED); 818 return false; 819 case XIVE_ESB_OFF: 820 xive_esb_set(pq, XIVE_ESB_OFF); 821 return false; 822 default: 823 g_assert_not_reached(); 824 } 825 } 826 827 static bool xive_esb_eoi(uint8_t *pq) 828 { 829 uint8_t old_pq = *pq & 0x3; 830 831 switch (old_pq) { 832 case XIVE_ESB_RESET: 833 case XIVE_ESB_PENDING: 834 xive_esb_set(pq, XIVE_ESB_RESET); 835 return false; 836 case XIVE_ESB_QUEUED: 837 xive_esb_set(pq, XIVE_ESB_PENDING); 838 return true; 839 case XIVE_ESB_OFF: 840 xive_esb_set(pq, XIVE_ESB_OFF); 841 return false; 842 default: 843 g_assert_not_reached(); 844 } 845 } 846 847 /* 848 * XIVE Interrupt Source (or IVSE) 849 */ 850 851 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 852 { 853 assert(srcno < xsrc->nr_irqs); 854 855 return xsrc->status[srcno] & 0x3; 856 } 857 858 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 859 { 860 assert(srcno < xsrc->nr_irqs); 861 862 return xive_esb_set(&xsrc->status[srcno], pq); 863 } 864 865 /* 866 * Returns whether the event notification should be forwarded. 867 */ 868 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 869 { 870 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 871 872 xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; 873 874 switch (old_pq) { 875 case XIVE_ESB_RESET: 876 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 877 return true; 878 default: 879 return false; 880 } 881 } 882 883 /* 884 * Returns whether the event notification should be forwarded. 885 */ 886 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 887 { 888 bool ret; 889 890 assert(srcno < xsrc->nr_irqs); 891 892 ret = xive_esb_trigger(&xsrc->status[srcno]); 893 894 if (xive_source_irq_is_lsi(xsrc, srcno) && 895 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 896 qemu_log_mask(LOG_GUEST_ERROR, 897 "XIVE: queued an event on LSI IRQ %d\n", srcno); 898 } 899 900 return ret; 901 } 902 903 /* 904 * Returns whether the event notification should be forwarded. 905 */ 906 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 907 { 908 bool ret; 909 910 assert(srcno < xsrc->nr_irqs); 911 912 ret = xive_esb_eoi(&xsrc->status[srcno]); 913 914 /* 915 * LSI sources do not set the Q bit but they can still be 916 * asserted, in which case we should forward a new event 917 * notification 918 */ 919 if (xive_source_irq_is_lsi(xsrc, srcno) && 920 xsrc->status[srcno] & XIVE_STATUS_ASSERTED) { 921 ret = xive_source_lsi_trigger(xsrc, srcno); 922 } 923 924 return ret; 925 } 926 927 /* 928 * Forward the source event notification to the Router 929 */ 930 static void xive_source_notify(XiveSource *xsrc, int srcno) 931 { 932 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 933 934 if (xnc->notify) { 935 xnc->notify(xsrc->xive, srcno); 936 } 937 } 938 939 /* 940 * In a two pages ESB MMIO setting, even page is the trigger page, odd 941 * page is for management 942 */ 943 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 944 { 945 return !((addr >> shift) & 1); 946 } 947 948 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 949 { 950 return xive_source_esb_has_2page(xsrc) && 951 addr_is_even(addr, xsrc->esb_shift - 1); 952 } 953 954 /* 955 * ESB MMIO loads 956 * Trigger page Management/EOI page 957 * 958 * ESB MMIO setting 2 pages 1 or 2 pages 959 * 960 * 0x000 .. 0x3FF -1 EOI and return 0|1 961 * 0x400 .. 0x7FF -1 EOI and return 0|1 962 * 0x800 .. 0xBFF -1 return PQ 963 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 964 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 965 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 966 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 967 */ 968 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 969 { 970 XiveSource *xsrc = XIVE_SOURCE(opaque); 971 uint32_t offset = addr & 0xFFF; 972 uint32_t srcno = addr >> xsrc->esb_shift; 973 uint64_t ret = -1; 974 975 /* In a two pages ESB MMIO setting, trigger page should not be read */ 976 if (xive_source_is_trigger_page(xsrc, addr)) { 977 qemu_log_mask(LOG_GUEST_ERROR, 978 "XIVE: invalid load on IRQ %d trigger page at " 979 "0x%"HWADDR_PRIx"\n", srcno, addr); 980 return -1; 981 } 982 983 switch (offset) { 984 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 985 ret = xive_source_esb_eoi(xsrc, srcno); 986 987 /* Forward the source event notification for routing */ 988 if (ret) { 989 xive_source_notify(xsrc, srcno); 990 } 991 break; 992 993 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 994 ret = xive_source_esb_get(xsrc, srcno); 995 break; 996 997 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 998 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 999 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1000 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1001 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1002 break; 1003 default: 1004 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 1005 offset); 1006 } 1007 1008 return ret; 1009 } 1010 1011 /* 1012 * ESB MMIO stores 1013 * Trigger page Management/EOI page 1014 * 1015 * ESB MMIO setting 2 pages 1 or 2 pages 1016 * 1017 * 0x000 .. 0x3FF Trigger Trigger 1018 * 0x400 .. 0x7FF Trigger EOI 1019 * 0x800 .. 0xBFF Trigger undefined 1020 * 0xC00 .. 0xCFF Trigger PQ=00 1021 * 0xD00 .. 0xDFF Trigger PQ=01 1022 * 0xE00 .. 0xDFF Trigger PQ=10 1023 * 0xF00 .. 0xDFF Trigger PQ=11 1024 */ 1025 static void xive_source_esb_write(void *opaque, hwaddr addr, 1026 uint64_t value, unsigned size) 1027 { 1028 XiveSource *xsrc = XIVE_SOURCE(opaque); 1029 uint32_t offset = addr & 0xFFF; 1030 uint32_t srcno = addr >> xsrc->esb_shift; 1031 bool notify = false; 1032 1033 /* In a two pages ESB MMIO setting, trigger page only triggers */ 1034 if (xive_source_is_trigger_page(xsrc, addr)) { 1035 notify = xive_source_esb_trigger(xsrc, srcno); 1036 goto out; 1037 } 1038 1039 switch (offset) { 1040 case 0 ... 0x3FF: 1041 notify = xive_source_esb_trigger(xsrc, srcno); 1042 break; 1043 1044 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 1045 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 1046 qemu_log_mask(LOG_GUEST_ERROR, 1047 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 1048 return; 1049 } 1050 1051 notify = xive_source_esb_eoi(xsrc, srcno); 1052 break; 1053 1054 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1055 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1056 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1057 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1058 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1059 break; 1060 1061 default: 1062 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 1063 offset); 1064 return; 1065 } 1066 1067 out: 1068 /* Forward the source event notification for routing */ 1069 if (notify) { 1070 xive_source_notify(xsrc, srcno); 1071 } 1072 } 1073 1074 static const MemoryRegionOps xive_source_esb_ops = { 1075 .read = xive_source_esb_read, 1076 .write = xive_source_esb_write, 1077 .endianness = DEVICE_BIG_ENDIAN, 1078 .valid = { 1079 .min_access_size = 8, 1080 .max_access_size = 8, 1081 }, 1082 .impl = { 1083 .min_access_size = 8, 1084 .max_access_size = 8, 1085 }, 1086 }; 1087 1088 void xive_source_set_irq(void *opaque, int srcno, int val) 1089 { 1090 XiveSource *xsrc = XIVE_SOURCE(opaque); 1091 bool notify = false; 1092 1093 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1094 if (val) { 1095 notify = xive_source_lsi_trigger(xsrc, srcno); 1096 } else { 1097 xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; 1098 } 1099 } else { 1100 if (val) { 1101 notify = xive_source_esb_trigger(xsrc, srcno); 1102 } 1103 } 1104 1105 /* Forward the source event notification for routing */ 1106 if (notify) { 1107 xive_source_notify(xsrc, srcno); 1108 } 1109 } 1110 1111 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 1112 { 1113 int i; 1114 1115 for (i = 0; i < xsrc->nr_irqs; i++) { 1116 uint8_t pq = xive_source_esb_get(xsrc, i); 1117 1118 if (pq == XIVE_ESB_OFF) { 1119 continue; 1120 } 1121 1122 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 1123 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1124 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1125 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1126 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' '); 1127 } 1128 } 1129 1130 static void xive_source_reset(void *dev) 1131 { 1132 XiveSource *xsrc = XIVE_SOURCE(dev); 1133 1134 /* Do not clear the LSI bitmap */ 1135 1136 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 1137 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 1138 } 1139 1140 static void xive_source_realize(DeviceState *dev, Error **errp) 1141 { 1142 XiveSource *xsrc = XIVE_SOURCE(dev); 1143 size_t esb_len = xive_source_esb_len(xsrc); 1144 1145 assert(xsrc->xive); 1146 1147 if (!xsrc->nr_irqs) { 1148 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1149 return; 1150 } 1151 1152 if (xsrc->esb_shift != XIVE_ESB_4K && 1153 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1154 xsrc->esb_shift != XIVE_ESB_64K && 1155 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1156 error_setg(errp, "Invalid ESB shift setting"); 1157 return; 1158 } 1159 1160 xsrc->status = g_malloc0(xsrc->nr_irqs); 1161 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1162 1163 memory_region_init(&xsrc->esb_mmio, OBJECT(xsrc), "xive.esb", esb_len); 1164 memory_region_init_io(&xsrc->esb_mmio_emulated, OBJECT(xsrc), 1165 &xive_source_esb_ops, xsrc, "xive.esb-emulated", 1166 esb_len); 1167 memory_region_add_subregion(&xsrc->esb_mmio, 0, &xsrc->esb_mmio_emulated); 1168 1169 qemu_register_reset(xive_source_reset, dev); 1170 } 1171 1172 static const VMStateDescription vmstate_xive_source = { 1173 .name = TYPE_XIVE_SOURCE, 1174 .version_id = 1, 1175 .minimum_version_id = 1, 1176 .fields = (VMStateField[]) { 1177 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1178 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1179 VMSTATE_END_OF_LIST() 1180 }, 1181 }; 1182 1183 /* 1184 * The default XIVE interrupt source setting for the ESB MMIOs is two 1185 * 64k pages without Store EOI, to be in sync with KVM. 1186 */ 1187 static Property xive_source_properties[] = { 1188 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1189 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1190 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1191 DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, 1192 XiveNotifier *), 1193 DEFINE_PROP_END_OF_LIST(), 1194 }; 1195 1196 static void xive_source_class_init(ObjectClass *klass, void *data) 1197 { 1198 DeviceClass *dc = DEVICE_CLASS(klass); 1199 1200 dc->desc = "XIVE Interrupt Source"; 1201 device_class_set_props(dc, xive_source_properties); 1202 dc->realize = xive_source_realize; 1203 dc->vmsd = &vmstate_xive_source; 1204 /* 1205 * Reason: part of XIVE interrupt controller, needs to be wired up, 1206 * e.g. by spapr_xive_instance_init(). 1207 */ 1208 dc->user_creatable = false; 1209 } 1210 1211 static const TypeInfo xive_source_info = { 1212 .name = TYPE_XIVE_SOURCE, 1213 .parent = TYPE_DEVICE, 1214 .instance_size = sizeof(XiveSource), 1215 .class_init = xive_source_class_init, 1216 }; 1217 1218 /* 1219 * XiveEND helpers 1220 */ 1221 1222 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1223 { 1224 uint64_t qaddr_base = xive_end_qaddr(end); 1225 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1226 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1227 uint32_t qentries = 1 << (qsize + 10); 1228 int i; 1229 1230 /* 1231 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1232 */ 1233 monitor_printf(mon, " [ "); 1234 qindex = (qindex - (width - 1)) & (qentries - 1); 1235 for (i = 0; i < width; i++) { 1236 uint64_t qaddr = qaddr_base + (qindex << 2); 1237 uint32_t qdata = -1; 1238 1239 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 1240 sizeof(qdata))) { 1241 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1242 HWADDR_PRIx "\n", qaddr); 1243 return; 1244 } 1245 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1246 be32_to_cpu(qdata)); 1247 qindex = (qindex + 1) & (qentries - 1); 1248 } 1249 monitor_printf(mon, "]"); 1250 } 1251 1252 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1253 { 1254 uint64_t qaddr_base = xive_end_qaddr(end); 1255 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1256 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1257 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1258 uint32_t qentries = 1 << (qsize + 10); 1259 1260 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1261 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1262 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1263 uint8_t pq; 1264 1265 if (!xive_end_is_valid(end)) { 1266 return; 1267 } 1268 1269 pq = xive_get_field32(END_W1_ESn, end->w1); 1270 1271 monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1272 end_idx, 1273 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1274 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1275 xive_end_is_valid(end) ? 'v' : '-', 1276 xive_end_is_enqueue(end) ? 'q' : '-', 1277 xive_end_is_notify(end) ? 'n' : '-', 1278 xive_end_is_backlog(end) ? 'b' : '-', 1279 xive_end_is_escalate(end) ? 'e' : '-', 1280 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1281 xive_end_is_silent_escalation(end) ? 's' : '-', 1282 priority, nvt_blk, nvt_idx); 1283 1284 if (qaddr_base) { 1285 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1286 qaddr_base, qindex, qentries, qgen); 1287 xive_end_queue_pic_print_info(end, 6, mon); 1288 } 1289 monitor_printf(mon, "\n"); 1290 } 1291 1292 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1293 { 1294 uint64_t qaddr_base = xive_end_qaddr(end); 1295 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1296 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1297 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1298 1299 uint64_t qaddr = qaddr_base + (qindex << 2); 1300 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1301 uint32_t qentries = 1 << (qsize + 10); 1302 1303 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) { 1304 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1305 HWADDR_PRIx "\n", qaddr); 1306 return; 1307 } 1308 1309 qindex = (qindex + 1) & (qentries - 1); 1310 if (qindex == 0) { 1311 qgen ^= 1; 1312 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1313 } 1314 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1315 } 1316 1317 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, 1318 Monitor *mon) 1319 { 1320 XiveEAS *eas = (XiveEAS *) &end->w4; 1321 uint8_t pq; 1322 1323 if (!xive_end_is_escalate(end)) { 1324 return; 1325 } 1326 1327 pq = xive_get_field32(END_W1_ESe, end->w1); 1328 1329 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1330 end_idx, 1331 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1332 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1333 xive_eas_is_valid(eas) ? 'V' : ' ', 1334 xive_eas_is_masked(eas) ? 'M' : ' ', 1335 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1336 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1337 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1338 } 1339 1340 /* 1341 * XIVE Router (aka. Virtualization Controller or IVRE) 1342 */ 1343 1344 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1345 XiveEAS *eas) 1346 { 1347 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1348 1349 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1350 } 1351 1352 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1353 XiveEND *end) 1354 { 1355 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1356 1357 return xrc->get_end(xrtr, end_blk, end_idx, end); 1358 } 1359 1360 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1361 XiveEND *end, uint8_t word_number) 1362 { 1363 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1364 1365 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1366 } 1367 1368 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1369 XiveNVT *nvt) 1370 { 1371 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1372 1373 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1374 } 1375 1376 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1377 XiveNVT *nvt, uint8_t word_number) 1378 { 1379 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1380 1381 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1382 } 1383 1384 static int xive_router_get_block_id(XiveRouter *xrtr) 1385 { 1386 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1387 1388 return xrc->get_block_id(xrtr); 1389 } 1390 1391 static void xive_router_realize(DeviceState *dev, Error **errp) 1392 { 1393 XiveRouter *xrtr = XIVE_ROUTER(dev); 1394 1395 assert(xrtr->xfb); 1396 } 1397 1398 /* 1399 * Encode the HW CAM line in the block group mode format : 1400 * 1401 * chip << 19 | 0000000 0 0001 thread (7Bit) 1402 */ 1403 static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 1404 { 1405 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1406 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1407 uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr)); 1408 1409 return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); 1410 } 1411 1412 /* 1413 * The thread context register words are in big-endian format. 1414 */ 1415 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1416 uint8_t format, 1417 uint8_t nvt_blk, uint32_t nvt_idx, 1418 bool cam_ignore, uint32_t logic_serv) 1419 { 1420 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1421 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1422 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1423 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1424 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1425 1426 /* 1427 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1428 * identifier are ignored in the "CAM" match. 1429 */ 1430 1431 if (format == 0) { 1432 if (cam_ignore == true) { 1433 /* 1434 * F=0 & i=1: Logical server notification (bits ignored at 1435 * the end of the NVT identifier) 1436 */ 1437 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1438 nvt_blk, nvt_idx); 1439 return -1; 1440 } 1441 1442 /* F=0 & i=0: Specific NVT notification */ 1443 1444 /* PHYS ring */ 1445 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1446 cam == xive_tctx_hw_cam_line(xptr, tctx)) { 1447 return TM_QW3_HV_PHYS; 1448 } 1449 1450 /* HV POOL ring */ 1451 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1452 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1453 return TM_QW2_HV_POOL; 1454 } 1455 1456 /* OS ring */ 1457 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1458 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1459 return TM_QW1_OS; 1460 } 1461 } else { 1462 /* F=1 : User level Event-Based Branch (EBB) notification */ 1463 1464 /* USER ring */ 1465 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1466 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1467 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1468 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1469 return TM_QW0_USER; 1470 } 1471 } 1472 return -1; 1473 } 1474 1475 /* 1476 * This is our simple Xive Presenter Engine model. It is merged in the 1477 * Router as it does not require an extra object. 1478 * 1479 * It receives notification requests sent by the IVRE to find one 1480 * matching NVT (or more) dispatched on the processor threads. In case 1481 * of a single NVT notification, the process is abreviated and the 1482 * thread is signaled if a match is found. In case of a logical server 1483 * notification (bits ignored at the end of the NVT identifier), the 1484 * IVPE and IVRE select a winning thread using different filters. This 1485 * involves 2 or 3 exchanges on the PowerBus that the model does not 1486 * support. 1487 * 1488 * The parameters represent what is sent on the PowerBus 1489 */ 1490 static bool xive_presenter_notify(XiveFabric *xfb, uint8_t format, 1491 uint8_t nvt_blk, uint32_t nvt_idx, 1492 bool cam_ignore, uint8_t priority, 1493 uint32_t logic_serv) 1494 { 1495 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb); 1496 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1497 int count; 1498 1499 /* 1500 * Ask the machine to scan the interrupt controllers for a match 1501 */ 1502 count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore, 1503 priority, logic_serv, &match); 1504 if (count < 0) { 1505 return false; 1506 } 1507 1508 /* handle CPU exception delivery */ 1509 if (count) { 1510 xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(priority)); 1511 } 1512 1513 return !!count; 1514 } 1515 1516 /* 1517 * Notification using the END ESe/ESn bit (Event State Buffer for 1518 * escalation and notification). Provide further coalescing in the 1519 * Router. 1520 */ 1521 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1522 uint32_t end_idx, XiveEND *end, 1523 uint32_t end_esmask) 1524 { 1525 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1526 bool notify = xive_esb_trigger(&pq); 1527 1528 if (pq != xive_get_field32(end_esmask, end->w1)) { 1529 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1530 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1531 } 1532 1533 /* ESe/n[Q]=1 : end of notification */ 1534 return notify; 1535 } 1536 1537 /* 1538 * An END trigger can come from an event trigger (IPI or HW) or from 1539 * another chip. We don't model the PowerBus but the END trigger 1540 * message has the same parameters than in the function below. 1541 */ 1542 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1543 uint32_t end_idx, uint32_t end_data) 1544 { 1545 XiveEND end; 1546 uint8_t priority; 1547 uint8_t format; 1548 uint8_t nvt_blk; 1549 uint32_t nvt_idx; 1550 XiveNVT nvt; 1551 bool found; 1552 1553 /* END cache lookup */ 1554 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1555 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1556 end_idx); 1557 return; 1558 } 1559 1560 if (!xive_end_is_valid(&end)) { 1561 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1562 end_blk, end_idx); 1563 return; 1564 } 1565 1566 if (xive_end_is_enqueue(&end)) { 1567 xive_end_enqueue(&end, end_data); 1568 /* Enqueuing event data modifies the EQ toggle and index */ 1569 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1570 } 1571 1572 /* 1573 * When the END is silent, we skip the notification part. 1574 */ 1575 if (xive_end_is_silent_escalation(&end)) { 1576 goto do_escalation; 1577 } 1578 1579 /* 1580 * The W7 format depends on the F bit in W6. It defines the type 1581 * of the notification : 1582 * 1583 * F=0 : single or multiple NVT notification 1584 * F=1 : User level Event-Based Branch (EBB) notification, no 1585 * priority 1586 */ 1587 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1588 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1589 1590 /* The END is masked */ 1591 if (format == 0 && priority == 0xff) { 1592 return; 1593 } 1594 1595 /* 1596 * Check the END ESn (Event State Buffer for notification) for 1597 * even further coalescing in the Router 1598 */ 1599 if (!xive_end_is_notify(&end)) { 1600 /* ESn[Q]=1 : end of notification */ 1601 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1602 &end, END_W1_ESn)) { 1603 return; 1604 } 1605 } 1606 1607 /* 1608 * Follows IVPE notification 1609 */ 1610 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1611 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1612 1613 /* NVT cache lookup */ 1614 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1615 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1616 nvt_blk, nvt_idx); 1617 return; 1618 } 1619 1620 if (!xive_nvt_is_valid(&nvt)) { 1621 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1622 nvt_blk, nvt_idx); 1623 return; 1624 } 1625 1626 found = xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx, 1627 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1628 priority, 1629 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1630 1631 /* TODO: Auto EOI. */ 1632 1633 if (found) { 1634 return; 1635 } 1636 1637 /* 1638 * If no matching NVT is dispatched on a HW thread : 1639 * - specific VP: update the NVT structure if backlog is activated 1640 * - logical server : forward request to IVPE (not supported) 1641 */ 1642 if (xive_end_is_backlog(&end)) { 1643 uint8_t ipb; 1644 1645 if (format == 1) { 1646 qemu_log_mask(LOG_GUEST_ERROR, 1647 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1648 end_blk, end_idx); 1649 return; 1650 } 1651 /* 1652 * Record the IPB in the associated NVT structure for later 1653 * use. The presenter will resend the interrupt when the vCPU 1654 * is dispatched again on a HW thread. 1655 */ 1656 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priority); 1657 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); 1658 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1659 1660 /* 1661 * On HW, follows a "Broadcast Backlog" to IVPEs 1662 */ 1663 } 1664 1665 do_escalation: 1666 /* 1667 * If activated, escalate notification using the ESe PQ bits and 1668 * the EAS in w4-5 1669 */ 1670 if (!xive_end_is_escalate(&end)) { 1671 return; 1672 } 1673 1674 /* 1675 * Check the END ESe (Event State Buffer for escalation) for even 1676 * further coalescing in the Router 1677 */ 1678 if (!xive_end_is_uncond_escalation(&end)) { 1679 /* ESe[Q]=1 : end of notification */ 1680 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1681 &end, END_W1_ESe)) { 1682 return; 1683 } 1684 } 1685 1686 /* 1687 * The END trigger becomes an Escalation trigger 1688 */ 1689 xive_router_end_notify(xrtr, 1690 xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1691 xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1692 xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1693 } 1694 1695 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 1696 { 1697 XiveRouter *xrtr = XIVE_ROUTER(xn); 1698 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1699 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1700 XiveEAS eas; 1701 1702 /* EAS cache lookup */ 1703 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1704 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1705 return; 1706 } 1707 1708 /* 1709 * The IVRE checks the State Bit Cache at this point. We skip the 1710 * SBC lookup because the state bits of the sources are modeled 1711 * internally in QEMU. 1712 */ 1713 1714 if (!xive_eas_is_valid(&eas)) { 1715 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1716 return; 1717 } 1718 1719 if (xive_eas_is_masked(&eas)) { 1720 /* Notification completed */ 1721 return; 1722 } 1723 1724 /* 1725 * The event trigger becomes an END trigger 1726 */ 1727 xive_router_end_notify(xrtr, 1728 xive_get_field64(EAS_END_BLOCK, eas.w), 1729 xive_get_field64(EAS_END_INDEX, eas.w), 1730 xive_get_field64(EAS_END_DATA, eas.w)); 1731 } 1732 1733 static Property xive_router_properties[] = { 1734 DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb, 1735 TYPE_XIVE_FABRIC, XiveFabric *), 1736 DEFINE_PROP_END_OF_LIST(), 1737 }; 1738 1739 static void xive_router_class_init(ObjectClass *klass, void *data) 1740 { 1741 DeviceClass *dc = DEVICE_CLASS(klass); 1742 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1743 1744 dc->desc = "XIVE Router Engine"; 1745 device_class_set_props(dc, xive_router_properties); 1746 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 1747 dc->realize = xive_router_realize; 1748 xnc->notify = xive_router_notify; 1749 } 1750 1751 static const TypeInfo xive_router_info = { 1752 .name = TYPE_XIVE_ROUTER, 1753 .parent = TYPE_SYS_BUS_DEVICE, 1754 .abstract = true, 1755 .instance_size = sizeof(XiveRouter), 1756 .class_size = sizeof(XiveRouterClass), 1757 .class_init = xive_router_class_init, 1758 .interfaces = (InterfaceInfo[]) { 1759 { TYPE_XIVE_NOTIFIER }, 1760 { TYPE_XIVE_PRESENTER }, 1761 { } 1762 } 1763 }; 1764 1765 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1766 { 1767 if (!xive_eas_is_valid(eas)) { 1768 return; 1769 } 1770 1771 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1772 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1773 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1774 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1775 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1776 } 1777 1778 /* 1779 * END ESB MMIO loads 1780 */ 1781 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1782 { 1783 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1784 uint32_t offset = addr & 0xFFF; 1785 uint8_t end_blk; 1786 uint32_t end_idx; 1787 XiveEND end; 1788 uint32_t end_esmask; 1789 uint8_t pq; 1790 uint64_t ret = -1; 1791 1792 /* 1793 * The block id should be deduced from the load address on the END 1794 * ESB MMIO but our model only supports a single block per XIVE chip. 1795 */ 1796 end_blk = xive_router_get_block_id(xsrc->xrtr); 1797 end_idx = addr >> (xsrc->esb_shift + 1); 1798 1799 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1800 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1801 end_idx); 1802 return -1; 1803 } 1804 1805 if (!xive_end_is_valid(&end)) { 1806 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1807 end_blk, end_idx); 1808 return -1; 1809 } 1810 1811 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1812 pq = xive_get_field32(end_esmask, end.w1); 1813 1814 switch (offset) { 1815 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1816 ret = xive_esb_eoi(&pq); 1817 1818 /* Forward the source event notification for routing ?? */ 1819 break; 1820 1821 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1822 ret = pq; 1823 break; 1824 1825 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1826 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1827 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1828 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1829 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1830 break; 1831 default: 1832 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1833 offset); 1834 return -1; 1835 } 1836 1837 if (pq != xive_get_field32(end_esmask, end.w1)) { 1838 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1839 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1840 } 1841 1842 return ret; 1843 } 1844 1845 /* 1846 * END ESB MMIO stores are invalid 1847 */ 1848 static void xive_end_source_write(void *opaque, hwaddr addr, 1849 uint64_t value, unsigned size) 1850 { 1851 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1852 HWADDR_PRIx"\n", addr); 1853 } 1854 1855 static const MemoryRegionOps xive_end_source_ops = { 1856 .read = xive_end_source_read, 1857 .write = xive_end_source_write, 1858 .endianness = DEVICE_BIG_ENDIAN, 1859 .valid = { 1860 .min_access_size = 8, 1861 .max_access_size = 8, 1862 }, 1863 .impl = { 1864 .min_access_size = 8, 1865 .max_access_size = 8, 1866 }, 1867 }; 1868 1869 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1870 { 1871 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1872 1873 assert(xsrc->xrtr); 1874 1875 if (!xsrc->nr_ends) { 1876 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1877 return; 1878 } 1879 1880 if (xsrc->esb_shift != XIVE_ESB_4K && 1881 xsrc->esb_shift != XIVE_ESB_64K) { 1882 error_setg(errp, "Invalid ESB shift setting"); 1883 return; 1884 } 1885 1886 /* 1887 * Each END is assigned an even/odd pair of MMIO pages, the even page 1888 * manages the ESn field while the odd page manages the ESe field. 1889 */ 1890 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1891 &xive_end_source_ops, xsrc, "xive.end", 1892 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1893 } 1894 1895 static Property xive_end_source_properties[] = { 1896 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1897 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1898 DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, 1899 XiveRouter *), 1900 DEFINE_PROP_END_OF_LIST(), 1901 }; 1902 1903 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1904 { 1905 DeviceClass *dc = DEVICE_CLASS(klass); 1906 1907 dc->desc = "XIVE END Source"; 1908 device_class_set_props(dc, xive_end_source_properties); 1909 dc->realize = xive_end_source_realize; 1910 /* 1911 * Reason: part of XIVE interrupt controller, needs to be wired up, 1912 * e.g. by spapr_xive_instance_init(). 1913 */ 1914 dc->user_creatable = false; 1915 } 1916 1917 static const TypeInfo xive_end_source_info = { 1918 .name = TYPE_XIVE_END_SOURCE, 1919 .parent = TYPE_DEVICE, 1920 .instance_size = sizeof(XiveENDSource), 1921 .class_init = xive_end_source_class_init, 1922 }; 1923 1924 /* 1925 * XIVE Notifier 1926 */ 1927 static const TypeInfo xive_notifier_info = { 1928 .name = TYPE_XIVE_NOTIFIER, 1929 .parent = TYPE_INTERFACE, 1930 .class_size = sizeof(XiveNotifierClass), 1931 }; 1932 1933 /* 1934 * XIVE Presenter 1935 */ 1936 static const TypeInfo xive_presenter_info = { 1937 .name = TYPE_XIVE_PRESENTER, 1938 .parent = TYPE_INTERFACE, 1939 .class_size = sizeof(XivePresenterClass), 1940 }; 1941 1942 /* 1943 * XIVE Fabric 1944 */ 1945 static const TypeInfo xive_fabric_info = { 1946 .name = TYPE_XIVE_FABRIC, 1947 .parent = TYPE_INTERFACE, 1948 .class_size = sizeof(XiveFabricClass), 1949 }; 1950 1951 static void xive_register_types(void) 1952 { 1953 type_register_static(&xive_fabric_info); 1954 type_register_static(&xive_source_info); 1955 type_register_static(&xive_notifier_info); 1956 type_register_static(&xive_presenter_info); 1957 type_register_static(&xive_router_info); 1958 type_register_static(&xive_end_source_info); 1959 type_register_static(&xive_tctx_info); 1960 } 1961 1962 type_init(xive_register_types) 1963