1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "monitor/monitor.h" 21 #include "hw/irq.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive_regs.h" 24 25 /* 26 * XIVE Thread Interrupt Management context 27 */ 28 29 /* 30 * Convert a priority number to an Interrupt Pending Buffer (IPB) 31 * register, which indicates a pending interrupt at the priority 32 * corresponding to the bit number 33 */ 34 static uint8_t priority_to_ipb(uint8_t priority) 35 { 36 return priority > XIVE_PRIORITY_MAX ? 37 0 : 1 << (XIVE_PRIORITY_MAX - priority); 38 } 39 40 /* 41 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 42 * Interrupt Priority Register (PIPR), which contains the priority of 43 * the most favored pending notification. 44 */ 45 static uint8_t ipb_to_pipr(uint8_t ibp) 46 { 47 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 48 } 49 50 static uint8_t exception_mask(uint8_t ring) 51 { 52 switch (ring) { 53 case TM_QW1_OS: 54 return TM_QW1_NSR_EO; 55 case TM_QW3_HV_PHYS: 56 return TM_QW3_NSR_HE; 57 default: 58 g_assert_not_reached(); 59 } 60 } 61 62 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 63 { 64 switch (ring) { 65 case TM_QW0_USER: 66 return 0; /* Not supported */ 67 case TM_QW1_OS: 68 return tctx->os_output; 69 case TM_QW2_HV_POOL: 70 case TM_QW3_HV_PHYS: 71 return tctx->hv_output; 72 default: 73 return 0; 74 } 75 } 76 77 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 78 { 79 uint8_t *regs = &tctx->regs[ring]; 80 uint8_t nsr = regs[TM_NSR]; 81 uint8_t mask = exception_mask(ring); 82 83 qemu_irq_lower(xive_tctx_output(tctx, ring)); 84 85 if (regs[TM_NSR] & mask) { 86 uint8_t cppr = regs[TM_PIPR]; 87 88 regs[TM_CPPR] = cppr; 89 90 /* Reset the pending buffer bit */ 91 regs[TM_IPB] &= ~priority_to_ipb(cppr); 92 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 93 94 /* Drop Exception bit */ 95 regs[TM_NSR] &= ~mask; 96 } 97 98 return (nsr << 8) | regs[TM_CPPR]; 99 } 100 101 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 102 { 103 uint8_t *regs = &tctx->regs[ring]; 104 105 if (regs[TM_PIPR] < regs[TM_CPPR]) { 106 switch (ring) { 107 case TM_QW1_OS: 108 regs[TM_NSR] |= TM_QW1_NSR_EO; 109 break; 110 case TM_QW3_HV_PHYS: 111 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 112 break; 113 default: 114 g_assert_not_reached(); 115 } 116 qemu_irq_raise(xive_tctx_output(tctx, ring)); 117 } 118 } 119 120 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 121 { 122 if (cppr > XIVE_PRIORITY_MAX) { 123 cppr = 0xff; 124 } 125 126 tctx->regs[ring + TM_CPPR] = cppr; 127 128 /* CPPR has changed, check if we need to raise a pending exception */ 129 xive_tctx_notify(tctx, ring); 130 } 131 132 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) 133 { 134 uint8_t *regs = &tctx->regs[ring]; 135 136 regs[TM_IPB] |= ipb; 137 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 138 xive_tctx_notify(tctx, ring); 139 } 140 141 static inline uint32_t xive_tctx_word2(uint8_t *ring) 142 { 143 return *((uint32_t *) &ring[TM_WORD2]); 144 } 145 146 /* 147 * XIVE Thread Interrupt Management Area (TIMA) 148 */ 149 150 static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 151 hwaddr offset, uint64_t value, unsigned size) 152 { 153 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 154 } 155 156 static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx, 157 hwaddr offset, unsigned size) 158 { 159 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 160 } 161 162 static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 163 hwaddr offset, unsigned size) 164 { 165 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 166 uint32_t qw2w2; 167 168 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 169 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 170 return qw2w2; 171 } 172 173 static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 174 uint64_t value, unsigned size) 175 { 176 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 177 } 178 179 static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, 180 hwaddr offset, unsigned size) 181 { 182 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 183 } 184 185 /* 186 * Define an access map for each page of the TIMA that we will use in 187 * the memory region ops to filter values when doing loads and stores 188 * of raw registers values 189 * 190 * Registers accessibility bits : 191 * 192 * 0x0 - no access 193 * 0x1 - write only 194 * 0x2 - read only 195 * 0x3 - read/write 196 */ 197 198 static const uint8_t xive_tm_hw_view[] = { 199 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 200 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 201 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 202 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 203 }; 204 205 static const uint8_t xive_tm_hv_view[] = { 206 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 207 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 208 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 209 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 210 }; 211 212 static const uint8_t xive_tm_os_view[] = { 213 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 214 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 215 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 217 }; 218 219 static const uint8_t xive_tm_user_view[] = { 220 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 223 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 224 }; 225 226 /* 227 * Overall TIMA access map for the thread interrupt management context 228 * registers 229 */ 230 static const uint8_t *xive_tm_views[] = { 231 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 232 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 233 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 234 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 235 }; 236 237 /* 238 * Computes a register access mask for a given offset in the TIMA 239 */ 240 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 241 { 242 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 243 uint8_t reg_offset = offset & 0x3F; 244 uint8_t reg_mask = write ? 0x1 : 0x2; 245 uint64_t mask = 0x0; 246 int i; 247 248 for (i = 0; i < size; i++) { 249 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 250 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 251 } 252 } 253 254 return mask; 255 } 256 257 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 258 unsigned size) 259 { 260 uint8_t ring_offset = offset & 0x30; 261 uint8_t reg_offset = offset & 0x3F; 262 uint64_t mask = xive_tm_mask(offset, size, true); 263 int i; 264 265 /* 266 * Only 4 or 8 bytes stores are allowed and the User ring is 267 * excluded 268 */ 269 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 270 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 271 HWADDR_PRIx"\n", offset); 272 return; 273 } 274 275 /* 276 * Use the register offset for the raw values and filter out 277 * reserved values 278 */ 279 for (i = 0; i < size; i++) { 280 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 281 if (byte_mask) { 282 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 283 byte_mask; 284 } 285 } 286 } 287 288 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 289 { 290 uint8_t ring_offset = offset & 0x30; 291 uint8_t reg_offset = offset & 0x3F; 292 uint64_t mask = xive_tm_mask(offset, size, false); 293 uint64_t ret; 294 int i; 295 296 /* 297 * Only 4 or 8 bytes loads are allowed and the User ring is 298 * excluded 299 */ 300 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 301 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 302 HWADDR_PRIx"\n", offset); 303 return -1; 304 } 305 306 /* Use the register offset for the raw values */ 307 ret = 0; 308 for (i = 0; i < size; i++) { 309 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 310 } 311 312 /* filter out reserved values */ 313 return ret & mask; 314 } 315 316 /* 317 * The TM context is mapped twice within each page. Stores and loads 318 * to the first mapping below 2K write and read the specified values 319 * without modification. The second mapping above 2K performs specific 320 * state changes (side effects) in addition to setting/returning the 321 * interrupt management area context of the processor thread. 322 */ 323 static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx, 324 hwaddr offset, unsigned size) 325 { 326 return xive_tctx_accept(tctx, TM_QW1_OS); 327 } 328 329 static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 330 hwaddr offset, uint64_t value, unsigned size) 331 { 332 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 333 } 334 335 /* 336 * Adjust the IPB to allow a CPU to process event queues of other 337 * priorities during one physical interrupt cycle. 338 */ 339 static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, 340 hwaddr offset, uint64_t value, unsigned size) 341 { 342 xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff)); 343 } 344 345 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, 346 uint32_t *nvt_idx, bool *vo) 347 { 348 if (nvt_blk) { 349 *nvt_blk = xive_nvt_blk(cam); 350 } 351 if (nvt_idx) { 352 *nvt_idx = xive_nvt_idx(cam); 353 } 354 if (vo) { 355 *vo = !!(cam & TM_QW1W2_VO); 356 } 357 } 358 359 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk, 360 uint32_t *nvt_idx, bool *vo) 361 { 362 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 363 uint32_t cam = be32_to_cpu(qw1w2); 364 365 xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo); 366 return qw1w2; 367 } 368 369 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) 370 { 371 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 372 } 373 374 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 375 hwaddr offset, unsigned size) 376 { 377 uint32_t qw1w2; 378 uint32_t qw1w2_new; 379 uint8_t nvt_blk; 380 uint32_t nvt_idx; 381 bool vo; 382 383 qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); 384 385 if (!vo) { 386 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n", 387 nvt_blk, nvt_idx); 388 } 389 390 /* Invalidate CAM line */ 391 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); 392 xive_tctx_set_os_cam(tctx, qw1w2_new); 393 return qw1w2; 394 } 395 396 static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx, 397 uint8_t nvt_blk, uint32_t nvt_idx) 398 { 399 XiveNVT nvt; 400 uint8_t ipb; 401 402 /* 403 * Grab the associated NVT to pull the pending bits, and merge 404 * them with the IPB of the thread interrupt context registers 405 */ 406 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 407 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n", 408 nvt_blk, nvt_idx); 409 return; 410 } 411 412 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4); 413 414 if (ipb) { 415 /* Reset the NVT value */ 416 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0); 417 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 418 419 /* Merge in current context */ 420 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); 421 } 422 } 423 424 /* 425 * Updating the OS CAM line can trigger a resend of interrupt 426 */ 427 static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 428 hwaddr offset, uint64_t value, unsigned size) 429 { 430 uint32_t cam = value; 431 uint32_t qw1w2 = cpu_to_be32(cam); 432 uint8_t nvt_blk; 433 uint32_t nvt_idx; 434 bool vo; 435 436 xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); 437 438 /* First update the registers */ 439 xive_tctx_set_os_cam(tctx, qw1w2); 440 441 /* Check the interrupt pending bits */ 442 if (vo) { 443 xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); 444 } 445 } 446 447 /* 448 * Define a mapping of "special" operations depending on the TIMA page 449 * offset and the size of the operation. 450 */ 451 typedef struct XiveTmOp { 452 uint8_t page_offset; 453 uint32_t op_offset; 454 unsigned size; 455 void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, 456 hwaddr offset, 457 uint64_t value, unsigned size); 458 uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 459 unsigned size); 460 } XiveTmOp; 461 462 static const XiveTmOp xive_tm_operations[] = { 463 /* 464 * MMIOs below 2K : raw values and special operations without side 465 * effects 466 */ 467 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 468 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, NULL }, 469 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 470 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 471 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 472 473 /* MMIOs above 2K : special operations with side effects */ 474 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 475 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 476 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, 477 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, 478 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 479 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 480 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 481 }; 482 483 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 484 { 485 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 486 uint32_t op_offset = offset & 0xFFF; 487 int i; 488 489 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 490 const XiveTmOp *xto = &xive_tm_operations[i]; 491 492 /* Accesses done from a more privileged TIMA page is allowed */ 493 if (xto->page_offset >= page_offset && 494 xto->op_offset == op_offset && 495 xto->size == size && 496 ((write && xto->write_handler) || (!write && xto->read_handler))) { 497 return xto; 498 } 499 } 500 return NULL; 501 } 502 503 /* 504 * TIMA MMIO handlers 505 */ 506 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 507 uint64_t value, unsigned size) 508 { 509 const XiveTmOp *xto; 510 511 /* 512 * TODO: check V bit in Q[0-3]W2 513 */ 514 515 /* 516 * First, check for special operations in the 2K region 517 */ 518 if (offset & 0x800) { 519 xto = xive_tm_find_op(offset, size, true); 520 if (!xto) { 521 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 522 "@%"HWADDR_PRIx"\n", offset); 523 } else { 524 xto->write_handler(xptr, tctx, offset, value, size); 525 } 526 return; 527 } 528 529 /* 530 * Then, for special operations in the region below 2K. 531 */ 532 xto = xive_tm_find_op(offset, size, true); 533 if (xto) { 534 xto->write_handler(xptr, tctx, offset, value, size); 535 return; 536 } 537 538 /* 539 * Finish with raw access to the register values 540 */ 541 xive_tm_raw_write(tctx, offset, value, size); 542 } 543 544 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 545 unsigned size) 546 { 547 const XiveTmOp *xto; 548 549 /* 550 * TODO: check V bit in Q[0-3]W2 551 */ 552 553 /* 554 * First, check for special operations in the 2K region 555 */ 556 if (offset & 0x800) { 557 xto = xive_tm_find_op(offset, size, false); 558 if (!xto) { 559 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 560 "@%"HWADDR_PRIx"\n", offset); 561 return -1; 562 } 563 return xto->read_handler(xptr, tctx, offset, size); 564 } 565 566 /* 567 * Then, for special operations in the region below 2K. 568 */ 569 xto = xive_tm_find_op(offset, size, false); 570 if (xto) { 571 return xto->read_handler(xptr, tctx, offset, size); 572 } 573 574 /* 575 * Finish with raw access to the register values 576 */ 577 return xive_tm_raw_read(tctx, offset, size); 578 } 579 580 static char *xive_tctx_ring_print(uint8_t *ring) 581 { 582 uint32_t w2 = xive_tctx_word2(ring); 583 584 return g_strdup_printf("%02x %02x %02x %02x %02x " 585 "%02x %02x %02x %08x", 586 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 587 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 588 be32_to_cpu(w2)); 589 } 590 591 static const char * const xive_tctx_ring_names[] = { 592 "USER", "OS", "POOL", "PHYS", 593 }; 594 595 /* 596 * kvm_irqchip_in_kernel() will cause the compiler to turn this 597 * info a nop if CONFIG_KVM isn't defined. 598 */ 599 #define xive_in_kernel(xptr) \ 600 (kvm_irqchip_in_kernel() && \ 601 ({ \ 602 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); \ 603 xpc->in_kernel ? xpc->in_kernel(xptr) : false; \ 604 })) 605 606 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 607 { 608 int cpu_index; 609 int i; 610 611 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs 612 * are hot plugged or unplugged. 613 */ 614 if (!tctx) { 615 return; 616 } 617 618 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 619 620 if (xive_in_kernel(tctx->xptr)) { 621 Error *local_err = NULL; 622 623 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 624 if (local_err) { 625 error_report_err(local_err); 626 return; 627 } 628 } 629 630 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 631 " W2\n", cpu_index); 632 633 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 634 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 635 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 636 xive_tctx_ring_names[i], s); 637 g_free(s); 638 } 639 } 640 641 void xive_tctx_reset(XiveTCTX *tctx) 642 { 643 memset(tctx->regs, 0, sizeof(tctx->regs)); 644 645 /* Set some defaults */ 646 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 647 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 648 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 649 650 /* 651 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 652 * CPPR is first set. 653 */ 654 tctx->regs[TM_QW1_OS + TM_PIPR] = 655 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 656 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 657 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 658 } 659 660 static void xive_tctx_realize(DeviceState *dev, Error **errp) 661 { 662 XiveTCTX *tctx = XIVE_TCTX(dev); 663 PowerPCCPU *cpu; 664 CPUPPCState *env; 665 Error *local_err = NULL; 666 667 assert(tctx->cs); 668 assert(tctx->xptr); 669 670 cpu = POWERPC_CPU(tctx->cs); 671 env = &cpu->env; 672 switch (PPC_INPUT(env)) { 673 case PPC_FLAGS_INPUT_POWER9: 674 tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT]; 675 tctx->os_output = env->irq_inputs[POWER9_INPUT_INT]; 676 break; 677 678 default: 679 error_setg(errp, "XIVE interrupt controller does not support " 680 "this CPU bus model"); 681 return; 682 } 683 684 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 685 if (xive_in_kernel(tctx->xptr)) { 686 kvmppc_xive_cpu_connect(tctx, &local_err); 687 if (local_err) { 688 error_propagate(errp, local_err); 689 return; 690 } 691 } 692 } 693 694 static int vmstate_xive_tctx_pre_save(void *opaque) 695 { 696 XiveTCTX *tctx = XIVE_TCTX(opaque); 697 Error *local_err = NULL; 698 699 if (xive_in_kernel(tctx->xptr)) { 700 kvmppc_xive_cpu_get_state(tctx, &local_err); 701 if (local_err) { 702 error_report_err(local_err); 703 return -1; 704 } 705 } 706 707 return 0; 708 } 709 710 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 711 { 712 XiveTCTX *tctx = XIVE_TCTX(opaque); 713 Error *local_err = NULL; 714 715 if (xive_in_kernel(tctx->xptr)) { 716 /* 717 * Required for hotplugged CPU, for which the state comes 718 * after all states of the machine. 719 */ 720 kvmppc_xive_cpu_set_state(tctx, &local_err); 721 if (local_err) { 722 error_report_err(local_err); 723 return -1; 724 } 725 } 726 727 return 0; 728 } 729 730 static const VMStateDescription vmstate_xive_tctx = { 731 .name = TYPE_XIVE_TCTX, 732 .version_id = 1, 733 .minimum_version_id = 1, 734 .pre_save = vmstate_xive_tctx_pre_save, 735 .post_load = vmstate_xive_tctx_post_load, 736 .fields = (VMStateField[]) { 737 VMSTATE_BUFFER(regs, XiveTCTX), 738 VMSTATE_END_OF_LIST() 739 }, 740 }; 741 742 static Property xive_tctx_properties[] = { 743 DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), 744 DEFINE_PROP_LINK("presenter", XiveTCTX, xptr, TYPE_XIVE_PRESENTER, 745 XivePresenter *), 746 DEFINE_PROP_END_OF_LIST(), 747 }; 748 749 static void xive_tctx_class_init(ObjectClass *klass, void *data) 750 { 751 DeviceClass *dc = DEVICE_CLASS(klass); 752 753 dc->desc = "XIVE Interrupt Thread Context"; 754 dc->realize = xive_tctx_realize; 755 dc->vmsd = &vmstate_xive_tctx; 756 device_class_set_props(dc, xive_tctx_properties); 757 /* 758 * Reason: part of XIVE interrupt controller, needs to be wired up 759 * by xive_tctx_create(). 760 */ 761 dc->user_creatable = false; 762 } 763 764 static const TypeInfo xive_tctx_info = { 765 .name = TYPE_XIVE_TCTX, 766 .parent = TYPE_DEVICE, 767 .instance_size = sizeof(XiveTCTX), 768 .class_init = xive_tctx_class_init, 769 }; 770 771 Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp) 772 { 773 Object *obj; 774 775 obj = object_new(TYPE_XIVE_TCTX); 776 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj); 777 object_unref(obj); 778 object_property_set_link(obj, "cpu", cpu, &error_abort); 779 object_property_set_link(obj, "presenter", OBJECT(xptr), &error_abort); 780 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 781 object_unparent(obj); 782 return NULL; 783 } 784 return obj; 785 } 786 787 void xive_tctx_destroy(XiveTCTX *tctx) 788 { 789 Object *obj = OBJECT(tctx); 790 791 object_unparent(obj); 792 } 793 794 /* 795 * XIVE ESB helpers 796 */ 797 798 static uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 799 { 800 uint8_t old_pq = *pq & 0x3; 801 802 *pq &= ~0x3; 803 *pq |= value & 0x3; 804 805 return old_pq; 806 } 807 808 static bool xive_esb_trigger(uint8_t *pq) 809 { 810 uint8_t old_pq = *pq & 0x3; 811 812 switch (old_pq) { 813 case XIVE_ESB_RESET: 814 xive_esb_set(pq, XIVE_ESB_PENDING); 815 return true; 816 case XIVE_ESB_PENDING: 817 case XIVE_ESB_QUEUED: 818 xive_esb_set(pq, XIVE_ESB_QUEUED); 819 return false; 820 case XIVE_ESB_OFF: 821 xive_esb_set(pq, XIVE_ESB_OFF); 822 return false; 823 default: 824 g_assert_not_reached(); 825 } 826 } 827 828 static bool xive_esb_eoi(uint8_t *pq) 829 { 830 uint8_t old_pq = *pq & 0x3; 831 832 switch (old_pq) { 833 case XIVE_ESB_RESET: 834 case XIVE_ESB_PENDING: 835 xive_esb_set(pq, XIVE_ESB_RESET); 836 return false; 837 case XIVE_ESB_QUEUED: 838 xive_esb_set(pq, XIVE_ESB_PENDING); 839 return true; 840 case XIVE_ESB_OFF: 841 xive_esb_set(pq, XIVE_ESB_OFF); 842 return false; 843 default: 844 g_assert_not_reached(); 845 } 846 } 847 848 /* 849 * XIVE Interrupt Source (or IVSE) 850 */ 851 852 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 853 { 854 assert(srcno < xsrc->nr_irqs); 855 856 return xsrc->status[srcno] & 0x3; 857 } 858 859 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 860 { 861 assert(srcno < xsrc->nr_irqs); 862 863 return xive_esb_set(&xsrc->status[srcno], pq); 864 } 865 866 /* 867 * Returns whether the event notification should be forwarded. 868 */ 869 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 870 { 871 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 872 873 xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; 874 875 switch (old_pq) { 876 case XIVE_ESB_RESET: 877 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 878 return true; 879 default: 880 return false; 881 } 882 } 883 884 /* 885 * Returns whether the event notification should be forwarded. 886 */ 887 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 888 { 889 bool ret; 890 891 assert(srcno < xsrc->nr_irqs); 892 893 ret = xive_esb_trigger(&xsrc->status[srcno]); 894 895 if (xive_source_irq_is_lsi(xsrc, srcno) && 896 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 897 qemu_log_mask(LOG_GUEST_ERROR, 898 "XIVE: queued an event on LSI IRQ %d\n", srcno); 899 } 900 901 return ret; 902 } 903 904 /* 905 * Returns whether the event notification should be forwarded. 906 */ 907 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 908 { 909 bool ret; 910 911 assert(srcno < xsrc->nr_irqs); 912 913 ret = xive_esb_eoi(&xsrc->status[srcno]); 914 915 /* 916 * LSI sources do not set the Q bit but they can still be 917 * asserted, in which case we should forward a new event 918 * notification 919 */ 920 if (xive_source_irq_is_lsi(xsrc, srcno) && 921 xsrc->status[srcno] & XIVE_STATUS_ASSERTED) { 922 ret = xive_source_lsi_trigger(xsrc, srcno); 923 } 924 925 return ret; 926 } 927 928 /* 929 * Forward the source event notification to the Router 930 */ 931 static void xive_source_notify(XiveSource *xsrc, int srcno) 932 { 933 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 934 935 if (xnc->notify) { 936 xnc->notify(xsrc->xive, srcno); 937 } 938 } 939 940 /* 941 * In a two pages ESB MMIO setting, even page is the trigger page, odd 942 * page is for management 943 */ 944 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 945 { 946 return !((addr >> shift) & 1); 947 } 948 949 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 950 { 951 return xive_source_esb_has_2page(xsrc) && 952 addr_is_even(addr, xsrc->esb_shift - 1); 953 } 954 955 /* 956 * ESB MMIO loads 957 * Trigger page Management/EOI page 958 * 959 * ESB MMIO setting 2 pages 1 or 2 pages 960 * 961 * 0x000 .. 0x3FF -1 EOI and return 0|1 962 * 0x400 .. 0x7FF -1 EOI and return 0|1 963 * 0x800 .. 0xBFF -1 return PQ 964 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 965 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 966 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 967 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 968 */ 969 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 970 { 971 XiveSource *xsrc = XIVE_SOURCE(opaque); 972 uint32_t offset = addr & 0xFFF; 973 uint32_t srcno = addr >> xsrc->esb_shift; 974 uint64_t ret = -1; 975 976 /* In a two pages ESB MMIO setting, trigger page should not be read */ 977 if (xive_source_is_trigger_page(xsrc, addr)) { 978 qemu_log_mask(LOG_GUEST_ERROR, 979 "XIVE: invalid load on IRQ %d trigger page at " 980 "0x%"HWADDR_PRIx"\n", srcno, addr); 981 return -1; 982 } 983 984 switch (offset) { 985 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 986 ret = xive_source_esb_eoi(xsrc, srcno); 987 988 /* Forward the source event notification for routing */ 989 if (ret) { 990 xive_source_notify(xsrc, srcno); 991 } 992 break; 993 994 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 995 ret = xive_source_esb_get(xsrc, srcno); 996 break; 997 998 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 999 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1000 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1001 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1002 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1003 break; 1004 default: 1005 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 1006 offset); 1007 } 1008 1009 return ret; 1010 } 1011 1012 /* 1013 * ESB MMIO stores 1014 * Trigger page Management/EOI page 1015 * 1016 * ESB MMIO setting 2 pages 1 or 2 pages 1017 * 1018 * 0x000 .. 0x3FF Trigger Trigger 1019 * 0x400 .. 0x7FF Trigger EOI 1020 * 0x800 .. 0xBFF Trigger undefined 1021 * 0xC00 .. 0xCFF Trigger PQ=00 1022 * 0xD00 .. 0xDFF Trigger PQ=01 1023 * 0xE00 .. 0xDFF Trigger PQ=10 1024 * 0xF00 .. 0xDFF Trigger PQ=11 1025 */ 1026 static void xive_source_esb_write(void *opaque, hwaddr addr, 1027 uint64_t value, unsigned size) 1028 { 1029 XiveSource *xsrc = XIVE_SOURCE(opaque); 1030 uint32_t offset = addr & 0xFFF; 1031 uint32_t srcno = addr >> xsrc->esb_shift; 1032 bool notify = false; 1033 1034 /* In a two pages ESB MMIO setting, trigger page only triggers */ 1035 if (xive_source_is_trigger_page(xsrc, addr)) { 1036 notify = xive_source_esb_trigger(xsrc, srcno); 1037 goto out; 1038 } 1039 1040 switch (offset) { 1041 case 0 ... 0x3FF: 1042 notify = xive_source_esb_trigger(xsrc, srcno); 1043 break; 1044 1045 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 1046 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 1047 qemu_log_mask(LOG_GUEST_ERROR, 1048 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 1049 return; 1050 } 1051 1052 notify = xive_source_esb_eoi(xsrc, srcno); 1053 break; 1054 1055 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1056 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1057 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1058 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1059 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1060 break; 1061 1062 default: 1063 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 1064 offset); 1065 return; 1066 } 1067 1068 out: 1069 /* Forward the source event notification for routing */ 1070 if (notify) { 1071 xive_source_notify(xsrc, srcno); 1072 } 1073 } 1074 1075 static const MemoryRegionOps xive_source_esb_ops = { 1076 .read = xive_source_esb_read, 1077 .write = xive_source_esb_write, 1078 .endianness = DEVICE_BIG_ENDIAN, 1079 .valid = { 1080 .min_access_size = 8, 1081 .max_access_size = 8, 1082 }, 1083 .impl = { 1084 .min_access_size = 8, 1085 .max_access_size = 8, 1086 }, 1087 }; 1088 1089 void xive_source_set_irq(void *opaque, int srcno, int val) 1090 { 1091 XiveSource *xsrc = XIVE_SOURCE(opaque); 1092 bool notify = false; 1093 1094 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1095 if (val) { 1096 notify = xive_source_lsi_trigger(xsrc, srcno); 1097 } else { 1098 xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; 1099 } 1100 } else { 1101 if (val) { 1102 notify = xive_source_esb_trigger(xsrc, srcno); 1103 } 1104 } 1105 1106 /* Forward the source event notification for routing */ 1107 if (notify) { 1108 xive_source_notify(xsrc, srcno); 1109 } 1110 } 1111 1112 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 1113 { 1114 int i; 1115 1116 for (i = 0; i < xsrc->nr_irqs; i++) { 1117 uint8_t pq = xive_source_esb_get(xsrc, i); 1118 1119 if (pq == XIVE_ESB_OFF) { 1120 continue; 1121 } 1122 1123 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 1124 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1125 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1126 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1127 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' '); 1128 } 1129 } 1130 1131 static void xive_source_reset(void *dev) 1132 { 1133 XiveSource *xsrc = XIVE_SOURCE(dev); 1134 1135 /* Do not clear the LSI bitmap */ 1136 1137 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 1138 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 1139 } 1140 1141 static void xive_source_realize(DeviceState *dev, Error **errp) 1142 { 1143 XiveSource *xsrc = XIVE_SOURCE(dev); 1144 size_t esb_len = xive_source_esb_len(xsrc); 1145 1146 assert(xsrc->xive); 1147 1148 if (!xsrc->nr_irqs) { 1149 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1150 return; 1151 } 1152 1153 if (xsrc->esb_shift != XIVE_ESB_4K && 1154 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1155 xsrc->esb_shift != XIVE_ESB_64K && 1156 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1157 error_setg(errp, "Invalid ESB shift setting"); 1158 return; 1159 } 1160 1161 xsrc->status = g_malloc0(xsrc->nr_irqs); 1162 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1163 1164 memory_region_init(&xsrc->esb_mmio, OBJECT(xsrc), "xive.esb", esb_len); 1165 memory_region_init_io(&xsrc->esb_mmio_emulated, OBJECT(xsrc), 1166 &xive_source_esb_ops, xsrc, "xive.esb-emulated", 1167 esb_len); 1168 memory_region_add_subregion(&xsrc->esb_mmio, 0, &xsrc->esb_mmio_emulated); 1169 1170 qemu_register_reset(xive_source_reset, dev); 1171 } 1172 1173 static const VMStateDescription vmstate_xive_source = { 1174 .name = TYPE_XIVE_SOURCE, 1175 .version_id = 1, 1176 .minimum_version_id = 1, 1177 .fields = (VMStateField[]) { 1178 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1179 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1180 VMSTATE_END_OF_LIST() 1181 }, 1182 }; 1183 1184 /* 1185 * The default XIVE interrupt source setting for the ESB MMIOs is two 1186 * 64k pages without Store EOI, to be in sync with KVM. 1187 */ 1188 static Property xive_source_properties[] = { 1189 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1190 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1191 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1192 DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, 1193 XiveNotifier *), 1194 DEFINE_PROP_END_OF_LIST(), 1195 }; 1196 1197 static void xive_source_class_init(ObjectClass *klass, void *data) 1198 { 1199 DeviceClass *dc = DEVICE_CLASS(klass); 1200 1201 dc->desc = "XIVE Interrupt Source"; 1202 device_class_set_props(dc, xive_source_properties); 1203 dc->realize = xive_source_realize; 1204 dc->vmsd = &vmstate_xive_source; 1205 /* 1206 * Reason: part of XIVE interrupt controller, needs to be wired up, 1207 * e.g. by spapr_xive_instance_init(). 1208 */ 1209 dc->user_creatable = false; 1210 } 1211 1212 static const TypeInfo xive_source_info = { 1213 .name = TYPE_XIVE_SOURCE, 1214 .parent = TYPE_DEVICE, 1215 .instance_size = sizeof(XiveSource), 1216 .class_init = xive_source_class_init, 1217 }; 1218 1219 /* 1220 * XiveEND helpers 1221 */ 1222 1223 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1224 { 1225 uint64_t qaddr_base = xive_end_qaddr(end); 1226 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1227 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1228 uint32_t qentries = 1 << (qsize + 10); 1229 int i; 1230 1231 /* 1232 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1233 */ 1234 monitor_printf(mon, " [ "); 1235 qindex = (qindex - (width - 1)) & (qentries - 1); 1236 for (i = 0; i < width; i++) { 1237 uint64_t qaddr = qaddr_base + (qindex << 2); 1238 uint32_t qdata = -1; 1239 1240 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 1241 sizeof(qdata))) { 1242 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1243 HWADDR_PRIx "\n", qaddr); 1244 return; 1245 } 1246 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1247 be32_to_cpu(qdata)); 1248 qindex = (qindex + 1) & (qentries - 1); 1249 } 1250 monitor_printf(mon, "]"); 1251 } 1252 1253 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1254 { 1255 uint64_t qaddr_base = xive_end_qaddr(end); 1256 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1257 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1258 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1259 uint32_t qentries = 1 << (qsize + 10); 1260 1261 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1262 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1263 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1264 uint8_t pq; 1265 1266 if (!xive_end_is_valid(end)) { 1267 return; 1268 } 1269 1270 pq = xive_get_field32(END_W1_ESn, end->w1); 1271 1272 monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1273 end_idx, 1274 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1275 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1276 xive_end_is_valid(end) ? 'v' : '-', 1277 xive_end_is_enqueue(end) ? 'q' : '-', 1278 xive_end_is_notify(end) ? 'n' : '-', 1279 xive_end_is_backlog(end) ? 'b' : '-', 1280 xive_end_is_escalate(end) ? 'e' : '-', 1281 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1282 xive_end_is_silent_escalation(end) ? 's' : '-', 1283 priority, nvt_blk, nvt_idx); 1284 1285 if (qaddr_base) { 1286 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1287 qaddr_base, qindex, qentries, qgen); 1288 xive_end_queue_pic_print_info(end, 6, mon); 1289 } 1290 monitor_printf(mon, "\n"); 1291 } 1292 1293 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1294 { 1295 uint64_t qaddr_base = xive_end_qaddr(end); 1296 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1297 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1298 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1299 1300 uint64_t qaddr = qaddr_base + (qindex << 2); 1301 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1302 uint32_t qentries = 1 << (qsize + 10); 1303 1304 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) { 1305 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1306 HWADDR_PRIx "\n", qaddr); 1307 return; 1308 } 1309 1310 qindex = (qindex + 1) & (qentries - 1); 1311 if (qindex == 0) { 1312 qgen ^= 1; 1313 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1314 } 1315 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1316 } 1317 1318 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, 1319 Monitor *mon) 1320 { 1321 XiveEAS *eas = (XiveEAS *) &end->w4; 1322 uint8_t pq; 1323 1324 if (!xive_end_is_escalate(end)) { 1325 return; 1326 } 1327 1328 pq = xive_get_field32(END_W1_ESe, end->w1); 1329 1330 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1331 end_idx, 1332 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1333 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1334 xive_eas_is_valid(eas) ? 'V' : ' ', 1335 xive_eas_is_masked(eas) ? 'M' : ' ', 1336 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1337 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1338 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1339 } 1340 1341 /* 1342 * XIVE Router (aka. Virtualization Controller or IVRE) 1343 */ 1344 1345 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1346 XiveEAS *eas) 1347 { 1348 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1349 1350 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1351 } 1352 1353 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1354 XiveEND *end) 1355 { 1356 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1357 1358 return xrc->get_end(xrtr, end_blk, end_idx, end); 1359 } 1360 1361 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1362 XiveEND *end, uint8_t word_number) 1363 { 1364 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1365 1366 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1367 } 1368 1369 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1370 XiveNVT *nvt) 1371 { 1372 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1373 1374 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1375 } 1376 1377 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1378 XiveNVT *nvt, uint8_t word_number) 1379 { 1380 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1381 1382 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1383 } 1384 1385 static int xive_router_get_block_id(XiveRouter *xrtr) 1386 { 1387 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1388 1389 return xrc->get_block_id(xrtr); 1390 } 1391 1392 static void xive_router_realize(DeviceState *dev, Error **errp) 1393 { 1394 XiveRouter *xrtr = XIVE_ROUTER(dev); 1395 1396 assert(xrtr->xfb); 1397 } 1398 1399 /* 1400 * Encode the HW CAM line in the block group mode format : 1401 * 1402 * chip << 19 | 0000000 0 0001 thread (7Bit) 1403 */ 1404 static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 1405 { 1406 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1407 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1408 uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr)); 1409 1410 return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); 1411 } 1412 1413 /* 1414 * The thread context register words are in big-endian format. 1415 */ 1416 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1417 uint8_t format, 1418 uint8_t nvt_blk, uint32_t nvt_idx, 1419 bool cam_ignore, uint32_t logic_serv) 1420 { 1421 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1422 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1423 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1424 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1425 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1426 1427 /* 1428 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1429 * identifier are ignored in the "CAM" match. 1430 */ 1431 1432 if (format == 0) { 1433 if (cam_ignore == true) { 1434 /* 1435 * F=0 & i=1: Logical server notification (bits ignored at 1436 * the end of the NVT identifier) 1437 */ 1438 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1439 nvt_blk, nvt_idx); 1440 return -1; 1441 } 1442 1443 /* F=0 & i=0: Specific NVT notification */ 1444 1445 /* PHYS ring */ 1446 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1447 cam == xive_tctx_hw_cam_line(xptr, tctx)) { 1448 return TM_QW3_HV_PHYS; 1449 } 1450 1451 /* HV POOL ring */ 1452 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1453 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1454 return TM_QW2_HV_POOL; 1455 } 1456 1457 /* OS ring */ 1458 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1459 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1460 return TM_QW1_OS; 1461 } 1462 } else { 1463 /* F=1 : User level Event-Based Branch (EBB) notification */ 1464 1465 /* USER ring */ 1466 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1467 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1468 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1469 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1470 return TM_QW0_USER; 1471 } 1472 } 1473 return -1; 1474 } 1475 1476 /* 1477 * This is our simple Xive Presenter Engine model. It is merged in the 1478 * Router as it does not require an extra object. 1479 * 1480 * It receives notification requests sent by the IVRE to find one 1481 * matching NVT (or more) dispatched on the processor threads. In case 1482 * of a single NVT notification, the process is abreviated and the 1483 * thread is signaled if a match is found. In case of a logical server 1484 * notification (bits ignored at the end of the NVT identifier), the 1485 * IVPE and IVRE select a winning thread using different filters. This 1486 * involves 2 or 3 exchanges on the PowerBus that the model does not 1487 * support. 1488 * 1489 * The parameters represent what is sent on the PowerBus 1490 */ 1491 static bool xive_presenter_notify(XiveFabric *xfb, uint8_t format, 1492 uint8_t nvt_blk, uint32_t nvt_idx, 1493 bool cam_ignore, uint8_t priority, 1494 uint32_t logic_serv) 1495 { 1496 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb); 1497 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1498 int count; 1499 1500 /* 1501 * Ask the machine to scan the interrupt controllers for a match 1502 */ 1503 count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore, 1504 priority, logic_serv, &match); 1505 if (count < 0) { 1506 return false; 1507 } 1508 1509 /* handle CPU exception delivery */ 1510 if (count) { 1511 xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(priority)); 1512 } 1513 1514 return !!count; 1515 } 1516 1517 /* 1518 * Notification using the END ESe/ESn bit (Event State Buffer for 1519 * escalation and notification). Provide further coalescing in the 1520 * Router. 1521 */ 1522 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1523 uint32_t end_idx, XiveEND *end, 1524 uint32_t end_esmask) 1525 { 1526 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1527 bool notify = xive_esb_trigger(&pq); 1528 1529 if (pq != xive_get_field32(end_esmask, end->w1)) { 1530 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1531 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1532 } 1533 1534 /* ESe/n[Q]=1 : end of notification */ 1535 return notify; 1536 } 1537 1538 /* 1539 * An END trigger can come from an event trigger (IPI or HW) or from 1540 * another chip. We don't model the PowerBus but the END trigger 1541 * message has the same parameters than in the function below. 1542 */ 1543 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1544 uint32_t end_idx, uint32_t end_data) 1545 { 1546 XiveEND end; 1547 uint8_t priority; 1548 uint8_t format; 1549 uint8_t nvt_blk; 1550 uint32_t nvt_idx; 1551 XiveNVT nvt; 1552 bool found; 1553 1554 /* END cache lookup */ 1555 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1556 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1557 end_idx); 1558 return; 1559 } 1560 1561 if (!xive_end_is_valid(&end)) { 1562 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1563 end_blk, end_idx); 1564 return; 1565 } 1566 1567 if (xive_end_is_enqueue(&end)) { 1568 xive_end_enqueue(&end, end_data); 1569 /* Enqueuing event data modifies the EQ toggle and index */ 1570 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1571 } 1572 1573 /* 1574 * When the END is silent, we skip the notification part. 1575 */ 1576 if (xive_end_is_silent_escalation(&end)) { 1577 goto do_escalation; 1578 } 1579 1580 /* 1581 * The W7 format depends on the F bit in W6. It defines the type 1582 * of the notification : 1583 * 1584 * F=0 : single or multiple NVT notification 1585 * F=1 : User level Event-Based Branch (EBB) notification, no 1586 * priority 1587 */ 1588 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1589 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1590 1591 /* The END is masked */ 1592 if (format == 0 && priority == 0xff) { 1593 return; 1594 } 1595 1596 /* 1597 * Check the END ESn (Event State Buffer for notification) for 1598 * even further coalescing in the Router 1599 */ 1600 if (!xive_end_is_notify(&end)) { 1601 /* ESn[Q]=1 : end of notification */ 1602 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1603 &end, END_W1_ESn)) { 1604 return; 1605 } 1606 } 1607 1608 /* 1609 * Follows IVPE notification 1610 */ 1611 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1612 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1613 1614 /* NVT cache lookup */ 1615 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1616 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1617 nvt_blk, nvt_idx); 1618 return; 1619 } 1620 1621 if (!xive_nvt_is_valid(&nvt)) { 1622 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1623 nvt_blk, nvt_idx); 1624 return; 1625 } 1626 1627 found = xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx, 1628 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1629 priority, 1630 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1631 1632 /* TODO: Auto EOI. */ 1633 1634 if (found) { 1635 return; 1636 } 1637 1638 /* 1639 * If no matching NVT is dispatched on a HW thread : 1640 * - specific VP: update the NVT structure if backlog is activated 1641 * - logical server : forward request to IVPE (not supported) 1642 */ 1643 if (xive_end_is_backlog(&end)) { 1644 uint8_t ipb; 1645 1646 if (format == 1) { 1647 qemu_log_mask(LOG_GUEST_ERROR, 1648 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1649 end_blk, end_idx); 1650 return; 1651 } 1652 /* 1653 * Record the IPB in the associated NVT structure for later 1654 * use. The presenter will resend the interrupt when the vCPU 1655 * is dispatched again on a HW thread. 1656 */ 1657 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priority); 1658 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); 1659 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1660 1661 /* 1662 * On HW, follows a "Broadcast Backlog" to IVPEs 1663 */ 1664 } 1665 1666 do_escalation: 1667 /* 1668 * If activated, escalate notification using the ESe PQ bits and 1669 * the EAS in w4-5 1670 */ 1671 if (!xive_end_is_escalate(&end)) { 1672 return; 1673 } 1674 1675 /* 1676 * Check the END ESe (Event State Buffer for escalation) for even 1677 * further coalescing in the Router 1678 */ 1679 if (!xive_end_is_uncond_escalation(&end)) { 1680 /* ESe[Q]=1 : end of notification */ 1681 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1682 &end, END_W1_ESe)) { 1683 return; 1684 } 1685 } 1686 1687 /* 1688 * The END trigger becomes an Escalation trigger 1689 */ 1690 xive_router_end_notify(xrtr, 1691 xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1692 xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1693 xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1694 } 1695 1696 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 1697 { 1698 XiveRouter *xrtr = XIVE_ROUTER(xn); 1699 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1700 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1701 XiveEAS eas; 1702 1703 /* EAS cache lookup */ 1704 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1705 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1706 return; 1707 } 1708 1709 /* 1710 * The IVRE checks the State Bit Cache at this point. We skip the 1711 * SBC lookup because the state bits of the sources are modeled 1712 * internally in QEMU. 1713 */ 1714 1715 if (!xive_eas_is_valid(&eas)) { 1716 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1717 return; 1718 } 1719 1720 if (xive_eas_is_masked(&eas)) { 1721 /* Notification completed */ 1722 return; 1723 } 1724 1725 /* 1726 * The event trigger becomes an END trigger 1727 */ 1728 xive_router_end_notify(xrtr, 1729 xive_get_field64(EAS_END_BLOCK, eas.w), 1730 xive_get_field64(EAS_END_INDEX, eas.w), 1731 xive_get_field64(EAS_END_DATA, eas.w)); 1732 } 1733 1734 static Property xive_router_properties[] = { 1735 DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb, 1736 TYPE_XIVE_FABRIC, XiveFabric *), 1737 DEFINE_PROP_END_OF_LIST(), 1738 }; 1739 1740 static void xive_router_class_init(ObjectClass *klass, void *data) 1741 { 1742 DeviceClass *dc = DEVICE_CLASS(klass); 1743 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1744 1745 dc->desc = "XIVE Router Engine"; 1746 device_class_set_props(dc, xive_router_properties); 1747 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 1748 dc->realize = xive_router_realize; 1749 xnc->notify = xive_router_notify; 1750 } 1751 1752 static const TypeInfo xive_router_info = { 1753 .name = TYPE_XIVE_ROUTER, 1754 .parent = TYPE_SYS_BUS_DEVICE, 1755 .abstract = true, 1756 .instance_size = sizeof(XiveRouter), 1757 .class_size = sizeof(XiveRouterClass), 1758 .class_init = xive_router_class_init, 1759 .interfaces = (InterfaceInfo[]) { 1760 { TYPE_XIVE_NOTIFIER }, 1761 { TYPE_XIVE_PRESENTER }, 1762 { } 1763 } 1764 }; 1765 1766 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1767 { 1768 if (!xive_eas_is_valid(eas)) { 1769 return; 1770 } 1771 1772 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1773 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1774 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1775 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1776 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1777 } 1778 1779 /* 1780 * END ESB MMIO loads 1781 */ 1782 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1783 { 1784 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1785 uint32_t offset = addr & 0xFFF; 1786 uint8_t end_blk; 1787 uint32_t end_idx; 1788 XiveEND end; 1789 uint32_t end_esmask; 1790 uint8_t pq; 1791 uint64_t ret = -1; 1792 1793 /* 1794 * The block id should be deduced from the load address on the END 1795 * ESB MMIO but our model only supports a single block per XIVE chip. 1796 */ 1797 end_blk = xive_router_get_block_id(xsrc->xrtr); 1798 end_idx = addr >> (xsrc->esb_shift + 1); 1799 1800 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1801 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1802 end_idx); 1803 return -1; 1804 } 1805 1806 if (!xive_end_is_valid(&end)) { 1807 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1808 end_blk, end_idx); 1809 return -1; 1810 } 1811 1812 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1813 pq = xive_get_field32(end_esmask, end.w1); 1814 1815 switch (offset) { 1816 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1817 ret = xive_esb_eoi(&pq); 1818 1819 /* Forward the source event notification for routing ?? */ 1820 break; 1821 1822 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1823 ret = pq; 1824 break; 1825 1826 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1827 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1828 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1829 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1830 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1831 break; 1832 default: 1833 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1834 offset); 1835 return -1; 1836 } 1837 1838 if (pq != xive_get_field32(end_esmask, end.w1)) { 1839 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1840 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1841 } 1842 1843 return ret; 1844 } 1845 1846 /* 1847 * END ESB MMIO stores are invalid 1848 */ 1849 static void xive_end_source_write(void *opaque, hwaddr addr, 1850 uint64_t value, unsigned size) 1851 { 1852 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1853 HWADDR_PRIx"\n", addr); 1854 } 1855 1856 static const MemoryRegionOps xive_end_source_ops = { 1857 .read = xive_end_source_read, 1858 .write = xive_end_source_write, 1859 .endianness = DEVICE_BIG_ENDIAN, 1860 .valid = { 1861 .min_access_size = 8, 1862 .max_access_size = 8, 1863 }, 1864 .impl = { 1865 .min_access_size = 8, 1866 .max_access_size = 8, 1867 }, 1868 }; 1869 1870 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1871 { 1872 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1873 1874 assert(xsrc->xrtr); 1875 1876 if (!xsrc->nr_ends) { 1877 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1878 return; 1879 } 1880 1881 if (xsrc->esb_shift != XIVE_ESB_4K && 1882 xsrc->esb_shift != XIVE_ESB_64K) { 1883 error_setg(errp, "Invalid ESB shift setting"); 1884 return; 1885 } 1886 1887 /* 1888 * Each END is assigned an even/odd pair of MMIO pages, the even page 1889 * manages the ESn field while the odd page manages the ESe field. 1890 */ 1891 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1892 &xive_end_source_ops, xsrc, "xive.end", 1893 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1894 } 1895 1896 static Property xive_end_source_properties[] = { 1897 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1898 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1899 DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, 1900 XiveRouter *), 1901 DEFINE_PROP_END_OF_LIST(), 1902 }; 1903 1904 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1905 { 1906 DeviceClass *dc = DEVICE_CLASS(klass); 1907 1908 dc->desc = "XIVE END Source"; 1909 device_class_set_props(dc, xive_end_source_properties); 1910 dc->realize = xive_end_source_realize; 1911 /* 1912 * Reason: part of XIVE interrupt controller, needs to be wired up, 1913 * e.g. by spapr_xive_instance_init(). 1914 */ 1915 dc->user_creatable = false; 1916 } 1917 1918 static const TypeInfo xive_end_source_info = { 1919 .name = TYPE_XIVE_END_SOURCE, 1920 .parent = TYPE_DEVICE, 1921 .instance_size = sizeof(XiveENDSource), 1922 .class_init = xive_end_source_class_init, 1923 }; 1924 1925 /* 1926 * XIVE Notifier 1927 */ 1928 static const TypeInfo xive_notifier_info = { 1929 .name = TYPE_XIVE_NOTIFIER, 1930 .parent = TYPE_INTERFACE, 1931 .class_size = sizeof(XiveNotifierClass), 1932 }; 1933 1934 /* 1935 * XIVE Presenter 1936 */ 1937 static const TypeInfo xive_presenter_info = { 1938 .name = TYPE_XIVE_PRESENTER, 1939 .parent = TYPE_INTERFACE, 1940 .class_size = sizeof(XivePresenterClass), 1941 }; 1942 1943 /* 1944 * XIVE Fabric 1945 */ 1946 static const TypeInfo xive_fabric_info = { 1947 .name = TYPE_XIVE_FABRIC, 1948 .parent = TYPE_INTERFACE, 1949 .class_size = sizeof(XiveFabricClass), 1950 }; 1951 1952 static void xive_register_types(void) 1953 { 1954 type_register_static(&xive_fabric_info); 1955 type_register_static(&xive_source_info); 1956 type_register_static(&xive_notifier_info); 1957 type_register_static(&xive_presenter_info); 1958 type_register_static(&xive_router_info); 1959 type_register_static(&xive_end_source_info); 1960 type_register_static(&xive_tctx_info); 1961 } 1962 1963 type_init(xive_register_types) 1964