1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "monitor/monitor.h" 21 #include "hw/irq.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive_regs.h" 24 25 /* 26 * XIVE Thread Interrupt Management context 27 */ 28 29 /* 30 * Convert a priority number to an Interrupt Pending Buffer (IPB) 31 * register, which indicates a pending interrupt at the priority 32 * corresponding to the bit number 33 */ 34 static uint8_t priority_to_ipb(uint8_t priority) 35 { 36 return priority > XIVE_PRIORITY_MAX ? 37 0 : 1 << (XIVE_PRIORITY_MAX - priority); 38 } 39 40 /* 41 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 42 * Interrupt Priority Register (PIPR), which contains the priority of 43 * the most favored pending notification. 44 */ 45 static uint8_t ipb_to_pipr(uint8_t ibp) 46 { 47 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 48 } 49 50 static void ipb_update(uint8_t *regs, uint8_t priority) 51 { 52 regs[TM_IPB] |= priority_to_ipb(priority); 53 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 54 } 55 56 static uint8_t exception_mask(uint8_t ring) 57 { 58 switch (ring) { 59 case TM_QW1_OS: 60 return TM_QW1_NSR_EO; 61 case TM_QW3_HV_PHYS: 62 return TM_QW3_NSR_HE; 63 default: 64 g_assert_not_reached(); 65 } 66 } 67 68 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 69 { 70 switch (ring) { 71 case TM_QW0_USER: 72 return 0; /* Not supported */ 73 case TM_QW1_OS: 74 return tctx->os_output; 75 case TM_QW2_HV_POOL: 76 case TM_QW3_HV_PHYS: 77 return tctx->hv_output; 78 default: 79 return 0; 80 } 81 } 82 83 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 84 { 85 uint8_t *regs = &tctx->regs[ring]; 86 uint8_t nsr = regs[TM_NSR]; 87 uint8_t mask = exception_mask(ring); 88 89 qemu_irq_lower(xive_tctx_output(tctx, ring)); 90 91 if (regs[TM_NSR] & mask) { 92 uint8_t cppr = regs[TM_PIPR]; 93 94 regs[TM_CPPR] = cppr; 95 96 /* Reset the pending buffer bit */ 97 regs[TM_IPB] &= ~priority_to_ipb(cppr); 98 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 99 100 /* Drop Exception bit */ 101 regs[TM_NSR] &= ~mask; 102 } 103 104 return (nsr << 8) | regs[TM_CPPR]; 105 } 106 107 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 108 { 109 uint8_t *regs = &tctx->regs[ring]; 110 111 if (regs[TM_PIPR] < regs[TM_CPPR]) { 112 switch (ring) { 113 case TM_QW1_OS: 114 regs[TM_NSR] |= TM_QW1_NSR_EO; 115 break; 116 case TM_QW3_HV_PHYS: 117 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 118 break; 119 default: 120 g_assert_not_reached(); 121 } 122 qemu_irq_raise(xive_tctx_output(tctx, ring)); 123 } 124 } 125 126 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 127 { 128 if (cppr > XIVE_PRIORITY_MAX) { 129 cppr = 0xff; 130 } 131 132 tctx->regs[ring + TM_CPPR] = cppr; 133 134 /* CPPR has changed, check if we need to raise a pending exception */ 135 xive_tctx_notify(tctx, ring); 136 } 137 138 static inline uint32_t xive_tctx_word2(uint8_t *ring) 139 { 140 return *((uint32_t *) &ring[TM_WORD2]); 141 } 142 143 /* 144 * XIVE Thread Interrupt Management Area (TIMA) 145 */ 146 147 static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 148 hwaddr offset, uint64_t value, unsigned size) 149 { 150 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 151 } 152 153 static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx, 154 hwaddr offset, unsigned size) 155 { 156 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 157 } 158 159 static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 160 hwaddr offset, unsigned size) 161 { 162 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 163 uint32_t qw2w2; 164 165 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 166 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 167 return qw2w2; 168 } 169 170 static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 171 uint64_t value, unsigned size) 172 { 173 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 174 } 175 176 static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, 177 hwaddr offset, unsigned size) 178 { 179 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 180 } 181 182 /* 183 * Define an access map for each page of the TIMA that we will use in 184 * the memory region ops to filter values when doing loads and stores 185 * of raw registers values 186 * 187 * Registers accessibility bits : 188 * 189 * 0x0 - no access 190 * 0x1 - write only 191 * 0x2 - read only 192 * 0x3 - read/write 193 */ 194 195 static const uint8_t xive_tm_hw_view[] = { 196 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 197 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 198 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 199 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 200 }; 201 202 static const uint8_t xive_tm_hv_view[] = { 203 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 204 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 205 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 206 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 207 }; 208 209 static const uint8_t xive_tm_os_view[] = { 210 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 211 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 212 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 213 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 214 }; 215 216 static const uint8_t xive_tm_user_view[] = { 217 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 219 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 221 }; 222 223 /* 224 * Overall TIMA access map for the thread interrupt management context 225 * registers 226 */ 227 static const uint8_t *xive_tm_views[] = { 228 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 229 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 230 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 231 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 232 }; 233 234 /* 235 * Computes a register access mask for a given offset in the TIMA 236 */ 237 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 238 { 239 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 240 uint8_t reg_offset = offset & 0x3F; 241 uint8_t reg_mask = write ? 0x1 : 0x2; 242 uint64_t mask = 0x0; 243 int i; 244 245 for (i = 0; i < size; i++) { 246 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 247 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 248 } 249 } 250 251 return mask; 252 } 253 254 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 255 unsigned size) 256 { 257 uint8_t ring_offset = offset & 0x30; 258 uint8_t reg_offset = offset & 0x3F; 259 uint64_t mask = xive_tm_mask(offset, size, true); 260 int i; 261 262 /* 263 * Only 4 or 8 bytes stores are allowed and the User ring is 264 * excluded 265 */ 266 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 267 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 268 HWADDR_PRIx"\n", offset); 269 return; 270 } 271 272 /* 273 * Use the register offset for the raw values and filter out 274 * reserved values 275 */ 276 for (i = 0; i < size; i++) { 277 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 278 if (byte_mask) { 279 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 280 byte_mask; 281 } 282 } 283 } 284 285 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 286 { 287 uint8_t ring_offset = offset & 0x30; 288 uint8_t reg_offset = offset & 0x3F; 289 uint64_t mask = xive_tm_mask(offset, size, false); 290 uint64_t ret; 291 int i; 292 293 /* 294 * Only 4 or 8 bytes loads are allowed and the User ring is 295 * excluded 296 */ 297 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 298 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 299 HWADDR_PRIx"\n", offset); 300 return -1; 301 } 302 303 /* Use the register offset for the raw values */ 304 ret = 0; 305 for (i = 0; i < size; i++) { 306 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 307 } 308 309 /* filter out reserved values */ 310 return ret & mask; 311 } 312 313 /* 314 * The TM context is mapped twice within each page. Stores and loads 315 * to the first mapping below 2K write and read the specified values 316 * without modification. The second mapping above 2K performs specific 317 * state changes (side effects) in addition to setting/returning the 318 * interrupt management area context of the processor thread. 319 */ 320 static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx, 321 hwaddr offset, unsigned size) 322 { 323 return xive_tctx_accept(tctx, TM_QW1_OS); 324 } 325 326 static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 327 hwaddr offset, uint64_t value, unsigned size) 328 { 329 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 330 } 331 332 /* 333 * Adjust the IPB to allow a CPU to process event queues of other 334 * priorities during one physical interrupt cycle. 335 */ 336 static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, 337 hwaddr offset, uint64_t value, unsigned size) 338 { 339 ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff); 340 xive_tctx_notify(tctx, TM_QW1_OS); 341 } 342 343 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, 344 uint32_t *nvt_idx, bool *vo) 345 { 346 if (nvt_blk) { 347 *nvt_blk = xive_nvt_blk(cam); 348 } 349 if (nvt_idx) { 350 *nvt_idx = xive_nvt_idx(cam); 351 } 352 if (vo) { 353 *vo = !!(cam & TM_QW1W2_VO); 354 } 355 } 356 357 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk, 358 uint32_t *nvt_idx, bool *vo) 359 { 360 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 361 uint32_t cam = be32_to_cpu(qw1w2); 362 363 xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo); 364 return qw1w2; 365 } 366 367 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) 368 { 369 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 370 } 371 372 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 373 hwaddr offset, unsigned size) 374 { 375 uint32_t qw1w2; 376 uint32_t qw1w2_new; 377 uint8_t nvt_blk; 378 uint32_t nvt_idx; 379 bool vo; 380 381 qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); 382 383 if (!vo) { 384 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n", 385 nvt_blk, nvt_idx); 386 } 387 388 /* Invalidate CAM line */ 389 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); 390 xive_tctx_set_os_cam(tctx, qw1w2_new); 391 return qw1w2; 392 } 393 394 /* 395 * Define a mapping of "special" operations depending on the TIMA page 396 * offset and the size of the operation. 397 */ 398 typedef struct XiveTmOp { 399 uint8_t page_offset; 400 uint32_t op_offset; 401 unsigned size; 402 void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, 403 hwaddr offset, 404 uint64_t value, unsigned size); 405 uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 406 unsigned size); 407 } XiveTmOp; 408 409 static const XiveTmOp xive_tm_operations[] = { 410 /* 411 * MMIOs below 2K : raw values and special operations without side 412 * effects 413 */ 414 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 415 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 416 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 417 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 418 419 /* MMIOs above 2K : special operations with side effects */ 420 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 421 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 422 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, 423 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, 424 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 425 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 426 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 427 }; 428 429 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 430 { 431 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 432 uint32_t op_offset = offset & 0xFFF; 433 int i; 434 435 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 436 const XiveTmOp *xto = &xive_tm_operations[i]; 437 438 /* Accesses done from a more privileged TIMA page is allowed */ 439 if (xto->page_offset >= page_offset && 440 xto->op_offset == op_offset && 441 xto->size == size && 442 ((write && xto->write_handler) || (!write && xto->read_handler))) { 443 return xto; 444 } 445 } 446 return NULL; 447 } 448 449 /* 450 * TIMA MMIO handlers 451 */ 452 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 453 uint64_t value, unsigned size) 454 { 455 const XiveTmOp *xto; 456 457 /* 458 * TODO: check V bit in Q[0-3]W2 459 */ 460 461 /* 462 * First, check for special operations in the 2K region 463 */ 464 if (offset & 0x800) { 465 xto = xive_tm_find_op(offset, size, true); 466 if (!xto) { 467 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 468 "@%"HWADDR_PRIx"\n", offset); 469 } else { 470 xto->write_handler(xptr, tctx, offset, value, size); 471 } 472 return; 473 } 474 475 /* 476 * Then, for special operations in the region below 2K. 477 */ 478 xto = xive_tm_find_op(offset, size, true); 479 if (xto) { 480 xto->write_handler(xptr, tctx, offset, value, size); 481 return; 482 } 483 484 /* 485 * Finish with raw access to the register values 486 */ 487 xive_tm_raw_write(tctx, offset, value, size); 488 } 489 490 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 491 unsigned size) 492 { 493 const XiveTmOp *xto; 494 495 /* 496 * TODO: check V bit in Q[0-3]W2 497 */ 498 499 /* 500 * First, check for special operations in the 2K region 501 */ 502 if (offset & 0x800) { 503 xto = xive_tm_find_op(offset, size, false); 504 if (!xto) { 505 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 506 "@%"HWADDR_PRIx"\n", offset); 507 return -1; 508 } 509 return xto->read_handler(xptr, tctx, offset, size); 510 } 511 512 /* 513 * Then, for special operations in the region below 2K. 514 */ 515 xto = xive_tm_find_op(offset, size, false); 516 if (xto) { 517 return xto->read_handler(xptr, tctx, offset, size); 518 } 519 520 /* 521 * Finish with raw access to the register values 522 */ 523 return xive_tm_raw_read(tctx, offset, size); 524 } 525 526 static char *xive_tctx_ring_print(uint8_t *ring) 527 { 528 uint32_t w2 = xive_tctx_word2(ring); 529 530 return g_strdup_printf("%02x %02x %02x %02x %02x " 531 "%02x %02x %02x %08x", 532 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 533 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 534 be32_to_cpu(w2)); 535 } 536 537 static const char * const xive_tctx_ring_names[] = { 538 "USER", "OS", "POOL", "PHYS", 539 }; 540 541 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 542 { 543 int cpu_index; 544 int i; 545 546 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs 547 * are hot plugged or unplugged. 548 */ 549 if (!tctx) { 550 return; 551 } 552 553 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 554 555 if (kvm_irqchip_in_kernel()) { 556 Error *local_err = NULL; 557 558 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 559 if (local_err) { 560 error_report_err(local_err); 561 return; 562 } 563 } 564 565 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 566 " W2\n", cpu_index); 567 568 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 569 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 570 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 571 xive_tctx_ring_names[i], s); 572 g_free(s); 573 } 574 } 575 576 void xive_tctx_reset(XiveTCTX *tctx) 577 { 578 memset(tctx->regs, 0, sizeof(tctx->regs)); 579 580 /* Set some defaults */ 581 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 582 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 583 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 584 585 /* 586 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 587 * CPPR is first set. 588 */ 589 tctx->regs[TM_QW1_OS + TM_PIPR] = 590 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 591 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 592 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 593 } 594 595 static void xive_tctx_realize(DeviceState *dev, Error **errp) 596 { 597 XiveTCTX *tctx = XIVE_TCTX(dev); 598 PowerPCCPU *cpu; 599 CPUPPCState *env; 600 Error *local_err = NULL; 601 602 assert(tctx->cs); 603 604 cpu = POWERPC_CPU(tctx->cs); 605 env = &cpu->env; 606 switch (PPC_INPUT(env)) { 607 case PPC_FLAGS_INPUT_POWER9: 608 tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT]; 609 tctx->os_output = env->irq_inputs[POWER9_INPUT_INT]; 610 break; 611 612 default: 613 error_setg(errp, "XIVE interrupt controller does not support " 614 "this CPU bus model"); 615 return; 616 } 617 618 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 619 if (kvm_irqchip_in_kernel()) { 620 kvmppc_xive_cpu_connect(tctx, &local_err); 621 if (local_err) { 622 error_propagate(errp, local_err); 623 return; 624 } 625 } 626 } 627 628 static int vmstate_xive_tctx_pre_save(void *opaque) 629 { 630 Error *local_err = NULL; 631 632 if (kvm_irqchip_in_kernel()) { 633 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque), &local_err); 634 if (local_err) { 635 error_report_err(local_err); 636 return -1; 637 } 638 } 639 640 return 0; 641 } 642 643 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 644 { 645 Error *local_err = NULL; 646 647 if (kvm_irqchip_in_kernel()) { 648 /* 649 * Required for hotplugged CPU, for which the state comes 650 * after all states of the machine. 651 */ 652 kvmppc_xive_cpu_set_state(XIVE_TCTX(opaque), &local_err); 653 if (local_err) { 654 error_report_err(local_err); 655 return -1; 656 } 657 } 658 659 return 0; 660 } 661 662 static const VMStateDescription vmstate_xive_tctx = { 663 .name = TYPE_XIVE_TCTX, 664 .version_id = 1, 665 .minimum_version_id = 1, 666 .pre_save = vmstate_xive_tctx_pre_save, 667 .post_load = vmstate_xive_tctx_post_load, 668 .fields = (VMStateField[]) { 669 VMSTATE_BUFFER(regs, XiveTCTX), 670 VMSTATE_END_OF_LIST() 671 }, 672 }; 673 674 static Property xive_tctx_properties[] = { 675 DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), 676 DEFINE_PROP_END_OF_LIST(), 677 }; 678 679 static void xive_tctx_class_init(ObjectClass *klass, void *data) 680 { 681 DeviceClass *dc = DEVICE_CLASS(klass); 682 683 dc->desc = "XIVE Interrupt Thread Context"; 684 dc->realize = xive_tctx_realize; 685 dc->vmsd = &vmstate_xive_tctx; 686 dc->props = xive_tctx_properties; 687 /* 688 * Reason: part of XIVE interrupt controller, needs to be wired up 689 * by xive_tctx_create(). 690 */ 691 dc->user_creatable = false; 692 } 693 694 static const TypeInfo xive_tctx_info = { 695 .name = TYPE_XIVE_TCTX, 696 .parent = TYPE_DEVICE, 697 .instance_size = sizeof(XiveTCTX), 698 .class_init = xive_tctx_class_init, 699 }; 700 701 Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) 702 { 703 Error *local_err = NULL; 704 Object *obj; 705 706 obj = object_new(TYPE_XIVE_TCTX); 707 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); 708 object_unref(obj); 709 object_property_set_link(obj, cpu, "cpu", &error_abort); 710 object_property_set_bool(obj, true, "realized", &local_err); 711 if (local_err) { 712 goto error; 713 } 714 715 return obj; 716 717 error: 718 object_unparent(obj); 719 error_propagate(errp, local_err); 720 return NULL; 721 } 722 723 void xive_tctx_destroy(XiveTCTX *tctx) 724 { 725 Object *obj = OBJECT(tctx); 726 727 object_unparent(obj); 728 } 729 730 /* 731 * XIVE ESB helpers 732 */ 733 734 static uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 735 { 736 uint8_t old_pq = *pq & 0x3; 737 738 *pq &= ~0x3; 739 *pq |= value & 0x3; 740 741 return old_pq; 742 } 743 744 static bool xive_esb_trigger(uint8_t *pq) 745 { 746 uint8_t old_pq = *pq & 0x3; 747 748 switch (old_pq) { 749 case XIVE_ESB_RESET: 750 xive_esb_set(pq, XIVE_ESB_PENDING); 751 return true; 752 case XIVE_ESB_PENDING: 753 case XIVE_ESB_QUEUED: 754 xive_esb_set(pq, XIVE_ESB_QUEUED); 755 return false; 756 case XIVE_ESB_OFF: 757 xive_esb_set(pq, XIVE_ESB_OFF); 758 return false; 759 default: 760 g_assert_not_reached(); 761 } 762 } 763 764 static bool xive_esb_eoi(uint8_t *pq) 765 { 766 uint8_t old_pq = *pq & 0x3; 767 768 switch (old_pq) { 769 case XIVE_ESB_RESET: 770 case XIVE_ESB_PENDING: 771 xive_esb_set(pq, XIVE_ESB_RESET); 772 return false; 773 case XIVE_ESB_QUEUED: 774 xive_esb_set(pq, XIVE_ESB_PENDING); 775 return true; 776 case XIVE_ESB_OFF: 777 xive_esb_set(pq, XIVE_ESB_OFF); 778 return false; 779 default: 780 g_assert_not_reached(); 781 } 782 } 783 784 /* 785 * XIVE Interrupt Source (or IVSE) 786 */ 787 788 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 789 { 790 assert(srcno < xsrc->nr_irqs); 791 792 return xsrc->status[srcno] & 0x3; 793 } 794 795 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 796 { 797 assert(srcno < xsrc->nr_irqs); 798 799 return xive_esb_set(&xsrc->status[srcno], pq); 800 } 801 802 /* 803 * Returns whether the event notification should be forwarded. 804 */ 805 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 806 { 807 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 808 809 xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; 810 811 switch (old_pq) { 812 case XIVE_ESB_RESET: 813 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 814 return true; 815 default: 816 return false; 817 } 818 } 819 820 /* 821 * Returns whether the event notification should be forwarded. 822 */ 823 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 824 { 825 bool ret; 826 827 assert(srcno < xsrc->nr_irqs); 828 829 ret = xive_esb_trigger(&xsrc->status[srcno]); 830 831 if (xive_source_irq_is_lsi(xsrc, srcno) && 832 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 833 qemu_log_mask(LOG_GUEST_ERROR, 834 "XIVE: queued an event on LSI IRQ %d\n", srcno); 835 } 836 837 return ret; 838 } 839 840 /* 841 * Returns whether the event notification should be forwarded. 842 */ 843 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 844 { 845 bool ret; 846 847 assert(srcno < xsrc->nr_irqs); 848 849 ret = xive_esb_eoi(&xsrc->status[srcno]); 850 851 /* 852 * LSI sources do not set the Q bit but they can still be 853 * asserted, in which case we should forward a new event 854 * notification 855 */ 856 if (xive_source_irq_is_lsi(xsrc, srcno) && 857 xsrc->status[srcno] & XIVE_STATUS_ASSERTED) { 858 ret = xive_source_lsi_trigger(xsrc, srcno); 859 } 860 861 return ret; 862 } 863 864 /* 865 * Forward the source event notification to the Router 866 */ 867 static void xive_source_notify(XiveSource *xsrc, int srcno) 868 { 869 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 870 871 if (xnc->notify) { 872 xnc->notify(xsrc->xive, srcno); 873 } 874 } 875 876 /* 877 * In a two pages ESB MMIO setting, even page is the trigger page, odd 878 * page is for management 879 */ 880 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 881 { 882 return !((addr >> shift) & 1); 883 } 884 885 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 886 { 887 return xive_source_esb_has_2page(xsrc) && 888 addr_is_even(addr, xsrc->esb_shift - 1); 889 } 890 891 /* 892 * ESB MMIO loads 893 * Trigger page Management/EOI page 894 * 895 * ESB MMIO setting 2 pages 1 or 2 pages 896 * 897 * 0x000 .. 0x3FF -1 EOI and return 0|1 898 * 0x400 .. 0x7FF -1 EOI and return 0|1 899 * 0x800 .. 0xBFF -1 return PQ 900 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 901 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 902 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 903 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 904 */ 905 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 906 { 907 XiveSource *xsrc = XIVE_SOURCE(opaque); 908 uint32_t offset = addr & 0xFFF; 909 uint32_t srcno = addr >> xsrc->esb_shift; 910 uint64_t ret = -1; 911 912 /* In a two pages ESB MMIO setting, trigger page should not be read */ 913 if (xive_source_is_trigger_page(xsrc, addr)) { 914 qemu_log_mask(LOG_GUEST_ERROR, 915 "XIVE: invalid load on IRQ %d trigger page at " 916 "0x%"HWADDR_PRIx"\n", srcno, addr); 917 return -1; 918 } 919 920 switch (offset) { 921 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 922 ret = xive_source_esb_eoi(xsrc, srcno); 923 924 /* Forward the source event notification for routing */ 925 if (ret) { 926 xive_source_notify(xsrc, srcno); 927 } 928 break; 929 930 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 931 ret = xive_source_esb_get(xsrc, srcno); 932 break; 933 934 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 935 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 936 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 937 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 938 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 939 break; 940 default: 941 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 942 offset); 943 } 944 945 return ret; 946 } 947 948 /* 949 * ESB MMIO stores 950 * Trigger page Management/EOI page 951 * 952 * ESB MMIO setting 2 pages 1 or 2 pages 953 * 954 * 0x000 .. 0x3FF Trigger Trigger 955 * 0x400 .. 0x7FF Trigger EOI 956 * 0x800 .. 0xBFF Trigger undefined 957 * 0xC00 .. 0xCFF Trigger PQ=00 958 * 0xD00 .. 0xDFF Trigger PQ=01 959 * 0xE00 .. 0xDFF Trigger PQ=10 960 * 0xF00 .. 0xDFF Trigger PQ=11 961 */ 962 static void xive_source_esb_write(void *opaque, hwaddr addr, 963 uint64_t value, unsigned size) 964 { 965 XiveSource *xsrc = XIVE_SOURCE(opaque); 966 uint32_t offset = addr & 0xFFF; 967 uint32_t srcno = addr >> xsrc->esb_shift; 968 bool notify = false; 969 970 /* In a two pages ESB MMIO setting, trigger page only triggers */ 971 if (xive_source_is_trigger_page(xsrc, addr)) { 972 notify = xive_source_esb_trigger(xsrc, srcno); 973 goto out; 974 } 975 976 switch (offset) { 977 case 0 ... 0x3FF: 978 notify = xive_source_esb_trigger(xsrc, srcno); 979 break; 980 981 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 982 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 983 qemu_log_mask(LOG_GUEST_ERROR, 984 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 985 return; 986 } 987 988 notify = xive_source_esb_eoi(xsrc, srcno); 989 break; 990 991 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 992 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 993 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 994 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 995 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 996 break; 997 998 default: 999 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 1000 offset); 1001 return; 1002 } 1003 1004 out: 1005 /* Forward the source event notification for routing */ 1006 if (notify) { 1007 xive_source_notify(xsrc, srcno); 1008 } 1009 } 1010 1011 static const MemoryRegionOps xive_source_esb_ops = { 1012 .read = xive_source_esb_read, 1013 .write = xive_source_esb_write, 1014 .endianness = DEVICE_BIG_ENDIAN, 1015 .valid = { 1016 .min_access_size = 8, 1017 .max_access_size = 8, 1018 }, 1019 .impl = { 1020 .min_access_size = 8, 1021 .max_access_size = 8, 1022 }, 1023 }; 1024 1025 void xive_source_set_irq(void *opaque, int srcno, int val) 1026 { 1027 XiveSource *xsrc = XIVE_SOURCE(opaque); 1028 bool notify = false; 1029 1030 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1031 if (val) { 1032 notify = xive_source_lsi_trigger(xsrc, srcno); 1033 } else { 1034 xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; 1035 } 1036 } else { 1037 if (val) { 1038 notify = xive_source_esb_trigger(xsrc, srcno); 1039 } 1040 } 1041 1042 /* Forward the source event notification for routing */ 1043 if (notify) { 1044 xive_source_notify(xsrc, srcno); 1045 } 1046 } 1047 1048 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 1049 { 1050 int i; 1051 1052 for (i = 0; i < xsrc->nr_irqs; i++) { 1053 uint8_t pq = xive_source_esb_get(xsrc, i); 1054 1055 if (pq == XIVE_ESB_OFF) { 1056 continue; 1057 } 1058 1059 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 1060 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1061 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1062 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1063 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' '); 1064 } 1065 } 1066 1067 static void xive_source_reset(void *dev) 1068 { 1069 XiveSource *xsrc = XIVE_SOURCE(dev); 1070 1071 /* Do not clear the LSI bitmap */ 1072 1073 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 1074 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 1075 } 1076 1077 static void xive_source_realize(DeviceState *dev, Error **errp) 1078 { 1079 XiveSource *xsrc = XIVE_SOURCE(dev); 1080 1081 assert(xsrc->xive); 1082 1083 if (!xsrc->nr_irqs) { 1084 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1085 return; 1086 } 1087 1088 if (xsrc->esb_shift != XIVE_ESB_4K && 1089 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1090 xsrc->esb_shift != XIVE_ESB_64K && 1091 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1092 error_setg(errp, "Invalid ESB shift setting"); 1093 return; 1094 } 1095 1096 xsrc->status = g_malloc0(xsrc->nr_irqs); 1097 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1098 1099 if (!kvm_irqchip_in_kernel()) { 1100 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1101 &xive_source_esb_ops, xsrc, "xive.esb", 1102 (1ull << xsrc->esb_shift) * xsrc->nr_irqs); 1103 } 1104 1105 qemu_register_reset(xive_source_reset, dev); 1106 } 1107 1108 static const VMStateDescription vmstate_xive_source = { 1109 .name = TYPE_XIVE_SOURCE, 1110 .version_id = 1, 1111 .minimum_version_id = 1, 1112 .fields = (VMStateField[]) { 1113 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1114 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1115 VMSTATE_END_OF_LIST() 1116 }, 1117 }; 1118 1119 /* 1120 * The default XIVE interrupt source setting for the ESB MMIOs is two 1121 * 64k pages without Store EOI, to be in sync with KVM. 1122 */ 1123 static Property xive_source_properties[] = { 1124 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1125 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1126 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1127 DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, 1128 XiveNotifier *), 1129 DEFINE_PROP_END_OF_LIST(), 1130 }; 1131 1132 static void xive_source_class_init(ObjectClass *klass, void *data) 1133 { 1134 DeviceClass *dc = DEVICE_CLASS(klass); 1135 1136 dc->desc = "XIVE Interrupt Source"; 1137 dc->props = xive_source_properties; 1138 dc->realize = xive_source_realize; 1139 dc->vmsd = &vmstate_xive_source; 1140 /* 1141 * Reason: part of XIVE interrupt controller, needs to be wired up, 1142 * e.g. by spapr_xive_instance_init(). 1143 */ 1144 dc->user_creatable = false; 1145 } 1146 1147 static const TypeInfo xive_source_info = { 1148 .name = TYPE_XIVE_SOURCE, 1149 .parent = TYPE_DEVICE, 1150 .instance_size = sizeof(XiveSource), 1151 .class_init = xive_source_class_init, 1152 }; 1153 1154 /* 1155 * XiveEND helpers 1156 */ 1157 1158 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1159 { 1160 uint64_t qaddr_base = xive_end_qaddr(end); 1161 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1162 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1163 uint32_t qentries = 1 << (qsize + 10); 1164 int i; 1165 1166 /* 1167 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1168 */ 1169 monitor_printf(mon, " [ "); 1170 qindex = (qindex - (width - 1)) & (qentries - 1); 1171 for (i = 0; i < width; i++) { 1172 uint64_t qaddr = qaddr_base + (qindex << 2); 1173 uint32_t qdata = -1; 1174 1175 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 1176 sizeof(qdata))) { 1177 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1178 HWADDR_PRIx "\n", qaddr); 1179 return; 1180 } 1181 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1182 be32_to_cpu(qdata)); 1183 qindex = (qindex + 1) & (qentries - 1); 1184 } 1185 monitor_printf(mon, "]"); 1186 } 1187 1188 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1189 { 1190 uint64_t qaddr_base = xive_end_qaddr(end); 1191 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1192 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1193 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1194 uint32_t qentries = 1 << (qsize + 10); 1195 1196 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1197 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1198 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1199 uint8_t pq; 1200 1201 if (!xive_end_is_valid(end)) { 1202 return; 1203 } 1204 1205 pq = xive_get_field32(END_W1_ESn, end->w1); 1206 1207 monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1208 end_idx, 1209 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1210 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1211 xive_end_is_valid(end) ? 'v' : '-', 1212 xive_end_is_enqueue(end) ? 'q' : '-', 1213 xive_end_is_notify(end) ? 'n' : '-', 1214 xive_end_is_backlog(end) ? 'b' : '-', 1215 xive_end_is_escalate(end) ? 'e' : '-', 1216 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1217 xive_end_is_silent_escalation(end) ? 's' : '-', 1218 priority, nvt_blk, nvt_idx); 1219 1220 if (qaddr_base) { 1221 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1222 qaddr_base, qindex, qentries, qgen); 1223 xive_end_queue_pic_print_info(end, 6, mon); 1224 } 1225 monitor_printf(mon, "\n"); 1226 } 1227 1228 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1229 { 1230 uint64_t qaddr_base = xive_end_qaddr(end); 1231 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1232 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1233 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1234 1235 uint64_t qaddr = qaddr_base + (qindex << 2); 1236 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1237 uint32_t qentries = 1 << (qsize + 10); 1238 1239 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) { 1240 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1241 HWADDR_PRIx "\n", qaddr); 1242 return; 1243 } 1244 1245 qindex = (qindex + 1) & (qentries - 1); 1246 if (qindex == 0) { 1247 qgen ^= 1; 1248 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1249 } 1250 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1251 } 1252 1253 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, 1254 Monitor *mon) 1255 { 1256 XiveEAS *eas = (XiveEAS *) &end->w4; 1257 uint8_t pq; 1258 1259 if (!xive_end_is_escalate(end)) { 1260 return; 1261 } 1262 1263 pq = xive_get_field32(END_W1_ESe, end->w1); 1264 1265 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1266 end_idx, 1267 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1268 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1269 xive_eas_is_valid(eas) ? 'V' : ' ', 1270 xive_eas_is_masked(eas) ? 'M' : ' ', 1271 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1272 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1273 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1274 } 1275 1276 /* 1277 * XIVE Router (aka. Virtualization Controller or IVRE) 1278 */ 1279 1280 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1281 XiveEAS *eas) 1282 { 1283 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1284 1285 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1286 } 1287 1288 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1289 XiveEND *end) 1290 { 1291 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1292 1293 return xrc->get_end(xrtr, end_blk, end_idx, end); 1294 } 1295 1296 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1297 XiveEND *end, uint8_t word_number) 1298 { 1299 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1300 1301 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1302 } 1303 1304 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1305 XiveNVT *nvt) 1306 { 1307 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1308 1309 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1310 } 1311 1312 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1313 XiveNVT *nvt, uint8_t word_number) 1314 { 1315 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1316 1317 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1318 } 1319 1320 XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) 1321 { 1322 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1323 1324 return xrc->get_tctx(xrtr, cs); 1325 } 1326 1327 /* 1328 * Encode the HW CAM line in the block group mode format : 1329 * 1330 * chip << 19 | 0000000 0 0001 thread (7Bit) 1331 */ 1332 static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) 1333 { 1334 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1335 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1336 1337 return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f)); 1338 } 1339 1340 /* 1341 * The thread context register words are in big-endian format. 1342 */ 1343 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1344 uint8_t format, 1345 uint8_t nvt_blk, uint32_t nvt_idx, 1346 bool cam_ignore, uint32_t logic_serv) 1347 { 1348 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1349 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1350 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1351 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1352 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1353 1354 /* 1355 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1356 * identifier are ignored in the "CAM" match. 1357 */ 1358 1359 if (format == 0) { 1360 if (cam_ignore == true) { 1361 /* 1362 * F=0 & i=1: Logical server notification (bits ignored at 1363 * the end of the NVT identifier) 1364 */ 1365 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1366 nvt_blk, nvt_idx); 1367 return -1; 1368 } 1369 1370 /* F=0 & i=0: Specific NVT notification */ 1371 1372 /* PHYS ring */ 1373 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1374 cam == xive_tctx_hw_cam_line(tctx)) { 1375 return TM_QW3_HV_PHYS; 1376 } 1377 1378 /* HV POOL ring */ 1379 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1380 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1381 return TM_QW2_HV_POOL; 1382 } 1383 1384 /* OS ring */ 1385 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1386 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1387 return TM_QW1_OS; 1388 } 1389 } else { 1390 /* F=1 : User level Event-Based Branch (EBB) notification */ 1391 1392 /* USER ring */ 1393 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1394 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1395 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1396 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1397 return TM_QW0_USER; 1398 } 1399 } 1400 return -1; 1401 } 1402 1403 /* 1404 * This is our simple Xive Presenter Engine model. It is merged in the 1405 * Router as it does not require an extra object. 1406 * 1407 * It receives notification requests sent by the IVRE to find one 1408 * matching NVT (or more) dispatched on the processor threads. In case 1409 * of a single NVT notification, the process is abreviated and the 1410 * thread is signaled if a match is found. In case of a logical server 1411 * notification (bits ignored at the end of the NVT identifier), the 1412 * IVPE and IVRE select a winning thread using different filters. This 1413 * involves 2 or 3 exchanges on the PowerBus that the model does not 1414 * support. 1415 * 1416 * The parameters represent what is sent on the PowerBus 1417 */ 1418 static bool xive_presenter_notify(uint8_t format, 1419 uint8_t nvt_blk, uint32_t nvt_idx, 1420 bool cam_ignore, uint8_t priority, 1421 uint32_t logic_serv) 1422 { 1423 XiveFabric *xfb = XIVE_FABRIC(qdev_get_machine()); 1424 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb); 1425 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1426 int count; 1427 1428 /* 1429 * Ask the machine to scan the interrupt controllers for a match 1430 */ 1431 count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore, 1432 priority, logic_serv, &match); 1433 if (count < 0) { 1434 return false; 1435 } 1436 1437 /* handle CPU exception delivery */ 1438 if (count) { 1439 ipb_update(&match.tctx->regs[match.ring], priority); 1440 xive_tctx_notify(match.tctx, match.ring); 1441 } 1442 1443 return !!count; 1444 } 1445 1446 /* 1447 * Notification using the END ESe/ESn bit (Event State Buffer for 1448 * escalation and notification). Profide futher coalescing in the 1449 * Router. 1450 */ 1451 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1452 uint32_t end_idx, XiveEND *end, 1453 uint32_t end_esmask) 1454 { 1455 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1456 bool notify = xive_esb_trigger(&pq); 1457 1458 if (pq != xive_get_field32(end_esmask, end->w1)) { 1459 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1460 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1461 } 1462 1463 /* ESe/n[Q]=1 : end of notification */ 1464 return notify; 1465 } 1466 1467 /* 1468 * An END trigger can come from an event trigger (IPI or HW) or from 1469 * another chip. We don't model the PowerBus but the END trigger 1470 * message has the same parameters than in the function below. 1471 */ 1472 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1473 uint32_t end_idx, uint32_t end_data) 1474 { 1475 XiveEND end; 1476 uint8_t priority; 1477 uint8_t format; 1478 uint8_t nvt_blk; 1479 uint32_t nvt_idx; 1480 XiveNVT nvt; 1481 bool found; 1482 1483 /* END cache lookup */ 1484 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1485 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1486 end_idx); 1487 return; 1488 } 1489 1490 if (!xive_end_is_valid(&end)) { 1491 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1492 end_blk, end_idx); 1493 return; 1494 } 1495 1496 if (xive_end_is_enqueue(&end)) { 1497 xive_end_enqueue(&end, end_data); 1498 /* Enqueuing event data modifies the EQ toggle and index */ 1499 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1500 } 1501 1502 /* 1503 * When the END is silent, we skip the notification part. 1504 */ 1505 if (xive_end_is_silent_escalation(&end)) { 1506 goto do_escalation; 1507 } 1508 1509 /* 1510 * The W7 format depends on the F bit in W6. It defines the type 1511 * of the notification : 1512 * 1513 * F=0 : single or multiple NVT notification 1514 * F=1 : User level Event-Based Branch (EBB) notification, no 1515 * priority 1516 */ 1517 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1518 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1519 1520 /* The END is masked */ 1521 if (format == 0 && priority == 0xff) { 1522 return; 1523 } 1524 1525 /* 1526 * Check the END ESn (Event State Buffer for notification) for 1527 * even futher coalescing in the Router 1528 */ 1529 if (!xive_end_is_notify(&end)) { 1530 /* ESn[Q]=1 : end of notification */ 1531 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1532 &end, END_W1_ESn)) { 1533 return; 1534 } 1535 } 1536 1537 /* 1538 * Follows IVPE notification 1539 */ 1540 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1541 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1542 1543 /* NVT cache lookup */ 1544 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1545 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1546 nvt_blk, nvt_idx); 1547 return; 1548 } 1549 1550 if (!xive_nvt_is_valid(&nvt)) { 1551 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1552 nvt_blk, nvt_idx); 1553 return; 1554 } 1555 1556 found = xive_presenter_notify(format, nvt_blk, nvt_idx, 1557 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1558 priority, 1559 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1560 1561 /* TODO: Auto EOI. */ 1562 1563 if (found) { 1564 return; 1565 } 1566 1567 /* 1568 * If no matching NVT is dispatched on a HW thread : 1569 * - specific VP: update the NVT structure if backlog is activated 1570 * - logical server : forward request to IVPE (not supported) 1571 */ 1572 if (xive_end_is_backlog(&end)) { 1573 uint8_t ipb; 1574 1575 if (format == 1) { 1576 qemu_log_mask(LOG_GUEST_ERROR, 1577 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1578 end_blk, end_idx); 1579 return; 1580 } 1581 /* 1582 * Record the IPB in the associated NVT structure for later 1583 * use. The presenter will resend the interrupt when the vCPU 1584 * is dispatched again on a HW thread. 1585 */ 1586 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priority); 1587 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); 1588 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1589 1590 /* 1591 * On HW, follows a "Broadcast Backlog" to IVPEs 1592 */ 1593 } 1594 1595 do_escalation: 1596 /* 1597 * If activated, escalate notification using the ESe PQ bits and 1598 * the EAS in w4-5 1599 */ 1600 if (!xive_end_is_escalate(&end)) { 1601 return; 1602 } 1603 1604 /* 1605 * Check the END ESe (Event State Buffer for escalation) for even 1606 * futher coalescing in the Router 1607 */ 1608 if (!xive_end_is_uncond_escalation(&end)) { 1609 /* ESe[Q]=1 : end of notification */ 1610 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1611 &end, END_W1_ESe)) { 1612 return; 1613 } 1614 } 1615 1616 /* 1617 * The END trigger becomes an Escalation trigger 1618 */ 1619 xive_router_end_notify(xrtr, 1620 xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1621 xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1622 xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1623 } 1624 1625 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 1626 { 1627 XiveRouter *xrtr = XIVE_ROUTER(xn); 1628 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1629 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1630 XiveEAS eas; 1631 1632 /* EAS cache lookup */ 1633 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1634 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1635 return; 1636 } 1637 1638 /* 1639 * The IVRE checks the State Bit Cache at this point. We skip the 1640 * SBC lookup because the state bits of the sources are modeled 1641 * internally in QEMU. 1642 */ 1643 1644 if (!xive_eas_is_valid(&eas)) { 1645 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1646 return; 1647 } 1648 1649 if (xive_eas_is_masked(&eas)) { 1650 /* Notification completed */ 1651 return; 1652 } 1653 1654 /* 1655 * The event trigger becomes an END trigger 1656 */ 1657 xive_router_end_notify(xrtr, 1658 xive_get_field64(EAS_END_BLOCK, eas.w), 1659 xive_get_field64(EAS_END_INDEX, eas.w), 1660 xive_get_field64(EAS_END_DATA, eas.w)); 1661 } 1662 1663 static void xive_router_class_init(ObjectClass *klass, void *data) 1664 { 1665 DeviceClass *dc = DEVICE_CLASS(klass); 1666 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1667 1668 dc->desc = "XIVE Router Engine"; 1669 xnc->notify = xive_router_notify; 1670 } 1671 1672 static const TypeInfo xive_router_info = { 1673 .name = TYPE_XIVE_ROUTER, 1674 .parent = TYPE_SYS_BUS_DEVICE, 1675 .abstract = true, 1676 .class_size = sizeof(XiveRouterClass), 1677 .class_init = xive_router_class_init, 1678 .interfaces = (InterfaceInfo[]) { 1679 { TYPE_XIVE_NOTIFIER }, 1680 { TYPE_XIVE_PRESENTER }, 1681 { } 1682 } 1683 }; 1684 1685 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1686 { 1687 if (!xive_eas_is_valid(eas)) { 1688 return; 1689 } 1690 1691 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1692 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1693 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1694 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1695 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1696 } 1697 1698 /* 1699 * END ESB MMIO loads 1700 */ 1701 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1702 { 1703 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1704 uint32_t offset = addr & 0xFFF; 1705 uint8_t end_blk; 1706 uint32_t end_idx; 1707 XiveEND end; 1708 uint32_t end_esmask; 1709 uint8_t pq; 1710 uint64_t ret = -1; 1711 1712 end_blk = xsrc->block_id; 1713 end_idx = addr >> (xsrc->esb_shift + 1); 1714 1715 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1716 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1717 end_idx); 1718 return -1; 1719 } 1720 1721 if (!xive_end_is_valid(&end)) { 1722 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1723 end_blk, end_idx); 1724 return -1; 1725 } 1726 1727 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1728 pq = xive_get_field32(end_esmask, end.w1); 1729 1730 switch (offset) { 1731 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1732 ret = xive_esb_eoi(&pq); 1733 1734 /* Forward the source event notification for routing ?? */ 1735 break; 1736 1737 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1738 ret = pq; 1739 break; 1740 1741 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1742 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1743 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1744 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1745 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1746 break; 1747 default: 1748 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1749 offset); 1750 return -1; 1751 } 1752 1753 if (pq != xive_get_field32(end_esmask, end.w1)) { 1754 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1755 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1756 } 1757 1758 return ret; 1759 } 1760 1761 /* 1762 * END ESB MMIO stores are invalid 1763 */ 1764 static void xive_end_source_write(void *opaque, hwaddr addr, 1765 uint64_t value, unsigned size) 1766 { 1767 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1768 HWADDR_PRIx"\n", addr); 1769 } 1770 1771 static const MemoryRegionOps xive_end_source_ops = { 1772 .read = xive_end_source_read, 1773 .write = xive_end_source_write, 1774 .endianness = DEVICE_BIG_ENDIAN, 1775 .valid = { 1776 .min_access_size = 8, 1777 .max_access_size = 8, 1778 }, 1779 .impl = { 1780 .min_access_size = 8, 1781 .max_access_size = 8, 1782 }, 1783 }; 1784 1785 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1786 { 1787 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1788 1789 assert(xsrc->xrtr); 1790 1791 if (!xsrc->nr_ends) { 1792 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1793 return; 1794 } 1795 1796 if (xsrc->esb_shift != XIVE_ESB_4K && 1797 xsrc->esb_shift != XIVE_ESB_64K) { 1798 error_setg(errp, "Invalid ESB shift setting"); 1799 return; 1800 } 1801 1802 /* 1803 * Each END is assigned an even/odd pair of MMIO pages, the even page 1804 * manages the ESn field while the odd page manages the ESe field. 1805 */ 1806 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1807 &xive_end_source_ops, xsrc, "xive.end", 1808 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1809 } 1810 1811 static Property xive_end_source_properties[] = { 1812 DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0), 1813 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1814 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1815 DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, 1816 XiveRouter *), 1817 DEFINE_PROP_END_OF_LIST(), 1818 }; 1819 1820 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1821 { 1822 DeviceClass *dc = DEVICE_CLASS(klass); 1823 1824 dc->desc = "XIVE END Source"; 1825 dc->props = xive_end_source_properties; 1826 dc->realize = xive_end_source_realize; 1827 /* 1828 * Reason: part of XIVE interrupt controller, needs to be wired up, 1829 * e.g. by spapr_xive_instance_init(). 1830 */ 1831 dc->user_creatable = false; 1832 } 1833 1834 static const TypeInfo xive_end_source_info = { 1835 .name = TYPE_XIVE_END_SOURCE, 1836 .parent = TYPE_DEVICE, 1837 .instance_size = sizeof(XiveENDSource), 1838 .class_init = xive_end_source_class_init, 1839 }; 1840 1841 /* 1842 * XIVE Notifier 1843 */ 1844 static const TypeInfo xive_notifier_info = { 1845 .name = TYPE_XIVE_NOTIFIER, 1846 .parent = TYPE_INTERFACE, 1847 .class_size = sizeof(XiveNotifierClass), 1848 }; 1849 1850 /* 1851 * XIVE Presenter 1852 */ 1853 static const TypeInfo xive_presenter_info = { 1854 .name = TYPE_XIVE_PRESENTER, 1855 .parent = TYPE_INTERFACE, 1856 .class_size = sizeof(XivePresenterClass), 1857 }; 1858 1859 /* 1860 * XIVE Fabric 1861 */ 1862 static const TypeInfo xive_fabric_info = { 1863 .name = TYPE_XIVE_FABRIC, 1864 .parent = TYPE_INTERFACE, 1865 .class_size = sizeof(XiveFabricClass), 1866 }; 1867 1868 static void xive_register_types(void) 1869 { 1870 type_register_static(&xive_fabric_info); 1871 type_register_static(&xive_source_info); 1872 type_register_static(&xive_notifier_info); 1873 type_register_static(&xive_presenter_info); 1874 type_register_static(&xive_router_info); 1875 type_register_static(&xive_end_source_info); 1876 type_register_static(&xive_tctx_info); 1877 } 1878 1879 type_init(xive_register_types) 1880