1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "monitor/monitor.h" 21 #include "hw/irq.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive_regs.h" 24 25 /* 26 * XIVE Thread Interrupt Management context 27 */ 28 29 /* 30 * Convert a priority number to an Interrupt Pending Buffer (IPB) 31 * register, which indicates a pending interrupt at the priority 32 * corresponding to the bit number 33 */ 34 static uint8_t priority_to_ipb(uint8_t priority) 35 { 36 return priority > XIVE_PRIORITY_MAX ? 37 0 : 1 << (XIVE_PRIORITY_MAX - priority); 38 } 39 40 /* 41 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 42 * Interrupt Priority Register (PIPR), which contains the priority of 43 * the most favored pending notification. 44 */ 45 static uint8_t ipb_to_pipr(uint8_t ibp) 46 { 47 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 48 } 49 50 static uint8_t exception_mask(uint8_t ring) 51 { 52 switch (ring) { 53 case TM_QW1_OS: 54 return TM_QW1_NSR_EO; 55 case TM_QW3_HV_PHYS: 56 return TM_QW3_NSR_HE; 57 default: 58 g_assert_not_reached(); 59 } 60 } 61 62 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 63 { 64 switch (ring) { 65 case TM_QW0_USER: 66 return 0; /* Not supported */ 67 case TM_QW1_OS: 68 return tctx->os_output; 69 case TM_QW2_HV_POOL: 70 case TM_QW3_HV_PHYS: 71 return tctx->hv_output; 72 default: 73 return 0; 74 } 75 } 76 77 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 78 { 79 uint8_t *regs = &tctx->regs[ring]; 80 uint8_t nsr = regs[TM_NSR]; 81 uint8_t mask = exception_mask(ring); 82 83 qemu_irq_lower(xive_tctx_output(tctx, ring)); 84 85 if (regs[TM_NSR] & mask) { 86 uint8_t cppr = regs[TM_PIPR]; 87 88 regs[TM_CPPR] = cppr; 89 90 /* Reset the pending buffer bit */ 91 regs[TM_IPB] &= ~priority_to_ipb(cppr); 92 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 93 94 /* Drop Exception bit */ 95 regs[TM_NSR] &= ~mask; 96 } 97 98 return (nsr << 8) | regs[TM_CPPR]; 99 } 100 101 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 102 { 103 uint8_t *regs = &tctx->regs[ring]; 104 105 if (regs[TM_PIPR] < regs[TM_CPPR]) { 106 switch (ring) { 107 case TM_QW1_OS: 108 regs[TM_NSR] |= TM_QW1_NSR_EO; 109 break; 110 case TM_QW3_HV_PHYS: 111 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 112 break; 113 default: 114 g_assert_not_reached(); 115 } 116 qemu_irq_raise(xive_tctx_output(tctx, ring)); 117 } 118 } 119 120 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 121 { 122 if (cppr > XIVE_PRIORITY_MAX) { 123 cppr = 0xff; 124 } 125 126 tctx->regs[ring + TM_CPPR] = cppr; 127 128 /* CPPR has changed, check if we need to raise a pending exception */ 129 xive_tctx_notify(tctx, ring); 130 } 131 132 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) 133 { 134 uint8_t *regs = &tctx->regs[ring]; 135 136 regs[TM_IPB] |= ipb; 137 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 138 xive_tctx_notify(tctx, ring); 139 } 140 141 static inline uint32_t xive_tctx_word2(uint8_t *ring) 142 { 143 return *((uint32_t *) &ring[TM_WORD2]); 144 } 145 146 /* 147 * XIVE Thread Interrupt Management Area (TIMA) 148 */ 149 150 static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 151 hwaddr offset, uint64_t value, unsigned size) 152 { 153 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 154 } 155 156 static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx, 157 hwaddr offset, unsigned size) 158 { 159 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 160 } 161 162 static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 163 hwaddr offset, unsigned size) 164 { 165 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 166 uint32_t qw2w2; 167 168 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 169 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 170 return qw2w2; 171 } 172 173 static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 174 uint64_t value, unsigned size) 175 { 176 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 177 } 178 179 static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, 180 hwaddr offset, unsigned size) 181 { 182 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 183 } 184 185 /* 186 * Define an access map for each page of the TIMA that we will use in 187 * the memory region ops to filter values when doing loads and stores 188 * of raw registers values 189 * 190 * Registers accessibility bits : 191 * 192 * 0x0 - no access 193 * 0x1 - write only 194 * 0x2 - read only 195 * 0x3 - read/write 196 */ 197 198 static const uint8_t xive_tm_hw_view[] = { 199 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 200 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 201 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 202 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 203 }; 204 205 static const uint8_t xive_tm_hv_view[] = { 206 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 207 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 208 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 209 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 210 }; 211 212 static const uint8_t xive_tm_os_view[] = { 213 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 214 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 215 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 217 }; 218 219 static const uint8_t xive_tm_user_view[] = { 220 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 223 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 224 }; 225 226 /* 227 * Overall TIMA access map for the thread interrupt management context 228 * registers 229 */ 230 static const uint8_t *xive_tm_views[] = { 231 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 232 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 233 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 234 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 235 }; 236 237 /* 238 * Computes a register access mask for a given offset in the TIMA 239 */ 240 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 241 { 242 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 243 uint8_t reg_offset = offset & 0x3F; 244 uint8_t reg_mask = write ? 0x1 : 0x2; 245 uint64_t mask = 0x0; 246 int i; 247 248 for (i = 0; i < size; i++) { 249 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 250 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 251 } 252 } 253 254 return mask; 255 } 256 257 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 258 unsigned size) 259 { 260 uint8_t ring_offset = offset & 0x30; 261 uint8_t reg_offset = offset & 0x3F; 262 uint64_t mask = xive_tm_mask(offset, size, true); 263 int i; 264 265 /* 266 * Only 4 or 8 bytes stores are allowed and the User ring is 267 * excluded 268 */ 269 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 270 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 271 HWADDR_PRIx"\n", offset); 272 return; 273 } 274 275 /* 276 * Use the register offset for the raw values and filter out 277 * reserved values 278 */ 279 for (i = 0; i < size; i++) { 280 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 281 if (byte_mask) { 282 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 283 byte_mask; 284 } 285 } 286 } 287 288 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 289 { 290 uint8_t ring_offset = offset & 0x30; 291 uint8_t reg_offset = offset & 0x3F; 292 uint64_t mask = xive_tm_mask(offset, size, false); 293 uint64_t ret; 294 int i; 295 296 /* 297 * Only 4 or 8 bytes loads are allowed and the User ring is 298 * excluded 299 */ 300 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 301 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 302 HWADDR_PRIx"\n", offset); 303 return -1; 304 } 305 306 /* Use the register offset for the raw values */ 307 ret = 0; 308 for (i = 0; i < size; i++) { 309 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 310 } 311 312 /* filter out reserved values */ 313 return ret & mask; 314 } 315 316 /* 317 * The TM context is mapped twice within each page. Stores and loads 318 * to the first mapping below 2K write and read the specified values 319 * without modification. The second mapping above 2K performs specific 320 * state changes (side effects) in addition to setting/returning the 321 * interrupt management area context of the processor thread. 322 */ 323 static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx, 324 hwaddr offset, unsigned size) 325 { 326 return xive_tctx_accept(tctx, TM_QW1_OS); 327 } 328 329 static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 330 hwaddr offset, uint64_t value, unsigned size) 331 { 332 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 333 } 334 335 /* 336 * Adjust the IPB to allow a CPU to process event queues of other 337 * priorities during one physical interrupt cycle. 338 */ 339 static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, 340 hwaddr offset, uint64_t value, unsigned size) 341 { 342 xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff)); 343 } 344 345 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, 346 uint32_t *nvt_idx, bool *vo) 347 { 348 if (nvt_blk) { 349 *nvt_blk = xive_nvt_blk(cam); 350 } 351 if (nvt_idx) { 352 *nvt_idx = xive_nvt_idx(cam); 353 } 354 if (vo) { 355 *vo = !!(cam & TM_QW1W2_VO); 356 } 357 } 358 359 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk, 360 uint32_t *nvt_idx, bool *vo) 361 { 362 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 363 uint32_t cam = be32_to_cpu(qw1w2); 364 365 xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo); 366 return qw1w2; 367 } 368 369 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) 370 { 371 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 372 } 373 374 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 375 hwaddr offset, unsigned size) 376 { 377 uint32_t qw1w2; 378 uint32_t qw1w2_new; 379 uint8_t nvt_blk; 380 uint32_t nvt_idx; 381 bool vo; 382 383 qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); 384 385 if (!vo) { 386 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n", 387 nvt_blk, nvt_idx); 388 } 389 390 /* Invalidate CAM line */ 391 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); 392 xive_tctx_set_os_cam(tctx, qw1w2_new); 393 return qw1w2; 394 } 395 396 static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx, 397 uint8_t nvt_blk, uint32_t nvt_idx) 398 { 399 XiveNVT nvt; 400 uint8_t ipb; 401 402 /* 403 * Grab the associated NVT to pull the pending bits, and merge 404 * them with the IPB of the thread interrupt context registers 405 */ 406 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 407 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n", 408 nvt_blk, nvt_idx); 409 return; 410 } 411 412 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4); 413 414 if (ipb) { 415 /* Reset the NVT value */ 416 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0); 417 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 418 419 /* Merge in current context */ 420 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); 421 } 422 } 423 424 /* 425 * Updating the OS CAM line can trigger a resend of interrupt 426 */ 427 static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 428 hwaddr offset, uint64_t value, unsigned size) 429 { 430 uint32_t cam = value; 431 uint32_t qw1w2 = cpu_to_be32(cam); 432 uint8_t nvt_blk; 433 uint32_t nvt_idx; 434 bool vo; 435 436 xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); 437 438 /* First update the registers */ 439 xive_tctx_set_os_cam(tctx, qw1w2); 440 441 /* Check the interrupt pending bits */ 442 if (vo) { 443 xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); 444 } 445 } 446 447 /* 448 * Define a mapping of "special" operations depending on the TIMA page 449 * offset and the size of the operation. 450 */ 451 typedef struct XiveTmOp { 452 uint8_t page_offset; 453 uint32_t op_offset; 454 unsigned size; 455 void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, 456 hwaddr offset, 457 uint64_t value, unsigned size); 458 uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 459 unsigned size); 460 } XiveTmOp; 461 462 static const XiveTmOp xive_tm_operations[] = { 463 /* 464 * MMIOs below 2K : raw values and special operations without side 465 * effects 466 */ 467 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 468 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, NULL }, 469 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 470 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 471 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 472 473 /* MMIOs above 2K : special operations with side effects */ 474 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 475 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 476 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, 477 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, 478 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 479 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 480 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 481 }; 482 483 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 484 { 485 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 486 uint32_t op_offset = offset & 0xFFF; 487 int i; 488 489 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 490 const XiveTmOp *xto = &xive_tm_operations[i]; 491 492 /* Accesses done from a more privileged TIMA page is allowed */ 493 if (xto->page_offset >= page_offset && 494 xto->op_offset == op_offset && 495 xto->size == size && 496 ((write && xto->write_handler) || (!write && xto->read_handler))) { 497 return xto; 498 } 499 } 500 return NULL; 501 } 502 503 /* 504 * TIMA MMIO handlers 505 */ 506 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 507 uint64_t value, unsigned size) 508 { 509 const XiveTmOp *xto; 510 511 /* 512 * TODO: check V bit in Q[0-3]W2 513 */ 514 515 /* 516 * First, check for special operations in the 2K region 517 */ 518 if (offset & 0x800) { 519 xto = xive_tm_find_op(offset, size, true); 520 if (!xto) { 521 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 522 "@%"HWADDR_PRIx"\n", offset); 523 } else { 524 xto->write_handler(xptr, tctx, offset, value, size); 525 } 526 return; 527 } 528 529 /* 530 * Then, for special operations in the region below 2K. 531 */ 532 xto = xive_tm_find_op(offset, size, true); 533 if (xto) { 534 xto->write_handler(xptr, tctx, offset, value, size); 535 return; 536 } 537 538 /* 539 * Finish with raw access to the register values 540 */ 541 xive_tm_raw_write(tctx, offset, value, size); 542 } 543 544 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 545 unsigned size) 546 { 547 const XiveTmOp *xto; 548 549 /* 550 * TODO: check V bit in Q[0-3]W2 551 */ 552 553 /* 554 * First, check for special operations in the 2K region 555 */ 556 if (offset & 0x800) { 557 xto = xive_tm_find_op(offset, size, false); 558 if (!xto) { 559 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 560 "@%"HWADDR_PRIx"\n", offset); 561 return -1; 562 } 563 return xto->read_handler(xptr, tctx, offset, size); 564 } 565 566 /* 567 * Then, for special operations in the region below 2K. 568 */ 569 xto = xive_tm_find_op(offset, size, false); 570 if (xto) { 571 return xto->read_handler(xptr, tctx, offset, size); 572 } 573 574 /* 575 * Finish with raw access to the register values 576 */ 577 return xive_tm_raw_read(tctx, offset, size); 578 } 579 580 static char *xive_tctx_ring_print(uint8_t *ring) 581 { 582 uint32_t w2 = xive_tctx_word2(ring); 583 584 return g_strdup_printf("%02x %02x %02x %02x %02x " 585 "%02x %02x %02x %08x", 586 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 587 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 588 be32_to_cpu(w2)); 589 } 590 591 static const char * const xive_tctx_ring_names[] = { 592 "USER", "OS", "POOL", "PHYS", 593 }; 594 595 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 596 { 597 int cpu_index; 598 int i; 599 600 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs 601 * are hot plugged or unplugged. 602 */ 603 if (!tctx) { 604 return; 605 } 606 607 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 608 609 if (kvm_irqchip_in_kernel()) { 610 Error *local_err = NULL; 611 612 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 613 if (local_err) { 614 error_report_err(local_err); 615 return; 616 } 617 } 618 619 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 620 " W2\n", cpu_index); 621 622 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 623 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 624 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 625 xive_tctx_ring_names[i], s); 626 g_free(s); 627 } 628 } 629 630 void xive_tctx_reset(XiveTCTX *tctx) 631 { 632 memset(tctx->regs, 0, sizeof(tctx->regs)); 633 634 /* Set some defaults */ 635 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 636 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 637 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 638 639 /* 640 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 641 * CPPR is first set. 642 */ 643 tctx->regs[TM_QW1_OS + TM_PIPR] = 644 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 645 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 646 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 647 } 648 649 static void xive_tctx_realize(DeviceState *dev, Error **errp) 650 { 651 XiveTCTX *tctx = XIVE_TCTX(dev); 652 PowerPCCPU *cpu; 653 CPUPPCState *env; 654 Error *local_err = NULL; 655 656 assert(tctx->cs); 657 assert(tctx->xptr); 658 659 cpu = POWERPC_CPU(tctx->cs); 660 env = &cpu->env; 661 switch (PPC_INPUT(env)) { 662 case PPC_FLAGS_INPUT_POWER9: 663 tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT]; 664 tctx->os_output = env->irq_inputs[POWER9_INPUT_INT]; 665 break; 666 667 default: 668 error_setg(errp, "XIVE interrupt controller does not support " 669 "this CPU bus model"); 670 return; 671 } 672 673 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 674 if (kvm_irqchip_in_kernel()) { 675 kvmppc_xive_cpu_connect(tctx, &local_err); 676 if (local_err) { 677 error_propagate(errp, local_err); 678 return; 679 } 680 } 681 } 682 683 static int vmstate_xive_tctx_pre_save(void *opaque) 684 { 685 Error *local_err = NULL; 686 687 if (kvm_irqchip_in_kernel()) { 688 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque), &local_err); 689 if (local_err) { 690 error_report_err(local_err); 691 return -1; 692 } 693 } 694 695 return 0; 696 } 697 698 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 699 { 700 Error *local_err = NULL; 701 702 if (kvm_irqchip_in_kernel()) { 703 /* 704 * Required for hotplugged CPU, for which the state comes 705 * after all states of the machine. 706 */ 707 kvmppc_xive_cpu_set_state(XIVE_TCTX(opaque), &local_err); 708 if (local_err) { 709 error_report_err(local_err); 710 return -1; 711 } 712 } 713 714 return 0; 715 } 716 717 static const VMStateDescription vmstate_xive_tctx = { 718 .name = TYPE_XIVE_TCTX, 719 .version_id = 1, 720 .minimum_version_id = 1, 721 .pre_save = vmstate_xive_tctx_pre_save, 722 .post_load = vmstate_xive_tctx_post_load, 723 .fields = (VMStateField[]) { 724 VMSTATE_BUFFER(regs, XiveTCTX), 725 VMSTATE_END_OF_LIST() 726 }, 727 }; 728 729 static Property xive_tctx_properties[] = { 730 DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), 731 DEFINE_PROP_LINK("presenter", XiveTCTX, xptr, TYPE_XIVE_PRESENTER, 732 XivePresenter *), 733 DEFINE_PROP_END_OF_LIST(), 734 }; 735 736 static void xive_tctx_class_init(ObjectClass *klass, void *data) 737 { 738 DeviceClass *dc = DEVICE_CLASS(klass); 739 740 dc->desc = "XIVE Interrupt Thread Context"; 741 dc->realize = xive_tctx_realize; 742 dc->vmsd = &vmstate_xive_tctx; 743 device_class_set_props(dc, xive_tctx_properties); 744 /* 745 * Reason: part of XIVE interrupt controller, needs to be wired up 746 * by xive_tctx_create(). 747 */ 748 dc->user_creatable = false; 749 } 750 751 static const TypeInfo xive_tctx_info = { 752 .name = TYPE_XIVE_TCTX, 753 .parent = TYPE_DEVICE, 754 .instance_size = sizeof(XiveTCTX), 755 .class_init = xive_tctx_class_init, 756 }; 757 758 Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp) 759 { 760 Object *obj; 761 762 obj = object_new(TYPE_XIVE_TCTX); 763 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj); 764 object_unref(obj); 765 object_property_set_link(obj, "cpu", cpu, &error_abort); 766 object_property_set_link(obj, "presenter", OBJECT(xptr), &error_abort); 767 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 768 object_unparent(obj); 769 return NULL; 770 } 771 return obj; 772 } 773 774 void xive_tctx_destroy(XiveTCTX *tctx) 775 { 776 Object *obj = OBJECT(tctx); 777 778 object_unparent(obj); 779 } 780 781 /* 782 * XIVE ESB helpers 783 */ 784 785 static uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 786 { 787 uint8_t old_pq = *pq & 0x3; 788 789 *pq &= ~0x3; 790 *pq |= value & 0x3; 791 792 return old_pq; 793 } 794 795 static bool xive_esb_trigger(uint8_t *pq) 796 { 797 uint8_t old_pq = *pq & 0x3; 798 799 switch (old_pq) { 800 case XIVE_ESB_RESET: 801 xive_esb_set(pq, XIVE_ESB_PENDING); 802 return true; 803 case XIVE_ESB_PENDING: 804 case XIVE_ESB_QUEUED: 805 xive_esb_set(pq, XIVE_ESB_QUEUED); 806 return false; 807 case XIVE_ESB_OFF: 808 xive_esb_set(pq, XIVE_ESB_OFF); 809 return false; 810 default: 811 g_assert_not_reached(); 812 } 813 } 814 815 static bool xive_esb_eoi(uint8_t *pq) 816 { 817 uint8_t old_pq = *pq & 0x3; 818 819 switch (old_pq) { 820 case XIVE_ESB_RESET: 821 case XIVE_ESB_PENDING: 822 xive_esb_set(pq, XIVE_ESB_RESET); 823 return false; 824 case XIVE_ESB_QUEUED: 825 xive_esb_set(pq, XIVE_ESB_PENDING); 826 return true; 827 case XIVE_ESB_OFF: 828 xive_esb_set(pq, XIVE_ESB_OFF); 829 return false; 830 default: 831 g_assert_not_reached(); 832 } 833 } 834 835 /* 836 * XIVE Interrupt Source (or IVSE) 837 */ 838 839 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 840 { 841 assert(srcno < xsrc->nr_irqs); 842 843 return xsrc->status[srcno] & 0x3; 844 } 845 846 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 847 { 848 assert(srcno < xsrc->nr_irqs); 849 850 return xive_esb_set(&xsrc->status[srcno], pq); 851 } 852 853 /* 854 * Returns whether the event notification should be forwarded. 855 */ 856 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 857 { 858 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 859 860 xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; 861 862 switch (old_pq) { 863 case XIVE_ESB_RESET: 864 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 865 return true; 866 default: 867 return false; 868 } 869 } 870 871 /* 872 * Returns whether the event notification should be forwarded. 873 */ 874 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 875 { 876 bool ret; 877 878 assert(srcno < xsrc->nr_irqs); 879 880 ret = xive_esb_trigger(&xsrc->status[srcno]); 881 882 if (xive_source_irq_is_lsi(xsrc, srcno) && 883 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 884 qemu_log_mask(LOG_GUEST_ERROR, 885 "XIVE: queued an event on LSI IRQ %d\n", srcno); 886 } 887 888 return ret; 889 } 890 891 /* 892 * Returns whether the event notification should be forwarded. 893 */ 894 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 895 { 896 bool ret; 897 898 assert(srcno < xsrc->nr_irqs); 899 900 ret = xive_esb_eoi(&xsrc->status[srcno]); 901 902 /* 903 * LSI sources do not set the Q bit but they can still be 904 * asserted, in which case we should forward a new event 905 * notification 906 */ 907 if (xive_source_irq_is_lsi(xsrc, srcno) && 908 xsrc->status[srcno] & XIVE_STATUS_ASSERTED) { 909 ret = xive_source_lsi_trigger(xsrc, srcno); 910 } 911 912 return ret; 913 } 914 915 /* 916 * Forward the source event notification to the Router 917 */ 918 static void xive_source_notify(XiveSource *xsrc, int srcno) 919 { 920 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 921 922 if (xnc->notify) { 923 xnc->notify(xsrc->xive, srcno); 924 } 925 } 926 927 /* 928 * In a two pages ESB MMIO setting, even page is the trigger page, odd 929 * page is for management 930 */ 931 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 932 { 933 return !((addr >> shift) & 1); 934 } 935 936 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 937 { 938 return xive_source_esb_has_2page(xsrc) && 939 addr_is_even(addr, xsrc->esb_shift - 1); 940 } 941 942 /* 943 * ESB MMIO loads 944 * Trigger page Management/EOI page 945 * 946 * ESB MMIO setting 2 pages 1 or 2 pages 947 * 948 * 0x000 .. 0x3FF -1 EOI and return 0|1 949 * 0x400 .. 0x7FF -1 EOI and return 0|1 950 * 0x800 .. 0xBFF -1 return PQ 951 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 952 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 953 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 954 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 955 */ 956 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 957 { 958 XiveSource *xsrc = XIVE_SOURCE(opaque); 959 uint32_t offset = addr & 0xFFF; 960 uint32_t srcno = addr >> xsrc->esb_shift; 961 uint64_t ret = -1; 962 963 /* In a two pages ESB MMIO setting, trigger page should not be read */ 964 if (xive_source_is_trigger_page(xsrc, addr)) { 965 qemu_log_mask(LOG_GUEST_ERROR, 966 "XIVE: invalid load on IRQ %d trigger page at " 967 "0x%"HWADDR_PRIx"\n", srcno, addr); 968 return -1; 969 } 970 971 switch (offset) { 972 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 973 ret = xive_source_esb_eoi(xsrc, srcno); 974 975 /* Forward the source event notification for routing */ 976 if (ret) { 977 xive_source_notify(xsrc, srcno); 978 } 979 break; 980 981 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 982 ret = xive_source_esb_get(xsrc, srcno); 983 break; 984 985 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 986 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 987 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 988 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 989 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 990 break; 991 default: 992 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 993 offset); 994 } 995 996 return ret; 997 } 998 999 /* 1000 * ESB MMIO stores 1001 * Trigger page Management/EOI page 1002 * 1003 * ESB MMIO setting 2 pages 1 or 2 pages 1004 * 1005 * 0x000 .. 0x3FF Trigger Trigger 1006 * 0x400 .. 0x7FF Trigger EOI 1007 * 0x800 .. 0xBFF Trigger undefined 1008 * 0xC00 .. 0xCFF Trigger PQ=00 1009 * 0xD00 .. 0xDFF Trigger PQ=01 1010 * 0xE00 .. 0xDFF Trigger PQ=10 1011 * 0xF00 .. 0xDFF Trigger PQ=11 1012 */ 1013 static void xive_source_esb_write(void *opaque, hwaddr addr, 1014 uint64_t value, unsigned size) 1015 { 1016 XiveSource *xsrc = XIVE_SOURCE(opaque); 1017 uint32_t offset = addr & 0xFFF; 1018 uint32_t srcno = addr >> xsrc->esb_shift; 1019 bool notify = false; 1020 1021 /* In a two pages ESB MMIO setting, trigger page only triggers */ 1022 if (xive_source_is_trigger_page(xsrc, addr)) { 1023 notify = xive_source_esb_trigger(xsrc, srcno); 1024 goto out; 1025 } 1026 1027 switch (offset) { 1028 case 0 ... 0x3FF: 1029 notify = xive_source_esb_trigger(xsrc, srcno); 1030 break; 1031 1032 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 1033 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 1034 qemu_log_mask(LOG_GUEST_ERROR, 1035 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 1036 return; 1037 } 1038 1039 notify = xive_source_esb_eoi(xsrc, srcno); 1040 break; 1041 1042 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1043 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1044 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1045 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1046 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1047 break; 1048 1049 default: 1050 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 1051 offset); 1052 return; 1053 } 1054 1055 out: 1056 /* Forward the source event notification for routing */ 1057 if (notify) { 1058 xive_source_notify(xsrc, srcno); 1059 } 1060 } 1061 1062 static const MemoryRegionOps xive_source_esb_ops = { 1063 .read = xive_source_esb_read, 1064 .write = xive_source_esb_write, 1065 .endianness = DEVICE_BIG_ENDIAN, 1066 .valid = { 1067 .min_access_size = 8, 1068 .max_access_size = 8, 1069 }, 1070 .impl = { 1071 .min_access_size = 8, 1072 .max_access_size = 8, 1073 }, 1074 }; 1075 1076 void xive_source_set_irq(void *opaque, int srcno, int val) 1077 { 1078 XiveSource *xsrc = XIVE_SOURCE(opaque); 1079 bool notify = false; 1080 1081 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1082 if (val) { 1083 notify = xive_source_lsi_trigger(xsrc, srcno); 1084 } else { 1085 xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; 1086 } 1087 } else { 1088 if (val) { 1089 notify = xive_source_esb_trigger(xsrc, srcno); 1090 } 1091 } 1092 1093 /* Forward the source event notification for routing */ 1094 if (notify) { 1095 xive_source_notify(xsrc, srcno); 1096 } 1097 } 1098 1099 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 1100 { 1101 int i; 1102 1103 for (i = 0; i < xsrc->nr_irqs; i++) { 1104 uint8_t pq = xive_source_esb_get(xsrc, i); 1105 1106 if (pq == XIVE_ESB_OFF) { 1107 continue; 1108 } 1109 1110 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 1111 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1112 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1113 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1114 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' '); 1115 } 1116 } 1117 1118 static void xive_source_reset(void *dev) 1119 { 1120 XiveSource *xsrc = XIVE_SOURCE(dev); 1121 1122 /* Do not clear the LSI bitmap */ 1123 1124 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 1125 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 1126 } 1127 1128 static void xive_source_realize(DeviceState *dev, Error **errp) 1129 { 1130 XiveSource *xsrc = XIVE_SOURCE(dev); 1131 size_t esb_len = xive_source_esb_len(xsrc); 1132 1133 assert(xsrc->xive); 1134 1135 if (!xsrc->nr_irqs) { 1136 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1137 return; 1138 } 1139 1140 if (xsrc->esb_shift != XIVE_ESB_4K && 1141 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1142 xsrc->esb_shift != XIVE_ESB_64K && 1143 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1144 error_setg(errp, "Invalid ESB shift setting"); 1145 return; 1146 } 1147 1148 xsrc->status = g_malloc0(xsrc->nr_irqs); 1149 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1150 1151 memory_region_init(&xsrc->esb_mmio, OBJECT(xsrc), "xive.esb", esb_len); 1152 memory_region_init_io(&xsrc->esb_mmio_emulated, OBJECT(xsrc), 1153 &xive_source_esb_ops, xsrc, "xive.esb-emulated", 1154 esb_len); 1155 memory_region_add_subregion(&xsrc->esb_mmio, 0, &xsrc->esb_mmio_emulated); 1156 1157 qemu_register_reset(xive_source_reset, dev); 1158 } 1159 1160 static const VMStateDescription vmstate_xive_source = { 1161 .name = TYPE_XIVE_SOURCE, 1162 .version_id = 1, 1163 .minimum_version_id = 1, 1164 .fields = (VMStateField[]) { 1165 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1166 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1167 VMSTATE_END_OF_LIST() 1168 }, 1169 }; 1170 1171 /* 1172 * The default XIVE interrupt source setting for the ESB MMIOs is two 1173 * 64k pages without Store EOI, to be in sync with KVM. 1174 */ 1175 static Property xive_source_properties[] = { 1176 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1177 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1178 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1179 DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, 1180 XiveNotifier *), 1181 DEFINE_PROP_END_OF_LIST(), 1182 }; 1183 1184 static void xive_source_class_init(ObjectClass *klass, void *data) 1185 { 1186 DeviceClass *dc = DEVICE_CLASS(klass); 1187 1188 dc->desc = "XIVE Interrupt Source"; 1189 device_class_set_props(dc, xive_source_properties); 1190 dc->realize = xive_source_realize; 1191 dc->vmsd = &vmstate_xive_source; 1192 /* 1193 * Reason: part of XIVE interrupt controller, needs to be wired up, 1194 * e.g. by spapr_xive_instance_init(). 1195 */ 1196 dc->user_creatable = false; 1197 } 1198 1199 static const TypeInfo xive_source_info = { 1200 .name = TYPE_XIVE_SOURCE, 1201 .parent = TYPE_DEVICE, 1202 .instance_size = sizeof(XiveSource), 1203 .class_init = xive_source_class_init, 1204 }; 1205 1206 /* 1207 * XiveEND helpers 1208 */ 1209 1210 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1211 { 1212 uint64_t qaddr_base = xive_end_qaddr(end); 1213 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1214 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1215 uint32_t qentries = 1 << (qsize + 10); 1216 int i; 1217 1218 /* 1219 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1220 */ 1221 monitor_printf(mon, " [ "); 1222 qindex = (qindex - (width - 1)) & (qentries - 1); 1223 for (i = 0; i < width; i++) { 1224 uint64_t qaddr = qaddr_base + (qindex << 2); 1225 uint32_t qdata = -1; 1226 1227 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 1228 sizeof(qdata))) { 1229 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1230 HWADDR_PRIx "\n", qaddr); 1231 return; 1232 } 1233 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1234 be32_to_cpu(qdata)); 1235 qindex = (qindex + 1) & (qentries - 1); 1236 } 1237 monitor_printf(mon, "]"); 1238 } 1239 1240 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1241 { 1242 uint64_t qaddr_base = xive_end_qaddr(end); 1243 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1244 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1245 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1246 uint32_t qentries = 1 << (qsize + 10); 1247 1248 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1249 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1250 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1251 uint8_t pq; 1252 1253 if (!xive_end_is_valid(end)) { 1254 return; 1255 } 1256 1257 pq = xive_get_field32(END_W1_ESn, end->w1); 1258 1259 monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1260 end_idx, 1261 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1262 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1263 xive_end_is_valid(end) ? 'v' : '-', 1264 xive_end_is_enqueue(end) ? 'q' : '-', 1265 xive_end_is_notify(end) ? 'n' : '-', 1266 xive_end_is_backlog(end) ? 'b' : '-', 1267 xive_end_is_escalate(end) ? 'e' : '-', 1268 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1269 xive_end_is_silent_escalation(end) ? 's' : '-', 1270 priority, nvt_blk, nvt_idx); 1271 1272 if (qaddr_base) { 1273 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1274 qaddr_base, qindex, qentries, qgen); 1275 xive_end_queue_pic_print_info(end, 6, mon); 1276 } 1277 monitor_printf(mon, "\n"); 1278 } 1279 1280 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1281 { 1282 uint64_t qaddr_base = xive_end_qaddr(end); 1283 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1284 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1285 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1286 1287 uint64_t qaddr = qaddr_base + (qindex << 2); 1288 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1289 uint32_t qentries = 1 << (qsize + 10); 1290 1291 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) { 1292 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1293 HWADDR_PRIx "\n", qaddr); 1294 return; 1295 } 1296 1297 qindex = (qindex + 1) & (qentries - 1); 1298 if (qindex == 0) { 1299 qgen ^= 1; 1300 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1301 } 1302 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1303 } 1304 1305 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, 1306 Monitor *mon) 1307 { 1308 XiveEAS *eas = (XiveEAS *) &end->w4; 1309 uint8_t pq; 1310 1311 if (!xive_end_is_escalate(end)) { 1312 return; 1313 } 1314 1315 pq = xive_get_field32(END_W1_ESe, end->w1); 1316 1317 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1318 end_idx, 1319 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1320 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1321 xive_eas_is_valid(eas) ? 'V' : ' ', 1322 xive_eas_is_masked(eas) ? 'M' : ' ', 1323 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1324 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1325 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1326 } 1327 1328 /* 1329 * XIVE Router (aka. Virtualization Controller or IVRE) 1330 */ 1331 1332 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1333 XiveEAS *eas) 1334 { 1335 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1336 1337 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1338 } 1339 1340 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1341 XiveEND *end) 1342 { 1343 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1344 1345 return xrc->get_end(xrtr, end_blk, end_idx, end); 1346 } 1347 1348 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1349 XiveEND *end, uint8_t word_number) 1350 { 1351 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1352 1353 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1354 } 1355 1356 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1357 XiveNVT *nvt) 1358 { 1359 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1360 1361 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1362 } 1363 1364 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1365 XiveNVT *nvt, uint8_t word_number) 1366 { 1367 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1368 1369 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1370 } 1371 1372 static int xive_router_get_block_id(XiveRouter *xrtr) 1373 { 1374 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1375 1376 return xrc->get_block_id(xrtr); 1377 } 1378 1379 static void xive_router_realize(DeviceState *dev, Error **errp) 1380 { 1381 XiveRouter *xrtr = XIVE_ROUTER(dev); 1382 1383 assert(xrtr->xfb); 1384 } 1385 1386 /* 1387 * Encode the HW CAM line in the block group mode format : 1388 * 1389 * chip << 19 | 0000000 0 0001 thread (7Bit) 1390 */ 1391 static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 1392 { 1393 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1394 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1395 uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr)); 1396 1397 return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); 1398 } 1399 1400 /* 1401 * The thread context register words are in big-endian format. 1402 */ 1403 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1404 uint8_t format, 1405 uint8_t nvt_blk, uint32_t nvt_idx, 1406 bool cam_ignore, uint32_t logic_serv) 1407 { 1408 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1409 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1410 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1411 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1412 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1413 1414 /* 1415 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1416 * identifier are ignored in the "CAM" match. 1417 */ 1418 1419 if (format == 0) { 1420 if (cam_ignore == true) { 1421 /* 1422 * F=0 & i=1: Logical server notification (bits ignored at 1423 * the end of the NVT identifier) 1424 */ 1425 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1426 nvt_blk, nvt_idx); 1427 return -1; 1428 } 1429 1430 /* F=0 & i=0: Specific NVT notification */ 1431 1432 /* PHYS ring */ 1433 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1434 cam == xive_tctx_hw_cam_line(xptr, tctx)) { 1435 return TM_QW3_HV_PHYS; 1436 } 1437 1438 /* HV POOL ring */ 1439 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1440 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1441 return TM_QW2_HV_POOL; 1442 } 1443 1444 /* OS ring */ 1445 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1446 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1447 return TM_QW1_OS; 1448 } 1449 } else { 1450 /* F=1 : User level Event-Based Branch (EBB) notification */ 1451 1452 /* USER ring */ 1453 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1454 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1455 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1456 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1457 return TM_QW0_USER; 1458 } 1459 } 1460 return -1; 1461 } 1462 1463 /* 1464 * This is our simple Xive Presenter Engine model. It is merged in the 1465 * Router as it does not require an extra object. 1466 * 1467 * It receives notification requests sent by the IVRE to find one 1468 * matching NVT (or more) dispatched on the processor threads. In case 1469 * of a single NVT notification, the process is abreviated and the 1470 * thread is signaled if a match is found. In case of a logical server 1471 * notification (bits ignored at the end of the NVT identifier), the 1472 * IVPE and IVRE select a winning thread using different filters. This 1473 * involves 2 or 3 exchanges on the PowerBus that the model does not 1474 * support. 1475 * 1476 * The parameters represent what is sent on the PowerBus 1477 */ 1478 static bool xive_presenter_notify(XiveFabric *xfb, uint8_t format, 1479 uint8_t nvt_blk, uint32_t nvt_idx, 1480 bool cam_ignore, uint8_t priority, 1481 uint32_t logic_serv) 1482 { 1483 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb); 1484 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1485 int count; 1486 1487 /* 1488 * Ask the machine to scan the interrupt controllers for a match 1489 */ 1490 count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore, 1491 priority, logic_serv, &match); 1492 if (count < 0) { 1493 return false; 1494 } 1495 1496 /* handle CPU exception delivery */ 1497 if (count) { 1498 xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(priority)); 1499 } 1500 1501 return !!count; 1502 } 1503 1504 /* 1505 * Notification using the END ESe/ESn bit (Event State Buffer for 1506 * escalation and notification). Provide further coalescing in the 1507 * Router. 1508 */ 1509 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1510 uint32_t end_idx, XiveEND *end, 1511 uint32_t end_esmask) 1512 { 1513 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1514 bool notify = xive_esb_trigger(&pq); 1515 1516 if (pq != xive_get_field32(end_esmask, end->w1)) { 1517 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1518 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1519 } 1520 1521 /* ESe/n[Q]=1 : end of notification */ 1522 return notify; 1523 } 1524 1525 /* 1526 * An END trigger can come from an event trigger (IPI or HW) or from 1527 * another chip. We don't model the PowerBus but the END trigger 1528 * message has the same parameters than in the function below. 1529 */ 1530 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1531 uint32_t end_idx, uint32_t end_data) 1532 { 1533 XiveEND end; 1534 uint8_t priority; 1535 uint8_t format; 1536 uint8_t nvt_blk; 1537 uint32_t nvt_idx; 1538 XiveNVT nvt; 1539 bool found; 1540 1541 /* END cache lookup */ 1542 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1543 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1544 end_idx); 1545 return; 1546 } 1547 1548 if (!xive_end_is_valid(&end)) { 1549 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1550 end_blk, end_idx); 1551 return; 1552 } 1553 1554 if (xive_end_is_enqueue(&end)) { 1555 xive_end_enqueue(&end, end_data); 1556 /* Enqueuing event data modifies the EQ toggle and index */ 1557 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1558 } 1559 1560 /* 1561 * When the END is silent, we skip the notification part. 1562 */ 1563 if (xive_end_is_silent_escalation(&end)) { 1564 goto do_escalation; 1565 } 1566 1567 /* 1568 * The W7 format depends on the F bit in W6. It defines the type 1569 * of the notification : 1570 * 1571 * F=0 : single or multiple NVT notification 1572 * F=1 : User level Event-Based Branch (EBB) notification, no 1573 * priority 1574 */ 1575 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1576 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1577 1578 /* The END is masked */ 1579 if (format == 0 && priority == 0xff) { 1580 return; 1581 } 1582 1583 /* 1584 * Check the END ESn (Event State Buffer for notification) for 1585 * even further coalescing in the Router 1586 */ 1587 if (!xive_end_is_notify(&end)) { 1588 /* ESn[Q]=1 : end of notification */ 1589 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1590 &end, END_W1_ESn)) { 1591 return; 1592 } 1593 } 1594 1595 /* 1596 * Follows IVPE notification 1597 */ 1598 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1599 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1600 1601 /* NVT cache lookup */ 1602 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1603 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1604 nvt_blk, nvt_idx); 1605 return; 1606 } 1607 1608 if (!xive_nvt_is_valid(&nvt)) { 1609 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1610 nvt_blk, nvt_idx); 1611 return; 1612 } 1613 1614 found = xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx, 1615 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1616 priority, 1617 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1618 1619 /* TODO: Auto EOI. */ 1620 1621 if (found) { 1622 return; 1623 } 1624 1625 /* 1626 * If no matching NVT is dispatched on a HW thread : 1627 * - specific VP: update the NVT structure if backlog is activated 1628 * - logical server : forward request to IVPE (not supported) 1629 */ 1630 if (xive_end_is_backlog(&end)) { 1631 uint8_t ipb; 1632 1633 if (format == 1) { 1634 qemu_log_mask(LOG_GUEST_ERROR, 1635 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1636 end_blk, end_idx); 1637 return; 1638 } 1639 /* 1640 * Record the IPB in the associated NVT structure for later 1641 * use. The presenter will resend the interrupt when the vCPU 1642 * is dispatched again on a HW thread. 1643 */ 1644 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priority); 1645 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); 1646 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1647 1648 /* 1649 * On HW, follows a "Broadcast Backlog" to IVPEs 1650 */ 1651 } 1652 1653 do_escalation: 1654 /* 1655 * If activated, escalate notification using the ESe PQ bits and 1656 * the EAS in w4-5 1657 */ 1658 if (!xive_end_is_escalate(&end)) { 1659 return; 1660 } 1661 1662 /* 1663 * Check the END ESe (Event State Buffer for escalation) for even 1664 * further coalescing in the Router 1665 */ 1666 if (!xive_end_is_uncond_escalation(&end)) { 1667 /* ESe[Q]=1 : end of notification */ 1668 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1669 &end, END_W1_ESe)) { 1670 return; 1671 } 1672 } 1673 1674 /* 1675 * The END trigger becomes an Escalation trigger 1676 */ 1677 xive_router_end_notify(xrtr, 1678 xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1679 xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1680 xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1681 } 1682 1683 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 1684 { 1685 XiveRouter *xrtr = XIVE_ROUTER(xn); 1686 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1687 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1688 XiveEAS eas; 1689 1690 /* EAS cache lookup */ 1691 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1692 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1693 return; 1694 } 1695 1696 /* 1697 * The IVRE checks the State Bit Cache at this point. We skip the 1698 * SBC lookup because the state bits of the sources are modeled 1699 * internally in QEMU. 1700 */ 1701 1702 if (!xive_eas_is_valid(&eas)) { 1703 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1704 return; 1705 } 1706 1707 if (xive_eas_is_masked(&eas)) { 1708 /* Notification completed */ 1709 return; 1710 } 1711 1712 /* 1713 * The event trigger becomes an END trigger 1714 */ 1715 xive_router_end_notify(xrtr, 1716 xive_get_field64(EAS_END_BLOCK, eas.w), 1717 xive_get_field64(EAS_END_INDEX, eas.w), 1718 xive_get_field64(EAS_END_DATA, eas.w)); 1719 } 1720 1721 static Property xive_router_properties[] = { 1722 DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb, 1723 TYPE_XIVE_FABRIC, XiveFabric *), 1724 DEFINE_PROP_END_OF_LIST(), 1725 }; 1726 1727 static void xive_router_class_init(ObjectClass *klass, void *data) 1728 { 1729 DeviceClass *dc = DEVICE_CLASS(klass); 1730 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1731 1732 dc->desc = "XIVE Router Engine"; 1733 device_class_set_props(dc, xive_router_properties); 1734 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 1735 dc->realize = xive_router_realize; 1736 xnc->notify = xive_router_notify; 1737 } 1738 1739 static const TypeInfo xive_router_info = { 1740 .name = TYPE_XIVE_ROUTER, 1741 .parent = TYPE_SYS_BUS_DEVICE, 1742 .abstract = true, 1743 .instance_size = sizeof(XiveRouter), 1744 .class_size = sizeof(XiveRouterClass), 1745 .class_init = xive_router_class_init, 1746 .interfaces = (InterfaceInfo[]) { 1747 { TYPE_XIVE_NOTIFIER }, 1748 { TYPE_XIVE_PRESENTER }, 1749 { } 1750 } 1751 }; 1752 1753 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1754 { 1755 if (!xive_eas_is_valid(eas)) { 1756 return; 1757 } 1758 1759 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1760 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1761 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1762 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1763 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1764 } 1765 1766 /* 1767 * END ESB MMIO loads 1768 */ 1769 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1770 { 1771 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1772 uint32_t offset = addr & 0xFFF; 1773 uint8_t end_blk; 1774 uint32_t end_idx; 1775 XiveEND end; 1776 uint32_t end_esmask; 1777 uint8_t pq; 1778 uint64_t ret = -1; 1779 1780 /* 1781 * The block id should be deduced from the load address on the END 1782 * ESB MMIO but our model only supports a single block per XIVE chip. 1783 */ 1784 end_blk = xive_router_get_block_id(xsrc->xrtr); 1785 end_idx = addr >> (xsrc->esb_shift + 1); 1786 1787 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1788 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1789 end_idx); 1790 return -1; 1791 } 1792 1793 if (!xive_end_is_valid(&end)) { 1794 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1795 end_blk, end_idx); 1796 return -1; 1797 } 1798 1799 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1800 pq = xive_get_field32(end_esmask, end.w1); 1801 1802 switch (offset) { 1803 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1804 ret = xive_esb_eoi(&pq); 1805 1806 /* Forward the source event notification for routing ?? */ 1807 break; 1808 1809 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1810 ret = pq; 1811 break; 1812 1813 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1814 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1815 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1816 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1817 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1818 break; 1819 default: 1820 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1821 offset); 1822 return -1; 1823 } 1824 1825 if (pq != xive_get_field32(end_esmask, end.w1)) { 1826 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1827 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1828 } 1829 1830 return ret; 1831 } 1832 1833 /* 1834 * END ESB MMIO stores are invalid 1835 */ 1836 static void xive_end_source_write(void *opaque, hwaddr addr, 1837 uint64_t value, unsigned size) 1838 { 1839 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1840 HWADDR_PRIx"\n", addr); 1841 } 1842 1843 static const MemoryRegionOps xive_end_source_ops = { 1844 .read = xive_end_source_read, 1845 .write = xive_end_source_write, 1846 .endianness = DEVICE_BIG_ENDIAN, 1847 .valid = { 1848 .min_access_size = 8, 1849 .max_access_size = 8, 1850 }, 1851 .impl = { 1852 .min_access_size = 8, 1853 .max_access_size = 8, 1854 }, 1855 }; 1856 1857 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1858 { 1859 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1860 1861 assert(xsrc->xrtr); 1862 1863 if (!xsrc->nr_ends) { 1864 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1865 return; 1866 } 1867 1868 if (xsrc->esb_shift != XIVE_ESB_4K && 1869 xsrc->esb_shift != XIVE_ESB_64K) { 1870 error_setg(errp, "Invalid ESB shift setting"); 1871 return; 1872 } 1873 1874 /* 1875 * Each END is assigned an even/odd pair of MMIO pages, the even page 1876 * manages the ESn field while the odd page manages the ESe field. 1877 */ 1878 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1879 &xive_end_source_ops, xsrc, "xive.end", 1880 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1881 } 1882 1883 static Property xive_end_source_properties[] = { 1884 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1885 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1886 DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, 1887 XiveRouter *), 1888 DEFINE_PROP_END_OF_LIST(), 1889 }; 1890 1891 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1892 { 1893 DeviceClass *dc = DEVICE_CLASS(klass); 1894 1895 dc->desc = "XIVE END Source"; 1896 device_class_set_props(dc, xive_end_source_properties); 1897 dc->realize = xive_end_source_realize; 1898 /* 1899 * Reason: part of XIVE interrupt controller, needs to be wired up, 1900 * e.g. by spapr_xive_instance_init(). 1901 */ 1902 dc->user_creatable = false; 1903 } 1904 1905 static const TypeInfo xive_end_source_info = { 1906 .name = TYPE_XIVE_END_SOURCE, 1907 .parent = TYPE_DEVICE, 1908 .instance_size = sizeof(XiveENDSource), 1909 .class_init = xive_end_source_class_init, 1910 }; 1911 1912 /* 1913 * XIVE Notifier 1914 */ 1915 static const TypeInfo xive_notifier_info = { 1916 .name = TYPE_XIVE_NOTIFIER, 1917 .parent = TYPE_INTERFACE, 1918 .class_size = sizeof(XiveNotifierClass), 1919 }; 1920 1921 /* 1922 * XIVE Presenter 1923 */ 1924 static const TypeInfo xive_presenter_info = { 1925 .name = TYPE_XIVE_PRESENTER, 1926 .parent = TYPE_INTERFACE, 1927 .class_size = sizeof(XivePresenterClass), 1928 }; 1929 1930 /* 1931 * XIVE Fabric 1932 */ 1933 static const TypeInfo xive_fabric_info = { 1934 .name = TYPE_XIVE_FABRIC, 1935 .parent = TYPE_INTERFACE, 1936 .class_size = sizeof(XiveFabricClass), 1937 }; 1938 1939 static void xive_register_types(void) 1940 { 1941 type_register_static(&xive_fabric_info); 1942 type_register_static(&xive_source_info); 1943 type_register_static(&xive_notifier_info); 1944 type_register_static(&xive_presenter_info); 1945 type_register_static(&xive_router_info); 1946 type_register_static(&xive_end_source_info); 1947 type_register_static(&xive_tctx_info); 1948 } 1949 1950 type_init(xive_register_types) 1951