1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "monitor/monitor.h" 21 #include "hw/irq.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive_regs.h" 24 25 /* 26 * XIVE Thread Interrupt Management context 27 */ 28 29 /* 30 * Convert a priority number to an Interrupt Pending Buffer (IPB) 31 * register, which indicates a pending interrupt at the priority 32 * corresponding to the bit number 33 */ 34 static uint8_t priority_to_ipb(uint8_t priority) 35 { 36 return priority > XIVE_PRIORITY_MAX ? 37 0 : 1 << (XIVE_PRIORITY_MAX - priority); 38 } 39 40 /* 41 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 42 * Interrupt Priority Register (PIPR), which contains the priority of 43 * the most favored pending notification. 44 */ 45 static uint8_t ipb_to_pipr(uint8_t ibp) 46 { 47 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 48 } 49 50 static void ipb_update(uint8_t *regs, uint8_t priority) 51 { 52 regs[TM_IPB] |= priority_to_ipb(priority); 53 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 54 } 55 56 static uint8_t exception_mask(uint8_t ring) 57 { 58 switch (ring) { 59 case TM_QW1_OS: 60 return TM_QW1_NSR_EO; 61 case TM_QW3_HV_PHYS: 62 return TM_QW3_NSR_HE; 63 default: 64 g_assert_not_reached(); 65 } 66 } 67 68 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 69 { 70 switch (ring) { 71 case TM_QW0_USER: 72 return 0; /* Not supported */ 73 case TM_QW1_OS: 74 return tctx->os_output; 75 case TM_QW2_HV_POOL: 76 case TM_QW3_HV_PHYS: 77 return tctx->hv_output; 78 default: 79 return 0; 80 } 81 } 82 83 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 84 { 85 uint8_t *regs = &tctx->regs[ring]; 86 uint8_t nsr = regs[TM_NSR]; 87 uint8_t mask = exception_mask(ring); 88 89 qemu_irq_lower(xive_tctx_output(tctx, ring)); 90 91 if (regs[TM_NSR] & mask) { 92 uint8_t cppr = regs[TM_PIPR]; 93 94 regs[TM_CPPR] = cppr; 95 96 /* Reset the pending buffer bit */ 97 regs[TM_IPB] &= ~priority_to_ipb(cppr); 98 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 99 100 /* Drop Exception bit */ 101 regs[TM_NSR] &= ~mask; 102 } 103 104 return (nsr << 8) | regs[TM_CPPR]; 105 } 106 107 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 108 { 109 uint8_t *regs = &tctx->regs[ring]; 110 111 if (regs[TM_PIPR] < regs[TM_CPPR]) { 112 switch (ring) { 113 case TM_QW1_OS: 114 regs[TM_NSR] |= TM_QW1_NSR_EO; 115 break; 116 case TM_QW3_HV_PHYS: 117 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 118 break; 119 default: 120 g_assert_not_reached(); 121 } 122 qemu_irq_raise(xive_tctx_output(tctx, ring)); 123 } 124 } 125 126 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 127 { 128 if (cppr > XIVE_PRIORITY_MAX) { 129 cppr = 0xff; 130 } 131 132 tctx->regs[ring + TM_CPPR] = cppr; 133 134 /* CPPR has changed, check if we need to raise a pending exception */ 135 xive_tctx_notify(tctx, ring); 136 } 137 138 static inline uint32_t xive_tctx_word2(uint8_t *ring) 139 { 140 return *((uint32_t *) &ring[TM_WORD2]); 141 } 142 143 /* 144 * XIVE Thread Interrupt Management Area (TIMA) 145 */ 146 147 static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset, 148 uint64_t value, unsigned size) 149 { 150 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 151 } 152 153 static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) 154 { 155 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 156 } 157 158 static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, 159 unsigned size) 160 { 161 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 162 uint32_t qw2w2; 163 164 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 165 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 166 return qw2w2; 167 } 168 169 static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset, 170 uint64_t value, unsigned size) 171 { 172 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 173 } 174 175 static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned size) 176 { 177 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 178 } 179 180 /* 181 * Define an access map for each page of the TIMA that we will use in 182 * the memory region ops to filter values when doing loads and stores 183 * of raw registers values 184 * 185 * Registers accessibility bits : 186 * 187 * 0x0 - no access 188 * 0x1 - write only 189 * 0x2 - read only 190 * 0x3 - read/write 191 */ 192 193 static const uint8_t xive_tm_hw_view[] = { 194 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 195 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 196 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 197 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 198 }; 199 200 static const uint8_t xive_tm_hv_view[] = { 201 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 202 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 203 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 204 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 205 }; 206 207 static const uint8_t xive_tm_os_view[] = { 208 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 209 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 210 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 211 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 212 }; 213 214 static const uint8_t xive_tm_user_view[] = { 215 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 219 }; 220 221 /* 222 * Overall TIMA access map for the thread interrupt management context 223 * registers 224 */ 225 static const uint8_t *xive_tm_views[] = { 226 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 227 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 228 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 229 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 230 }; 231 232 /* 233 * Computes a register access mask for a given offset in the TIMA 234 */ 235 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 236 { 237 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 238 uint8_t reg_offset = offset & 0x3F; 239 uint8_t reg_mask = write ? 0x1 : 0x2; 240 uint64_t mask = 0x0; 241 int i; 242 243 for (i = 0; i < size; i++) { 244 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 245 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 246 } 247 } 248 249 return mask; 250 } 251 252 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 253 unsigned size) 254 { 255 uint8_t ring_offset = offset & 0x30; 256 uint8_t reg_offset = offset & 0x3F; 257 uint64_t mask = xive_tm_mask(offset, size, true); 258 int i; 259 260 /* 261 * Only 4 or 8 bytes stores are allowed and the User ring is 262 * excluded 263 */ 264 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 265 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 266 HWADDR_PRIx"\n", offset); 267 return; 268 } 269 270 /* 271 * Use the register offset for the raw values and filter out 272 * reserved values 273 */ 274 for (i = 0; i < size; i++) { 275 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 276 if (byte_mask) { 277 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 278 byte_mask; 279 } 280 } 281 } 282 283 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 284 { 285 uint8_t ring_offset = offset & 0x30; 286 uint8_t reg_offset = offset & 0x3F; 287 uint64_t mask = xive_tm_mask(offset, size, false); 288 uint64_t ret; 289 int i; 290 291 /* 292 * Only 4 or 8 bytes loads are allowed and the User ring is 293 * excluded 294 */ 295 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 296 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 297 HWADDR_PRIx"\n", offset); 298 return -1; 299 } 300 301 /* Use the register offset for the raw values */ 302 ret = 0; 303 for (i = 0; i < size; i++) { 304 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 305 } 306 307 /* filter out reserved values */ 308 return ret & mask; 309 } 310 311 /* 312 * The TM context is mapped twice within each page. Stores and loads 313 * to the first mapping below 2K write and read the specified values 314 * without modification. The second mapping above 2K performs specific 315 * state changes (side effects) in addition to setting/returning the 316 * interrupt management area context of the processor thread. 317 */ 318 static uint64_t xive_tm_ack_os_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) 319 { 320 return xive_tctx_accept(tctx, TM_QW1_OS); 321 } 322 323 static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset, 324 uint64_t value, unsigned size) 325 { 326 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 327 } 328 329 /* 330 * Adjust the IPB to allow a CPU to process event queues of other 331 * priorities during one physical interrupt cycle. 332 */ 333 static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset, 334 uint64_t value, unsigned size) 335 { 336 ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff); 337 xive_tctx_notify(tctx, TM_QW1_OS); 338 } 339 340 static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset, 341 unsigned size) 342 { 343 uint32_t qw1w2_prev = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 344 uint32_t qw1w2; 345 346 qw1w2 = xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0); 347 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 348 return qw1w2; 349 } 350 351 /* 352 * Define a mapping of "special" operations depending on the TIMA page 353 * offset and the size of the operation. 354 */ 355 typedef struct XiveTmOp { 356 uint8_t page_offset; 357 uint32_t op_offset; 358 unsigned size; 359 void (*write_handler)(XiveTCTX *tctx, hwaddr offset, uint64_t value, 360 unsigned size); 361 uint64_t (*read_handler)(XiveTCTX *tctx, hwaddr offset, unsigned size); 362 } XiveTmOp; 363 364 static const XiveTmOp xive_tm_operations[] = { 365 /* 366 * MMIOs below 2K : raw values and special operations without side 367 * effects 368 */ 369 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 370 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 371 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 372 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 373 374 /* MMIOs above 2K : special operations with side effects */ 375 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 376 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 377 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, 378 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, 379 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 380 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 381 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 382 }; 383 384 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 385 { 386 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 387 uint32_t op_offset = offset & 0xFFF; 388 int i; 389 390 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 391 const XiveTmOp *xto = &xive_tm_operations[i]; 392 393 /* Accesses done from a more privileged TIMA page is allowed */ 394 if (xto->page_offset >= page_offset && 395 xto->op_offset == op_offset && 396 xto->size == size && 397 ((write && xto->write_handler) || (!write && xto->read_handler))) { 398 return xto; 399 } 400 } 401 return NULL; 402 } 403 404 /* 405 * TIMA MMIO handlers 406 */ 407 void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 408 unsigned size) 409 { 410 const XiveTmOp *xto; 411 412 /* 413 * TODO: check V bit in Q[0-3]W2 414 */ 415 416 /* 417 * First, check for special operations in the 2K region 418 */ 419 if (offset & 0x800) { 420 xto = xive_tm_find_op(offset, size, true); 421 if (!xto) { 422 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 423 "@%"HWADDR_PRIx"\n", offset); 424 } else { 425 xto->write_handler(tctx, offset, value, size); 426 } 427 return; 428 } 429 430 /* 431 * Then, for special operations in the region below 2K. 432 */ 433 xto = xive_tm_find_op(offset, size, true); 434 if (xto) { 435 xto->write_handler(tctx, offset, value, size); 436 return; 437 } 438 439 /* 440 * Finish with raw access to the register values 441 */ 442 xive_tm_raw_write(tctx, offset, value, size); 443 } 444 445 uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 446 { 447 const XiveTmOp *xto; 448 449 /* 450 * TODO: check V bit in Q[0-3]W2 451 */ 452 453 /* 454 * First, check for special operations in the 2K region 455 */ 456 if (offset & 0x800) { 457 xto = xive_tm_find_op(offset, size, false); 458 if (!xto) { 459 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 460 "@%"HWADDR_PRIx"\n", offset); 461 return -1; 462 } 463 return xto->read_handler(tctx, offset, size); 464 } 465 466 /* 467 * Then, for special operations in the region below 2K. 468 */ 469 xto = xive_tm_find_op(offset, size, false); 470 if (xto) { 471 return xto->read_handler(tctx, offset, size); 472 } 473 474 /* 475 * Finish with raw access to the register values 476 */ 477 return xive_tm_raw_read(tctx, offset, size); 478 } 479 480 static void xive_tm_write(void *opaque, hwaddr offset, 481 uint64_t value, unsigned size) 482 { 483 XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); 484 485 xive_tctx_tm_write(tctx, offset, value, size); 486 } 487 488 static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) 489 { 490 XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); 491 492 return xive_tctx_tm_read(tctx, offset, size); 493 } 494 495 const MemoryRegionOps xive_tm_ops = { 496 .read = xive_tm_read, 497 .write = xive_tm_write, 498 .endianness = DEVICE_BIG_ENDIAN, 499 .valid = { 500 .min_access_size = 1, 501 .max_access_size = 8, 502 }, 503 .impl = { 504 .min_access_size = 1, 505 .max_access_size = 8, 506 }, 507 }; 508 509 static char *xive_tctx_ring_print(uint8_t *ring) 510 { 511 uint32_t w2 = xive_tctx_word2(ring); 512 513 return g_strdup_printf("%02x %02x %02x %02x %02x " 514 "%02x %02x %02x %08x", 515 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 516 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 517 be32_to_cpu(w2)); 518 } 519 520 static const char * const xive_tctx_ring_names[] = { 521 "USER", "OS", "POOL", "PHYS", 522 }; 523 524 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 525 { 526 int cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 527 int i; 528 529 if (kvm_irqchip_in_kernel()) { 530 Error *local_err = NULL; 531 532 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 533 if (local_err) { 534 error_report_err(local_err); 535 return; 536 } 537 } 538 539 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 540 " W2\n", cpu_index); 541 542 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 543 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 544 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 545 xive_tctx_ring_names[i], s); 546 g_free(s); 547 } 548 } 549 550 static void xive_tctx_reset(void *dev) 551 { 552 XiveTCTX *tctx = XIVE_TCTX(dev); 553 554 memset(tctx->regs, 0, sizeof(tctx->regs)); 555 556 /* Set some defaults */ 557 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 558 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 559 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 560 561 /* 562 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 563 * CPPR is first set. 564 */ 565 tctx->regs[TM_QW1_OS + TM_PIPR] = 566 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 567 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 568 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 569 } 570 571 static void xive_tctx_realize(DeviceState *dev, Error **errp) 572 { 573 XiveTCTX *tctx = XIVE_TCTX(dev); 574 PowerPCCPU *cpu; 575 CPUPPCState *env; 576 Object *obj; 577 Error *local_err = NULL; 578 579 obj = object_property_get_link(OBJECT(dev), "cpu", &local_err); 580 if (!obj) { 581 error_propagate(errp, local_err); 582 error_prepend(errp, "required link 'cpu' not found: "); 583 return; 584 } 585 586 cpu = POWERPC_CPU(obj); 587 tctx->cs = CPU(obj); 588 589 env = &cpu->env; 590 switch (PPC_INPUT(env)) { 591 case PPC_FLAGS_INPUT_POWER9: 592 tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT]; 593 tctx->os_output = env->irq_inputs[POWER9_INPUT_INT]; 594 break; 595 596 default: 597 error_setg(errp, "XIVE interrupt controller does not support " 598 "this CPU bus model"); 599 return; 600 } 601 602 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 603 if (kvm_irqchip_in_kernel()) { 604 kvmppc_xive_cpu_connect(tctx, &local_err); 605 if (local_err) { 606 error_propagate(errp, local_err); 607 return; 608 } 609 } 610 611 qemu_register_reset(xive_tctx_reset, dev); 612 } 613 614 static void xive_tctx_unrealize(DeviceState *dev, Error **errp) 615 { 616 qemu_unregister_reset(xive_tctx_reset, dev); 617 } 618 619 static int vmstate_xive_tctx_pre_save(void *opaque) 620 { 621 Error *local_err = NULL; 622 623 if (kvm_irqchip_in_kernel()) { 624 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque), &local_err); 625 if (local_err) { 626 error_report_err(local_err); 627 return -1; 628 } 629 } 630 631 return 0; 632 } 633 634 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 635 { 636 Error *local_err = NULL; 637 638 if (kvm_irqchip_in_kernel()) { 639 /* 640 * Required for hotplugged CPU, for which the state comes 641 * after all states of the machine. 642 */ 643 kvmppc_xive_cpu_set_state(XIVE_TCTX(opaque), &local_err); 644 if (local_err) { 645 error_report_err(local_err); 646 return -1; 647 } 648 } 649 650 return 0; 651 } 652 653 static const VMStateDescription vmstate_xive_tctx = { 654 .name = TYPE_XIVE_TCTX, 655 .version_id = 1, 656 .minimum_version_id = 1, 657 .pre_save = vmstate_xive_tctx_pre_save, 658 .post_load = vmstate_xive_tctx_post_load, 659 .fields = (VMStateField[]) { 660 VMSTATE_BUFFER(regs, XiveTCTX), 661 VMSTATE_END_OF_LIST() 662 }, 663 }; 664 665 static void xive_tctx_class_init(ObjectClass *klass, void *data) 666 { 667 DeviceClass *dc = DEVICE_CLASS(klass); 668 669 dc->desc = "XIVE Interrupt Thread Context"; 670 dc->realize = xive_tctx_realize; 671 dc->unrealize = xive_tctx_unrealize; 672 dc->vmsd = &vmstate_xive_tctx; 673 /* 674 * Reason: part of XIVE interrupt controller, needs to be wired up 675 * by xive_tctx_create(). 676 */ 677 dc->user_creatable = false; 678 } 679 680 static const TypeInfo xive_tctx_info = { 681 .name = TYPE_XIVE_TCTX, 682 .parent = TYPE_DEVICE, 683 .instance_size = sizeof(XiveTCTX), 684 .class_init = xive_tctx_class_init, 685 }; 686 687 Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) 688 { 689 Error *local_err = NULL; 690 Object *obj; 691 692 obj = object_new(TYPE_XIVE_TCTX); 693 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); 694 object_unref(obj); 695 object_property_add_const_link(obj, "cpu", cpu, &error_abort); 696 object_property_set_bool(obj, true, "realized", &local_err); 697 if (local_err) { 698 goto error; 699 } 700 701 return obj; 702 703 error: 704 object_unparent(obj); 705 error_propagate(errp, local_err); 706 return NULL; 707 } 708 709 /* 710 * XIVE ESB helpers 711 */ 712 713 static uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 714 { 715 uint8_t old_pq = *pq & 0x3; 716 717 *pq &= ~0x3; 718 *pq |= value & 0x3; 719 720 return old_pq; 721 } 722 723 static bool xive_esb_trigger(uint8_t *pq) 724 { 725 uint8_t old_pq = *pq & 0x3; 726 727 switch (old_pq) { 728 case XIVE_ESB_RESET: 729 xive_esb_set(pq, XIVE_ESB_PENDING); 730 return true; 731 case XIVE_ESB_PENDING: 732 case XIVE_ESB_QUEUED: 733 xive_esb_set(pq, XIVE_ESB_QUEUED); 734 return false; 735 case XIVE_ESB_OFF: 736 xive_esb_set(pq, XIVE_ESB_OFF); 737 return false; 738 default: 739 g_assert_not_reached(); 740 } 741 } 742 743 static bool xive_esb_eoi(uint8_t *pq) 744 { 745 uint8_t old_pq = *pq & 0x3; 746 747 switch (old_pq) { 748 case XIVE_ESB_RESET: 749 case XIVE_ESB_PENDING: 750 xive_esb_set(pq, XIVE_ESB_RESET); 751 return false; 752 case XIVE_ESB_QUEUED: 753 xive_esb_set(pq, XIVE_ESB_PENDING); 754 return true; 755 case XIVE_ESB_OFF: 756 xive_esb_set(pq, XIVE_ESB_OFF); 757 return false; 758 default: 759 g_assert_not_reached(); 760 } 761 } 762 763 /* 764 * XIVE Interrupt Source (or IVSE) 765 */ 766 767 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 768 { 769 assert(srcno < xsrc->nr_irqs); 770 771 return xsrc->status[srcno] & 0x3; 772 } 773 774 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 775 { 776 assert(srcno < xsrc->nr_irqs); 777 778 return xive_esb_set(&xsrc->status[srcno], pq); 779 } 780 781 /* 782 * Returns whether the event notification should be forwarded. 783 */ 784 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 785 { 786 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 787 788 xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; 789 790 switch (old_pq) { 791 case XIVE_ESB_RESET: 792 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 793 return true; 794 default: 795 return false; 796 } 797 } 798 799 /* 800 * Returns whether the event notification should be forwarded. 801 */ 802 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 803 { 804 bool ret; 805 806 assert(srcno < xsrc->nr_irqs); 807 808 ret = xive_esb_trigger(&xsrc->status[srcno]); 809 810 if (xive_source_irq_is_lsi(xsrc, srcno) && 811 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 812 qemu_log_mask(LOG_GUEST_ERROR, 813 "XIVE: queued an event on LSI IRQ %d\n", srcno); 814 } 815 816 return ret; 817 } 818 819 /* 820 * Returns whether the event notification should be forwarded. 821 */ 822 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 823 { 824 bool ret; 825 826 assert(srcno < xsrc->nr_irqs); 827 828 ret = xive_esb_eoi(&xsrc->status[srcno]); 829 830 /* 831 * LSI sources do not set the Q bit but they can still be 832 * asserted, in which case we should forward a new event 833 * notification 834 */ 835 if (xive_source_irq_is_lsi(xsrc, srcno) && 836 xsrc->status[srcno] & XIVE_STATUS_ASSERTED) { 837 ret = xive_source_lsi_trigger(xsrc, srcno); 838 } 839 840 return ret; 841 } 842 843 /* 844 * Forward the source event notification to the Router 845 */ 846 static void xive_source_notify(XiveSource *xsrc, int srcno) 847 { 848 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 849 850 if (xnc->notify) { 851 xnc->notify(xsrc->xive, srcno); 852 } 853 } 854 855 /* 856 * In a two pages ESB MMIO setting, even page is the trigger page, odd 857 * page is for management 858 */ 859 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 860 { 861 return !((addr >> shift) & 1); 862 } 863 864 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 865 { 866 return xive_source_esb_has_2page(xsrc) && 867 addr_is_even(addr, xsrc->esb_shift - 1); 868 } 869 870 /* 871 * ESB MMIO loads 872 * Trigger page Management/EOI page 873 * 874 * ESB MMIO setting 2 pages 1 or 2 pages 875 * 876 * 0x000 .. 0x3FF -1 EOI and return 0|1 877 * 0x400 .. 0x7FF -1 EOI and return 0|1 878 * 0x800 .. 0xBFF -1 return PQ 879 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 880 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 881 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 882 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 883 */ 884 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 885 { 886 XiveSource *xsrc = XIVE_SOURCE(opaque); 887 uint32_t offset = addr & 0xFFF; 888 uint32_t srcno = addr >> xsrc->esb_shift; 889 uint64_t ret = -1; 890 891 /* In a two pages ESB MMIO setting, trigger page should not be read */ 892 if (xive_source_is_trigger_page(xsrc, addr)) { 893 qemu_log_mask(LOG_GUEST_ERROR, 894 "XIVE: invalid load on IRQ %d trigger page at " 895 "0x%"HWADDR_PRIx"\n", srcno, addr); 896 return -1; 897 } 898 899 switch (offset) { 900 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 901 ret = xive_source_esb_eoi(xsrc, srcno); 902 903 /* Forward the source event notification for routing */ 904 if (ret) { 905 xive_source_notify(xsrc, srcno); 906 } 907 break; 908 909 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 910 ret = xive_source_esb_get(xsrc, srcno); 911 break; 912 913 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 914 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 915 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 916 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 917 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 918 break; 919 default: 920 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 921 offset); 922 } 923 924 return ret; 925 } 926 927 /* 928 * ESB MMIO stores 929 * Trigger page Management/EOI page 930 * 931 * ESB MMIO setting 2 pages 1 or 2 pages 932 * 933 * 0x000 .. 0x3FF Trigger Trigger 934 * 0x400 .. 0x7FF Trigger EOI 935 * 0x800 .. 0xBFF Trigger undefined 936 * 0xC00 .. 0xCFF Trigger PQ=00 937 * 0xD00 .. 0xDFF Trigger PQ=01 938 * 0xE00 .. 0xDFF Trigger PQ=10 939 * 0xF00 .. 0xDFF Trigger PQ=11 940 */ 941 static void xive_source_esb_write(void *opaque, hwaddr addr, 942 uint64_t value, unsigned size) 943 { 944 XiveSource *xsrc = XIVE_SOURCE(opaque); 945 uint32_t offset = addr & 0xFFF; 946 uint32_t srcno = addr >> xsrc->esb_shift; 947 bool notify = false; 948 949 /* In a two pages ESB MMIO setting, trigger page only triggers */ 950 if (xive_source_is_trigger_page(xsrc, addr)) { 951 notify = xive_source_esb_trigger(xsrc, srcno); 952 goto out; 953 } 954 955 switch (offset) { 956 case 0 ... 0x3FF: 957 notify = xive_source_esb_trigger(xsrc, srcno); 958 break; 959 960 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 961 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 962 qemu_log_mask(LOG_GUEST_ERROR, 963 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 964 return; 965 } 966 967 notify = xive_source_esb_eoi(xsrc, srcno); 968 break; 969 970 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 971 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 972 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 973 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 974 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 975 break; 976 977 default: 978 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 979 offset); 980 return; 981 } 982 983 out: 984 /* Forward the source event notification for routing */ 985 if (notify) { 986 xive_source_notify(xsrc, srcno); 987 } 988 } 989 990 static const MemoryRegionOps xive_source_esb_ops = { 991 .read = xive_source_esb_read, 992 .write = xive_source_esb_write, 993 .endianness = DEVICE_BIG_ENDIAN, 994 .valid = { 995 .min_access_size = 8, 996 .max_access_size = 8, 997 }, 998 .impl = { 999 .min_access_size = 8, 1000 .max_access_size = 8, 1001 }, 1002 }; 1003 1004 void xive_source_set_irq(void *opaque, int srcno, int val) 1005 { 1006 XiveSource *xsrc = XIVE_SOURCE(opaque); 1007 bool notify = false; 1008 1009 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1010 if (val) { 1011 notify = xive_source_lsi_trigger(xsrc, srcno); 1012 } else { 1013 xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; 1014 } 1015 } else { 1016 if (val) { 1017 notify = xive_source_esb_trigger(xsrc, srcno); 1018 } 1019 } 1020 1021 /* Forward the source event notification for routing */ 1022 if (notify) { 1023 xive_source_notify(xsrc, srcno); 1024 } 1025 } 1026 1027 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 1028 { 1029 int i; 1030 1031 for (i = 0; i < xsrc->nr_irqs; i++) { 1032 uint8_t pq = xive_source_esb_get(xsrc, i); 1033 1034 if (pq == XIVE_ESB_OFF) { 1035 continue; 1036 } 1037 1038 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 1039 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1040 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1041 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1042 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' '); 1043 } 1044 } 1045 1046 static void xive_source_reset(void *dev) 1047 { 1048 XiveSource *xsrc = XIVE_SOURCE(dev); 1049 1050 /* Do not clear the LSI bitmap */ 1051 1052 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 1053 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 1054 } 1055 1056 static void xive_source_realize(DeviceState *dev, Error **errp) 1057 { 1058 XiveSource *xsrc = XIVE_SOURCE(dev); 1059 Object *obj; 1060 Error *local_err = NULL; 1061 1062 obj = object_property_get_link(OBJECT(dev), "xive", &local_err); 1063 if (!obj) { 1064 error_propagate(errp, local_err); 1065 error_prepend(errp, "required link 'xive' not found: "); 1066 return; 1067 } 1068 1069 xsrc->xive = XIVE_NOTIFIER(obj); 1070 1071 if (!xsrc->nr_irqs) { 1072 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1073 return; 1074 } 1075 1076 if (xsrc->esb_shift != XIVE_ESB_4K && 1077 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1078 xsrc->esb_shift != XIVE_ESB_64K && 1079 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1080 error_setg(errp, "Invalid ESB shift setting"); 1081 return; 1082 } 1083 1084 xsrc->status = g_malloc0(xsrc->nr_irqs); 1085 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1086 1087 if (!kvm_irqchip_in_kernel()) { 1088 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1089 &xive_source_esb_ops, xsrc, "xive.esb", 1090 (1ull << xsrc->esb_shift) * xsrc->nr_irqs); 1091 } 1092 1093 qemu_register_reset(xive_source_reset, dev); 1094 } 1095 1096 static const VMStateDescription vmstate_xive_source = { 1097 .name = TYPE_XIVE_SOURCE, 1098 .version_id = 1, 1099 .minimum_version_id = 1, 1100 .fields = (VMStateField[]) { 1101 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1102 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1103 VMSTATE_END_OF_LIST() 1104 }, 1105 }; 1106 1107 /* 1108 * The default XIVE interrupt source setting for the ESB MMIOs is two 1109 * 64k pages without Store EOI, to be in sync with KVM. 1110 */ 1111 static Property xive_source_properties[] = { 1112 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1113 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1114 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1115 DEFINE_PROP_END_OF_LIST(), 1116 }; 1117 1118 static void xive_source_class_init(ObjectClass *klass, void *data) 1119 { 1120 DeviceClass *dc = DEVICE_CLASS(klass); 1121 1122 dc->desc = "XIVE Interrupt Source"; 1123 dc->props = xive_source_properties; 1124 dc->realize = xive_source_realize; 1125 dc->vmsd = &vmstate_xive_source; 1126 /* 1127 * Reason: part of XIVE interrupt controller, needs to be wired up, 1128 * e.g. by spapr_xive_instance_init(). 1129 */ 1130 dc->user_creatable = false; 1131 } 1132 1133 static const TypeInfo xive_source_info = { 1134 .name = TYPE_XIVE_SOURCE, 1135 .parent = TYPE_DEVICE, 1136 .instance_size = sizeof(XiveSource), 1137 .class_init = xive_source_class_init, 1138 }; 1139 1140 /* 1141 * XiveEND helpers 1142 */ 1143 1144 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1145 { 1146 uint64_t qaddr_base = xive_end_qaddr(end); 1147 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1148 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1149 uint32_t qentries = 1 << (qsize + 10); 1150 int i; 1151 1152 /* 1153 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1154 */ 1155 monitor_printf(mon, " [ "); 1156 qindex = (qindex - (width - 1)) & (qentries - 1); 1157 for (i = 0; i < width; i++) { 1158 uint64_t qaddr = qaddr_base + (qindex << 2); 1159 uint32_t qdata = -1; 1160 1161 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 1162 sizeof(qdata))) { 1163 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1164 HWADDR_PRIx "\n", qaddr); 1165 return; 1166 } 1167 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1168 be32_to_cpu(qdata)); 1169 qindex = (qindex + 1) & (qentries - 1); 1170 } 1171 monitor_printf(mon, "]"); 1172 } 1173 1174 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1175 { 1176 uint64_t qaddr_base = xive_end_qaddr(end); 1177 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1178 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1179 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1180 uint32_t qentries = 1 << (qsize + 10); 1181 1182 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1183 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1184 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1185 uint8_t pq; 1186 1187 if (!xive_end_is_valid(end)) { 1188 return; 1189 } 1190 1191 pq = xive_get_field32(END_W1_ESn, end->w1); 1192 1193 monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1194 end_idx, 1195 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1196 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1197 xive_end_is_valid(end) ? 'v' : '-', 1198 xive_end_is_enqueue(end) ? 'q' : '-', 1199 xive_end_is_notify(end) ? 'n' : '-', 1200 xive_end_is_backlog(end) ? 'b' : '-', 1201 xive_end_is_escalate(end) ? 'e' : '-', 1202 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1203 xive_end_is_silent_escalation(end) ? 's' : '-', 1204 priority, nvt_blk, nvt_idx); 1205 1206 if (qaddr_base) { 1207 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1208 qaddr_base, qindex, qentries, qgen); 1209 xive_end_queue_pic_print_info(end, 6, mon); 1210 } 1211 monitor_printf(mon, "\n"); 1212 } 1213 1214 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1215 { 1216 uint64_t qaddr_base = xive_end_qaddr(end); 1217 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1218 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1219 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1220 1221 uint64_t qaddr = qaddr_base + (qindex << 2); 1222 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1223 uint32_t qentries = 1 << (qsize + 10); 1224 1225 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) { 1226 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1227 HWADDR_PRIx "\n", qaddr); 1228 return; 1229 } 1230 1231 qindex = (qindex + 1) & (qentries - 1); 1232 if (qindex == 0) { 1233 qgen ^= 1; 1234 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1235 } 1236 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1237 } 1238 1239 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, 1240 Monitor *mon) 1241 { 1242 XiveEAS *eas = (XiveEAS *) &end->w4; 1243 uint8_t pq; 1244 1245 if (!xive_end_is_escalate(end)) { 1246 return; 1247 } 1248 1249 pq = xive_get_field32(END_W1_ESe, end->w1); 1250 1251 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1252 end_idx, 1253 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1254 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1255 xive_eas_is_valid(eas) ? 'V' : ' ', 1256 xive_eas_is_masked(eas) ? 'M' : ' ', 1257 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1258 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1259 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1260 } 1261 1262 /* 1263 * XIVE Router (aka. Virtualization Controller or IVRE) 1264 */ 1265 1266 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1267 XiveEAS *eas) 1268 { 1269 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1270 1271 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1272 } 1273 1274 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1275 XiveEND *end) 1276 { 1277 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1278 1279 return xrc->get_end(xrtr, end_blk, end_idx, end); 1280 } 1281 1282 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1283 XiveEND *end, uint8_t word_number) 1284 { 1285 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1286 1287 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1288 } 1289 1290 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1291 XiveNVT *nvt) 1292 { 1293 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1294 1295 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1296 } 1297 1298 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1299 XiveNVT *nvt, uint8_t word_number) 1300 { 1301 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1302 1303 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1304 } 1305 1306 XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) 1307 { 1308 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1309 1310 return xrc->get_tctx(xrtr, cs); 1311 } 1312 1313 /* 1314 * Encode the HW CAM line in the block group mode format : 1315 * 1316 * chip << 19 | 0000000 0 0001 thread (7Bit) 1317 */ 1318 static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) 1319 { 1320 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1321 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1322 1323 return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f)); 1324 } 1325 1326 /* 1327 * The thread context register words are in big-endian format. 1328 */ 1329 static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format, 1330 uint8_t nvt_blk, uint32_t nvt_idx, 1331 bool cam_ignore, uint32_t logic_serv) 1332 { 1333 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1334 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1335 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1336 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1337 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1338 1339 /* 1340 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1341 * identifier are ignored in the "CAM" match. 1342 */ 1343 1344 if (format == 0) { 1345 if (cam_ignore == true) { 1346 /* 1347 * F=0 & i=1: Logical server notification (bits ignored at 1348 * the end of the NVT identifier) 1349 */ 1350 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1351 nvt_blk, nvt_idx); 1352 return -1; 1353 } 1354 1355 /* F=0 & i=0: Specific NVT notification */ 1356 1357 /* PHYS ring */ 1358 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1359 cam == xive_tctx_hw_cam_line(tctx)) { 1360 return TM_QW3_HV_PHYS; 1361 } 1362 1363 /* HV POOL ring */ 1364 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1365 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1366 return TM_QW2_HV_POOL; 1367 } 1368 1369 /* OS ring */ 1370 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1371 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1372 return TM_QW1_OS; 1373 } 1374 } else { 1375 /* F=1 : User level Event-Based Branch (EBB) notification */ 1376 1377 /* USER ring */ 1378 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1379 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1380 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1381 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1382 return TM_QW0_USER; 1383 } 1384 } 1385 return -1; 1386 } 1387 1388 typedef struct XiveTCTXMatch { 1389 XiveTCTX *tctx; 1390 uint8_t ring; 1391 } XiveTCTXMatch; 1392 1393 static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, 1394 uint8_t nvt_blk, uint32_t nvt_idx, 1395 bool cam_ignore, uint8_t priority, 1396 uint32_t logic_serv, XiveTCTXMatch *match) 1397 { 1398 CPUState *cs; 1399 1400 /* 1401 * TODO (PowerNV): handle chip_id overwrite of block field for 1402 * hardwired CAM compares 1403 */ 1404 1405 CPU_FOREACH(cs) { 1406 XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs); 1407 int ring; 1408 1409 /* 1410 * Skip partially initialized vCPUs. This can happen when 1411 * vCPUs are hotplugged. 1412 */ 1413 if (!tctx) { 1414 continue; 1415 } 1416 1417 /* 1418 * HW checks that the CPU is enabled in the Physical Thread 1419 * Enable Register (PTER). 1420 */ 1421 1422 /* 1423 * Check the thread context CAM lines and record matches. We 1424 * will handle CPU exception delivery later 1425 */ 1426 ring = xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx, 1427 cam_ignore, logic_serv); 1428 /* 1429 * Save the context and follow on to catch duplicates, that we 1430 * don't support yet. 1431 */ 1432 if (ring != -1) { 1433 if (match->tctx) { 1434 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread " 1435 "context NVT %x/%x\n", nvt_blk, nvt_idx); 1436 return false; 1437 } 1438 1439 match->ring = ring; 1440 match->tctx = tctx; 1441 } 1442 } 1443 1444 if (!match->tctx) { 1445 qemu_log_mask(LOG_UNIMP, "XIVE: NVT %x/%x is not dispatched\n", 1446 nvt_blk, nvt_idx); 1447 return false; 1448 } 1449 1450 return true; 1451 } 1452 1453 /* 1454 * This is our simple Xive Presenter Engine model. It is merged in the 1455 * Router as it does not require an extra object. 1456 * 1457 * It receives notification requests sent by the IVRE to find one 1458 * matching NVT (or more) dispatched on the processor threads. In case 1459 * of a single NVT notification, the process is abreviated and the 1460 * thread is signaled if a match is found. In case of a logical server 1461 * notification (bits ignored at the end of the NVT identifier), the 1462 * IVPE and IVRE select a winning thread using different filters. This 1463 * involves 2 or 3 exchanges on the PowerBus that the model does not 1464 * support. 1465 * 1466 * The parameters represent what is sent on the PowerBus 1467 */ 1468 static bool xive_presenter_notify(XiveRouter *xrtr, uint8_t format, 1469 uint8_t nvt_blk, uint32_t nvt_idx, 1470 bool cam_ignore, uint8_t priority, 1471 uint32_t logic_serv) 1472 { 1473 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1474 bool found; 1475 1476 found = xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ignore, 1477 priority, logic_serv, &match); 1478 if (found) { 1479 ipb_update(&match.tctx->regs[match.ring], priority); 1480 xive_tctx_notify(match.tctx, match.ring); 1481 } 1482 1483 return found; 1484 } 1485 1486 /* 1487 * Notification using the END ESe/ESn bit (Event State Buffer for 1488 * escalation and notification). Profide futher coalescing in the 1489 * Router. 1490 */ 1491 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1492 uint32_t end_idx, XiveEND *end, 1493 uint32_t end_esmask) 1494 { 1495 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1496 bool notify = xive_esb_trigger(&pq); 1497 1498 if (pq != xive_get_field32(end_esmask, end->w1)) { 1499 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1500 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1501 } 1502 1503 /* ESe/n[Q]=1 : end of notification */ 1504 return notify; 1505 } 1506 1507 /* 1508 * An END trigger can come from an event trigger (IPI or HW) or from 1509 * another chip. We don't model the PowerBus but the END trigger 1510 * message has the same parameters than in the function below. 1511 */ 1512 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1513 uint32_t end_idx, uint32_t end_data) 1514 { 1515 XiveEND end; 1516 uint8_t priority; 1517 uint8_t format; 1518 uint8_t nvt_blk; 1519 uint32_t nvt_idx; 1520 XiveNVT nvt; 1521 bool found; 1522 1523 /* END cache lookup */ 1524 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1525 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1526 end_idx); 1527 return; 1528 } 1529 1530 if (!xive_end_is_valid(&end)) { 1531 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1532 end_blk, end_idx); 1533 return; 1534 } 1535 1536 if (xive_end_is_enqueue(&end)) { 1537 xive_end_enqueue(&end, end_data); 1538 /* Enqueuing event data modifies the EQ toggle and index */ 1539 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1540 } 1541 1542 /* 1543 * When the END is silent, we skip the notification part. 1544 */ 1545 if (xive_end_is_silent_escalation(&end)) { 1546 goto do_escalation; 1547 } 1548 1549 /* 1550 * The W7 format depends on the F bit in W6. It defines the type 1551 * of the notification : 1552 * 1553 * F=0 : single or multiple NVT notification 1554 * F=1 : User level Event-Based Branch (EBB) notification, no 1555 * priority 1556 */ 1557 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1558 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1559 1560 /* The END is masked */ 1561 if (format == 0 && priority == 0xff) { 1562 return; 1563 } 1564 1565 /* 1566 * Check the END ESn (Event State Buffer for notification) for 1567 * even futher coalescing in the Router 1568 */ 1569 if (!xive_end_is_notify(&end)) { 1570 /* ESn[Q]=1 : end of notification */ 1571 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1572 &end, END_W1_ESn)) { 1573 return; 1574 } 1575 } 1576 1577 /* 1578 * Follows IVPE notification 1579 */ 1580 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1581 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1582 1583 /* NVT cache lookup */ 1584 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1585 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1586 nvt_blk, nvt_idx); 1587 return; 1588 } 1589 1590 if (!xive_nvt_is_valid(&nvt)) { 1591 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1592 nvt_blk, nvt_idx); 1593 return; 1594 } 1595 1596 found = xive_presenter_notify(xrtr, format, nvt_blk, nvt_idx, 1597 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1598 priority, 1599 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1600 1601 /* TODO: Auto EOI. */ 1602 1603 if (found) { 1604 return; 1605 } 1606 1607 /* 1608 * If no matching NVT is dispatched on a HW thread : 1609 * - specific VP: update the NVT structure if backlog is activated 1610 * - logical server : forward request to IVPE (not supported) 1611 */ 1612 if (xive_end_is_backlog(&end)) { 1613 if (format == 1) { 1614 qemu_log_mask(LOG_GUEST_ERROR, 1615 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1616 end_blk, end_idx); 1617 return; 1618 } 1619 /* Record the IPB in the associated NVT structure */ 1620 ipb_update((uint8_t *) &nvt.w4, priority); 1621 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1622 1623 /* 1624 * On HW, follows a "Broadcast Backlog" to IVPEs 1625 */ 1626 } 1627 1628 do_escalation: 1629 /* 1630 * If activated, escalate notification using the ESe PQ bits and 1631 * the EAS in w4-5 1632 */ 1633 if (!xive_end_is_escalate(&end)) { 1634 return; 1635 } 1636 1637 /* 1638 * Check the END ESe (Event State Buffer for escalation) for even 1639 * futher coalescing in the Router 1640 */ 1641 if (!xive_end_is_uncond_escalation(&end)) { 1642 /* ESe[Q]=1 : end of notification */ 1643 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1644 &end, END_W1_ESe)) { 1645 return; 1646 } 1647 } 1648 1649 /* 1650 * The END trigger becomes an Escalation trigger 1651 */ 1652 xive_router_end_notify(xrtr, 1653 xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1654 xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1655 xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1656 } 1657 1658 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 1659 { 1660 XiveRouter *xrtr = XIVE_ROUTER(xn); 1661 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1662 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1663 XiveEAS eas; 1664 1665 /* EAS cache lookup */ 1666 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1667 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1668 return; 1669 } 1670 1671 /* 1672 * The IVRE checks the State Bit Cache at this point. We skip the 1673 * SBC lookup because the state bits of the sources are modeled 1674 * internally in QEMU. 1675 */ 1676 1677 if (!xive_eas_is_valid(&eas)) { 1678 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1679 return; 1680 } 1681 1682 if (xive_eas_is_masked(&eas)) { 1683 /* Notification completed */ 1684 return; 1685 } 1686 1687 /* 1688 * The event trigger becomes an END trigger 1689 */ 1690 xive_router_end_notify(xrtr, 1691 xive_get_field64(EAS_END_BLOCK, eas.w), 1692 xive_get_field64(EAS_END_INDEX, eas.w), 1693 xive_get_field64(EAS_END_DATA, eas.w)); 1694 } 1695 1696 static void xive_router_class_init(ObjectClass *klass, void *data) 1697 { 1698 DeviceClass *dc = DEVICE_CLASS(klass); 1699 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1700 1701 dc->desc = "XIVE Router Engine"; 1702 xnc->notify = xive_router_notify; 1703 } 1704 1705 static const TypeInfo xive_router_info = { 1706 .name = TYPE_XIVE_ROUTER, 1707 .parent = TYPE_SYS_BUS_DEVICE, 1708 .abstract = true, 1709 .class_size = sizeof(XiveRouterClass), 1710 .class_init = xive_router_class_init, 1711 .interfaces = (InterfaceInfo[]) { 1712 { TYPE_XIVE_NOTIFIER }, 1713 { } 1714 } 1715 }; 1716 1717 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1718 { 1719 if (!xive_eas_is_valid(eas)) { 1720 return; 1721 } 1722 1723 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1724 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1725 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1726 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1727 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1728 } 1729 1730 /* 1731 * END ESB MMIO loads 1732 */ 1733 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1734 { 1735 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1736 uint32_t offset = addr & 0xFFF; 1737 uint8_t end_blk; 1738 uint32_t end_idx; 1739 XiveEND end; 1740 uint32_t end_esmask; 1741 uint8_t pq; 1742 uint64_t ret = -1; 1743 1744 end_blk = xsrc->block_id; 1745 end_idx = addr >> (xsrc->esb_shift + 1); 1746 1747 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1748 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1749 end_idx); 1750 return -1; 1751 } 1752 1753 if (!xive_end_is_valid(&end)) { 1754 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1755 end_blk, end_idx); 1756 return -1; 1757 } 1758 1759 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1760 pq = xive_get_field32(end_esmask, end.w1); 1761 1762 switch (offset) { 1763 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1764 ret = xive_esb_eoi(&pq); 1765 1766 /* Forward the source event notification for routing ?? */ 1767 break; 1768 1769 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1770 ret = pq; 1771 break; 1772 1773 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1774 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1775 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1776 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1777 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1778 break; 1779 default: 1780 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1781 offset); 1782 return -1; 1783 } 1784 1785 if (pq != xive_get_field32(end_esmask, end.w1)) { 1786 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1787 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1788 } 1789 1790 return ret; 1791 } 1792 1793 /* 1794 * END ESB MMIO stores are invalid 1795 */ 1796 static void xive_end_source_write(void *opaque, hwaddr addr, 1797 uint64_t value, unsigned size) 1798 { 1799 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1800 HWADDR_PRIx"\n", addr); 1801 } 1802 1803 static const MemoryRegionOps xive_end_source_ops = { 1804 .read = xive_end_source_read, 1805 .write = xive_end_source_write, 1806 .endianness = DEVICE_BIG_ENDIAN, 1807 .valid = { 1808 .min_access_size = 8, 1809 .max_access_size = 8, 1810 }, 1811 .impl = { 1812 .min_access_size = 8, 1813 .max_access_size = 8, 1814 }, 1815 }; 1816 1817 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1818 { 1819 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1820 Object *obj; 1821 Error *local_err = NULL; 1822 1823 obj = object_property_get_link(OBJECT(dev), "xive", &local_err); 1824 if (!obj) { 1825 error_propagate(errp, local_err); 1826 error_prepend(errp, "required link 'xive' not found: "); 1827 return; 1828 } 1829 1830 xsrc->xrtr = XIVE_ROUTER(obj); 1831 1832 if (!xsrc->nr_ends) { 1833 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1834 return; 1835 } 1836 1837 if (xsrc->esb_shift != XIVE_ESB_4K && 1838 xsrc->esb_shift != XIVE_ESB_64K) { 1839 error_setg(errp, "Invalid ESB shift setting"); 1840 return; 1841 } 1842 1843 /* 1844 * Each END is assigned an even/odd pair of MMIO pages, the even page 1845 * manages the ESn field while the odd page manages the ESe field. 1846 */ 1847 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1848 &xive_end_source_ops, xsrc, "xive.end", 1849 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1850 } 1851 1852 static Property xive_end_source_properties[] = { 1853 DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0), 1854 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1855 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1856 DEFINE_PROP_END_OF_LIST(), 1857 }; 1858 1859 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1860 { 1861 DeviceClass *dc = DEVICE_CLASS(klass); 1862 1863 dc->desc = "XIVE END Source"; 1864 dc->props = xive_end_source_properties; 1865 dc->realize = xive_end_source_realize; 1866 /* 1867 * Reason: part of XIVE interrupt controller, needs to be wired up, 1868 * e.g. by spapr_xive_instance_init(). 1869 */ 1870 dc->user_creatable = false; 1871 } 1872 1873 static const TypeInfo xive_end_source_info = { 1874 .name = TYPE_XIVE_END_SOURCE, 1875 .parent = TYPE_DEVICE, 1876 .instance_size = sizeof(XiveENDSource), 1877 .class_init = xive_end_source_class_init, 1878 }; 1879 1880 /* 1881 * XIVE Notifier 1882 */ 1883 static const TypeInfo xive_notifier_info = { 1884 .name = TYPE_XIVE_NOTIFIER, 1885 .parent = TYPE_INTERFACE, 1886 .class_size = sizeof(XiveNotifierClass), 1887 }; 1888 1889 static void xive_register_types(void) 1890 { 1891 type_register_static(&xive_source_info); 1892 type_register_static(&xive_notifier_info); 1893 type_register_static(&xive_router_info); 1894 type_register_static(&xive_end_source_info); 1895 type_register_static(&xive_tctx_info); 1896 } 1897 1898 type_init(xive_register_types) 1899