1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "monitor/monitor.h" 21 #include "hw/irq.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive_regs.h" 24 #include "trace.h" 25 26 /* 27 * XIVE Thread Interrupt Management context 28 */ 29 30 /* 31 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 32 * Interrupt Priority Register (PIPR), which contains the priority of 33 * the most favored pending notification. 34 */ 35 static uint8_t ipb_to_pipr(uint8_t ibp) 36 { 37 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 38 } 39 40 static uint8_t exception_mask(uint8_t ring) 41 { 42 switch (ring) { 43 case TM_QW1_OS: 44 return TM_QW1_NSR_EO; 45 case TM_QW3_HV_PHYS: 46 return TM_QW3_NSR_HE; 47 default: 48 g_assert_not_reached(); 49 } 50 } 51 52 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 53 { 54 switch (ring) { 55 case TM_QW0_USER: 56 return 0; /* Not supported */ 57 case TM_QW1_OS: 58 return tctx->os_output; 59 case TM_QW2_HV_POOL: 60 case TM_QW3_HV_PHYS: 61 return tctx->hv_output; 62 default: 63 return 0; 64 } 65 } 66 67 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 68 { 69 uint8_t *regs = &tctx->regs[ring]; 70 uint8_t nsr = regs[TM_NSR]; 71 uint8_t mask = exception_mask(ring); 72 73 qemu_irq_lower(xive_tctx_output(tctx, ring)); 74 75 if (regs[TM_NSR] & mask) { 76 uint8_t cppr = regs[TM_PIPR]; 77 78 regs[TM_CPPR] = cppr; 79 80 /* Reset the pending buffer bit */ 81 regs[TM_IPB] &= ~xive_priority_to_ipb(cppr); 82 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 83 84 /* Drop Exception bit */ 85 regs[TM_NSR] &= ~mask; 86 87 trace_xive_tctx_accept(tctx->cs->cpu_index, ring, 88 regs[TM_IPB], regs[TM_PIPR], 89 regs[TM_CPPR], regs[TM_NSR]); 90 } 91 92 return (nsr << 8) | regs[TM_CPPR]; 93 } 94 95 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 96 { 97 uint8_t *regs = &tctx->regs[ring]; 98 99 if (regs[TM_PIPR] < regs[TM_CPPR]) { 100 switch (ring) { 101 case TM_QW1_OS: 102 regs[TM_NSR] |= TM_QW1_NSR_EO; 103 break; 104 case TM_QW3_HV_PHYS: 105 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 106 break; 107 default: 108 g_assert_not_reached(); 109 } 110 trace_xive_tctx_notify(tctx->cs->cpu_index, ring, 111 regs[TM_IPB], regs[TM_PIPR], 112 regs[TM_CPPR], regs[TM_NSR]); 113 qemu_irq_raise(xive_tctx_output(tctx, ring)); 114 } 115 } 116 117 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 118 { 119 uint8_t *regs = &tctx->regs[ring]; 120 121 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, 122 regs[TM_IPB], regs[TM_PIPR], 123 cppr, regs[TM_NSR]); 124 125 if (cppr > XIVE_PRIORITY_MAX) { 126 cppr = 0xff; 127 } 128 129 tctx->regs[ring + TM_CPPR] = cppr; 130 131 /* CPPR has changed, check if we need to raise a pending exception */ 132 xive_tctx_notify(tctx, ring); 133 } 134 135 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) 136 { 137 uint8_t *regs = &tctx->regs[ring]; 138 139 regs[TM_IPB] |= ipb; 140 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 141 xive_tctx_notify(tctx, ring); 142 } 143 144 /* 145 * XIVE Thread Interrupt Management Area (TIMA) 146 */ 147 148 static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 149 hwaddr offset, uint64_t value, unsigned size) 150 { 151 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 152 } 153 154 static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx, 155 hwaddr offset, unsigned size) 156 { 157 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 158 } 159 160 static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 161 hwaddr offset, unsigned size) 162 { 163 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 164 uint32_t qw2w2; 165 166 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 167 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 168 return qw2w2; 169 } 170 171 static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 172 uint64_t value, unsigned size) 173 { 174 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 175 } 176 177 static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, 178 hwaddr offset, unsigned size) 179 { 180 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 181 } 182 183 /* 184 * Define an access map for each page of the TIMA that we will use in 185 * the memory region ops to filter values when doing loads and stores 186 * of raw registers values 187 * 188 * Registers accessibility bits : 189 * 190 * 0x0 - no access 191 * 0x1 - write only 192 * 0x2 - read only 193 * 0x3 - read/write 194 */ 195 196 static const uint8_t xive_tm_hw_view[] = { 197 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 198 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 199 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 200 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 201 }; 202 203 static const uint8_t xive_tm_hv_view[] = { 204 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 205 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 206 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 207 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 208 }; 209 210 static const uint8_t xive_tm_os_view[] = { 211 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 212 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 213 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 214 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 215 }; 216 217 static const uint8_t xive_tm_user_view[] = { 218 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 219 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 222 }; 223 224 /* 225 * Overall TIMA access map for the thread interrupt management context 226 * registers 227 */ 228 static const uint8_t *xive_tm_views[] = { 229 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 230 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 231 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 232 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 233 }; 234 235 /* 236 * Computes a register access mask for a given offset in the TIMA 237 */ 238 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 239 { 240 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 241 uint8_t reg_offset = offset & 0x3F; 242 uint8_t reg_mask = write ? 0x1 : 0x2; 243 uint64_t mask = 0x0; 244 int i; 245 246 for (i = 0; i < size; i++) { 247 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 248 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 249 } 250 } 251 252 return mask; 253 } 254 255 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 256 unsigned size) 257 { 258 uint8_t ring_offset = offset & 0x30; 259 uint8_t reg_offset = offset & 0x3F; 260 uint64_t mask = xive_tm_mask(offset, size, true); 261 int i; 262 263 /* 264 * Only 4 or 8 bytes stores are allowed and the User ring is 265 * excluded 266 */ 267 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 268 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 269 HWADDR_PRIx"\n", offset); 270 return; 271 } 272 273 /* 274 * Use the register offset for the raw values and filter out 275 * reserved values 276 */ 277 for (i = 0; i < size; i++) { 278 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 279 if (byte_mask) { 280 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 281 byte_mask; 282 } 283 } 284 } 285 286 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 287 { 288 uint8_t ring_offset = offset & 0x30; 289 uint8_t reg_offset = offset & 0x3F; 290 uint64_t mask = xive_tm_mask(offset, size, false); 291 uint64_t ret; 292 int i; 293 294 /* 295 * Only 4 or 8 bytes loads are allowed and the User ring is 296 * excluded 297 */ 298 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 299 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 300 HWADDR_PRIx"\n", offset); 301 return -1; 302 } 303 304 /* Use the register offset for the raw values */ 305 ret = 0; 306 for (i = 0; i < size; i++) { 307 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 308 } 309 310 /* filter out reserved values */ 311 return ret & mask; 312 } 313 314 /* 315 * The TM context is mapped twice within each page. Stores and loads 316 * to the first mapping below 2K write and read the specified values 317 * without modification. The second mapping above 2K performs specific 318 * state changes (side effects) in addition to setting/returning the 319 * interrupt management area context of the processor thread. 320 */ 321 static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx, 322 hwaddr offset, unsigned size) 323 { 324 return xive_tctx_accept(tctx, TM_QW1_OS); 325 } 326 327 static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 328 hwaddr offset, uint64_t value, unsigned size) 329 { 330 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 331 } 332 333 /* 334 * Adjust the IPB to allow a CPU to process event queues of other 335 * priorities during one physical interrupt cycle. 336 */ 337 static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, 338 hwaddr offset, uint64_t value, unsigned size) 339 { 340 xive_tctx_ipb_update(tctx, TM_QW1_OS, xive_priority_to_ipb(value & 0xff)); 341 } 342 343 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, 344 uint32_t *nvt_idx, bool *vo) 345 { 346 if (nvt_blk) { 347 *nvt_blk = xive_nvt_blk(cam); 348 } 349 if (nvt_idx) { 350 *nvt_idx = xive_nvt_idx(cam); 351 } 352 if (vo) { 353 *vo = !!(cam & TM_QW1W2_VO); 354 } 355 } 356 357 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk, 358 uint32_t *nvt_idx, bool *vo) 359 { 360 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 361 uint32_t cam = be32_to_cpu(qw1w2); 362 363 xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo); 364 return qw1w2; 365 } 366 367 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) 368 { 369 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 370 } 371 372 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 373 hwaddr offset, unsigned size) 374 { 375 uint32_t qw1w2; 376 uint32_t qw1w2_new; 377 uint8_t nvt_blk; 378 uint32_t nvt_idx; 379 bool vo; 380 381 qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); 382 383 if (!vo) { 384 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n", 385 nvt_blk, nvt_idx); 386 } 387 388 /* Invalidate CAM line */ 389 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); 390 xive_tctx_set_os_cam(tctx, qw1w2_new); 391 return qw1w2; 392 } 393 394 static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx, 395 uint8_t nvt_blk, uint32_t nvt_idx) 396 { 397 XiveNVT nvt; 398 uint8_t ipb; 399 400 /* 401 * Grab the associated NVT to pull the pending bits, and merge 402 * them with the IPB of the thread interrupt context registers 403 */ 404 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 405 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n", 406 nvt_blk, nvt_idx); 407 return; 408 } 409 410 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4); 411 412 if (ipb) { 413 /* Reset the NVT value */ 414 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0); 415 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 416 } 417 /* 418 * Always call xive_tctx_ipb_update(). Even if there were no 419 * escalation triggered, there could be a pending interrupt which 420 * was saved when the context was pulled and that we need to take 421 * into account by recalculating the PIPR (which is not 422 * saved/restored). 423 */ 424 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); 425 } 426 427 /* 428 * Updating the OS CAM line can trigger a resend of interrupt 429 */ 430 static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 431 hwaddr offset, uint64_t value, unsigned size) 432 { 433 uint32_t cam = value; 434 uint32_t qw1w2 = cpu_to_be32(cam); 435 uint8_t nvt_blk; 436 uint32_t nvt_idx; 437 bool vo; 438 439 xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); 440 441 /* First update the registers */ 442 xive_tctx_set_os_cam(tctx, qw1w2); 443 444 /* Check the interrupt pending bits */ 445 if (vo) { 446 xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); 447 } 448 } 449 450 /* 451 * Define a mapping of "special" operations depending on the TIMA page 452 * offset and the size of the operation. 453 */ 454 typedef struct XiveTmOp { 455 uint8_t page_offset; 456 uint32_t op_offset; 457 unsigned size; 458 void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, 459 hwaddr offset, 460 uint64_t value, unsigned size); 461 uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 462 unsigned size); 463 } XiveTmOp; 464 465 static const XiveTmOp xive_tm_operations[] = { 466 /* 467 * MMIOs below 2K : raw values and special operations without side 468 * effects 469 */ 470 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 471 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, NULL }, 472 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 473 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 474 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 475 476 /* MMIOs above 2K : special operations with side effects */ 477 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 478 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 479 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, 480 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, 481 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 482 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 483 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 484 }; 485 486 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 487 { 488 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 489 uint32_t op_offset = offset & 0xFFF; 490 int i; 491 492 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 493 const XiveTmOp *xto = &xive_tm_operations[i]; 494 495 /* Accesses done from a more privileged TIMA page is allowed */ 496 if (xto->page_offset >= page_offset && 497 xto->op_offset == op_offset && 498 xto->size == size && 499 ((write && xto->write_handler) || (!write && xto->read_handler))) { 500 return xto; 501 } 502 } 503 return NULL; 504 } 505 506 /* 507 * TIMA MMIO handlers 508 */ 509 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 510 uint64_t value, unsigned size) 511 { 512 const XiveTmOp *xto; 513 514 trace_xive_tctx_tm_write(offset, size, value); 515 516 /* 517 * TODO: check V bit in Q[0-3]W2 518 */ 519 520 /* 521 * First, check for special operations in the 2K region 522 */ 523 if (offset & 0x800) { 524 xto = xive_tm_find_op(offset, size, true); 525 if (!xto) { 526 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 527 "@%"HWADDR_PRIx"\n", offset); 528 } else { 529 xto->write_handler(xptr, tctx, offset, value, size); 530 } 531 return; 532 } 533 534 /* 535 * Then, for special operations in the region below 2K. 536 */ 537 xto = xive_tm_find_op(offset, size, true); 538 if (xto) { 539 xto->write_handler(xptr, tctx, offset, value, size); 540 return; 541 } 542 543 /* 544 * Finish with raw access to the register values 545 */ 546 xive_tm_raw_write(tctx, offset, value, size); 547 } 548 549 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 550 unsigned size) 551 { 552 const XiveTmOp *xto; 553 uint64_t ret; 554 555 /* 556 * TODO: check V bit in Q[0-3]W2 557 */ 558 559 /* 560 * First, check for special operations in the 2K region 561 */ 562 if (offset & 0x800) { 563 xto = xive_tm_find_op(offset, size, false); 564 if (!xto) { 565 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 566 "@%"HWADDR_PRIx"\n", offset); 567 return -1; 568 } 569 ret = xto->read_handler(xptr, tctx, offset, size); 570 goto out; 571 } 572 573 /* 574 * Then, for special operations in the region below 2K. 575 */ 576 xto = xive_tm_find_op(offset, size, false); 577 if (xto) { 578 ret = xto->read_handler(xptr, tctx, offset, size); 579 goto out; 580 } 581 582 /* 583 * Finish with raw access to the register values 584 */ 585 ret = xive_tm_raw_read(tctx, offset, size); 586 out: 587 trace_xive_tctx_tm_read(offset, size, ret); 588 return ret; 589 } 590 591 static char *xive_tctx_ring_print(uint8_t *ring) 592 { 593 uint32_t w2 = xive_tctx_word2(ring); 594 595 return g_strdup_printf("%02x %02x %02x %02x %02x " 596 "%02x %02x %02x %08x", 597 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 598 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 599 be32_to_cpu(w2)); 600 } 601 602 static const char * const xive_tctx_ring_names[] = { 603 "USER", "OS", "POOL", "PHYS", 604 }; 605 606 /* 607 * kvm_irqchip_in_kernel() will cause the compiler to turn this 608 * info a nop if CONFIG_KVM isn't defined. 609 */ 610 #define xive_in_kernel(xptr) \ 611 (kvm_irqchip_in_kernel() && \ 612 ({ \ 613 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); \ 614 xpc->in_kernel ? xpc->in_kernel(xptr) : false; \ 615 })) 616 617 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 618 { 619 int cpu_index; 620 int i; 621 622 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs 623 * are hot plugged or unplugged. 624 */ 625 if (!tctx) { 626 return; 627 } 628 629 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 630 631 if (xive_in_kernel(tctx->xptr)) { 632 Error *local_err = NULL; 633 634 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 635 if (local_err) { 636 error_report_err(local_err); 637 return; 638 } 639 } 640 641 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 642 " W2\n", cpu_index); 643 644 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 645 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 646 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 647 xive_tctx_ring_names[i], s); 648 g_free(s); 649 } 650 } 651 652 void xive_tctx_reset(XiveTCTX *tctx) 653 { 654 memset(tctx->regs, 0, sizeof(tctx->regs)); 655 656 /* Set some defaults */ 657 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 658 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 659 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 660 661 /* 662 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 663 * CPPR is first set. 664 */ 665 tctx->regs[TM_QW1_OS + TM_PIPR] = 666 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 667 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 668 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 669 } 670 671 static void xive_tctx_realize(DeviceState *dev, Error **errp) 672 { 673 XiveTCTX *tctx = XIVE_TCTX(dev); 674 PowerPCCPU *cpu; 675 CPUPPCState *env; 676 677 assert(tctx->cs); 678 assert(tctx->xptr); 679 680 cpu = POWERPC_CPU(tctx->cs); 681 env = &cpu->env; 682 switch (PPC_INPUT(env)) { 683 case PPC_FLAGS_INPUT_POWER9: 684 tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT]; 685 tctx->os_output = env->irq_inputs[POWER9_INPUT_INT]; 686 break; 687 688 default: 689 error_setg(errp, "XIVE interrupt controller does not support " 690 "this CPU bus model"); 691 return; 692 } 693 694 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 695 if (xive_in_kernel(tctx->xptr)) { 696 if (kvmppc_xive_cpu_connect(tctx, errp) < 0) { 697 return; 698 } 699 } 700 } 701 702 static int vmstate_xive_tctx_pre_save(void *opaque) 703 { 704 XiveTCTX *tctx = XIVE_TCTX(opaque); 705 Error *local_err = NULL; 706 int ret; 707 708 if (xive_in_kernel(tctx->xptr)) { 709 ret = kvmppc_xive_cpu_get_state(tctx, &local_err); 710 if (ret < 0) { 711 error_report_err(local_err); 712 return ret; 713 } 714 } 715 716 return 0; 717 } 718 719 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 720 { 721 XiveTCTX *tctx = XIVE_TCTX(opaque); 722 Error *local_err = NULL; 723 int ret; 724 725 if (xive_in_kernel(tctx->xptr)) { 726 /* 727 * Required for hotplugged CPU, for which the state comes 728 * after all states of the machine. 729 */ 730 ret = kvmppc_xive_cpu_set_state(tctx, &local_err); 731 if (ret < 0) { 732 error_report_err(local_err); 733 return ret; 734 } 735 } 736 737 return 0; 738 } 739 740 static const VMStateDescription vmstate_xive_tctx = { 741 .name = TYPE_XIVE_TCTX, 742 .version_id = 1, 743 .minimum_version_id = 1, 744 .pre_save = vmstate_xive_tctx_pre_save, 745 .post_load = vmstate_xive_tctx_post_load, 746 .fields = (VMStateField[]) { 747 VMSTATE_BUFFER(regs, XiveTCTX), 748 VMSTATE_END_OF_LIST() 749 }, 750 }; 751 752 static Property xive_tctx_properties[] = { 753 DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), 754 DEFINE_PROP_LINK("presenter", XiveTCTX, xptr, TYPE_XIVE_PRESENTER, 755 XivePresenter *), 756 DEFINE_PROP_END_OF_LIST(), 757 }; 758 759 static void xive_tctx_class_init(ObjectClass *klass, void *data) 760 { 761 DeviceClass *dc = DEVICE_CLASS(klass); 762 763 dc->desc = "XIVE Interrupt Thread Context"; 764 dc->realize = xive_tctx_realize; 765 dc->vmsd = &vmstate_xive_tctx; 766 device_class_set_props(dc, xive_tctx_properties); 767 /* 768 * Reason: part of XIVE interrupt controller, needs to be wired up 769 * by xive_tctx_create(). 770 */ 771 dc->user_creatable = false; 772 } 773 774 static const TypeInfo xive_tctx_info = { 775 .name = TYPE_XIVE_TCTX, 776 .parent = TYPE_DEVICE, 777 .instance_size = sizeof(XiveTCTX), 778 .class_init = xive_tctx_class_init, 779 }; 780 781 Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp) 782 { 783 Object *obj; 784 785 obj = object_new(TYPE_XIVE_TCTX); 786 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj); 787 object_unref(obj); 788 object_property_set_link(obj, "cpu", cpu, &error_abort); 789 object_property_set_link(obj, "presenter", OBJECT(xptr), &error_abort); 790 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 791 object_unparent(obj); 792 return NULL; 793 } 794 return obj; 795 } 796 797 void xive_tctx_destroy(XiveTCTX *tctx) 798 { 799 Object *obj = OBJECT(tctx); 800 801 object_unparent(obj); 802 } 803 804 /* 805 * XIVE ESB helpers 806 */ 807 808 uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 809 { 810 uint8_t old_pq = *pq & 0x3; 811 812 *pq &= ~0x3; 813 *pq |= value & 0x3; 814 815 return old_pq; 816 } 817 818 bool xive_esb_trigger(uint8_t *pq) 819 { 820 uint8_t old_pq = *pq & 0x3; 821 822 switch (old_pq) { 823 case XIVE_ESB_RESET: 824 xive_esb_set(pq, XIVE_ESB_PENDING); 825 return true; 826 case XIVE_ESB_PENDING: 827 case XIVE_ESB_QUEUED: 828 xive_esb_set(pq, XIVE_ESB_QUEUED); 829 return false; 830 case XIVE_ESB_OFF: 831 xive_esb_set(pq, XIVE_ESB_OFF); 832 return false; 833 default: 834 g_assert_not_reached(); 835 } 836 } 837 838 bool xive_esb_eoi(uint8_t *pq) 839 { 840 uint8_t old_pq = *pq & 0x3; 841 842 switch (old_pq) { 843 case XIVE_ESB_RESET: 844 case XIVE_ESB_PENDING: 845 xive_esb_set(pq, XIVE_ESB_RESET); 846 return false; 847 case XIVE_ESB_QUEUED: 848 xive_esb_set(pq, XIVE_ESB_PENDING); 849 return true; 850 case XIVE_ESB_OFF: 851 xive_esb_set(pq, XIVE_ESB_OFF); 852 return false; 853 default: 854 g_assert_not_reached(); 855 } 856 } 857 858 /* 859 * XIVE Interrupt Source (or IVSE) 860 */ 861 862 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 863 { 864 assert(srcno < xsrc->nr_irqs); 865 866 return xsrc->status[srcno] & 0x3; 867 } 868 869 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 870 { 871 assert(srcno < xsrc->nr_irqs); 872 873 return xive_esb_set(&xsrc->status[srcno], pq); 874 } 875 876 /* 877 * Returns whether the event notification should be forwarded. 878 */ 879 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 880 { 881 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 882 883 xive_source_set_asserted(xsrc, srcno, true); 884 885 switch (old_pq) { 886 case XIVE_ESB_RESET: 887 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 888 return true; 889 default: 890 return false; 891 } 892 } 893 894 /* 895 * Sources can be configured with PQ offloading in which case the check 896 * on the PQ state bits of MSIs is disabled 897 */ 898 static bool xive_source_esb_disabled(XiveSource *xsrc, uint32_t srcno) 899 { 900 return (xsrc->esb_flags & XIVE_SRC_PQ_DISABLE) && 901 !xive_source_irq_is_lsi(xsrc, srcno); 902 } 903 904 /* 905 * Returns whether the event notification should be forwarded. 906 */ 907 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 908 { 909 bool ret; 910 911 assert(srcno < xsrc->nr_irqs); 912 913 if (xive_source_esb_disabled(xsrc, srcno)) { 914 return true; 915 } 916 917 ret = xive_esb_trigger(&xsrc->status[srcno]); 918 919 if (xive_source_irq_is_lsi(xsrc, srcno) && 920 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 921 qemu_log_mask(LOG_GUEST_ERROR, 922 "XIVE: queued an event on LSI IRQ %d\n", srcno); 923 } 924 925 return ret; 926 } 927 928 /* 929 * Returns whether the event notification should be forwarded. 930 */ 931 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 932 { 933 bool ret; 934 935 assert(srcno < xsrc->nr_irqs); 936 937 if (xive_source_esb_disabled(xsrc, srcno)) { 938 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EOI for IRQ %d\n", srcno); 939 return false; 940 } 941 942 ret = xive_esb_eoi(&xsrc->status[srcno]); 943 944 /* 945 * LSI sources do not set the Q bit but they can still be 946 * asserted, in which case we should forward a new event 947 * notification 948 */ 949 if (xive_source_irq_is_lsi(xsrc, srcno) && 950 xive_source_is_asserted(xsrc, srcno)) { 951 ret = xive_source_lsi_trigger(xsrc, srcno); 952 } 953 954 return ret; 955 } 956 957 /* 958 * Forward the source event notification to the Router 959 */ 960 static void xive_source_notify(XiveSource *xsrc, int srcno) 961 { 962 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 963 bool pq_checked = !xive_source_esb_disabled(xsrc, srcno); 964 965 if (xnc->notify) { 966 xnc->notify(xsrc->xive, srcno, pq_checked); 967 } 968 } 969 970 /* 971 * In a two pages ESB MMIO setting, even page is the trigger page, odd 972 * page is for management 973 */ 974 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 975 { 976 return !((addr >> shift) & 1); 977 } 978 979 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 980 { 981 return xive_source_esb_has_2page(xsrc) && 982 addr_is_even(addr, xsrc->esb_shift - 1); 983 } 984 985 /* 986 * ESB MMIO loads 987 * Trigger page Management/EOI page 988 * 989 * ESB MMIO setting 2 pages 1 or 2 pages 990 * 991 * 0x000 .. 0x3FF -1 EOI and return 0|1 992 * 0x400 .. 0x7FF -1 EOI and return 0|1 993 * 0x800 .. 0xBFF -1 return PQ 994 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 995 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 996 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 997 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 998 */ 999 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 1000 { 1001 XiveSource *xsrc = XIVE_SOURCE(opaque); 1002 uint32_t offset = addr & 0xFFF; 1003 uint32_t srcno = addr >> xsrc->esb_shift; 1004 uint64_t ret = -1; 1005 1006 /* In a two pages ESB MMIO setting, trigger page should not be read */ 1007 if (xive_source_is_trigger_page(xsrc, addr)) { 1008 qemu_log_mask(LOG_GUEST_ERROR, 1009 "XIVE: invalid load on IRQ %d trigger page at " 1010 "0x%"HWADDR_PRIx"\n", srcno, addr); 1011 return -1; 1012 } 1013 1014 switch (offset) { 1015 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1016 ret = xive_source_esb_eoi(xsrc, srcno); 1017 1018 /* Forward the source event notification for routing */ 1019 if (ret) { 1020 xive_source_notify(xsrc, srcno); 1021 } 1022 break; 1023 1024 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1025 ret = xive_source_esb_get(xsrc, srcno); 1026 break; 1027 1028 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1029 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1030 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1031 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1032 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1033 break; 1034 default: 1035 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 1036 offset); 1037 } 1038 1039 trace_xive_source_esb_read(addr, srcno, ret); 1040 1041 return ret; 1042 } 1043 1044 /* 1045 * ESB MMIO stores 1046 * Trigger page Management/EOI page 1047 * 1048 * ESB MMIO setting 2 pages 1 or 2 pages 1049 * 1050 * 0x000 .. 0x3FF Trigger Trigger 1051 * 0x400 .. 0x7FF Trigger EOI 1052 * 0x800 .. 0xBFF Trigger undefined 1053 * 0xC00 .. 0xCFF Trigger PQ=00 1054 * 0xD00 .. 0xDFF Trigger PQ=01 1055 * 0xE00 .. 0xDFF Trigger PQ=10 1056 * 0xF00 .. 0xDFF Trigger PQ=11 1057 */ 1058 static void xive_source_esb_write(void *opaque, hwaddr addr, 1059 uint64_t value, unsigned size) 1060 { 1061 XiveSource *xsrc = XIVE_SOURCE(opaque); 1062 uint32_t offset = addr & 0xFFF; 1063 uint32_t srcno = addr >> xsrc->esb_shift; 1064 bool notify = false; 1065 1066 trace_xive_source_esb_write(addr, srcno, value); 1067 1068 /* In a two pages ESB MMIO setting, trigger page only triggers */ 1069 if (xive_source_is_trigger_page(xsrc, addr)) { 1070 notify = xive_source_esb_trigger(xsrc, srcno); 1071 goto out; 1072 } 1073 1074 switch (offset) { 1075 case 0 ... 0x3FF: 1076 notify = xive_source_esb_trigger(xsrc, srcno); 1077 break; 1078 1079 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 1080 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 1081 qemu_log_mask(LOG_GUEST_ERROR, 1082 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 1083 return; 1084 } 1085 1086 notify = xive_source_esb_eoi(xsrc, srcno); 1087 break; 1088 1089 /* 1090 * This is an internal offset used to inject triggers when the PQ 1091 * state bits are not controlled locally. Such as for LSIs when 1092 * under ABT mode. 1093 */ 1094 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: 1095 notify = true; 1096 break; 1097 1098 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1099 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1100 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1101 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1102 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1103 break; 1104 1105 default: 1106 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 1107 offset); 1108 return; 1109 } 1110 1111 out: 1112 /* Forward the source event notification for routing */ 1113 if (notify) { 1114 xive_source_notify(xsrc, srcno); 1115 } 1116 } 1117 1118 static const MemoryRegionOps xive_source_esb_ops = { 1119 .read = xive_source_esb_read, 1120 .write = xive_source_esb_write, 1121 .endianness = DEVICE_BIG_ENDIAN, 1122 .valid = { 1123 .min_access_size = 8, 1124 .max_access_size = 8, 1125 }, 1126 .impl = { 1127 .min_access_size = 8, 1128 .max_access_size = 8, 1129 }, 1130 }; 1131 1132 void xive_source_set_irq(void *opaque, int srcno, int val) 1133 { 1134 XiveSource *xsrc = XIVE_SOURCE(opaque); 1135 bool notify = false; 1136 1137 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1138 if (val) { 1139 notify = xive_source_lsi_trigger(xsrc, srcno); 1140 } else { 1141 xive_source_set_asserted(xsrc, srcno, false); 1142 } 1143 } else { 1144 if (val) { 1145 notify = xive_source_esb_trigger(xsrc, srcno); 1146 } 1147 } 1148 1149 /* Forward the source event notification for routing */ 1150 if (notify) { 1151 xive_source_notify(xsrc, srcno); 1152 } 1153 } 1154 1155 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 1156 { 1157 int i; 1158 1159 for (i = 0; i < xsrc->nr_irqs; i++) { 1160 uint8_t pq = xive_source_esb_get(xsrc, i); 1161 1162 if (pq == XIVE_ESB_OFF) { 1163 continue; 1164 } 1165 1166 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 1167 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1168 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1169 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1170 xive_source_is_asserted(xsrc, i) ? 'A' : ' '); 1171 } 1172 } 1173 1174 static void xive_source_reset(void *dev) 1175 { 1176 XiveSource *xsrc = XIVE_SOURCE(dev); 1177 1178 /* Do not clear the LSI bitmap */ 1179 1180 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 1181 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 1182 } 1183 1184 static void xive_source_realize(DeviceState *dev, Error **errp) 1185 { 1186 XiveSource *xsrc = XIVE_SOURCE(dev); 1187 size_t esb_len = xive_source_esb_len(xsrc); 1188 1189 assert(xsrc->xive); 1190 1191 if (!xsrc->nr_irqs) { 1192 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1193 return; 1194 } 1195 1196 if (xsrc->esb_shift != XIVE_ESB_4K && 1197 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1198 xsrc->esb_shift != XIVE_ESB_64K && 1199 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1200 error_setg(errp, "Invalid ESB shift setting"); 1201 return; 1202 } 1203 1204 xsrc->status = g_malloc0(xsrc->nr_irqs); 1205 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1206 1207 memory_region_init(&xsrc->esb_mmio, OBJECT(xsrc), "xive.esb", esb_len); 1208 memory_region_init_io(&xsrc->esb_mmio_emulated, OBJECT(xsrc), 1209 &xive_source_esb_ops, xsrc, "xive.esb-emulated", 1210 esb_len); 1211 memory_region_add_subregion(&xsrc->esb_mmio, 0, &xsrc->esb_mmio_emulated); 1212 1213 qemu_register_reset(xive_source_reset, dev); 1214 } 1215 1216 static const VMStateDescription vmstate_xive_source = { 1217 .name = TYPE_XIVE_SOURCE, 1218 .version_id = 1, 1219 .minimum_version_id = 1, 1220 .fields = (VMStateField[]) { 1221 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1222 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1223 VMSTATE_END_OF_LIST() 1224 }, 1225 }; 1226 1227 /* 1228 * The default XIVE interrupt source setting for the ESB MMIOs is two 1229 * 64k pages without Store EOI, to be in sync with KVM. 1230 */ 1231 static Property xive_source_properties[] = { 1232 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1233 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1234 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1235 DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, 1236 XiveNotifier *), 1237 DEFINE_PROP_END_OF_LIST(), 1238 }; 1239 1240 static void xive_source_class_init(ObjectClass *klass, void *data) 1241 { 1242 DeviceClass *dc = DEVICE_CLASS(klass); 1243 1244 dc->desc = "XIVE Interrupt Source"; 1245 device_class_set_props(dc, xive_source_properties); 1246 dc->realize = xive_source_realize; 1247 dc->vmsd = &vmstate_xive_source; 1248 /* 1249 * Reason: part of XIVE interrupt controller, needs to be wired up, 1250 * e.g. by spapr_xive_instance_init(). 1251 */ 1252 dc->user_creatable = false; 1253 } 1254 1255 static const TypeInfo xive_source_info = { 1256 .name = TYPE_XIVE_SOURCE, 1257 .parent = TYPE_DEVICE, 1258 .instance_size = sizeof(XiveSource), 1259 .class_init = xive_source_class_init, 1260 }; 1261 1262 /* 1263 * XiveEND helpers 1264 */ 1265 1266 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1267 { 1268 uint64_t qaddr_base = xive_end_qaddr(end); 1269 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1270 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1271 uint32_t qentries = 1 << (qsize + 10); 1272 int i; 1273 1274 /* 1275 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1276 */ 1277 monitor_printf(mon, " [ "); 1278 qindex = (qindex - (width - 1)) & (qentries - 1); 1279 for (i = 0; i < width; i++) { 1280 uint64_t qaddr = qaddr_base + (qindex << 2); 1281 uint32_t qdata = -1; 1282 1283 if (dma_memory_read(&address_space_memory, qaddr, 1284 &qdata, sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 1285 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1286 HWADDR_PRIx "\n", qaddr); 1287 return; 1288 } 1289 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1290 be32_to_cpu(qdata)); 1291 qindex = (qindex + 1) & (qentries - 1); 1292 } 1293 monitor_printf(mon, "]"); 1294 } 1295 1296 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1297 { 1298 uint64_t qaddr_base = xive_end_qaddr(end); 1299 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1300 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1301 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1302 uint32_t qentries = 1 << (qsize + 10); 1303 1304 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1305 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1306 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1307 uint8_t pq; 1308 1309 if (!xive_end_is_valid(end)) { 1310 return; 1311 } 1312 1313 pq = xive_get_field32(END_W1_ESn, end->w1); 1314 1315 monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1316 end_idx, 1317 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1318 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1319 xive_end_is_valid(end) ? 'v' : '-', 1320 xive_end_is_enqueue(end) ? 'q' : '-', 1321 xive_end_is_notify(end) ? 'n' : '-', 1322 xive_end_is_backlog(end) ? 'b' : '-', 1323 xive_end_is_escalate(end) ? 'e' : '-', 1324 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1325 xive_end_is_silent_escalation(end) ? 's' : '-', 1326 xive_end_is_firmware(end) ? 'f' : '-', 1327 priority, nvt_blk, nvt_idx); 1328 1329 if (qaddr_base) { 1330 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1331 qaddr_base, qindex, qentries, qgen); 1332 xive_end_queue_pic_print_info(end, 6, mon); 1333 } 1334 monitor_printf(mon, "\n"); 1335 } 1336 1337 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1338 { 1339 uint64_t qaddr_base = xive_end_qaddr(end); 1340 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1341 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1342 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1343 1344 uint64_t qaddr = qaddr_base + (qindex << 2); 1345 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1346 uint32_t qentries = 1 << (qsize + 10); 1347 1348 if (dma_memory_write(&address_space_memory, qaddr, 1349 &qdata, sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 1350 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1351 HWADDR_PRIx "\n", qaddr); 1352 return; 1353 } 1354 1355 qindex = (qindex + 1) & (qentries - 1); 1356 if (qindex == 0) { 1357 qgen ^= 1; 1358 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1359 } 1360 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1361 } 1362 1363 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, 1364 Monitor *mon) 1365 { 1366 XiveEAS *eas = (XiveEAS *) &end->w4; 1367 uint8_t pq; 1368 1369 if (!xive_end_is_escalate(end)) { 1370 return; 1371 } 1372 1373 pq = xive_get_field32(END_W1_ESe, end->w1); 1374 1375 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1376 end_idx, 1377 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1378 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1379 xive_eas_is_valid(eas) ? 'V' : ' ', 1380 xive_eas_is_masked(eas) ? 'M' : ' ', 1381 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1382 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1383 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1384 } 1385 1386 /* 1387 * XIVE Router (aka. Virtualization Controller or IVRE) 1388 */ 1389 1390 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1391 XiveEAS *eas) 1392 { 1393 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1394 1395 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1396 } 1397 1398 static 1399 int xive_router_get_pq(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1400 uint8_t *pq) 1401 { 1402 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1403 1404 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); 1405 } 1406 1407 static 1408 int xive_router_set_pq(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1409 uint8_t *pq) 1410 { 1411 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1412 1413 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); 1414 } 1415 1416 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1417 XiveEND *end) 1418 { 1419 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1420 1421 return xrc->get_end(xrtr, end_blk, end_idx, end); 1422 } 1423 1424 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1425 XiveEND *end, uint8_t word_number) 1426 { 1427 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1428 1429 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1430 } 1431 1432 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1433 XiveNVT *nvt) 1434 { 1435 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1436 1437 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1438 } 1439 1440 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1441 XiveNVT *nvt, uint8_t word_number) 1442 { 1443 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1444 1445 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1446 } 1447 1448 static int xive_router_get_block_id(XiveRouter *xrtr) 1449 { 1450 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1451 1452 return xrc->get_block_id(xrtr); 1453 } 1454 1455 static void xive_router_realize(DeviceState *dev, Error **errp) 1456 { 1457 XiveRouter *xrtr = XIVE_ROUTER(dev); 1458 1459 assert(xrtr->xfb); 1460 } 1461 1462 /* 1463 * Encode the HW CAM line in the block group mode format : 1464 * 1465 * chip << 19 | 0000000 0 0001 thread (7Bit) 1466 */ 1467 static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 1468 { 1469 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1470 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1471 uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr)); 1472 1473 return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); 1474 } 1475 1476 /* 1477 * The thread context register words are in big-endian format. 1478 */ 1479 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1480 uint8_t format, 1481 uint8_t nvt_blk, uint32_t nvt_idx, 1482 bool cam_ignore, uint32_t logic_serv) 1483 { 1484 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1485 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1486 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1487 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1488 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1489 1490 /* 1491 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1492 * identifier are ignored in the "CAM" match. 1493 */ 1494 1495 if (format == 0) { 1496 if (cam_ignore == true) { 1497 /* 1498 * F=0 & i=1: Logical server notification (bits ignored at 1499 * the end of the NVT identifier) 1500 */ 1501 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1502 nvt_blk, nvt_idx); 1503 return -1; 1504 } 1505 1506 /* F=0 & i=0: Specific NVT notification */ 1507 1508 /* PHYS ring */ 1509 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1510 cam == xive_tctx_hw_cam_line(xptr, tctx)) { 1511 return TM_QW3_HV_PHYS; 1512 } 1513 1514 /* HV POOL ring */ 1515 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1516 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1517 return TM_QW2_HV_POOL; 1518 } 1519 1520 /* OS ring */ 1521 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1522 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1523 return TM_QW1_OS; 1524 } 1525 } else { 1526 /* F=1 : User level Event-Based Branch (EBB) notification */ 1527 1528 /* USER ring */ 1529 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1530 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1531 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1532 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1533 return TM_QW0_USER; 1534 } 1535 } 1536 return -1; 1537 } 1538 1539 /* 1540 * This is our simple Xive Presenter Engine model. It is merged in the 1541 * Router as it does not require an extra object. 1542 * 1543 * It receives notification requests sent by the IVRE to find one 1544 * matching NVT (or more) dispatched on the processor threads. In case 1545 * of a single NVT notification, the process is abreviated and the 1546 * thread is signaled if a match is found. In case of a logical server 1547 * notification (bits ignored at the end of the NVT identifier), the 1548 * IVPE and IVRE select a winning thread using different filters. This 1549 * involves 2 or 3 exchanges on the PowerBus that the model does not 1550 * support. 1551 * 1552 * The parameters represent what is sent on the PowerBus 1553 */ 1554 bool xive_presenter_notify(XiveFabric *xfb, uint8_t format, 1555 uint8_t nvt_blk, uint32_t nvt_idx, 1556 bool cam_ignore, uint8_t priority, 1557 uint32_t logic_serv) 1558 { 1559 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb); 1560 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1561 int count; 1562 1563 /* 1564 * Ask the machine to scan the interrupt controllers for a match 1565 */ 1566 count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore, 1567 priority, logic_serv, &match); 1568 if (count < 0) { 1569 return false; 1570 } 1571 1572 /* handle CPU exception delivery */ 1573 if (count) { 1574 trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring); 1575 xive_tctx_ipb_update(match.tctx, match.ring, 1576 xive_priority_to_ipb(priority)); 1577 } 1578 1579 return !!count; 1580 } 1581 1582 /* 1583 * Notification using the END ESe/ESn bit (Event State Buffer for 1584 * escalation and notification). Provide further coalescing in the 1585 * Router. 1586 */ 1587 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1588 uint32_t end_idx, XiveEND *end, 1589 uint32_t end_esmask) 1590 { 1591 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1592 bool notify = xive_esb_trigger(&pq); 1593 1594 if (pq != xive_get_field32(end_esmask, end->w1)) { 1595 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1596 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1597 } 1598 1599 /* ESe/n[Q]=1 : end of notification */ 1600 return notify; 1601 } 1602 1603 /* 1604 * An END trigger can come from an event trigger (IPI or HW) or from 1605 * another chip. We don't model the PowerBus but the END trigger 1606 * message has the same parameters than in the function below. 1607 */ 1608 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1609 uint32_t end_idx, uint32_t end_data) 1610 { 1611 XiveEND end; 1612 uint8_t priority; 1613 uint8_t format; 1614 uint8_t nvt_blk; 1615 uint32_t nvt_idx; 1616 XiveNVT nvt; 1617 bool found; 1618 1619 /* END cache lookup */ 1620 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1621 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1622 end_idx); 1623 return; 1624 } 1625 1626 if (!xive_end_is_valid(&end)) { 1627 trace_xive_router_end_notify(end_blk, end_idx, end_data); 1628 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1629 end_blk, end_idx); 1630 return; 1631 } 1632 1633 if (xive_end_is_enqueue(&end)) { 1634 xive_end_enqueue(&end, end_data); 1635 /* Enqueuing event data modifies the EQ toggle and index */ 1636 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1637 } 1638 1639 /* 1640 * When the END is silent, we skip the notification part. 1641 */ 1642 if (xive_end_is_silent_escalation(&end)) { 1643 goto do_escalation; 1644 } 1645 1646 /* 1647 * The W7 format depends on the F bit in W6. It defines the type 1648 * of the notification : 1649 * 1650 * F=0 : single or multiple NVT notification 1651 * F=1 : User level Event-Based Branch (EBB) notification, no 1652 * priority 1653 */ 1654 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1655 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1656 1657 /* The END is masked */ 1658 if (format == 0 && priority == 0xff) { 1659 return; 1660 } 1661 1662 /* 1663 * Check the END ESn (Event State Buffer for notification) for 1664 * even further coalescing in the Router 1665 */ 1666 if (!xive_end_is_notify(&end)) { 1667 /* ESn[Q]=1 : end of notification */ 1668 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1669 &end, END_W1_ESn)) { 1670 return; 1671 } 1672 } 1673 1674 /* 1675 * Follows IVPE notification 1676 */ 1677 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1678 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1679 1680 /* NVT cache lookup */ 1681 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1682 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1683 nvt_blk, nvt_idx); 1684 return; 1685 } 1686 1687 if (!xive_nvt_is_valid(&nvt)) { 1688 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1689 nvt_blk, nvt_idx); 1690 return; 1691 } 1692 1693 found = xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx, 1694 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1695 priority, 1696 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1697 1698 /* TODO: Auto EOI. */ 1699 1700 if (found) { 1701 return; 1702 } 1703 1704 /* 1705 * If no matching NVT is dispatched on a HW thread : 1706 * - specific VP: update the NVT structure if backlog is activated 1707 * - logical server : forward request to IVPE (not supported) 1708 */ 1709 if (xive_end_is_backlog(&end)) { 1710 uint8_t ipb; 1711 1712 if (format == 1) { 1713 qemu_log_mask(LOG_GUEST_ERROR, 1714 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1715 end_blk, end_idx); 1716 return; 1717 } 1718 /* 1719 * Record the IPB in the associated NVT structure for later 1720 * use. The presenter will resend the interrupt when the vCPU 1721 * is dispatched again on a HW thread. 1722 */ 1723 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | 1724 xive_priority_to_ipb(priority); 1725 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); 1726 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1727 1728 /* 1729 * On HW, follows a "Broadcast Backlog" to IVPEs 1730 */ 1731 } 1732 1733 do_escalation: 1734 /* 1735 * If activated, escalate notification using the ESe PQ bits and 1736 * the EAS in w4-5 1737 */ 1738 if (!xive_end_is_escalate(&end)) { 1739 return; 1740 } 1741 1742 /* 1743 * Check the END ESe (Event State Buffer for escalation) for even 1744 * further coalescing in the Router 1745 */ 1746 if (!xive_end_is_uncond_escalation(&end)) { 1747 /* ESe[Q]=1 : end of notification */ 1748 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1749 &end, END_W1_ESe)) { 1750 return; 1751 } 1752 } 1753 1754 trace_xive_router_end_escalate(end_blk, end_idx, 1755 (uint8_t) xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1756 (uint32_t) xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1757 (uint32_t) xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1758 /* 1759 * The END trigger becomes an Escalation trigger 1760 */ 1761 xive_router_end_notify(xrtr, 1762 xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1763 xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1764 xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1765 } 1766 1767 void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) 1768 { 1769 XiveRouter *xrtr = XIVE_ROUTER(xn); 1770 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1771 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1772 XiveEAS eas; 1773 1774 /* EAS cache lookup */ 1775 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1776 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1777 return; 1778 } 1779 1780 if (!pq_checked) { 1781 bool notify; 1782 uint8_t pq; 1783 1784 /* PQ cache lookup */ 1785 if (xive_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) { 1786 /* Set FIR */ 1787 g_assert_not_reached(); 1788 } 1789 1790 notify = xive_esb_trigger(&pq); 1791 1792 if (xive_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) { 1793 /* Set FIR */ 1794 g_assert_not_reached(); 1795 } 1796 1797 if (!notify) { 1798 return; 1799 } 1800 } 1801 1802 if (!xive_eas_is_valid(&eas)) { 1803 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1804 return; 1805 } 1806 1807 if (xive_eas_is_masked(&eas)) { 1808 /* Notification completed */ 1809 return; 1810 } 1811 1812 /* 1813 * The event trigger becomes an END trigger 1814 */ 1815 xive_router_end_notify(xrtr, 1816 xive_get_field64(EAS_END_BLOCK, eas.w), 1817 xive_get_field64(EAS_END_INDEX, eas.w), 1818 xive_get_field64(EAS_END_DATA, eas.w)); 1819 } 1820 1821 static Property xive_router_properties[] = { 1822 DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb, 1823 TYPE_XIVE_FABRIC, XiveFabric *), 1824 DEFINE_PROP_END_OF_LIST(), 1825 }; 1826 1827 static void xive_router_class_init(ObjectClass *klass, void *data) 1828 { 1829 DeviceClass *dc = DEVICE_CLASS(klass); 1830 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1831 1832 dc->desc = "XIVE Router Engine"; 1833 device_class_set_props(dc, xive_router_properties); 1834 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 1835 dc->realize = xive_router_realize; 1836 xnc->notify = xive_router_notify; 1837 } 1838 1839 static const TypeInfo xive_router_info = { 1840 .name = TYPE_XIVE_ROUTER, 1841 .parent = TYPE_SYS_BUS_DEVICE, 1842 .abstract = true, 1843 .instance_size = sizeof(XiveRouter), 1844 .class_size = sizeof(XiveRouterClass), 1845 .class_init = xive_router_class_init, 1846 .interfaces = (InterfaceInfo[]) { 1847 { TYPE_XIVE_NOTIFIER }, 1848 { TYPE_XIVE_PRESENTER }, 1849 { } 1850 } 1851 }; 1852 1853 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1854 { 1855 if (!xive_eas_is_valid(eas)) { 1856 return; 1857 } 1858 1859 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1860 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1861 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1862 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1863 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1864 } 1865 1866 /* 1867 * END ESB MMIO loads 1868 */ 1869 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1870 { 1871 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1872 uint32_t offset = addr & 0xFFF; 1873 uint8_t end_blk; 1874 uint32_t end_idx; 1875 XiveEND end; 1876 uint32_t end_esmask; 1877 uint8_t pq; 1878 uint64_t ret = -1; 1879 1880 /* 1881 * The block id should be deduced from the load address on the END 1882 * ESB MMIO but our model only supports a single block per XIVE chip. 1883 */ 1884 end_blk = xive_router_get_block_id(xsrc->xrtr); 1885 end_idx = addr >> (xsrc->esb_shift + 1); 1886 1887 trace_xive_end_source_read(end_blk, end_idx, addr); 1888 1889 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1890 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1891 end_idx); 1892 return -1; 1893 } 1894 1895 if (!xive_end_is_valid(&end)) { 1896 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1897 end_blk, end_idx); 1898 return -1; 1899 } 1900 1901 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1902 pq = xive_get_field32(end_esmask, end.w1); 1903 1904 switch (offset) { 1905 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1906 ret = xive_esb_eoi(&pq); 1907 1908 /* Forward the source event notification for routing ?? */ 1909 break; 1910 1911 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1912 ret = pq; 1913 break; 1914 1915 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1916 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1917 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1918 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1919 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1920 break; 1921 default: 1922 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1923 offset); 1924 return -1; 1925 } 1926 1927 if (pq != xive_get_field32(end_esmask, end.w1)) { 1928 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1929 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1930 } 1931 1932 return ret; 1933 } 1934 1935 /* 1936 * END ESB MMIO stores are invalid 1937 */ 1938 static void xive_end_source_write(void *opaque, hwaddr addr, 1939 uint64_t value, unsigned size) 1940 { 1941 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1942 HWADDR_PRIx"\n", addr); 1943 } 1944 1945 static const MemoryRegionOps xive_end_source_ops = { 1946 .read = xive_end_source_read, 1947 .write = xive_end_source_write, 1948 .endianness = DEVICE_BIG_ENDIAN, 1949 .valid = { 1950 .min_access_size = 8, 1951 .max_access_size = 8, 1952 }, 1953 .impl = { 1954 .min_access_size = 8, 1955 .max_access_size = 8, 1956 }, 1957 }; 1958 1959 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1960 { 1961 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1962 1963 assert(xsrc->xrtr); 1964 1965 if (!xsrc->nr_ends) { 1966 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1967 return; 1968 } 1969 1970 if (xsrc->esb_shift != XIVE_ESB_4K && 1971 xsrc->esb_shift != XIVE_ESB_64K) { 1972 error_setg(errp, "Invalid ESB shift setting"); 1973 return; 1974 } 1975 1976 /* 1977 * Each END is assigned an even/odd pair of MMIO pages, the even page 1978 * manages the ESn field while the odd page manages the ESe field. 1979 */ 1980 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1981 &xive_end_source_ops, xsrc, "xive.end", 1982 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1983 } 1984 1985 static Property xive_end_source_properties[] = { 1986 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1987 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1988 DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, 1989 XiveRouter *), 1990 DEFINE_PROP_END_OF_LIST(), 1991 }; 1992 1993 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1994 { 1995 DeviceClass *dc = DEVICE_CLASS(klass); 1996 1997 dc->desc = "XIVE END Source"; 1998 device_class_set_props(dc, xive_end_source_properties); 1999 dc->realize = xive_end_source_realize; 2000 /* 2001 * Reason: part of XIVE interrupt controller, needs to be wired up, 2002 * e.g. by spapr_xive_instance_init(). 2003 */ 2004 dc->user_creatable = false; 2005 } 2006 2007 static const TypeInfo xive_end_source_info = { 2008 .name = TYPE_XIVE_END_SOURCE, 2009 .parent = TYPE_DEVICE, 2010 .instance_size = sizeof(XiveENDSource), 2011 .class_init = xive_end_source_class_init, 2012 }; 2013 2014 /* 2015 * XIVE Notifier 2016 */ 2017 static const TypeInfo xive_notifier_info = { 2018 .name = TYPE_XIVE_NOTIFIER, 2019 .parent = TYPE_INTERFACE, 2020 .class_size = sizeof(XiveNotifierClass), 2021 }; 2022 2023 /* 2024 * XIVE Presenter 2025 */ 2026 static const TypeInfo xive_presenter_info = { 2027 .name = TYPE_XIVE_PRESENTER, 2028 .parent = TYPE_INTERFACE, 2029 .class_size = sizeof(XivePresenterClass), 2030 }; 2031 2032 /* 2033 * XIVE Fabric 2034 */ 2035 static const TypeInfo xive_fabric_info = { 2036 .name = TYPE_XIVE_FABRIC, 2037 .parent = TYPE_INTERFACE, 2038 .class_size = sizeof(XiveFabricClass), 2039 }; 2040 2041 static void xive_register_types(void) 2042 { 2043 type_register_static(&xive_fabric_info); 2044 type_register_static(&xive_source_info); 2045 type_register_static(&xive_notifier_info); 2046 type_register_static(&xive_presenter_info); 2047 type_register_static(&xive_router_info); 2048 type_register_static(&xive_end_source_info); 2049 type_register_static(&xive_tctx_info); 2050 } 2051 2052 type_init(xive_register_types) 2053