1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "monitor/monitor.h" 21 #include "hw/irq.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive_regs.h" 24 25 /* 26 * XIVE Thread Interrupt Management context 27 */ 28 29 /* 30 * Convert a priority number to an Interrupt Pending Buffer (IPB) 31 * register, which indicates a pending interrupt at the priority 32 * corresponding to the bit number 33 */ 34 static uint8_t priority_to_ipb(uint8_t priority) 35 { 36 return priority > XIVE_PRIORITY_MAX ? 37 0 : 1 << (XIVE_PRIORITY_MAX - priority); 38 } 39 40 /* 41 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 42 * Interrupt Priority Register (PIPR), which contains the priority of 43 * the most favored pending notification. 44 */ 45 static uint8_t ipb_to_pipr(uint8_t ibp) 46 { 47 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 48 } 49 50 static uint8_t exception_mask(uint8_t ring) 51 { 52 switch (ring) { 53 case TM_QW1_OS: 54 return TM_QW1_NSR_EO; 55 case TM_QW3_HV_PHYS: 56 return TM_QW3_NSR_HE; 57 default: 58 g_assert_not_reached(); 59 } 60 } 61 62 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 63 { 64 switch (ring) { 65 case TM_QW0_USER: 66 return 0; /* Not supported */ 67 case TM_QW1_OS: 68 return tctx->os_output; 69 case TM_QW2_HV_POOL: 70 case TM_QW3_HV_PHYS: 71 return tctx->hv_output; 72 default: 73 return 0; 74 } 75 } 76 77 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 78 { 79 uint8_t *regs = &tctx->regs[ring]; 80 uint8_t nsr = regs[TM_NSR]; 81 uint8_t mask = exception_mask(ring); 82 83 qemu_irq_lower(xive_tctx_output(tctx, ring)); 84 85 if (regs[TM_NSR] & mask) { 86 uint8_t cppr = regs[TM_PIPR]; 87 88 regs[TM_CPPR] = cppr; 89 90 /* Reset the pending buffer bit */ 91 regs[TM_IPB] &= ~priority_to_ipb(cppr); 92 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 93 94 /* Drop Exception bit */ 95 regs[TM_NSR] &= ~mask; 96 } 97 98 return (nsr << 8) | regs[TM_CPPR]; 99 } 100 101 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 102 { 103 uint8_t *regs = &tctx->regs[ring]; 104 105 if (regs[TM_PIPR] < regs[TM_CPPR]) { 106 switch (ring) { 107 case TM_QW1_OS: 108 regs[TM_NSR] |= TM_QW1_NSR_EO; 109 break; 110 case TM_QW3_HV_PHYS: 111 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 112 break; 113 default: 114 g_assert_not_reached(); 115 } 116 qemu_irq_raise(xive_tctx_output(tctx, ring)); 117 } 118 } 119 120 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 121 { 122 if (cppr > XIVE_PRIORITY_MAX) { 123 cppr = 0xff; 124 } 125 126 tctx->regs[ring + TM_CPPR] = cppr; 127 128 /* CPPR has changed, check if we need to raise a pending exception */ 129 xive_tctx_notify(tctx, ring); 130 } 131 132 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) 133 { 134 uint8_t *regs = &tctx->regs[ring]; 135 136 regs[TM_IPB] |= ipb; 137 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 138 xive_tctx_notify(tctx, ring); 139 } 140 141 static inline uint32_t xive_tctx_word2(uint8_t *ring) 142 { 143 return *((uint32_t *) &ring[TM_WORD2]); 144 } 145 146 /* 147 * XIVE Thread Interrupt Management Area (TIMA) 148 */ 149 150 static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 151 hwaddr offset, uint64_t value, unsigned size) 152 { 153 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 154 } 155 156 static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx, 157 hwaddr offset, unsigned size) 158 { 159 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 160 } 161 162 static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 163 hwaddr offset, unsigned size) 164 { 165 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 166 uint32_t qw2w2; 167 168 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 169 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 170 return qw2w2; 171 } 172 173 static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 174 uint64_t value, unsigned size) 175 { 176 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 177 } 178 179 static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, 180 hwaddr offset, unsigned size) 181 { 182 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 183 } 184 185 /* 186 * Define an access map for each page of the TIMA that we will use in 187 * the memory region ops to filter values when doing loads and stores 188 * of raw registers values 189 * 190 * Registers accessibility bits : 191 * 192 * 0x0 - no access 193 * 0x1 - write only 194 * 0x2 - read only 195 * 0x3 - read/write 196 */ 197 198 static const uint8_t xive_tm_hw_view[] = { 199 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 200 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 201 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 202 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 203 }; 204 205 static const uint8_t xive_tm_hv_view[] = { 206 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 207 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 208 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 209 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 210 }; 211 212 static const uint8_t xive_tm_os_view[] = { 213 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 214 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 215 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 217 }; 218 219 static const uint8_t xive_tm_user_view[] = { 220 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 223 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 224 }; 225 226 /* 227 * Overall TIMA access map for the thread interrupt management context 228 * registers 229 */ 230 static const uint8_t *xive_tm_views[] = { 231 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 232 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 233 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 234 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 235 }; 236 237 /* 238 * Computes a register access mask for a given offset in the TIMA 239 */ 240 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 241 { 242 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 243 uint8_t reg_offset = offset & 0x3F; 244 uint8_t reg_mask = write ? 0x1 : 0x2; 245 uint64_t mask = 0x0; 246 int i; 247 248 for (i = 0; i < size; i++) { 249 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 250 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 251 } 252 } 253 254 return mask; 255 } 256 257 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 258 unsigned size) 259 { 260 uint8_t ring_offset = offset & 0x30; 261 uint8_t reg_offset = offset & 0x3F; 262 uint64_t mask = xive_tm_mask(offset, size, true); 263 int i; 264 265 /* 266 * Only 4 or 8 bytes stores are allowed and the User ring is 267 * excluded 268 */ 269 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 270 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 271 HWADDR_PRIx"\n", offset); 272 return; 273 } 274 275 /* 276 * Use the register offset for the raw values and filter out 277 * reserved values 278 */ 279 for (i = 0; i < size; i++) { 280 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 281 if (byte_mask) { 282 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 283 byte_mask; 284 } 285 } 286 } 287 288 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 289 { 290 uint8_t ring_offset = offset & 0x30; 291 uint8_t reg_offset = offset & 0x3F; 292 uint64_t mask = xive_tm_mask(offset, size, false); 293 uint64_t ret; 294 int i; 295 296 /* 297 * Only 4 or 8 bytes loads are allowed and the User ring is 298 * excluded 299 */ 300 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 301 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 302 HWADDR_PRIx"\n", offset); 303 return -1; 304 } 305 306 /* Use the register offset for the raw values */ 307 ret = 0; 308 for (i = 0; i < size; i++) { 309 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 310 } 311 312 /* filter out reserved values */ 313 return ret & mask; 314 } 315 316 /* 317 * The TM context is mapped twice within each page. Stores and loads 318 * to the first mapping below 2K write and read the specified values 319 * without modification. The second mapping above 2K performs specific 320 * state changes (side effects) in addition to setting/returning the 321 * interrupt management area context of the processor thread. 322 */ 323 static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx, 324 hwaddr offset, unsigned size) 325 { 326 return xive_tctx_accept(tctx, TM_QW1_OS); 327 } 328 329 static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 330 hwaddr offset, uint64_t value, unsigned size) 331 { 332 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 333 } 334 335 /* 336 * Adjust the IPB to allow a CPU to process event queues of other 337 * priorities during one physical interrupt cycle. 338 */ 339 static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, 340 hwaddr offset, uint64_t value, unsigned size) 341 { 342 xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff)); 343 } 344 345 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, 346 uint32_t *nvt_idx, bool *vo) 347 { 348 if (nvt_blk) { 349 *nvt_blk = xive_nvt_blk(cam); 350 } 351 if (nvt_idx) { 352 *nvt_idx = xive_nvt_idx(cam); 353 } 354 if (vo) { 355 *vo = !!(cam & TM_QW1W2_VO); 356 } 357 } 358 359 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk, 360 uint32_t *nvt_idx, bool *vo) 361 { 362 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 363 uint32_t cam = be32_to_cpu(qw1w2); 364 365 xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo); 366 return qw1w2; 367 } 368 369 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) 370 { 371 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 372 } 373 374 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 375 hwaddr offset, unsigned size) 376 { 377 uint32_t qw1w2; 378 uint32_t qw1w2_new; 379 uint8_t nvt_blk; 380 uint32_t nvt_idx; 381 bool vo; 382 383 qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); 384 385 if (!vo) { 386 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n", 387 nvt_blk, nvt_idx); 388 } 389 390 /* Invalidate CAM line */ 391 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); 392 xive_tctx_set_os_cam(tctx, qw1w2_new); 393 return qw1w2; 394 } 395 396 /* 397 * Define a mapping of "special" operations depending on the TIMA page 398 * offset and the size of the operation. 399 */ 400 typedef struct XiveTmOp { 401 uint8_t page_offset; 402 uint32_t op_offset; 403 unsigned size; 404 void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, 405 hwaddr offset, 406 uint64_t value, unsigned size); 407 uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 408 unsigned size); 409 } XiveTmOp; 410 411 static const XiveTmOp xive_tm_operations[] = { 412 /* 413 * MMIOs below 2K : raw values and special operations without side 414 * effects 415 */ 416 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 417 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 418 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 419 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 420 421 /* MMIOs above 2K : special operations with side effects */ 422 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 423 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 424 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, 425 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, 426 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 427 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 428 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 429 }; 430 431 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 432 { 433 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 434 uint32_t op_offset = offset & 0xFFF; 435 int i; 436 437 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 438 const XiveTmOp *xto = &xive_tm_operations[i]; 439 440 /* Accesses done from a more privileged TIMA page is allowed */ 441 if (xto->page_offset >= page_offset && 442 xto->op_offset == op_offset && 443 xto->size == size && 444 ((write && xto->write_handler) || (!write && xto->read_handler))) { 445 return xto; 446 } 447 } 448 return NULL; 449 } 450 451 /* 452 * TIMA MMIO handlers 453 */ 454 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 455 uint64_t value, unsigned size) 456 { 457 const XiveTmOp *xto; 458 459 /* 460 * TODO: check V bit in Q[0-3]W2 461 */ 462 463 /* 464 * First, check for special operations in the 2K region 465 */ 466 if (offset & 0x800) { 467 xto = xive_tm_find_op(offset, size, true); 468 if (!xto) { 469 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 470 "@%"HWADDR_PRIx"\n", offset); 471 } else { 472 xto->write_handler(xptr, tctx, offset, value, size); 473 } 474 return; 475 } 476 477 /* 478 * Then, for special operations in the region below 2K. 479 */ 480 xto = xive_tm_find_op(offset, size, true); 481 if (xto) { 482 xto->write_handler(xptr, tctx, offset, value, size); 483 return; 484 } 485 486 /* 487 * Finish with raw access to the register values 488 */ 489 xive_tm_raw_write(tctx, offset, value, size); 490 } 491 492 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 493 unsigned size) 494 { 495 const XiveTmOp *xto; 496 497 /* 498 * TODO: check V bit in Q[0-3]W2 499 */ 500 501 /* 502 * First, check for special operations in the 2K region 503 */ 504 if (offset & 0x800) { 505 xto = xive_tm_find_op(offset, size, false); 506 if (!xto) { 507 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 508 "@%"HWADDR_PRIx"\n", offset); 509 return -1; 510 } 511 return xto->read_handler(xptr, tctx, offset, size); 512 } 513 514 /* 515 * Then, for special operations in the region below 2K. 516 */ 517 xto = xive_tm_find_op(offset, size, false); 518 if (xto) { 519 return xto->read_handler(xptr, tctx, offset, size); 520 } 521 522 /* 523 * Finish with raw access to the register values 524 */ 525 return xive_tm_raw_read(tctx, offset, size); 526 } 527 528 static char *xive_tctx_ring_print(uint8_t *ring) 529 { 530 uint32_t w2 = xive_tctx_word2(ring); 531 532 return g_strdup_printf("%02x %02x %02x %02x %02x " 533 "%02x %02x %02x %08x", 534 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 535 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 536 be32_to_cpu(w2)); 537 } 538 539 static const char * const xive_tctx_ring_names[] = { 540 "USER", "OS", "POOL", "PHYS", 541 }; 542 543 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 544 { 545 int cpu_index; 546 int i; 547 548 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs 549 * are hot plugged or unplugged. 550 */ 551 if (!tctx) { 552 return; 553 } 554 555 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 556 557 if (kvm_irqchip_in_kernel()) { 558 Error *local_err = NULL; 559 560 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 561 if (local_err) { 562 error_report_err(local_err); 563 return; 564 } 565 } 566 567 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 568 " W2\n", cpu_index); 569 570 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 571 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 572 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 573 xive_tctx_ring_names[i], s); 574 g_free(s); 575 } 576 } 577 578 void xive_tctx_reset(XiveTCTX *tctx) 579 { 580 memset(tctx->regs, 0, sizeof(tctx->regs)); 581 582 /* Set some defaults */ 583 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 584 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 585 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 586 587 /* 588 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 589 * CPPR is first set. 590 */ 591 tctx->regs[TM_QW1_OS + TM_PIPR] = 592 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 593 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 594 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 595 } 596 597 static void xive_tctx_realize(DeviceState *dev, Error **errp) 598 { 599 XiveTCTX *tctx = XIVE_TCTX(dev); 600 PowerPCCPU *cpu; 601 CPUPPCState *env; 602 Error *local_err = NULL; 603 604 assert(tctx->cs); 605 606 cpu = POWERPC_CPU(tctx->cs); 607 env = &cpu->env; 608 switch (PPC_INPUT(env)) { 609 case PPC_FLAGS_INPUT_POWER9: 610 tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT]; 611 tctx->os_output = env->irq_inputs[POWER9_INPUT_INT]; 612 break; 613 614 default: 615 error_setg(errp, "XIVE interrupt controller does not support " 616 "this CPU bus model"); 617 return; 618 } 619 620 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 621 if (kvm_irqchip_in_kernel()) { 622 kvmppc_xive_cpu_connect(tctx, &local_err); 623 if (local_err) { 624 error_propagate(errp, local_err); 625 return; 626 } 627 } 628 } 629 630 static int vmstate_xive_tctx_pre_save(void *opaque) 631 { 632 Error *local_err = NULL; 633 634 if (kvm_irqchip_in_kernel()) { 635 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque), &local_err); 636 if (local_err) { 637 error_report_err(local_err); 638 return -1; 639 } 640 } 641 642 return 0; 643 } 644 645 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 646 { 647 Error *local_err = NULL; 648 649 if (kvm_irqchip_in_kernel()) { 650 /* 651 * Required for hotplugged CPU, for which the state comes 652 * after all states of the machine. 653 */ 654 kvmppc_xive_cpu_set_state(XIVE_TCTX(opaque), &local_err); 655 if (local_err) { 656 error_report_err(local_err); 657 return -1; 658 } 659 } 660 661 return 0; 662 } 663 664 static const VMStateDescription vmstate_xive_tctx = { 665 .name = TYPE_XIVE_TCTX, 666 .version_id = 1, 667 .minimum_version_id = 1, 668 .pre_save = vmstate_xive_tctx_pre_save, 669 .post_load = vmstate_xive_tctx_post_load, 670 .fields = (VMStateField[]) { 671 VMSTATE_BUFFER(regs, XiveTCTX), 672 VMSTATE_END_OF_LIST() 673 }, 674 }; 675 676 static Property xive_tctx_properties[] = { 677 DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), 678 DEFINE_PROP_END_OF_LIST(), 679 }; 680 681 static void xive_tctx_class_init(ObjectClass *klass, void *data) 682 { 683 DeviceClass *dc = DEVICE_CLASS(klass); 684 685 dc->desc = "XIVE Interrupt Thread Context"; 686 dc->realize = xive_tctx_realize; 687 dc->vmsd = &vmstate_xive_tctx; 688 dc->props = xive_tctx_properties; 689 /* 690 * Reason: part of XIVE interrupt controller, needs to be wired up 691 * by xive_tctx_create(). 692 */ 693 dc->user_creatable = false; 694 } 695 696 static const TypeInfo xive_tctx_info = { 697 .name = TYPE_XIVE_TCTX, 698 .parent = TYPE_DEVICE, 699 .instance_size = sizeof(XiveTCTX), 700 .class_init = xive_tctx_class_init, 701 }; 702 703 Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) 704 { 705 Error *local_err = NULL; 706 Object *obj; 707 708 obj = object_new(TYPE_XIVE_TCTX); 709 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); 710 object_unref(obj); 711 object_property_set_link(obj, cpu, "cpu", &error_abort); 712 object_property_set_bool(obj, true, "realized", &local_err); 713 if (local_err) { 714 goto error; 715 } 716 717 return obj; 718 719 error: 720 object_unparent(obj); 721 error_propagate(errp, local_err); 722 return NULL; 723 } 724 725 void xive_tctx_destroy(XiveTCTX *tctx) 726 { 727 Object *obj = OBJECT(tctx); 728 729 object_unparent(obj); 730 } 731 732 /* 733 * XIVE ESB helpers 734 */ 735 736 static uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 737 { 738 uint8_t old_pq = *pq & 0x3; 739 740 *pq &= ~0x3; 741 *pq |= value & 0x3; 742 743 return old_pq; 744 } 745 746 static bool xive_esb_trigger(uint8_t *pq) 747 { 748 uint8_t old_pq = *pq & 0x3; 749 750 switch (old_pq) { 751 case XIVE_ESB_RESET: 752 xive_esb_set(pq, XIVE_ESB_PENDING); 753 return true; 754 case XIVE_ESB_PENDING: 755 case XIVE_ESB_QUEUED: 756 xive_esb_set(pq, XIVE_ESB_QUEUED); 757 return false; 758 case XIVE_ESB_OFF: 759 xive_esb_set(pq, XIVE_ESB_OFF); 760 return false; 761 default: 762 g_assert_not_reached(); 763 } 764 } 765 766 static bool xive_esb_eoi(uint8_t *pq) 767 { 768 uint8_t old_pq = *pq & 0x3; 769 770 switch (old_pq) { 771 case XIVE_ESB_RESET: 772 case XIVE_ESB_PENDING: 773 xive_esb_set(pq, XIVE_ESB_RESET); 774 return false; 775 case XIVE_ESB_QUEUED: 776 xive_esb_set(pq, XIVE_ESB_PENDING); 777 return true; 778 case XIVE_ESB_OFF: 779 xive_esb_set(pq, XIVE_ESB_OFF); 780 return false; 781 default: 782 g_assert_not_reached(); 783 } 784 } 785 786 /* 787 * XIVE Interrupt Source (or IVSE) 788 */ 789 790 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 791 { 792 assert(srcno < xsrc->nr_irqs); 793 794 return xsrc->status[srcno] & 0x3; 795 } 796 797 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 798 { 799 assert(srcno < xsrc->nr_irqs); 800 801 return xive_esb_set(&xsrc->status[srcno], pq); 802 } 803 804 /* 805 * Returns whether the event notification should be forwarded. 806 */ 807 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 808 { 809 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 810 811 xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; 812 813 switch (old_pq) { 814 case XIVE_ESB_RESET: 815 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 816 return true; 817 default: 818 return false; 819 } 820 } 821 822 /* 823 * Returns whether the event notification should be forwarded. 824 */ 825 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 826 { 827 bool ret; 828 829 assert(srcno < xsrc->nr_irqs); 830 831 ret = xive_esb_trigger(&xsrc->status[srcno]); 832 833 if (xive_source_irq_is_lsi(xsrc, srcno) && 834 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 835 qemu_log_mask(LOG_GUEST_ERROR, 836 "XIVE: queued an event on LSI IRQ %d\n", srcno); 837 } 838 839 return ret; 840 } 841 842 /* 843 * Returns whether the event notification should be forwarded. 844 */ 845 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 846 { 847 bool ret; 848 849 assert(srcno < xsrc->nr_irqs); 850 851 ret = xive_esb_eoi(&xsrc->status[srcno]); 852 853 /* 854 * LSI sources do not set the Q bit but they can still be 855 * asserted, in which case we should forward a new event 856 * notification 857 */ 858 if (xive_source_irq_is_lsi(xsrc, srcno) && 859 xsrc->status[srcno] & XIVE_STATUS_ASSERTED) { 860 ret = xive_source_lsi_trigger(xsrc, srcno); 861 } 862 863 return ret; 864 } 865 866 /* 867 * Forward the source event notification to the Router 868 */ 869 static void xive_source_notify(XiveSource *xsrc, int srcno) 870 { 871 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 872 873 if (xnc->notify) { 874 xnc->notify(xsrc->xive, srcno); 875 } 876 } 877 878 /* 879 * In a two pages ESB MMIO setting, even page is the trigger page, odd 880 * page is for management 881 */ 882 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 883 { 884 return !((addr >> shift) & 1); 885 } 886 887 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 888 { 889 return xive_source_esb_has_2page(xsrc) && 890 addr_is_even(addr, xsrc->esb_shift - 1); 891 } 892 893 /* 894 * ESB MMIO loads 895 * Trigger page Management/EOI page 896 * 897 * ESB MMIO setting 2 pages 1 or 2 pages 898 * 899 * 0x000 .. 0x3FF -1 EOI and return 0|1 900 * 0x400 .. 0x7FF -1 EOI and return 0|1 901 * 0x800 .. 0xBFF -1 return PQ 902 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 903 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 904 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 905 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 906 */ 907 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 908 { 909 XiveSource *xsrc = XIVE_SOURCE(opaque); 910 uint32_t offset = addr & 0xFFF; 911 uint32_t srcno = addr >> xsrc->esb_shift; 912 uint64_t ret = -1; 913 914 /* In a two pages ESB MMIO setting, trigger page should not be read */ 915 if (xive_source_is_trigger_page(xsrc, addr)) { 916 qemu_log_mask(LOG_GUEST_ERROR, 917 "XIVE: invalid load on IRQ %d trigger page at " 918 "0x%"HWADDR_PRIx"\n", srcno, addr); 919 return -1; 920 } 921 922 switch (offset) { 923 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 924 ret = xive_source_esb_eoi(xsrc, srcno); 925 926 /* Forward the source event notification for routing */ 927 if (ret) { 928 xive_source_notify(xsrc, srcno); 929 } 930 break; 931 932 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 933 ret = xive_source_esb_get(xsrc, srcno); 934 break; 935 936 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 937 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 938 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 939 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 940 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 941 break; 942 default: 943 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 944 offset); 945 } 946 947 return ret; 948 } 949 950 /* 951 * ESB MMIO stores 952 * Trigger page Management/EOI page 953 * 954 * ESB MMIO setting 2 pages 1 or 2 pages 955 * 956 * 0x000 .. 0x3FF Trigger Trigger 957 * 0x400 .. 0x7FF Trigger EOI 958 * 0x800 .. 0xBFF Trigger undefined 959 * 0xC00 .. 0xCFF Trigger PQ=00 960 * 0xD00 .. 0xDFF Trigger PQ=01 961 * 0xE00 .. 0xDFF Trigger PQ=10 962 * 0xF00 .. 0xDFF Trigger PQ=11 963 */ 964 static void xive_source_esb_write(void *opaque, hwaddr addr, 965 uint64_t value, unsigned size) 966 { 967 XiveSource *xsrc = XIVE_SOURCE(opaque); 968 uint32_t offset = addr & 0xFFF; 969 uint32_t srcno = addr >> xsrc->esb_shift; 970 bool notify = false; 971 972 /* In a two pages ESB MMIO setting, trigger page only triggers */ 973 if (xive_source_is_trigger_page(xsrc, addr)) { 974 notify = xive_source_esb_trigger(xsrc, srcno); 975 goto out; 976 } 977 978 switch (offset) { 979 case 0 ... 0x3FF: 980 notify = xive_source_esb_trigger(xsrc, srcno); 981 break; 982 983 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 984 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 985 qemu_log_mask(LOG_GUEST_ERROR, 986 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 987 return; 988 } 989 990 notify = xive_source_esb_eoi(xsrc, srcno); 991 break; 992 993 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 994 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 995 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 996 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 997 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 998 break; 999 1000 default: 1001 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 1002 offset); 1003 return; 1004 } 1005 1006 out: 1007 /* Forward the source event notification for routing */ 1008 if (notify) { 1009 xive_source_notify(xsrc, srcno); 1010 } 1011 } 1012 1013 static const MemoryRegionOps xive_source_esb_ops = { 1014 .read = xive_source_esb_read, 1015 .write = xive_source_esb_write, 1016 .endianness = DEVICE_BIG_ENDIAN, 1017 .valid = { 1018 .min_access_size = 8, 1019 .max_access_size = 8, 1020 }, 1021 .impl = { 1022 .min_access_size = 8, 1023 .max_access_size = 8, 1024 }, 1025 }; 1026 1027 void xive_source_set_irq(void *opaque, int srcno, int val) 1028 { 1029 XiveSource *xsrc = XIVE_SOURCE(opaque); 1030 bool notify = false; 1031 1032 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1033 if (val) { 1034 notify = xive_source_lsi_trigger(xsrc, srcno); 1035 } else { 1036 xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; 1037 } 1038 } else { 1039 if (val) { 1040 notify = xive_source_esb_trigger(xsrc, srcno); 1041 } 1042 } 1043 1044 /* Forward the source event notification for routing */ 1045 if (notify) { 1046 xive_source_notify(xsrc, srcno); 1047 } 1048 } 1049 1050 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 1051 { 1052 int i; 1053 1054 for (i = 0; i < xsrc->nr_irqs; i++) { 1055 uint8_t pq = xive_source_esb_get(xsrc, i); 1056 1057 if (pq == XIVE_ESB_OFF) { 1058 continue; 1059 } 1060 1061 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 1062 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1063 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1064 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1065 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' '); 1066 } 1067 } 1068 1069 static void xive_source_reset(void *dev) 1070 { 1071 XiveSource *xsrc = XIVE_SOURCE(dev); 1072 1073 /* Do not clear the LSI bitmap */ 1074 1075 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 1076 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 1077 } 1078 1079 static void xive_source_realize(DeviceState *dev, Error **errp) 1080 { 1081 XiveSource *xsrc = XIVE_SOURCE(dev); 1082 1083 assert(xsrc->xive); 1084 1085 if (!xsrc->nr_irqs) { 1086 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1087 return; 1088 } 1089 1090 if (xsrc->esb_shift != XIVE_ESB_4K && 1091 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1092 xsrc->esb_shift != XIVE_ESB_64K && 1093 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1094 error_setg(errp, "Invalid ESB shift setting"); 1095 return; 1096 } 1097 1098 xsrc->status = g_malloc0(xsrc->nr_irqs); 1099 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1100 1101 if (!kvm_irqchip_in_kernel()) { 1102 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1103 &xive_source_esb_ops, xsrc, "xive.esb", 1104 (1ull << xsrc->esb_shift) * xsrc->nr_irqs); 1105 } 1106 1107 qemu_register_reset(xive_source_reset, dev); 1108 } 1109 1110 static const VMStateDescription vmstate_xive_source = { 1111 .name = TYPE_XIVE_SOURCE, 1112 .version_id = 1, 1113 .minimum_version_id = 1, 1114 .fields = (VMStateField[]) { 1115 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1116 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1117 VMSTATE_END_OF_LIST() 1118 }, 1119 }; 1120 1121 /* 1122 * The default XIVE interrupt source setting for the ESB MMIOs is two 1123 * 64k pages without Store EOI, to be in sync with KVM. 1124 */ 1125 static Property xive_source_properties[] = { 1126 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1127 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1128 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1129 DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, 1130 XiveNotifier *), 1131 DEFINE_PROP_END_OF_LIST(), 1132 }; 1133 1134 static void xive_source_class_init(ObjectClass *klass, void *data) 1135 { 1136 DeviceClass *dc = DEVICE_CLASS(klass); 1137 1138 dc->desc = "XIVE Interrupt Source"; 1139 dc->props = xive_source_properties; 1140 dc->realize = xive_source_realize; 1141 dc->vmsd = &vmstate_xive_source; 1142 /* 1143 * Reason: part of XIVE interrupt controller, needs to be wired up, 1144 * e.g. by spapr_xive_instance_init(). 1145 */ 1146 dc->user_creatable = false; 1147 } 1148 1149 static const TypeInfo xive_source_info = { 1150 .name = TYPE_XIVE_SOURCE, 1151 .parent = TYPE_DEVICE, 1152 .instance_size = sizeof(XiveSource), 1153 .class_init = xive_source_class_init, 1154 }; 1155 1156 /* 1157 * XiveEND helpers 1158 */ 1159 1160 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1161 { 1162 uint64_t qaddr_base = xive_end_qaddr(end); 1163 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1164 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1165 uint32_t qentries = 1 << (qsize + 10); 1166 int i; 1167 1168 /* 1169 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1170 */ 1171 monitor_printf(mon, " [ "); 1172 qindex = (qindex - (width - 1)) & (qentries - 1); 1173 for (i = 0; i < width; i++) { 1174 uint64_t qaddr = qaddr_base + (qindex << 2); 1175 uint32_t qdata = -1; 1176 1177 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 1178 sizeof(qdata))) { 1179 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1180 HWADDR_PRIx "\n", qaddr); 1181 return; 1182 } 1183 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1184 be32_to_cpu(qdata)); 1185 qindex = (qindex + 1) & (qentries - 1); 1186 } 1187 monitor_printf(mon, "]"); 1188 } 1189 1190 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1191 { 1192 uint64_t qaddr_base = xive_end_qaddr(end); 1193 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1194 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1195 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1196 uint32_t qentries = 1 << (qsize + 10); 1197 1198 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1199 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1200 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1201 uint8_t pq; 1202 1203 if (!xive_end_is_valid(end)) { 1204 return; 1205 } 1206 1207 pq = xive_get_field32(END_W1_ESn, end->w1); 1208 1209 monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1210 end_idx, 1211 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1212 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1213 xive_end_is_valid(end) ? 'v' : '-', 1214 xive_end_is_enqueue(end) ? 'q' : '-', 1215 xive_end_is_notify(end) ? 'n' : '-', 1216 xive_end_is_backlog(end) ? 'b' : '-', 1217 xive_end_is_escalate(end) ? 'e' : '-', 1218 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1219 xive_end_is_silent_escalation(end) ? 's' : '-', 1220 priority, nvt_blk, nvt_idx); 1221 1222 if (qaddr_base) { 1223 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1224 qaddr_base, qindex, qentries, qgen); 1225 xive_end_queue_pic_print_info(end, 6, mon); 1226 } 1227 monitor_printf(mon, "\n"); 1228 } 1229 1230 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1231 { 1232 uint64_t qaddr_base = xive_end_qaddr(end); 1233 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1234 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1235 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1236 1237 uint64_t qaddr = qaddr_base + (qindex << 2); 1238 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1239 uint32_t qentries = 1 << (qsize + 10); 1240 1241 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) { 1242 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1243 HWADDR_PRIx "\n", qaddr); 1244 return; 1245 } 1246 1247 qindex = (qindex + 1) & (qentries - 1); 1248 if (qindex == 0) { 1249 qgen ^= 1; 1250 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1251 } 1252 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1253 } 1254 1255 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, 1256 Monitor *mon) 1257 { 1258 XiveEAS *eas = (XiveEAS *) &end->w4; 1259 uint8_t pq; 1260 1261 if (!xive_end_is_escalate(end)) { 1262 return; 1263 } 1264 1265 pq = xive_get_field32(END_W1_ESe, end->w1); 1266 1267 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1268 end_idx, 1269 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1270 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1271 xive_eas_is_valid(eas) ? 'V' : ' ', 1272 xive_eas_is_masked(eas) ? 'M' : ' ', 1273 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1274 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1275 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1276 } 1277 1278 /* 1279 * XIVE Router (aka. Virtualization Controller or IVRE) 1280 */ 1281 1282 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1283 XiveEAS *eas) 1284 { 1285 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1286 1287 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1288 } 1289 1290 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1291 XiveEND *end) 1292 { 1293 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1294 1295 return xrc->get_end(xrtr, end_blk, end_idx, end); 1296 } 1297 1298 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1299 XiveEND *end, uint8_t word_number) 1300 { 1301 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1302 1303 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1304 } 1305 1306 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1307 XiveNVT *nvt) 1308 { 1309 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1310 1311 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1312 } 1313 1314 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1315 XiveNVT *nvt, uint8_t word_number) 1316 { 1317 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1318 1319 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1320 } 1321 1322 /* 1323 * Encode the HW CAM line in the block group mode format : 1324 * 1325 * chip << 19 | 0000000 0 0001 thread (7Bit) 1326 */ 1327 static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) 1328 { 1329 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1330 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1331 1332 return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f)); 1333 } 1334 1335 /* 1336 * The thread context register words are in big-endian format. 1337 */ 1338 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1339 uint8_t format, 1340 uint8_t nvt_blk, uint32_t nvt_idx, 1341 bool cam_ignore, uint32_t logic_serv) 1342 { 1343 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1344 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1345 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1346 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1347 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1348 1349 /* 1350 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1351 * identifier are ignored in the "CAM" match. 1352 */ 1353 1354 if (format == 0) { 1355 if (cam_ignore == true) { 1356 /* 1357 * F=0 & i=1: Logical server notification (bits ignored at 1358 * the end of the NVT identifier) 1359 */ 1360 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1361 nvt_blk, nvt_idx); 1362 return -1; 1363 } 1364 1365 /* F=0 & i=0: Specific NVT notification */ 1366 1367 /* PHYS ring */ 1368 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1369 cam == xive_tctx_hw_cam_line(tctx)) { 1370 return TM_QW3_HV_PHYS; 1371 } 1372 1373 /* HV POOL ring */ 1374 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1375 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1376 return TM_QW2_HV_POOL; 1377 } 1378 1379 /* OS ring */ 1380 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1381 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1382 return TM_QW1_OS; 1383 } 1384 } else { 1385 /* F=1 : User level Event-Based Branch (EBB) notification */ 1386 1387 /* USER ring */ 1388 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1389 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1390 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1391 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1392 return TM_QW0_USER; 1393 } 1394 } 1395 return -1; 1396 } 1397 1398 /* 1399 * This is our simple Xive Presenter Engine model. It is merged in the 1400 * Router as it does not require an extra object. 1401 * 1402 * It receives notification requests sent by the IVRE to find one 1403 * matching NVT (or more) dispatched on the processor threads. In case 1404 * of a single NVT notification, the process is abreviated and the 1405 * thread is signaled if a match is found. In case of a logical server 1406 * notification (bits ignored at the end of the NVT identifier), the 1407 * IVPE and IVRE select a winning thread using different filters. This 1408 * involves 2 or 3 exchanges on the PowerBus that the model does not 1409 * support. 1410 * 1411 * The parameters represent what is sent on the PowerBus 1412 */ 1413 static bool xive_presenter_notify(uint8_t format, 1414 uint8_t nvt_blk, uint32_t nvt_idx, 1415 bool cam_ignore, uint8_t priority, 1416 uint32_t logic_serv) 1417 { 1418 XiveFabric *xfb = XIVE_FABRIC(qdev_get_machine()); 1419 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb); 1420 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1421 int count; 1422 1423 /* 1424 * Ask the machine to scan the interrupt controllers for a match 1425 */ 1426 count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore, 1427 priority, logic_serv, &match); 1428 if (count < 0) { 1429 return false; 1430 } 1431 1432 /* handle CPU exception delivery */ 1433 if (count) { 1434 xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(priority)); 1435 } 1436 1437 return !!count; 1438 } 1439 1440 /* 1441 * Notification using the END ESe/ESn bit (Event State Buffer for 1442 * escalation and notification). Profide futher coalescing in the 1443 * Router. 1444 */ 1445 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1446 uint32_t end_idx, XiveEND *end, 1447 uint32_t end_esmask) 1448 { 1449 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1450 bool notify = xive_esb_trigger(&pq); 1451 1452 if (pq != xive_get_field32(end_esmask, end->w1)) { 1453 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1454 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1455 } 1456 1457 /* ESe/n[Q]=1 : end of notification */ 1458 return notify; 1459 } 1460 1461 /* 1462 * An END trigger can come from an event trigger (IPI or HW) or from 1463 * another chip. We don't model the PowerBus but the END trigger 1464 * message has the same parameters than in the function below. 1465 */ 1466 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1467 uint32_t end_idx, uint32_t end_data) 1468 { 1469 XiveEND end; 1470 uint8_t priority; 1471 uint8_t format; 1472 uint8_t nvt_blk; 1473 uint32_t nvt_idx; 1474 XiveNVT nvt; 1475 bool found; 1476 1477 /* END cache lookup */ 1478 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1479 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1480 end_idx); 1481 return; 1482 } 1483 1484 if (!xive_end_is_valid(&end)) { 1485 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1486 end_blk, end_idx); 1487 return; 1488 } 1489 1490 if (xive_end_is_enqueue(&end)) { 1491 xive_end_enqueue(&end, end_data); 1492 /* Enqueuing event data modifies the EQ toggle and index */ 1493 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1494 } 1495 1496 /* 1497 * When the END is silent, we skip the notification part. 1498 */ 1499 if (xive_end_is_silent_escalation(&end)) { 1500 goto do_escalation; 1501 } 1502 1503 /* 1504 * The W7 format depends on the F bit in W6. It defines the type 1505 * of the notification : 1506 * 1507 * F=0 : single or multiple NVT notification 1508 * F=1 : User level Event-Based Branch (EBB) notification, no 1509 * priority 1510 */ 1511 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1512 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1513 1514 /* The END is masked */ 1515 if (format == 0 && priority == 0xff) { 1516 return; 1517 } 1518 1519 /* 1520 * Check the END ESn (Event State Buffer for notification) for 1521 * even futher coalescing in the Router 1522 */ 1523 if (!xive_end_is_notify(&end)) { 1524 /* ESn[Q]=1 : end of notification */ 1525 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1526 &end, END_W1_ESn)) { 1527 return; 1528 } 1529 } 1530 1531 /* 1532 * Follows IVPE notification 1533 */ 1534 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1535 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1536 1537 /* NVT cache lookup */ 1538 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1539 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1540 nvt_blk, nvt_idx); 1541 return; 1542 } 1543 1544 if (!xive_nvt_is_valid(&nvt)) { 1545 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1546 nvt_blk, nvt_idx); 1547 return; 1548 } 1549 1550 found = xive_presenter_notify(format, nvt_blk, nvt_idx, 1551 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1552 priority, 1553 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1554 1555 /* TODO: Auto EOI. */ 1556 1557 if (found) { 1558 return; 1559 } 1560 1561 /* 1562 * If no matching NVT is dispatched on a HW thread : 1563 * - specific VP: update the NVT structure if backlog is activated 1564 * - logical server : forward request to IVPE (not supported) 1565 */ 1566 if (xive_end_is_backlog(&end)) { 1567 uint8_t ipb; 1568 1569 if (format == 1) { 1570 qemu_log_mask(LOG_GUEST_ERROR, 1571 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1572 end_blk, end_idx); 1573 return; 1574 } 1575 /* 1576 * Record the IPB in the associated NVT structure for later 1577 * use. The presenter will resend the interrupt when the vCPU 1578 * is dispatched again on a HW thread. 1579 */ 1580 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priority); 1581 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); 1582 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1583 1584 /* 1585 * On HW, follows a "Broadcast Backlog" to IVPEs 1586 */ 1587 } 1588 1589 do_escalation: 1590 /* 1591 * If activated, escalate notification using the ESe PQ bits and 1592 * the EAS in w4-5 1593 */ 1594 if (!xive_end_is_escalate(&end)) { 1595 return; 1596 } 1597 1598 /* 1599 * Check the END ESe (Event State Buffer for escalation) for even 1600 * futher coalescing in the Router 1601 */ 1602 if (!xive_end_is_uncond_escalation(&end)) { 1603 /* ESe[Q]=1 : end of notification */ 1604 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1605 &end, END_W1_ESe)) { 1606 return; 1607 } 1608 } 1609 1610 /* 1611 * The END trigger becomes an Escalation trigger 1612 */ 1613 xive_router_end_notify(xrtr, 1614 xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1615 xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1616 xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1617 } 1618 1619 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 1620 { 1621 XiveRouter *xrtr = XIVE_ROUTER(xn); 1622 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1623 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1624 XiveEAS eas; 1625 1626 /* EAS cache lookup */ 1627 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1628 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1629 return; 1630 } 1631 1632 /* 1633 * The IVRE checks the State Bit Cache at this point. We skip the 1634 * SBC lookup because the state bits of the sources are modeled 1635 * internally in QEMU. 1636 */ 1637 1638 if (!xive_eas_is_valid(&eas)) { 1639 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1640 return; 1641 } 1642 1643 if (xive_eas_is_masked(&eas)) { 1644 /* Notification completed */ 1645 return; 1646 } 1647 1648 /* 1649 * The event trigger becomes an END trigger 1650 */ 1651 xive_router_end_notify(xrtr, 1652 xive_get_field64(EAS_END_BLOCK, eas.w), 1653 xive_get_field64(EAS_END_INDEX, eas.w), 1654 xive_get_field64(EAS_END_DATA, eas.w)); 1655 } 1656 1657 static void xive_router_class_init(ObjectClass *klass, void *data) 1658 { 1659 DeviceClass *dc = DEVICE_CLASS(klass); 1660 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1661 1662 dc->desc = "XIVE Router Engine"; 1663 xnc->notify = xive_router_notify; 1664 } 1665 1666 static const TypeInfo xive_router_info = { 1667 .name = TYPE_XIVE_ROUTER, 1668 .parent = TYPE_SYS_BUS_DEVICE, 1669 .abstract = true, 1670 .class_size = sizeof(XiveRouterClass), 1671 .class_init = xive_router_class_init, 1672 .interfaces = (InterfaceInfo[]) { 1673 { TYPE_XIVE_NOTIFIER }, 1674 { TYPE_XIVE_PRESENTER }, 1675 { } 1676 } 1677 }; 1678 1679 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1680 { 1681 if (!xive_eas_is_valid(eas)) { 1682 return; 1683 } 1684 1685 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1686 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1687 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1688 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1689 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1690 } 1691 1692 /* 1693 * END ESB MMIO loads 1694 */ 1695 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1696 { 1697 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1698 uint32_t offset = addr & 0xFFF; 1699 uint8_t end_blk; 1700 uint32_t end_idx; 1701 XiveEND end; 1702 uint32_t end_esmask; 1703 uint8_t pq; 1704 uint64_t ret = -1; 1705 1706 end_blk = xsrc->block_id; 1707 end_idx = addr >> (xsrc->esb_shift + 1); 1708 1709 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1710 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1711 end_idx); 1712 return -1; 1713 } 1714 1715 if (!xive_end_is_valid(&end)) { 1716 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1717 end_blk, end_idx); 1718 return -1; 1719 } 1720 1721 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1722 pq = xive_get_field32(end_esmask, end.w1); 1723 1724 switch (offset) { 1725 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1726 ret = xive_esb_eoi(&pq); 1727 1728 /* Forward the source event notification for routing ?? */ 1729 break; 1730 1731 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1732 ret = pq; 1733 break; 1734 1735 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1736 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1737 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1738 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1739 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1740 break; 1741 default: 1742 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1743 offset); 1744 return -1; 1745 } 1746 1747 if (pq != xive_get_field32(end_esmask, end.w1)) { 1748 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1749 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1750 } 1751 1752 return ret; 1753 } 1754 1755 /* 1756 * END ESB MMIO stores are invalid 1757 */ 1758 static void xive_end_source_write(void *opaque, hwaddr addr, 1759 uint64_t value, unsigned size) 1760 { 1761 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1762 HWADDR_PRIx"\n", addr); 1763 } 1764 1765 static const MemoryRegionOps xive_end_source_ops = { 1766 .read = xive_end_source_read, 1767 .write = xive_end_source_write, 1768 .endianness = DEVICE_BIG_ENDIAN, 1769 .valid = { 1770 .min_access_size = 8, 1771 .max_access_size = 8, 1772 }, 1773 .impl = { 1774 .min_access_size = 8, 1775 .max_access_size = 8, 1776 }, 1777 }; 1778 1779 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1780 { 1781 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1782 1783 assert(xsrc->xrtr); 1784 1785 if (!xsrc->nr_ends) { 1786 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1787 return; 1788 } 1789 1790 if (xsrc->esb_shift != XIVE_ESB_4K && 1791 xsrc->esb_shift != XIVE_ESB_64K) { 1792 error_setg(errp, "Invalid ESB shift setting"); 1793 return; 1794 } 1795 1796 /* 1797 * Each END is assigned an even/odd pair of MMIO pages, the even page 1798 * manages the ESn field while the odd page manages the ESe field. 1799 */ 1800 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1801 &xive_end_source_ops, xsrc, "xive.end", 1802 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1803 } 1804 1805 static Property xive_end_source_properties[] = { 1806 DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0), 1807 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1808 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1809 DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, 1810 XiveRouter *), 1811 DEFINE_PROP_END_OF_LIST(), 1812 }; 1813 1814 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1815 { 1816 DeviceClass *dc = DEVICE_CLASS(klass); 1817 1818 dc->desc = "XIVE END Source"; 1819 dc->props = xive_end_source_properties; 1820 dc->realize = xive_end_source_realize; 1821 /* 1822 * Reason: part of XIVE interrupt controller, needs to be wired up, 1823 * e.g. by spapr_xive_instance_init(). 1824 */ 1825 dc->user_creatable = false; 1826 } 1827 1828 static const TypeInfo xive_end_source_info = { 1829 .name = TYPE_XIVE_END_SOURCE, 1830 .parent = TYPE_DEVICE, 1831 .instance_size = sizeof(XiveENDSource), 1832 .class_init = xive_end_source_class_init, 1833 }; 1834 1835 /* 1836 * XIVE Notifier 1837 */ 1838 static const TypeInfo xive_notifier_info = { 1839 .name = TYPE_XIVE_NOTIFIER, 1840 .parent = TYPE_INTERFACE, 1841 .class_size = sizeof(XiveNotifierClass), 1842 }; 1843 1844 /* 1845 * XIVE Presenter 1846 */ 1847 static const TypeInfo xive_presenter_info = { 1848 .name = TYPE_XIVE_PRESENTER, 1849 .parent = TYPE_INTERFACE, 1850 .class_size = sizeof(XivePresenterClass), 1851 }; 1852 1853 /* 1854 * XIVE Fabric 1855 */ 1856 static const TypeInfo xive_fabric_info = { 1857 .name = TYPE_XIVE_FABRIC, 1858 .parent = TYPE_INTERFACE, 1859 .class_size = sizeof(XiveFabricClass), 1860 }; 1861 1862 static void xive_register_types(void) 1863 { 1864 type_register_static(&xive_fabric_info); 1865 type_register_static(&xive_source_info); 1866 type_register_static(&xive_notifier_info); 1867 type_register_static(&xive_presenter_info); 1868 type_register_static(&xive_router_info); 1869 type_register_static(&xive_end_source_info); 1870 type_register_static(&xive_tctx_info); 1871 } 1872 1873 type_init(xive_register_types) 1874