1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/log.h" 11 #include "qemu/module.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "system/cpus.h" 15 #include "system/dma.h" 16 #include "system/reset.h" 17 #include "hw/qdev-properties.h" 18 #include "migration/vmstate.h" 19 #include "hw/irq.h" 20 #include "hw/ppc/xive.h" 21 #include "hw/ppc/xive2.h" 22 #include "hw/ppc/xive_regs.h" 23 #include "trace.h" 24 25 /* 26 * XIVE Thread Interrupt Management context 27 */ 28 29 30 static uint8_t exception_mask(uint8_t ring) 31 { 32 switch (ring) { 33 case TM_QW1_OS: 34 return TM_QW1_NSR_EO; 35 case TM_QW3_HV_PHYS: 36 return TM_QW3_NSR_HE; 37 default: 38 g_assert_not_reached(); 39 } 40 } 41 42 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 43 { 44 switch (ring) { 45 case TM_QW0_USER: 46 return 0; /* Not supported */ 47 case TM_QW1_OS: 48 return tctx->os_output; 49 case TM_QW2_HV_POOL: 50 case TM_QW3_HV_PHYS: 51 return tctx->hv_output; 52 default: 53 return 0; 54 } 55 } 56 57 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 58 { 59 uint8_t *regs = &tctx->regs[ring]; 60 uint8_t nsr = regs[TM_NSR]; 61 uint8_t mask = exception_mask(ring); 62 63 qemu_irq_lower(xive_tctx_output(tctx, ring)); 64 65 if (regs[TM_NSR] & mask) { 66 uint8_t cppr = regs[TM_PIPR]; 67 uint8_t alt_ring; 68 uint8_t *alt_regs; 69 70 /* POOL interrupt uses IPB in QW2, POOL ring */ 71 if ((ring == TM_QW3_HV_PHYS) && (nsr & (TM_QW3_NSR_HE_POOL << 6))) { 72 alt_ring = TM_QW2_HV_POOL; 73 } else { 74 alt_ring = ring; 75 } 76 alt_regs = &tctx->regs[alt_ring]; 77 78 regs[TM_CPPR] = cppr; 79 80 /* Reset the pending buffer bit */ 81 alt_regs[TM_IPB] &= ~xive_priority_to_ipb(cppr); 82 83 /* Drop Exception bit */ 84 regs[TM_NSR] &= ~mask; 85 86 trace_xive_tctx_accept(tctx->cs->cpu_index, alt_ring, 87 alt_regs[TM_IPB], regs[TM_PIPR], 88 regs[TM_CPPR], regs[TM_NSR]); 89 } 90 91 return ((uint64_t)nsr << 8) | regs[TM_CPPR]; 92 } 93 94 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 95 { 96 /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ 97 uint8_t alt_ring = (ring == TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : ring; 98 uint8_t *alt_regs = &tctx->regs[alt_ring]; 99 uint8_t *regs = &tctx->regs[ring]; 100 101 if (alt_regs[TM_PIPR] < alt_regs[TM_CPPR]) { 102 switch (ring) { 103 case TM_QW1_OS: 104 regs[TM_NSR] |= TM_QW1_NSR_EO; 105 break; 106 case TM_QW2_HV_POOL: 107 alt_regs[TM_NSR] = (TM_QW3_NSR_HE_POOL << 6); 108 break; 109 case TM_QW3_HV_PHYS: 110 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 111 break; 112 default: 113 g_assert_not_reached(); 114 } 115 trace_xive_tctx_notify(tctx->cs->cpu_index, ring, 116 regs[TM_IPB], alt_regs[TM_PIPR], 117 alt_regs[TM_CPPR], alt_regs[TM_NSR]); 118 qemu_irq_raise(xive_tctx_output(tctx, ring)); 119 } 120 } 121 122 void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring) 123 { 124 /* 125 * Lower the External interrupt. Used when pulling a context. It is 126 * necessary to avoid catching it in the higher privilege context. It 127 * should be raised again when re-pushing the lower privilege context. 128 */ 129 qemu_irq_lower(xive_tctx_output(tctx, ring)); 130 } 131 132 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 133 { 134 uint8_t *regs = &tctx->regs[ring]; 135 uint8_t pipr_min; 136 uint8_t ring_min; 137 138 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, 139 regs[TM_IPB], regs[TM_PIPR], 140 cppr, regs[TM_NSR]); 141 142 if (cppr > XIVE_PRIORITY_MAX) { 143 cppr = 0xff; 144 } 145 146 tctx->regs[ring + TM_CPPR] = cppr; 147 148 /* 149 * Recompute the PIPR based on local pending interrupts. The PHYS 150 * ring must take the minimum of both the PHYS and POOL PIPR values. 151 */ 152 pipr_min = xive_ipb_to_pipr(regs[TM_IPB]); 153 ring_min = ring; 154 155 /* PHYS updates also depend on POOL values */ 156 if (ring == TM_QW3_HV_PHYS) { 157 uint8_t *pool_regs = &tctx->regs[TM_QW2_HV_POOL]; 158 159 /* POOL values only matter if POOL ctx is valid */ 160 if (pool_regs[TM_WORD2] & 0x80) { 161 162 uint8_t pool_pipr = xive_ipb_to_pipr(pool_regs[TM_IPB]); 163 164 /* 165 * Determine highest priority interrupt and 166 * remember which ring has it. 167 */ 168 if (pool_pipr < pipr_min) { 169 pipr_min = pool_pipr; 170 ring_min = TM_QW2_HV_POOL; 171 } 172 } 173 } 174 175 regs[TM_PIPR] = pipr_min; 176 177 /* CPPR has changed, check if we need to raise a pending exception */ 178 xive_tctx_notify(tctx, ring_min); 179 } 180 181 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) 182 { 183 uint8_t *regs = &tctx->regs[ring]; 184 185 regs[TM_IPB] |= ipb; 186 regs[TM_PIPR] = xive_ipb_to_pipr(regs[TM_IPB]); 187 xive_tctx_notify(tctx, ring); 188 } 189 190 /* 191 * XIVE Thread Interrupt Management Area (TIMA) 192 */ 193 194 static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 195 hwaddr offset, uint64_t value, unsigned size) 196 { 197 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 198 } 199 200 static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx, 201 hwaddr offset, unsigned size) 202 { 203 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 204 } 205 206 static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 207 hwaddr offset, unsigned size) 208 { 209 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 210 uint32_t qw2w2; 211 212 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 213 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 214 return qw2w2; 215 } 216 217 static uint64_t xive_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, 218 hwaddr offset, unsigned size) 219 { 220 uint8_t qw3b8_prev = tctx->regs[TM_QW3_HV_PHYS + TM_WORD2]; 221 uint8_t qw3b8; 222 223 qw3b8 = qw3b8_prev & ~TM_QW3B8_VT; 224 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = qw3b8; 225 return qw3b8; 226 } 227 228 static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 229 uint64_t value, unsigned size) 230 { 231 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 232 } 233 234 static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, 235 hwaddr offset, unsigned size) 236 { 237 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 238 } 239 240 /* 241 * Define an access map for each page of the TIMA that we will use in 242 * the memory region ops to filter values when doing loads and stores 243 * of raw registers values 244 * 245 * Registers accessibility bits : 246 * 247 * 0x0 - no access 248 * 0x1 - write only 249 * 0x2 - read only 250 * 0x3 - read/write 251 */ 252 253 static const uint8_t xive_tm_hw_view[] = { 254 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 255 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 256 0, 0, 3, 3, 0, 3, 3, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 257 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 258 }; 259 260 static const uint8_t xive_tm_hv_view[] = { 261 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 262 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 263 0, 0, 3, 3, 0, 3, 3, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 264 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 265 }; 266 267 static const uint8_t xive_tm_os_view[] = { 268 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 269 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 270 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 271 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 272 }; 273 274 static const uint8_t xive_tm_user_view[] = { 275 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 276 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 277 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 278 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 279 }; 280 281 /* 282 * Overall TIMA access map for the thread interrupt management context 283 * registers 284 */ 285 static const uint8_t *xive_tm_views[] = { 286 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 287 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 288 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 289 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 290 }; 291 292 /* 293 * Computes a register access mask for a given offset in the TIMA 294 */ 295 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 296 { 297 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 298 uint8_t reg_offset = offset & TM_REG_OFFSET; 299 uint8_t reg_mask = write ? 0x1 : 0x2; 300 uint64_t mask = 0x0; 301 int i; 302 303 for (i = 0; i < size; i++) { 304 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 305 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 306 } 307 } 308 309 return mask; 310 } 311 312 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 313 unsigned size) 314 { 315 uint8_t ring_offset = offset & TM_RING_OFFSET; 316 uint8_t reg_offset = offset & TM_REG_OFFSET; 317 uint64_t mask = xive_tm_mask(offset, size, true); 318 int i; 319 320 /* 321 * Only 4 or 8 bytes stores are allowed and the User ring is 322 * excluded 323 */ 324 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 325 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 326 HWADDR_PRIx"\n", offset); 327 return; 328 } 329 330 /* 331 * Use the register offset for the raw values and filter out 332 * reserved values 333 */ 334 for (i = 0; i < size; i++) { 335 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 336 if (byte_mask) { 337 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 338 byte_mask; 339 } 340 } 341 } 342 343 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 344 { 345 uint8_t ring_offset = offset & TM_RING_OFFSET; 346 uint8_t reg_offset = offset & TM_REG_OFFSET; 347 uint64_t mask = xive_tm_mask(offset, size, false); 348 uint64_t ret; 349 int i; 350 351 /* 352 * Only 4 or 8 bytes loads are allowed and the User ring is 353 * excluded 354 */ 355 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 356 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 357 HWADDR_PRIx"\n", offset); 358 return -1; 359 } 360 361 /* Use the register offset for the raw values */ 362 ret = 0; 363 for (i = 0; i < size; i++) { 364 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 365 } 366 367 /* filter out reserved values */ 368 return ret & mask; 369 } 370 371 /* 372 * The TM context is mapped twice within each page. Stores and loads 373 * to the first mapping below 2K write and read the specified values 374 * without modification. The second mapping above 2K performs specific 375 * state changes (side effects) in addition to setting/returning the 376 * interrupt management area context of the processor thread. 377 */ 378 static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx, 379 hwaddr offset, unsigned size) 380 { 381 return xive_tctx_accept(tctx, TM_QW1_OS); 382 } 383 384 static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 385 hwaddr offset, uint64_t value, unsigned size) 386 { 387 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 388 } 389 390 static void xive_tctx_set_lgs(XiveTCTX *tctx, uint8_t ring, uint8_t lgs) 391 { 392 uint8_t *regs = &tctx->regs[ring]; 393 394 regs[TM_LGS] = lgs; 395 } 396 397 static void xive_tm_set_os_lgs(XivePresenter *xptr, XiveTCTX *tctx, 398 hwaddr offset, uint64_t value, unsigned size) 399 { 400 xive_tctx_set_lgs(tctx, TM_QW1_OS, value & 0xff); 401 } 402 403 /* 404 * Adjust the IPB to allow a CPU to process event queues of other 405 * priorities during one physical interrupt cycle. 406 */ 407 static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, 408 hwaddr offset, uint64_t value, unsigned size) 409 { 410 xive_tctx_ipb_update(tctx, TM_QW1_OS, xive_priority_to_ipb(value & 0xff)); 411 } 412 413 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, 414 uint32_t *nvt_idx, bool *vo) 415 { 416 if (nvt_blk) { 417 *nvt_blk = xive_nvt_blk(cam); 418 } 419 if (nvt_idx) { 420 *nvt_idx = xive_nvt_idx(cam); 421 } 422 if (vo) { 423 *vo = !!(cam & TM_QW1W2_VO); 424 } 425 } 426 427 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk, 428 uint32_t *nvt_idx, bool *vo) 429 { 430 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 431 uint32_t cam = be32_to_cpu(qw1w2); 432 433 xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo); 434 return qw1w2; 435 } 436 437 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) 438 { 439 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 440 } 441 442 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 443 hwaddr offset, unsigned size) 444 { 445 uint32_t qw1w2; 446 uint32_t qw1w2_new; 447 uint8_t nvt_blk; 448 uint32_t nvt_idx; 449 bool vo; 450 451 qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); 452 453 if (!vo) { 454 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n", 455 nvt_blk, nvt_idx); 456 } 457 458 /* Invalidate CAM line */ 459 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); 460 xive_tctx_set_os_cam(tctx, qw1w2_new); 461 462 xive_tctx_reset_signal(tctx, TM_QW1_OS); 463 return qw1w2; 464 } 465 466 static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx, 467 uint8_t nvt_blk, uint32_t nvt_idx) 468 { 469 XiveNVT nvt; 470 uint8_t ipb; 471 472 /* 473 * Grab the associated NVT to pull the pending bits, and merge 474 * them with the IPB of the thread interrupt context registers 475 */ 476 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 477 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n", 478 nvt_blk, nvt_idx); 479 return; 480 } 481 482 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4); 483 484 if (ipb) { 485 /* Reset the NVT value */ 486 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0); 487 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 488 } 489 /* 490 * Always call xive_tctx_ipb_update(). Even if there were no 491 * escalation triggered, there could be a pending interrupt which 492 * was saved when the context was pulled and that we need to take 493 * into account by recalculating the PIPR (which is not 494 * saved/restored). 495 * It will also raise the External interrupt signal if needed. 496 */ 497 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); 498 } 499 500 /* 501 * Updating the OS CAM line can trigger a resend of interrupt 502 */ 503 static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 504 hwaddr offset, uint64_t value, unsigned size) 505 { 506 uint32_t cam = value; 507 uint32_t qw1w2 = cpu_to_be32(cam); 508 uint8_t nvt_blk; 509 uint32_t nvt_idx; 510 bool vo; 511 512 xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); 513 514 /* First update the registers */ 515 xive_tctx_set_os_cam(tctx, qw1w2); 516 517 /* Check the interrupt pending bits */ 518 if (vo) { 519 xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); 520 } 521 } 522 523 static uint32_t xive_presenter_get_config(XivePresenter *xptr) 524 { 525 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 526 527 return xpc->get_config(xptr); 528 } 529 530 /* 531 * Define a mapping of "special" operations depending on the TIMA page 532 * offset and the size of the operation. 533 */ 534 typedef struct XiveTmOp { 535 uint8_t page_offset; 536 uint32_t op_offset; 537 unsigned size; 538 void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, 539 hwaddr offset, 540 uint64_t value, unsigned size); 541 uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 542 unsigned size); 543 } XiveTmOp; 544 545 static const XiveTmOp xive_tm_operations[] = { 546 /* 547 * MMIOs below 2K : raw values and special operations without side 548 * effects 549 */ 550 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, 551 NULL }, 552 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, 553 NULL }, 554 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, 555 NULL }, 556 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, 557 NULL }, 558 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, 559 xive_tm_vt_poll }, 560 561 /* MMIOs above 2K : special operations with side effects */ 562 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, 563 xive_tm_ack_os_reg }, 564 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, 565 NULL }, 566 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, 567 xive_tm_pull_os_ctx }, 568 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, 569 xive_tm_pull_os_ctx }, 570 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, 571 xive_tm_ack_hv_reg }, 572 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, 573 xive_tm_pull_pool_ctx }, 574 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, 575 xive_tm_pull_pool_ctx }, 576 { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL, 577 xive_tm_pull_phys_ctx }, 578 }; 579 580 static const XiveTmOp xive2_tm_operations[] = { 581 /* 582 * MMIOs below 2K : raw values and special operations without side 583 * effects 584 */ 585 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, 586 NULL }, 587 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx, 588 NULL }, 589 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 8, xive2_tm_push_os_ctx, 590 NULL }, 591 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, xive_tm_set_os_lgs, 592 NULL }, 593 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, 594 NULL }, 595 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, 596 NULL }, 597 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, 598 xive_tm_vt_poll }, 599 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_T, 1, xive2_tm_set_hv_target, 600 NULL }, 601 602 /* MMIOs above 2K : special operations with side effects */ 603 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, 604 xive_tm_ack_os_reg }, 605 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, 606 NULL }, 607 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_G2, 4, NULL, 608 xive2_tm_pull_os_ctx }, 609 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, 610 xive2_tm_pull_os_ctx }, 611 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, 612 xive2_tm_pull_os_ctx }, 613 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, 614 xive_tm_ack_hv_reg }, 615 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX_G2, 4, NULL, 616 xive_tm_pull_pool_ctx }, 617 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, 618 xive_tm_pull_pool_ctx }, 619 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, 620 xive_tm_pull_pool_ctx }, 621 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_OL, 1, xive2_tm_pull_os_ctx_ol, 622 NULL }, 623 { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_G2, 4, NULL, 624 xive_tm_pull_phys_ctx }, 625 { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL, 626 xive_tm_pull_phys_ctx }, 627 { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_OL, 1, xive2_tm_pull_phys_ctx_ol, 628 NULL }, 629 }; 630 631 static const XiveTmOp *xive_tm_find_op(XivePresenter *xptr, hwaddr offset, 632 unsigned size, bool write) 633 { 634 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 635 uint32_t op_offset = offset & TM_ADDRESS_MASK; 636 const XiveTmOp *tm_ops; 637 int i, tm_ops_count; 638 uint32_t cfg; 639 640 cfg = xive_presenter_get_config(xptr); 641 if (cfg & XIVE_PRESENTER_GEN1_TIMA_OS) { 642 tm_ops = xive_tm_operations; 643 tm_ops_count = ARRAY_SIZE(xive_tm_operations); 644 } else { 645 tm_ops = xive2_tm_operations; 646 tm_ops_count = ARRAY_SIZE(xive2_tm_operations); 647 } 648 649 for (i = 0; i < tm_ops_count; i++) { 650 const XiveTmOp *xto = &tm_ops[i]; 651 652 /* Accesses done from a more privileged TIMA page is allowed */ 653 if (xto->page_offset >= page_offset && 654 xto->op_offset == op_offset && 655 xto->size == size && 656 ((write && xto->write_handler) || (!write && xto->read_handler))) { 657 return xto; 658 } 659 } 660 return NULL; 661 } 662 663 /* 664 * TIMA MMIO handlers 665 */ 666 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 667 uint64_t value, unsigned size) 668 { 669 const XiveTmOp *xto; 670 671 trace_xive_tctx_tm_write(tctx->cs->cpu_index, offset, size, value); 672 673 /* 674 * TODO: check V bit in Q[0-3]W2 675 */ 676 677 /* 678 * First, check for special operations in the 2K region 679 */ 680 if (offset & TM_SPECIAL_OP) { 681 xto = xive_tm_find_op(tctx->xptr, offset, size, true); 682 if (!xto) { 683 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 684 "@%"HWADDR_PRIx"\n", offset); 685 } else { 686 xto->write_handler(xptr, tctx, offset, value, size); 687 } 688 return; 689 } 690 691 /* 692 * Then, for special operations in the region below 2K. 693 */ 694 xto = xive_tm_find_op(tctx->xptr, offset, size, true); 695 if (xto) { 696 xto->write_handler(xptr, tctx, offset, value, size); 697 return; 698 } 699 700 /* 701 * Finish with raw access to the register values 702 */ 703 xive_tm_raw_write(tctx, offset, value, size); 704 } 705 706 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 707 unsigned size) 708 { 709 const XiveTmOp *xto; 710 uint64_t ret; 711 712 /* 713 * TODO: check V bit in Q[0-3]W2 714 */ 715 716 /* 717 * First, check for special operations in the 2K region 718 */ 719 if (offset & TM_SPECIAL_OP) { 720 xto = xive_tm_find_op(tctx->xptr, offset, size, false); 721 if (!xto) { 722 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 723 "@%"HWADDR_PRIx"\n", offset); 724 return -1; 725 } 726 ret = xto->read_handler(xptr, tctx, offset, size); 727 goto out; 728 } 729 730 /* 731 * Then, for special operations in the region below 2K. 732 */ 733 xto = xive_tm_find_op(tctx->xptr, offset, size, false); 734 if (xto) { 735 ret = xto->read_handler(xptr, tctx, offset, size); 736 goto out; 737 } 738 739 /* 740 * Finish with raw access to the register values 741 */ 742 ret = xive_tm_raw_read(tctx, offset, size); 743 out: 744 trace_xive_tctx_tm_read(tctx->cs->cpu_index, offset, size, ret); 745 return ret; 746 } 747 748 static char *xive_tctx_ring_print(uint8_t *ring) 749 { 750 uint32_t w2 = xive_tctx_word2(ring); 751 752 return g_strdup_printf("%02x %02x %02x %02x %02x " 753 "%02x %02x %02x %08x", 754 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 755 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 756 be32_to_cpu(w2)); 757 } 758 759 static const char * const xive_tctx_ring_names[] = { 760 "USER", "OS", "POOL", "PHYS", 761 }; 762 763 /* 764 * kvm_irqchip_in_kernel() will cause the compiler to turn this 765 * info a nop if CONFIG_KVM isn't defined. 766 */ 767 #define xive_in_kernel(xptr) \ 768 (kvm_irqchip_in_kernel() && \ 769 ({ \ 770 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); \ 771 xpc->in_kernel ? xpc->in_kernel(xptr) : false; \ 772 })) 773 774 void xive_tctx_pic_print_info(XiveTCTX *tctx, GString *buf) 775 { 776 int cpu_index; 777 int i; 778 779 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs 780 * are hot plugged or unplugged. 781 */ 782 if (!tctx) { 783 return; 784 } 785 786 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 787 788 if (xive_in_kernel(tctx->xptr)) { 789 Error *local_err = NULL; 790 791 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 792 if (local_err) { 793 error_report_err(local_err); 794 return; 795 } 796 } 797 798 if (xive_presenter_get_config(tctx->xptr) & XIVE_PRESENTER_GEN1_TIMA_OS) { 799 g_string_append_printf(buf, "CPU[%04x]: " 800 "QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 801 " W2\n", cpu_index); 802 } else { 803 g_string_append_printf(buf, "CPU[%04x]: " 804 "QW NSR CPPR IPB LSMFB - LGS T PIPR" 805 " W2\n", cpu_index); 806 } 807 808 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 809 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 810 g_string_append_printf(buf, "CPU[%04x]: %4s %s\n", 811 cpu_index, xive_tctx_ring_names[i], s); 812 g_free(s); 813 } 814 } 815 816 void xive_tctx_reset(XiveTCTX *tctx) 817 { 818 memset(tctx->regs, 0, sizeof(tctx->regs)); 819 820 /* Set some defaults */ 821 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 822 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 823 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 824 if (!(xive_presenter_get_config(tctx->xptr) & 825 XIVE_PRESENTER_GEN1_TIMA_OS)) { 826 tctx->regs[TM_QW1_OS + TM_OGEN] = 2; 827 } 828 829 /* 830 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 831 * CPPR is first set. 832 */ 833 tctx->regs[TM_QW1_OS + TM_PIPR] = 834 xive_ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 835 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 836 xive_ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 837 } 838 839 static void xive_tctx_realize(DeviceState *dev, Error **errp) 840 { 841 XiveTCTX *tctx = XIVE_TCTX(dev); 842 PowerPCCPU *cpu; 843 CPUPPCState *env; 844 845 assert(tctx->cs); 846 assert(tctx->xptr); 847 848 cpu = POWERPC_CPU(tctx->cs); 849 env = &cpu->env; 850 switch (PPC_INPUT(env)) { 851 case PPC_FLAGS_INPUT_POWER9: 852 tctx->hv_output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_HINT); 853 tctx->os_output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_INT); 854 break; 855 856 default: 857 error_setg(errp, "XIVE interrupt controller does not support " 858 "this CPU bus model"); 859 return; 860 } 861 862 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 863 if (xive_in_kernel(tctx->xptr)) { 864 if (kvmppc_xive_cpu_connect(tctx, errp) < 0) { 865 return; 866 } 867 } 868 } 869 870 static int vmstate_xive_tctx_pre_save(void *opaque) 871 { 872 XiveTCTX *tctx = XIVE_TCTX(opaque); 873 Error *local_err = NULL; 874 int ret; 875 876 if (xive_in_kernel(tctx->xptr)) { 877 ret = kvmppc_xive_cpu_get_state(tctx, &local_err); 878 if (ret < 0) { 879 error_report_err(local_err); 880 return ret; 881 } 882 } 883 884 return 0; 885 } 886 887 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 888 { 889 XiveTCTX *tctx = XIVE_TCTX(opaque); 890 Error *local_err = NULL; 891 int ret; 892 893 if (xive_in_kernel(tctx->xptr)) { 894 /* 895 * Required for hotplugged CPU, for which the state comes 896 * after all states of the machine. 897 */ 898 ret = kvmppc_xive_cpu_set_state(tctx, &local_err); 899 if (ret < 0) { 900 error_report_err(local_err); 901 return ret; 902 } 903 } 904 905 return 0; 906 } 907 908 static const VMStateDescription vmstate_xive_tctx = { 909 .name = TYPE_XIVE_TCTX, 910 .version_id = 1, 911 .minimum_version_id = 1, 912 .pre_save = vmstate_xive_tctx_pre_save, 913 .post_load = vmstate_xive_tctx_post_load, 914 .fields = (const VMStateField[]) { 915 VMSTATE_BUFFER(regs, XiveTCTX), 916 VMSTATE_END_OF_LIST() 917 }, 918 }; 919 920 static const Property xive_tctx_properties[] = { 921 DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), 922 DEFINE_PROP_LINK("presenter", XiveTCTX, xptr, TYPE_XIVE_PRESENTER, 923 XivePresenter *), 924 }; 925 926 static void xive_tctx_class_init(ObjectClass *klass, void *data) 927 { 928 DeviceClass *dc = DEVICE_CLASS(klass); 929 930 dc->desc = "XIVE Interrupt Thread Context"; 931 dc->realize = xive_tctx_realize; 932 dc->vmsd = &vmstate_xive_tctx; 933 device_class_set_props(dc, xive_tctx_properties); 934 /* 935 * Reason: part of XIVE interrupt controller, needs to be wired up 936 * by xive_tctx_create(). 937 */ 938 dc->user_creatable = false; 939 } 940 941 static const TypeInfo xive_tctx_info = { 942 .name = TYPE_XIVE_TCTX, 943 .parent = TYPE_DEVICE, 944 .instance_size = sizeof(XiveTCTX), 945 .class_init = xive_tctx_class_init, 946 }; 947 948 Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp) 949 { 950 Object *obj; 951 952 obj = object_new(TYPE_XIVE_TCTX); 953 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj); 954 object_unref(obj); 955 object_property_set_link(obj, "cpu", cpu, &error_abort); 956 object_property_set_link(obj, "presenter", OBJECT(xptr), &error_abort); 957 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 958 object_unparent(obj); 959 return NULL; 960 } 961 return obj; 962 } 963 964 void xive_tctx_destroy(XiveTCTX *tctx) 965 { 966 Object *obj = OBJECT(tctx); 967 968 object_unparent(obj); 969 } 970 971 /* 972 * XIVE ESB helpers 973 */ 974 975 uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 976 { 977 uint8_t old_pq = *pq & 0x3; 978 979 *pq &= ~0x3; 980 *pq |= value & 0x3; 981 982 return old_pq; 983 } 984 985 bool xive_esb_trigger(uint8_t *pq) 986 { 987 uint8_t old_pq = *pq & 0x3; 988 989 switch (old_pq) { 990 case XIVE_ESB_RESET: 991 xive_esb_set(pq, XIVE_ESB_PENDING); 992 return true; 993 case XIVE_ESB_PENDING: 994 case XIVE_ESB_QUEUED: 995 xive_esb_set(pq, XIVE_ESB_QUEUED); 996 return false; 997 case XIVE_ESB_OFF: 998 xive_esb_set(pq, XIVE_ESB_OFF); 999 return false; 1000 default: 1001 g_assert_not_reached(); 1002 } 1003 } 1004 1005 bool xive_esb_eoi(uint8_t *pq) 1006 { 1007 uint8_t old_pq = *pq & 0x3; 1008 1009 switch (old_pq) { 1010 case XIVE_ESB_RESET: 1011 case XIVE_ESB_PENDING: 1012 xive_esb_set(pq, XIVE_ESB_RESET); 1013 return false; 1014 case XIVE_ESB_QUEUED: 1015 xive_esb_set(pq, XIVE_ESB_PENDING); 1016 return true; 1017 case XIVE_ESB_OFF: 1018 xive_esb_set(pq, XIVE_ESB_OFF); 1019 return false; 1020 default: 1021 g_assert_not_reached(); 1022 } 1023 } 1024 1025 /* 1026 * XIVE Interrupt Source (or IVSE) 1027 */ 1028 1029 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 1030 { 1031 assert(srcno < xsrc->nr_irqs); 1032 1033 return xsrc->status[srcno] & 0x3; 1034 } 1035 1036 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 1037 { 1038 assert(srcno < xsrc->nr_irqs); 1039 1040 return xive_esb_set(&xsrc->status[srcno], pq); 1041 } 1042 1043 /* 1044 * Returns whether the event notification should be forwarded. 1045 */ 1046 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 1047 { 1048 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 1049 1050 xive_source_set_asserted(xsrc, srcno, true); 1051 1052 switch (old_pq) { 1053 case XIVE_ESB_RESET: 1054 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 1055 return true; 1056 default: 1057 return false; 1058 } 1059 } 1060 1061 /* 1062 * Sources can be configured with PQ offloading in which case the check 1063 * on the PQ state bits of MSIs is disabled 1064 */ 1065 static bool xive_source_esb_disabled(XiveSource *xsrc, uint32_t srcno) 1066 { 1067 return (xsrc->esb_flags & XIVE_SRC_PQ_DISABLE) && 1068 !xive_source_irq_is_lsi(xsrc, srcno); 1069 } 1070 1071 /* 1072 * Returns whether the event notification should be forwarded. 1073 */ 1074 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 1075 { 1076 bool ret; 1077 1078 assert(srcno < xsrc->nr_irqs); 1079 1080 if (xive_source_esb_disabled(xsrc, srcno)) { 1081 return true; 1082 } 1083 1084 ret = xive_esb_trigger(&xsrc->status[srcno]); 1085 1086 if (xive_source_irq_is_lsi(xsrc, srcno) && 1087 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 1088 qemu_log_mask(LOG_GUEST_ERROR, 1089 "XIVE: queued an event on LSI IRQ %d\n", srcno); 1090 } 1091 1092 return ret; 1093 } 1094 1095 /* 1096 * Returns whether the event notification should be forwarded. 1097 */ 1098 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 1099 { 1100 bool ret; 1101 1102 assert(srcno < xsrc->nr_irqs); 1103 1104 if (xive_source_esb_disabled(xsrc, srcno)) { 1105 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EOI for IRQ %d\n", srcno); 1106 return false; 1107 } 1108 1109 ret = xive_esb_eoi(&xsrc->status[srcno]); 1110 1111 /* 1112 * LSI sources do not set the Q bit but they can still be 1113 * asserted, in which case we should forward a new event 1114 * notification 1115 */ 1116 if (xive_source_irq_is_lsi(xsrc, srcno) && 1117 xive_source_is_asserted(xsrc, srcno)) { 1118 ret = xive_source_lsi_trigger(xsrc, srcno); 1119 } 1120 1121 return ret; 1122 } 1123 1124 /* 1125 * Forward the source event notification to the Router 1126 */ 1127 static void xive_source_notify(XiveSource *xsrc, int srcno) 1128 { 1129 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 1130 bool pq_checked = !xive_source_esb_disabled(xsrc, srcno); 1131 1132 if (xnc->notify) { 1133 xnc->notify(xsrc->xive, srcno, pq_checked); 1134 } 1135 } 1136 1137 /* 1138 * In a two pages ESB MMIO setting, even page is the trigger page, odd 1139 * page is for management 1140 */ 1141 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 1142 { 1143 return !((addr >> shift) & 1); 1144 } 1145 1146 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 1147 { 1148 return xive_source_esb_has_2page(xsrc) && 1149 addr_is_even(addr, xsrc->esb_shift - 1); 1150 } 1151 1152 /* 1153 * ESB MMIO loads 1154 * Trigger page Management/EOI page 1155 * 1156 * ESB MMIO setting 2 pages 1 or 2 pages 1157 * 1158 * 0x000 .. 0x3FF -1 EOI and return 0|1 1159 * 0x400 .. 0x7FF -1 EOI and return 0|1 1160 * 0x800 .. 0xBFF -1 return PQ 1161 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 1162 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 1163 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 1164 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 1165 */ 1166 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 1167 { 1168 XiveSource *xsrc = XIVE_SOURCE(opaque); 1169 uint32_t offset = addr & 0xFFF; 1170 uint32_t srcno = addr >> xsrc->esb_shift; 1171 uint64_t ret = -1; 1172 1173 /* In a two pages ESB MMIO setting, trigger page should not be read */ 1174 if (xive_source_is_trigger_page(xsrc, addr)) { 1175 qemu_log_mask(LOG_GUEST_ERROR, 1176 "XIVE: invalid load on IRQ %d trigger page at " 1177 "0x%"HWADDR_PRIx"\n", srcno, addr); 1178 return -1; 1179 } 1180 1181 switch (offset) { 1182 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1183 ret = xive_source_esb_eoi(xsrc, srcno); 1184 1185 /* Forward the source event notification for routing */ 1186 if (ret) { 1187 xive_source_notify(xsrc, srcno); 1188 } 1189 break; 1190 1191 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1192 ret = xive_source_esb_get(xsrc, srcno); 1193 break; 1194 1195 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1196 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1197 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1198 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1199 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1200 break; 1201 default: 1202 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 1203 offset); 1204 } 1205 1206 trace_xive_source_esb_read(addr, srcno, ret); 1207 1208 return ret; 1209 } 1210 1211 /* 1212 * ESB MMIO stores 1213 * Trigger page Management/EOI page 1214 * 1215 * ESB MMIO setting 2 pages 1 or 2 pages 1216 * 1217 * 0x000 .. 0x3FF Trigger Trigger 1218 * 0x400 .. 0x7FF Trigger EOI 1219 * 0x800 .. 0xBFF Trigger undefined 1220 * 0xC00 .. 0xCFF Trigger PQ=00 1221 * 0xD00 .. 0xDFF Trigger PQ=01 1222 * 0xE00 .. 0xDFF Trigger PQ=10 1223 * 0xF00 .. 0xDFF Trigger PQ=11 1224 */ 1225 static void xive_source_esb_write(void *opaque, hwaddr addr, 1226 uint64_t value, unsigned size) 1227 { 1228 XiveSource *xsrc = XIVE_SOURCE(opaque); 1229 uint32_t offset = addr & 0xFFF; 1230 uint32_t srcno = addr >> xsrc->esb_shift; 1231 bool notify = false; 1232 1233 trace_xive_source_esb_write(addr, srcno, value); 1234 1235 /* In a two pages ESB MMIO setting, trigger page only triggers */ 1236 if (xive_source_is_trigger_page(xsrc, addr)) { 1237 notify = xive_source_esb_trigger(xsrc, srcno); 1238 goto out; 1239 } 1240 1241 switch (offset) { 1242 case 0 ... 0x3FF: 1243 notify = xive_source_esb_trigger(xsrc, srcno); 1244 break; 1245 1246 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 1247 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 1248 qemu_log_mask(LOG_GUEST_ERROR, 1249 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 1250 return; 1251 } 1252 1253 notify = xive_source_esb_eoi(xsrc, srcno); 1254 break; 1255 1256 /* 1257 * This is an internal offset used to inject triggers when the PQ 1258 * state bits are not controlled locally. Such as for LSIs when 1259 * under ABT mode. 1260 */ 1261 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: 1262 notify = true; 1263 break; 1264 1265 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1266 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1267 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1268 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1269 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1270 break; 1271 1272 default: 1273 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 1274 offset); 1275 return; 1276 } 1277 1278 out: 1279 /* Forward the source event notification for routing */ 1280 if (notify) { 1281 xive_source_notify(xsrc, srcno); 1282 } 1283 } 1284 1285 static const MemoryRegionOps xive_source_esb_ops = { 1286 .read = xive_source_esb_read, 1287 .write = xive_source_esb_write, 1288 .endianness = DEVICE_BIG_ENDIAN, 1289 .valid = { 1290 .min_access_size = 1, 1291 .max_access_size = 8, 1292 }, 1293 .impl = { 1294 .min_access_size = 1, 1295 .max_access_size = 8, 1296 }, 1297 }; 1298 1299 void xive_source_set_irq(void *opaque, int srcno, int val) 1300 { 1301 XiveSource *xsrc = XIVE_SOURCE(opaque); 1302 bool notify = false; 1303 1304 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1305 if (val) { 1306 notify = xive_source_lsi_trigger(xsrc, srcno); 1307 } else { 1308 xive_source_set_asserted(xsrc, srcno, false); 1309 } 1310 } else { 1311 if (val) { 1312 notify = xive_source_esb_trigger(xsrc, srcno); 1313 } 1314 } 1315 1316 /* Forward the source event notification for routing */ 1317 if (notify) { 1318 xive_source_notify(xsrc, srcno); 1319 } 1320 } 1321 1322 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, GString *buf) 1323 { 1324 for (unsigned i = 0; i < xsrc->nr_irqs; i++) { 1325 uint8_t pq = xive_source_esb_get(xsrc, i); 1326 1327 if (pq == XIVE_ESB_OFF) { 1328 continue; 1329 } 1330 1331 g_string_append_printf(buf, " %08x %s %c%c%c\n", i + offset, 1332 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1333 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1334 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1335 xive_source_is_asserted(xsrc, i) ? 'A' : ' '); 1336 } 1337 } 1338 1339 static void xive_source_reset(void *dev) 1340 { 1341 XiveSource *xsrc = XIVE_SOURCE(dev); 1342 1343 /* Do not clear the LSI bitmap */ 1344 1345 memset(xsrc->status, xsrc->reset_pq, xsrc->nr_irqs); 1346 } 1347 1348 static void xive_source_realize(DeviceState *dev, Error **errp) 1349 { 1350 XiveSource *xsrc = XIVE_SOURCE(dev); 1351 uint64_t esb_len = xive_source_esb_len(xsrc); 1352 1353 assert(xsrc->xive); 1354 1355 if (!xsrc->nr_irqs) { 1356 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1357 return; 1358 } 1359 1360 if (xsrc->esb_shift != XIVE_ESB_4K && 1361 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1362 xsrc->esb_shift != XIVE_ESB_64K && 1363 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1364 error_setg(errp, "Invalid ESB shift setting"); 1365 return; 1366 } 1367 1368 xsrc->status = g_malloc0(xsrc->nr_irqs); 1369 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1370 1371 memory_region_init(&xsrc->esb_mmio, OBJECT(xsrc), "xive.esb", esb_len); 1372 memory_region_init_io(&xsrc->esb_mmio_emulated, OBJECT(xsrc), 1373 &xive_source_esb_ops, xsrc, "xive.esb-emulated", 1374 esb_len); 1375 memory_region_add_subregion(&xsrc->esb_mmio, 0, &xsrc->esb_mmio_emulated); 1376 1377 qemu_register_reset(xive_source_reset, dev); 1378 } 1379 1380 static const VMStateDescription vmstate_xive_source = { 1381 .name = TYPE_XIVE_SOURCE, 1382 .version_id = 1, 1383 .minimum_version_id = 1, 1384 .fields = (const VMStateField[]) { 1385 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1386 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1387 VMSTATE_END_OF_LIST() 1388 }, 1389 }; 1390 1391 /* 1392 * The default XIVE interrupt source setting for the ESB MMIOs is two 1393 * 64k pages without Store EOI, to be in sync with KVM. 1394 */ 1395 static const Property xive_source_properties[] = { 1396 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1397 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1398 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1399 /* 1400 * By default, PQs are initialized to 0b01 (Q=1) which corresponds 1401 * to "ints off" 1402 */ 1403 DEFINE_PROP_UINT8("reset-pq", XiveSource, reset_pq, XIVE_ESB_OFF), 1404 DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, 1405 XiveNotifier *), 1406 }; 1407 1408 static void xive_source_class_init(ObjectClass *klass, void *data) 1409 { 1410 DeviceClass *dc = DEVICE_CLASS(klass); 1411 1412 dc->desc = "XIVE Interrupt Source"; 1413 device_class_set_props(dc, xive_source_properties); 1414 dc->realize = xive_source_realize; 1415 dc->vmsd = &vmstate_xive_source; 1416 /* 1417 * Reason: part of XIVE interrupt controller, needs to be wired up, 1418 * e.g. by spapr_xive_instance_init(). 1419 */ 1420 dc->user_creatable = false; 1421 } 1422 1423 static const TypeInfo xive_source_info = { 1424 .name = TYPE_XIVE_SOURCE, 1425 .parent = TYPE_DEVICE, 1426 .instance_size = sizeof(XiveSource), 1427 .class_init = xive_source_class_init, 1428 }; 1429 1430 /* 1431 * XiveEND helpers 1432 */ 1433 1434 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, GString *buf) 1435 { 1436 uint64_t qaddr_base = xive_end_qaddr(end); 1437 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1438 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1439 uint32_t qentries = 1 << (qsize + 10); 1440 int i; 1441 1442 /* 1443 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1444 */ 1445 g_string_append_printf(buf, " [ "); 1446 qindex = (qindex - (width - 1)) & (qentries - 1); 1447 for (i = 0; i < width; i++) { 1448 uint64_t qaddr = qaddr_base + (qindex << 2); 1449 uint32_t qdata = -1; 1450 1451 if (dma_memory_read(&address_space_memory, qaddr, 1452 &qdata, sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 1453 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1454 HWADDR_PRIx "\n", qaddr); 1455 return; 1456 } 1457 g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "", 1458 be32_to_cpu(qdata)); 1459 qindex = (qindex + 1) & (qentries - 1); 1460 } 1461 g_string_append_c(buf, ']'); 1462 } 1463 1464 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf) 1465 { 1466 uint64_t qaddr_base = xive_end_qaddr(end); 1467 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1468 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1469 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1470 uint32_t qentries = 1 << (qsize + 10); 1471 1472 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1473 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1474 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1475 uint8_t pq; 1476 1477 if (!xive_end_is_valid(end)) { 1478 return; 1479 } 1480 1481 pq = xive_get_field32(END_W1_ESn, end->w1); 1482 1483 g_string_append_printf(buf, 1484 " %08x %c%c %c%c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1485 end_idx, 1486 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1487 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1488 xive_end_is_valid(end) ? 'v' : '-', 1489 xive_end_is_enqueue(end) ? 'q' : '-', 1490 xive_end_is_notify(end) ? 'n' : '-', 1491 xive_end_is_backlog(end) ? 'b' : '-', 1492 xive_end_is_escalate(end) ? 'e' : '-', 1493 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1494 xive_end_is_silent_escalation(end) ? 's' : '-', 1495 xive_end_is_firmware(end) ? 'f' : '-', 1496 priority, nvt_blk, nvt_idx); 1497 1498 if (qaddr_base) { 1499 g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1500 qaddr_base, qindex, qentries, qgen); 1501 xive_end_queue_pic_print_info(end, 6, buf); 1502 } 1503 g_string_append_c(buf, '\n'); 1504 } 1505 1506 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1507 { 1508 uint64_t qaddr_base = xive_end_qaddr(end); 1509 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1510 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1511 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1512 1513 uint64_t qaddr = qaddr_base + (qindex << 2); 1514 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1515 uint32_t qentries = 1 << (qsize + 10); 1516 1517 if (dma_memory_write(&address_space_memory, qaddr, 1518 &qdata, sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 1519 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1520 HWADDR_PRIx "\n", qaddr); 1521 return; 1522 } 1523 1524 qindex = (qindex + 1) & (qentries - 1); 1525 if (qindex == 0) { 1526 qgen ^= 1; 1527 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1528 } 1529 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1530 } 1531 1532 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf) 1533 { 1534 XiveEAS *eas = (XiveEAS *) &end->w4; 1535 uint8_t pq; 1536 1537 if (!xive_end_is_escalate(end)) { 1538 return; 1539 } 1540 1541 pq = xive_get_field32(END_W1_ESe, end->w1); 1542 1543 g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1544 end_idx, 1545 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1546 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1547 xive_eas_is_valid(eas) ? 'V' : ' ', 1548 xive_eas_is_masked(eas) ? 'M' : ' ', 1549 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1550 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1551 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1552 } 1553 1554 /* 1555 * XIVE Router (aka. Virtualization Controller or IVRE) 1556 */ 1557 1558 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1559 XiveEAS *eas) 1560 { 1561 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1562 1563 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1564 } 1565 1566 static 1567 int xive_router_get_pq(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1568 uint8_t *pq) 1569 { 1570 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1571 1572 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); 1573 } 1574 1575 static 1576 int xive_router_set_pq(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1577 uint8_t *pq) 1578 { 1579 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1580 1581 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); 1582 } 1583 1584 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1585 XiveEND *end) 1586 { 1587 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1588 1589 return xrc->get_end(xrtr, end_blk, end_idx, end); 1590 } 1591 1592 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1593 XiveEND *end, uint8_t word_number) 1594 { 1595 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1596 1597 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1598 } 1599 1600 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1601 XiveNVT *nvt) 1602 { 1603 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1604 1605 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1606 } 1607 1608 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1609 XiveNVT *nvt, uint8_t word_number) 1610 { 1611 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1612 1613 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1614 } 1615 1616 static int xive_router_get_block_id(XiveRouter *xrtr) 1617 { 1618 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1619 1620 return xrc->get_block_id(xrtr); 1621 } 1622 1623 static void xive_router_realize(DeviceState *dev, Error **errp) 1624 { 1625 XiveRouter *xrtr = XIVE_ROUTER(dev); 1626 1627 assert(xrtr->xfb); 1628 } 1629 1630 static void xive_router_end_notify_handler(XiveRouter *xrtr, XiveEAS *eas) 1631 { 1632 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1633 1634 return xrc->end_notify(xrtr, eas); 1635 } 1636 1637 /* 1638 * Encode the HW CAM line in the block group mode format : 1639 * 1640 * chip << 19 | 0000000 0 0001 thread (7Bit) 1641 */ 1642 static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 1643 { 1644 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1645 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1646 uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr)); 1647 1648 return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); 1649 } 1650 1651 /* 1652 * The thread context register words are in big-endian format. 1653 */ 1654 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1655 uint8_t format, 1656 uint8_t nvt_blk, uint32_t nvt_idx, 1657 bool cam_ignore, uint32_t logic_serv) 1658 { 1659 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1660 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1661 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1662 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1663 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1664 1665 /* 1666 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1667 * identifier are ignored in the "CAM" match. 1668 */ 1669 1670 if (format == 0) { 1671 if (cam_ignore == true) { 1672 /* 1673 * F=0 & i=1: Logical server notification (bits ignored at 1674 * the end of the NVT identifier) 1675 */ 1676 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1677 nvt_blk, nvt_idx); 1678 return -1; 1679 } 1680 1681 /* F=0 & i=0: Specific NVT notification */ 1682 1683 /* PHYS ring */ 1684 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1685 cam == xive_tctx_hw_cam_line(xptr, tctx)) { 1686 return TM_QW3_HV_PHYS; 1687 } 1688 1689 /* HV POOL ring */ 1690 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1691 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1692 return TM_QW2_HV_POOL; 1693 } 1694 1695 /* OS ring */ 1696 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1697 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1698 return TM_QW1_OS; 1699 } 1700 } else { 1701 /* F=1 : User level Event-Based Branch (EBB) notification */ 1702 1703 /* USER ring */ 1704 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1705 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1706 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1707 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1708 return TM_QW0_USER; 1709 } 1710 } 1711 return -1; 1712 } 1713 1714 /* 1715 * This is our simple Xive Presenter Engine model. It is merged in the 1716 * Router as it does not require an extra object. 1717 * 1718 * It receives notification requests sent by the IVRE to find one 1719 * matching NVT (or more) dispatched on the processor threads. In case 1720 * of a single NVT notification, the process is abbreviated and the 1721 * thread is signaled if a match is found. In case of a logical server 1722 * notification (bits ignored at the end of the NVT identifier), the 1723 * IVPE and IVRE select a winning thread using different filters. This 1724 * involves 2 or 3 exchanges on the PowerBus that the model does not 1725 * support. 1726 * 1727 * The parameters represent what is sent on the PowerBus 1728 */ 1729 bool xive_presenter_notify(XiveFabric *xfb, uint8_t format, 1730 uint8_t nvt_blk, uint32_t nvt_idx, 1731 bool cam_ignore, uint8_t priority, 1732 uint32_t logic_serv) 1733 { 1734 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb); 1735 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1736 int count; 1737 1738 /* 1739 * Ask the machine to scan the interrupt controllers for a match 1740 */ 1741 count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore, 1742 priority, logic_serv, &match); 1743 if (count < 0) { 1744 return false; 1745 } 1746 1747 /* handle CPU exception delivery */ 1748 if (count) { 1749 trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring); 1750 xive_tctx_ipb_update(match.tctx, match.ring, 1751 xive_priority_to_ipb(priority)); 1752 } 1753 1754 return !!count; 1755 } 1756 1757 /* 1758 * Notification using the END ESe/ESn bit (Event State Buffer for 1759 * escalation and notification). Provide further coalescing in the 1760 * Router. 1761 */ 1762 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1763 uint32_t end_idx, XiveEND *end, 1764 uint32_t end_esmask) 1765 { 1766 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1767 bool notify = xive_esb_trigger(&pq); 1768 1769 if (pq != xive_get_field32(end_esmask, end->w1)) { 1770 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1771 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1772 } 1773 1774 /* ESe/n[Q]=1 : end of notification */ 1775 return notify; 1776 } 1777 1778 /* 1779 * An END trigger can come from an event trigger (IPI or HW) or from 1780 * another chip. We don't model the PowerBus but the END trigger 1781 * message has the same parameters than in the function below. 1782 */ 1783 void xive_router_end_notify(XiveRouter *xrtr, XiveEAS *eas) 1784 { 1785 XiveEND end; 1786 uint8_t priority; 1787 uint8_t format; 1788 uint8_t nvt_blk; 1789 uint32_t nvt_idx; 1790 XiveNVT nvt; 1791 bool found; 1792 1793 uint8_t end_blk = xive_get_field64(EAS_END_BLOCK, eas->w); 1794 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 1795 uint32_t end_data = xive_get_field64(EAS_END_DATA, eas->w); 1796 1797 /* END cache lookup */ 1798 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1799 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1800 end_idx); 1801 return; 1802 } 1803 1804 if (!xive_end_is_valid(&end)) { 1805 trace_xive_router_end_notify(end_blk, end_idx, end_data); 1806 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1807 end_blk, end_idx); 1808 return; 1809 } 1810 1811 if (xive_end_is_enqueue(&end)) { 1812 xive_end_enqueue(&end, end_data); 1813 /* Enqueuing event data modifies the EQ toggle and index */ 1814 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1815 } 1816 1817 /* 1818 * When the END is silent, we skip the notification part. 1819 */ 1820 if (xive_end_is_silent_escalation(&end)) { 1821 goto do_escalation; 1822 } 1823 1824 /* 1825 * The W7 format depends on the F bit in W6. It defines the type 1826 * of the notification : 1827 * 1828 * F=0 : single or multiple NVT notification 1829 * F=1 : User level Event-Based Branch (EBB) notification, no 1830 * priority 1831 */ 1832 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1833 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1834 1835 /* The END is masked */ 1836 if (format == 0 && priority == 0xff) { 1837 return; 1838 } 1839 1840 /* 1841 * Check the END ESn (Event State Buffer for notification) for 1842 * even further coalescing in the Router 1843 */ 1844 if (!xive_end_is_notify(&end)) { 1845 /* ESn[Q]=1 : end of notification */ 1846 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1847 &end, END_W1_ESn)) { 1848 return; 1849 } 1850 } 1851 1852 /* 1853 * Follows IVPE notification 1854 */ 1855 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1856 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1857 1858 /* NVT cache lookup */ 1859 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1860 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1861 nvt_blk, nvt_idx); 1862 return; 1863 } 1864 1865 if (!xive_nvt_is_valid(&nvt)) { 1866 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1867 nvt_blk, nvt_idx); 1868 return; 1869 } 1870 1871 found = xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx, 1872 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1873 priority, 1874 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1875 1876 /* TODO: Auto EOI. */ 1877 1878 if (found) { 1879 return; 1880 } 1881 1882 /* 1883 * If no matching NVT is dispatched on a HW thread : 1884 * - specific VP: update the NVT structure if backlog is activated 1885 * - logical server : forward request to IVPE (not supported) 1886 */ 1887 if (xive_end_is_backlog(&end)) { 1888 uint8_t ipb; 1889 1890 if (format == 1) { 1891 qemu_log_mask(LOG_GUEST_ERROR, 1892 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1893 end_blk, end_idx); 1894 return; 1895 } 1896 /* 1897 * Record the IPB in the associated NVT structure for later 1898 * use. The presenter will resend the interrupt when the vCPU 1899 * is dispatched again on a HW thread. 1900 */ 1901 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | 1902 xive_priority_to_ipb(priority); 1903 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); 1904 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1905 1906 /* 1907 * On HW, follows a "Broadcast Backlog" to IVPEs 1908 */ 1909 } 1910 1911 do_escalation: 1912 /* 1913 * If activated, escalate notification using the ESe PQ bits and 1914 * the EAS in w4-5 1915 */ 1916 if (!xive_end_is_escalate(&end)) { 1917 return; 1918 } 1919 1920 /* 1921 * Check the END ESe (Event State Buffer for escalation) for even 1922 * further coalescing in the Router 1923 */ 1924 if (!xive_end_is_uncond_escalation(&end)) { 1925 /* ESe[Q]=1 : end of notification */ 1926 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1927 &end, END_W1_ESe)) { 1928 return; 1929 } 1930 } 1931 1932 trace_xive_router_end_escalate(end_blk, end_idx, 1933 (uint8_t) xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1934 (uint32_t) xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1935 (uint32_t) xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1936 /* 1937 * The END trigger becomes an Escalation trigger 1938 */ 1939 xive_router_end_notify_handler(xrtr, (XiveEAS *) &end.w4); 1940 } 1941 1942 void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) 1943 { 1944 XiveRouter *xrtr = XIVE_ROUTER(xn); 1945 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1946 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1947 XiveEAS eas; 1948 1949 /* EAS cache lookup */ 1950 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1951 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1952 return; 1953 } 1954 1955 if (!pq_checked) { 1956 bool notify; 1957 uint8_t pq; 1958 1959 /* PQ cache lookup */ 1960 if (xive_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) { 1961 /* Set FIR */ 1962 g_assert_not_reached(); 1963 } 1964 1965 notify = xive_esb_trigger(&pq); 1966 1967 if (xive_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) { 1968 /* Set FIR */ 1969 g_assert_not_reached(); 1970 } 1971 1972 if (!notify) { 1973 return; 1974 } 1975 } 1976 1977 if (!xive_eas_is_valid(&eas)) { 1978 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1979 return; 1980 } 1981 1982 if (xive_eas_is_masked(&eas)) { 1983 /* Notification completed */ 1984 return; 1985 } 1986 1987 /* 1988 * The event trigger becomes an END trigger 1989 */ 1990 xive_router_end_notify_handler(xrtr, &eas); 1991 } 1992 1993 static const Property xive_router_properties[] = { 1994 DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb, 1995 TYPE_XIVE_FABRIC, XiveFabric *), 1996 }; 1997 1998 static void xive_router_class_init(ObjectClass *klass, void *data) 1999 { 2000 DeviceClass *dc = DEVICE_CLASS(klass); 2001 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 2002 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 2003 2004 dc->desc = "XIVE Router Engine"; 2005 device_class_set_props(dc, xive_router_properties); 2006 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 2007 dc->realize = xive_router_realize; 2008 xnc->notify = xive_router_notify; 2009 2010 /* By default, the router handles END triggers locally */ 2011 xrc->end_notify = xive_router_end_notify; 2012 } 2013 2014 static const TypeInfo xive_router_info = { 2015 .name = TYPE_XIVE_ROUTER, 2016 .parent = TYPE_SYS_BUS_DEVICE, 2017 .abstract = true, 2018 .instance_size = sizeof(XiveRouter), 2019 .class_size = sizeof(XiveRouterClass), 2020 .class_init = xive_router_class_init, 2021 .interfaces = (InterfaceInfo[]) { 2022 { TYPE_XIVE_NOTIFIER }, 2023 { TYPE_XIVE_PRESENTER }, 2024 { } 2025 } 2026 }; 2027 2028 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, GString *buf) 2029 { 2030 if (!xive_eas_is_valid(eas)) { 2031 return; 2032 } 2033 2034 g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n", 2035 lisn, xive_eas_is_masked(eas) ? "M" : " ", 2036 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 2037 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 2038 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 2039 } 2040 2041 /* 2042 * END ESB MMIO loads 2043 */ 2044 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 2045 { 2046 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 2047 uint32_t offset = addr & 0xFFF; 2048 uint8_t end_blk; 2049 uint32_t end_idx; 2050 XiveEND end; 2051 uint32_t end_esmask; 2052 uint8_t pq; 2053 uint64_t ret = -1; 2054 2055 /* 2056 * The block id should be deduced from the load address on the END 2057 * ESB MMIO but our model only supports a single block per XIVE chip. 2058 */ 2059 end_blk = xive_router_get_block_id(xsrc->xrtr); 2060 end_idx = addr >> (xsrc->esb_shift + 1); 2061 2062 trace_xive_end_source_read(end_blk, end_idx, addr); 2063 2064 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 2065 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 2066 end_idx); 2067 return -1; 2068 } 2069 2070 if (!xive_end_is_valid(&end)) { 2071 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 2072 end_blk, end_idx); 2073 return -1; 2074 } 2075 2076 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 2077 pq = xive_get_field32(end_esmask, end.w1); 2078 2079 switch (offset) { 2080 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 2081 ret = xive_esb_eoi(&pq); 2082 2083 /* Forward the source event notification for routing ?? */ 2084 break; 2085 2086 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 2087 ret = pq; 2088 break; 2089 2090 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 2091 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 2092 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 2093 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 2094 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 2095 break; 2096 default: 2097 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 2098 offset); 2099 return -1; 2100 } 2101 2102 if (pq != xive_get_field32(end_esmask, end.w1)) { 2103 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 2104 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 2105 } 2106 2107 return ret; 2108 } 2109 2110 /* 2111 * END ESB MMIO stores are invalid 2112 */ 2113 static void xive_end_source_write(void *opaque, hwaddr addr, 2114 uint64_t value, unsigned size) 2115 { 2116 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 2117 HWADDR_PRIx"\n", addr); 2118 } 2119 2120 static const MemoryRegionOps xive_end_source_ops = { 2121 .read = xive_end_source_read, 2122 .write = xive_end_source_write, 2123 .endianness = DEVICE_BIG_ENDIAN, 2124 .valid = { 2125 .min_access_size = 1, 2126 .max_access_size = 8, 2127 }, 2128 .impl = { 2129 .min_access_size = 1, 2130 .max_access_size = 8, 2131 }, 2132 }; 2133 2134 static void xive_end_source_realize(DeviceState *dev, Error **errp) 2135 { 2136 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 2137 2138 assert(xsrc->xrtr); 2139 2140 if (!xsrc->nr_ends) { 2141 error_setg(errp, "Number of interrupt needs to be greater than 0"); 2142 return; 2143 } 2144 2145 if (xsrc->esb_shift != XIVE_ESB_4K && 2146 xsrc->esb_shift != XIVE_ESB_64K) { 2147 error_setg(errp, "Invalid ESB shift setting"); 2148 return; 2149 } 2150 2151 /* 2152 * Each END is assigned an even/odd pair of MMIO pages, the even page 2153 * manages the ESn field while the odd page manages the ESe field. 2154 */ 2155 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 2156 &xive_end_source_ops, xsrc, "xive.end", 2157 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 2158 } 2159 2160 static const Property xive_end_source_properties[] = { 2161 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 2162 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 2163 DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, 2164 XiveRouter *), 2165 }; 2166 2167 static void xive_end_source_class_init(ObjectClass *klass, void *data) 2168 { 2169 DeviceClass *dc = DEVICE_CLASS(klass); 2170 2171 dc->desc = "XIVE END Source"; 2172 device_class_set_props(dc, xive_end_source_properties); 2173 dc->realize = xive_end_source_realize; 2174 /* 2175 * Reason: part of XIVE interrupt controller, needs to be wired up, 2176 * e.g. by spapr_xive_instance_init(). 2177 */ 2178 dc->user_creatable = false; 2179 } 2180 2181 static const TypeInfo xive_end_source_info = { 2182 .name = TYPE_XIVE_END_SOURCE, 2183 .parent = TYPE_DEVICE, 2184 .instance_size = sizeof(XiveENDSource), 2185 .class_init = xive_end_source_class_init, 2186 }; 2187 2188 /* 2189 * XIVE Notifier 2190 */ 2191 static const TypeInfo xive_notifier_info = { 2192 .name = TYPE_XIVE_NOTIFIER, 2193 .parent = TYPE_INTERFACE, 2194 .class_size = sizeof(XiveNotifierClass), 2195 }; 2196 2197 /* 2198 * XIVE Presenter 2199 */ 2200 static const TypeInfo xive_presenter_info = { 2201 .name = TYPE_XIVE_PRESENTER, 2202 .parent = TYPE_INTERFACE, 2203 .class_size = sizeof(XivePresenterClass), 2204 }; 2205 2206 /* 2207 * XIVE Fabric 2208 */ 2209 static const TypeInfo xive_fabric_info = { 2210 .name = TYPE_XIVE_FABRIC, 2211 .parent = TYPE_INTERFACE, 2212 .class_size = sizeof(XiveFabricClass), 2213 }; 2214 2215 static void xive_register_types(void) 2216 { 2217 type_register_static(&xive_fabric_info); 2218 type_register_static(&xive_source_info); 2219 type_register_static(&xive_notifier_info); 2220 type_register_static(&xive_presenter_info); 2221 type_register_static(&xive_router_info); 2222 type_register_static(&xive_end_source_info); 2223 type_register_static(&xive_tctx_info); 2224 } 2225 2226 type_init(xive_register_types) 2227