1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "monitor/monitor.h" 21 #include "hw/irq.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive_regs.h" 24 #include "trace.h" 25 26 /* 27 * XIVE Thread Interrupt Management context 28 */ 29 30 /* 31 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 32 * Interrupt Priority Register (PIPR), which contains the priority of 33 * the most favored pending notification. 34 */ 35 static uint8_t ipb_to_pipr(uint8_t ibp) 36 { 37 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 38 } 39 40 static uint8_t exception_mask(uint8_t ring) 41 { 42 switch (ring) { 43 case TM_QW1_OS: 44 return TM_QW1_NSR_EO; 45 case TM_QW3_HV_PHYS: 46 return TM_QW3_NSR_HE; 47 default: 48 g_assert_not_reached(); 49 } 50 } 51 52 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 53 { 54 switch (ring) { 55 case TM_QW0_USER: 56 return 0; /* Not supported */ 57 case TM_QW1_OS: 58 return tctx->os_output; 59 case TM_QW2_HV_POOL: 60 case TM_QW3_HV_PHYS: 61 return tctx->hv_output; 62 default: 63 return 0; 64 } 65 } 66 67 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 68 { 69 uint8_t *regs = &tctx->regs[ring]; 70 uint8_t nsr = regs[TM_NSR]; 71 uint8_t mask = exception_mask(ring); 72 73 qemu_irq_lower(xive_tctx_output(tctx, ring)); 74 75 if (regs[TM_NSR] & mask) { 76 uint8_t cppr = regs[TM_PIPR]; 77 78 regs[TM_CPPR] = cppr; 79 80 /* Reset the pending buffer bit */ 81 regs[TM_IPB] &= ~xive_priority_to_ipb(cppr); 82 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 83 84 /* Drop Exception bit */ 85 regs[TM_NSR] &= ~mask; 86 87 trace_xive_tctx_accept(tctx->cs->cpu_index, ring, 88 regs[TM_IPB], regs[TM_PIPR], 89 regs[TM_CPPR], regs[TM_NSR]); 90 } 91 92 return (nsr << 8) | regs[TM_CPPR]; 93 } 94 95 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 96 { 97 uint8_t *regs = &tctx->regs[ring]; 98 99 if (regs[TM_PIPR] < regs[TM_CPPR]) { 100 switch (ring) { 101 case TM_QW1_OS: 102 regs[TM_NSR] |= TM_QW1_NSR_EO; 103 break; 104 case TM_QW3_HV_PHYS: 105 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 106 break; 107 default: 108 g_assert_not_reached(); 109 } 110 trace_xive_tctx_notify(tctx->cs->cpu_index, ring, 111 regs[TM_IPB], regs[TM_PIPR], 112 regs[TM_CPPR], regs[TM_NSR]); 113 qemu_irq_raise(xive_tctx_output(tctx, ring)); 114 } 115 } 116 117 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 118 { 119 uint8_t *regs = &tctx->regs[ring]; 120 121 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, 122 regs[TM_IPB], regs[TM_PIPR], 123 cppr, regs[TM_NSR]); 124 125 if (cppr > XIVE_PRIORITY_MAX) { 126 cppr = 0xff; 127 } 128 129 tctx->regs[ring + TM_CPPR] = cppr; 130 131 /* CPPR has changed, check if we need to raise a pending exception */ 132 xive_tctx_notify(tctx, ring); 133 } 134 135 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) 136 { 137 uint8_t *regs = &tctx->regs[ring]; 138 139 regs[TM_IPB] |= ipb; 140 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 141 xive_tctx_notify(tctx, ring); 142 } 143 144 static inline uint32_t xive_tctx_word2(uint8_t *ring) 145 { 146 return *((uint32_t *) &ring[TM_WORD2]); 147 } 148 149 /* 150 * XIVE Thread Interrupt Management Area (TIMA) 151 */ 152 153 static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 154 hwaddr offset, uint64_t value, unsigned size) 155 { 156 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 157 } 158 159 static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx, 160 hwaddr offset, unsigned size) 161 { 162 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 163 } 164 165 static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 166 hwaddr offset, unsigned size) 167 { 168 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 169 uint32_t qw2w2; 170 171 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 172 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 173 return qw2w2; 174 } 175 176 static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 177 uint64_t value, unsigned size) 178 { 179 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 180 } 181 182 static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, 183 hwaddr offset, unsigned size) 184 { 185 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 186 } 187 188 /* 189 * Define an access map for each page of the TIMA that we will use in 190 * the memory region ops to filter values when doing loads and stores 191 * of raw registers values 192 * 193 * Registers accessibility bits : 194 * 195 * 0x0 - no access 196 * 0x1 - write only 197 * 0x2 - read only 198 * 0x3 - read/write 199 */ 200 201 static const uint8_t xive_tm_hw_view[] = { 202 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 203 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 204 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 205 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 206 }; 207 208 static const uint8_t xive_tm_hv_view[] = { 209 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 210 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 211 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 212 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 213 }; 214 215 static const uint8_t xive_tm_os_view[] = { 216 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 217 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 219 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 220 }; 221 222 static const uint8_t xive_tm_user_view[] = { 223 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 224 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 225 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 226 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 227 }; 228 229 /* 230 * Overall TIMA access map for the thread interrupt management context 231 * registers 232 */ 233 static const uint8_t *xive_tm_views[] = { 234 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 235 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 236 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 237 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 238 }; 239 240 /* 241 * Computes a register access mask for a given offset in the TIMA 242 */ 243 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 244 { 245 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 246 uint8_t reg_offset = offset & 0x3F; 247 uint8_t reg_mask = write ? 0x1 : 0x2; 248 uint64_t mask = 0x0; 249 int i; 250 251 for (i = 0; i < size; i++) { 252 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 253 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 254 } 255 } 256 257 return mask; 258 } 259 260 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 261 unsigned size) 262 { 263 uint8_t ring_offset = offset & 0x30; 264 uint8_t reg_offset = offset & 0x3F; 265 uint64_t mask = xive_tm_mask(offset, size, true); 266 int i; 267 268 /* 269 * Only 4 or 8 bytes stores are allowed and the User ring is 270 * excluded 271 */ 272 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 273 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 274 HWADDR_PRIx"\n", offset); 275 return; 276 } 277 278 /* 279 * Use the register offset for the raw values and filter out 280 * reserved values 281 */ 282 for (i = 0; i < size; i++) { 283 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 284 if (byte_mask) { 285 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 286 byte_mask; 287 } 288 } 289 } 290 291 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 292 { 293 uint8_t ring_offset = offset & 0x30; 294 uint8_t reg_offset = offset & 0x3F; 295 uint64_t mask = xive_tm_mask(offset, size, false); 296 uint64_t ret; 297 int i; 298 299 /* 300 * Only 4 or 8 bytes loads are allowed and the User ring is 301 * excluded 302 */ 303 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 304 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 305 HWADDR_PRIx"\n", offset); 306 return -1; 307 } 308 309 /* Use the register offset for the raw values */ 310 ret = 0; 311 for (i = 0; i < size; i++) { 312 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 313 } 314 315 /* filter out reserved values */ 316 return ret & mask; 317 } 318 319 /* 320 * The TM context is mapped twice within each page. Stores and loads 321 * to the first mapping below 2K write and read the specified values 322 * without modification. The second mapping above 2K performs specific 323 * state changes (side effects) in addition to setting/returning the 324 * interrupt management area context of the processor thread. 325 */ 326 static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx, 327 hwaddr offset, unsigned size) 328 { 329 return xive_tctx_accept(tctx, TM_QW1_OS); 330 } 331 332 static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 333 hwaddr offset, uint64_t value, unsigned size) 334 { 335 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 336 } 337 338 /* 339 * Adjust the IPB to allow a CPU to process event queues of other 340 * priorities during one physical interrupt cycle. 341 */ 342 static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, 343 hwaddr offset, uint64_t value, unsigned size) 344 { 345 xive_tctx_ipb_update(tctx, TM_QW1_OS, xive_priority_to_ipb(value & 0xff)); 346 } 347 348 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, 349 uint32_t *nvt_idx, bool *vo) 350 { 351 if (nvt_blk) { 352 *nvt_blk = xive_nvt_blk(cam); 353 } 354 if (nvt_idx) { 355 *nvt_idx = xive_nvt_idx(cam); 356 } 357 if (vo) { 358 *vo = !!(cam & TM_QW1W2_VO); 359 } 360 } 361 362 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk, 363 uint32_t *nvt_idx, bool *vo) 364 { 365 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 366 uint32_t cam = be32_to_cpu(qw1w2); 367 368 xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo); 369 return qw1w2; 370 } 371 372 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) 373 { 374 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 375 } 376 377 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 378 hwaddr offset, unsigned size) 379 { 380 uint32_t qw1w2; 381 uint32_t qw1w2_new; 382 uint8_t nvt_blk; 383 uint32_t nvt_idx; 384 bool vo; 385 386 qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); 387 388 if (!vo) { 389 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n", 390 nvt_blk, nvt_idx); 391 } 392 393 /* Invalidate CAM line */ 394 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); 395 xive_tctx_set_os_cam(tctx, qw1w2_new); 396 return qw1w2; 397 } 398 399 static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx, 400 uint8_t nvt_blk, uint32_t nvt_idx) 401 { 402 XiveNVT nvt; 403 uint8_t ipb; 404 405 /* 406 * Grab the associated NVT to pull the pending bits, and merge 407 * them with the IPB of the thread interrupt context registers 408 */ 409 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 410 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n", 411 nvt_blk, nvt_idx); 412 return; 413 } 414 415 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4); 416 417 if (ipb) { 418 /* Reset the NVT value */ 419 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0); 420 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 421 422 /* Merge in current context */ 423 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); 424 } 425 } 426 427 /* 428 * Updating the OS CAM line can trigger a resend of interrupt 429 */ 430 static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 431 hwaddr offset, uint64_t value, unsigned size) 432 { 433 uint32_t cam = value; 434 uint32_t qw1w2 = cpu_to_be32(cam); 435 uint8_t nvt_blk; 436 uint32_t nvt_idx; 437 bool vo; 438 439 xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); 440 441 /* First update the registers */ 442 xive_tctx_set_os_cam(tctx, qw1w2); 443 444 /* Check the interrupt pending bits */ 445 if (vo) { 446 xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); 447 } 448 } 449 450 /* 451 * Define a mapping of "special" operations depending on the TIMA page 452 * offset and the size of the operation. 453 */ 454 typedef struct XiveTmOp { 455 uint8_t page_offset; 456 uint32_t op_offset; 457 unsigned size; 458 void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, 459 hwaddr offset, 460 uint64_t value, unsigned size); 461 uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 462 unsigned size); 463 } XiveTmOp; 464 465 static const XiveTmOp xive_tm_operations[] = { 466 /* 467 * MMIOs below 2K : raw values and special operations without side 468 * effects 469 */ 470 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 471 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, NULL }, 472 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 473 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 474 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 475 476 /* MMIOs above 2K : special operations with side effects */ 477 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 478 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 479 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, 480 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, 481 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 482 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 483 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 484 }; 485 486 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 487 { 488 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 489 uint32_t op_offset = offset & 0xFFF; 490 int i; 491 492 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 493 const XiveTmOp *xto = &xive_tm_operations[i]; 494 495 /* Accesses done from a more privileged TIMA page is allowed */ 496 if (xto->page_offset >= page_offset && 497 xto->op_offset == op_offset && 498 xto->size == size && 499 ((write && xto->write_handler) || (!write && xto->read_handler))) { 500 return xto; 501 } 502 } 503 return NULL; 504 } 505 506 /* 507 * TIMA MMIO handlers 508 */ 509 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 510 uint64_t value, unsigned size) 511 { 512 const XiveTmOp *xto; 513 514 trace_xive_tctx_tm_write(offset, size, value); 515 516 /* 517 * TODO: check V bit in Q[0-3]W2 518 */ 519 520 /* 521 * First, check for special operations in the 2K region 522 */ 523 if (offset & 0x800) { 524 xto = xive_tm_find_op(offset, size, true); 525 if (!xto) { 526 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 527 "@%"HWADDR_PRIx"\n", offset); 528 } else { 529 xto->write_handler(xptr, tctx, offset, value, size); 530 } 531 return; 532 } 533 534 /* 535 * Then, for special operations in the region below 2K. 536 */ 537 xto = xive_tm_find_op(offset, size, true); 538 if (xto) { 539 xto->write_handler(xptr, tctx, offset, value, size); 540 return; 541 } 542 543 /* 544 * Finish with raw access to the register values 545 */ 546 xive_tm_raw_write(tctx, offset, value, size); 547 } 548 549 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 550 unsigned size) 551 { 552 const XiveTmOp *xto; 553 uint64_t ret; 554 555 /* 556 * TODO: check V bit in Q[0-3]W2 557 */ 558 559 /* 560 * First, check for special operations in the 2K region 561 */ 562 if (offset & 0x800) { 563 xto = xive_tm_find_op(offset, size, false); 564 if (!xto) { 565 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 566 "@%"HWADDR_PRIx"\n", offset); 567 return -1; 568 } 569 ret = xto->read_handler(xptr, tctx, offset, size); 570 goto out; 571 } 572 573 /* 574 * Then, for special operations in the region below 2K. 575 */ 576 xto = xive_tm_find_op(offset, size, false); 577 if (xto) { 578 ret = xto->read_handler(xptr, tctx, offset, size); 579 goto out; 580 } 581 582 /* 583 * Finish with raw access to the register values 584 */ 585 ret = xive_tm_raw_read(tctx, offset, size); 586 out: 587 trace_xive_tctx_tm_read(offset, size, ret); 588 return ret; 589 } 590 591 static char *xive_tctx_ring_print(uint8_t *ring) 592 { 593 uint32_t w2 = xive_tctx_word2(ring); 594 595 return g_strdup_printf("%02x %02x %02x %02x %02x " 596 "%02x %02x %02x %08x", 597 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 598 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 599 be32_to_cpu(w2)); 600 } 601 602 static const char * const xive_tctx_ring_names[] = { 603 "USER", "OS", "POOL", "PHYS", 604 }; 605 606 /* 607 * kvm_irqchip_in_kernel() will cause the compiler to turn this 608 * info a nop if CONFIG_KVM isn't defined. 609 */ 610 #define xive_in_kernel(xptr) \ 611 (kvm_irqchip_in_kernel() && \ 612 ({ \ 613 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); \ 614 xpc->in_kernel ? xpc->in_kernel(xptr) : false; \ 615 })) 616 617 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 618 { 619 int cpu_index; 620 int i; 621 622 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs 623 * are hot plugged or unplugged. 624 */ 625 if (!tctx) { 626 return; 627 } 628 629 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 630 631 if (xive_in_kernel(tctx->xptr)) { 632 Error *local_err = NULL; 633 634 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 635 if (local_err) { 636 error_report_err(local_err); 637 return; 638 } 639 } 640 641 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 642 " W2\n", cpu_index); 643 644 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 645 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 646 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 647 xive_tctx_ring_names[i], s); 648 g_free(s); 649 } 650 } 651 652 void xive_tctx_reset(XiveTCTX *tctx) 653 { 654 memset(tctx->regs, 0, sizeof(tctx->regs)); 655 656 /* Set some defaults */ 657 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 658 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 659 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 660 661 /* 662 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 663 * CPPR is first set. 664 */ 665 tctx->regs[TM_QW1_OS + TM_PIPR] = 666 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 667 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 668 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 669 } 670 671 static void xive_tctx_realize(DeviceState *dev, Error **errp) 672 { 673 XiveTCTX *tctx = XIVE_TCTX(dev); 674 PowerPCCPU *cpu; 675 CPUPPCState *env; 676 677 assert(tctx->cs); 678 assert(tctx->xptr); 679 680 cpu = POWERPC_CPU(tctx->cs); 681 env = &cpu->env; 682 switch (PPC_INPUT(env)) { 683 case PPC_FLAGS_INPUT_POWER9: 684 tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT]; 685 tctx->os_output = env->irq_inputs[POWER9_INPUT_INT]; 686 break; 687 688 default: 689 error_setg(errp, "XIVE interrupt controller does not support " 690 "this CPU bus model"); 691 return; 692 } 693 694 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 695 if (xive_in_kernel(tctx->xptr)) { 696 if (kvmppc_xive_cpu_connect(tctx, errp) < 0) { 697 return; 698 } 699 } 700 } 701 702 static int vmstate_xive_tctx_pre_save(void *opaque) 703 { 704 XiveTCTX *tctx = XIVE_TCTX(opaque); 705 Error *local_err = NULL; 706 int ret; 707 708 if (xive_in_kernel(tctx->xptr)) { 709 ret = kvmppc_xive_cpu_get_state(tctx, &local_err); 710 if (ret < 0) { 711 error_report_err(local_err); 712 return ret; 713 } 714 } 715 716 return 0; 717 } 718 719 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 720 { 721 XiveTCTX *tctx = XIVE_TCTX(opaque); 722 Error *local_err = NULL; 723 int ret; 724 725 if (xive_in_kernel(tctx->xptr)) { 726 /* 727 * Required for hotplugged CPU, for which the state comes 728 * after all states of the machine. 729 */ 730 ret = kvmppc_xive_cpu_set_state(tctx, &local_err); 731 if (ret < 0) { 732 error_report_err(local_err); 733 return ret; 734 } 735 } 736 737 return 0; 738 } 739 740 static const VMStateDescription vmstate_xive_tctx = { 741 .name = TYPE_XIVE_TCTX, 742 .version_id = 1, 743 .minimum_version_id = 1, 744 .pre_save = vmstate_xive_tctx_pre_save, 745 .post_load = vmstate_xive_tctx_post_load, 746 .fields = (VMStateField[]) { 747 VMSTATE_BUFFER(regs, XiveTCTX), 748 VMSTATE_END_OF_LIST() 749 }, 750 }; 751 752 static Property xive_tctx_properties[] = { 753 DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), 754 DEFINE_PROP_LINK("presenter", XiveTCTX, xptr, TYPE_XIVE_PRESENTER, 755 XivePresenter *), 756 DEFINE_PROP_END_OF_LIST(), 757 }; 758 759 static void xive_tctx_class_init(ObjectClass *klass, void *data) 760 { 761 DeviceClass *dc = DEVICE_CLASS(klass); 762 763 dc->desc = "XIVE Interrupt Thread Context"; 764 dc->realize = xive_tctx_realize; 765 dc->vmsd = &vmstate_xive_tctx; 766 device_class_set_props(dc, xive_tctx_properties); 767 /* 768 * Reason: part of XIVE interrupt controller, needs to be wired up 769 * by xive_tctx_create(). 770 */ 771 dc->user_creatable = false; 772 } 773 774 static const TypeInfo xive_tctx_info = { 775 .name = TYPE_XIVE_TCTX, 776 .parent = TYPE_DEVICE, 777 .instance_size = sizeof(XiveTCTX), 778 .class_init = xive_tctx_class_init, 779 }; 780 781 Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp) 782 { 783 Object *obj; 784 785 obj = object_new(TYPE_XIVE_TCTX); 786 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj); 787 object_unref(obj); 788 object_property_set_link(obj, "cpu", cpu, &error_abort); 789 object_property_set_link(obj, "presenter", OBJECT(xptr), &error_abort); 790 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 791 object_unparent(obj); 792 return NULL; 793 } 794 return obj; 795 } 796 797 void xive_tctx_destroy(XiveTCTX *tctx) 798 { 799 Object *obj = OBJECT(tctx); 800 801 object_unparent(obj); 802 } 803 804 /* 805 * XIVE ESB helpers 806 */ 807 808 uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 809 { 810 uint8_t old_pq = *pq & 0x3; 811 812 *pq &= ~0x3; 813 *pq |= value & 0x3; 814 815 return old_pq; 816 } 817 818 bool xive_esb_trigger(uint8_t *pq) 819 { 820 uint8_t old_pq = *pq & 0x3; 821 822 switch (old_pq) { 823 case XIVE_ESB_RESET: 824 xive_esb_set(pq, XIVE_ESB_PENDING); 825 return true; 826 case XIVE_ESB_PENDING: 827 case XIVE_ESB_QUEUED: 828 xive_esb_set(pq, XIVE_ESB_QUEUED); 829 return false; 830 case XIVE_ESB_OFF: 831 xive_esb_set(pq, XIVE_ESB_OFF); 832 return false; 833 default: 834 g_assert_not_reached(); 835 } 836 } 837 838 bool xive_esb_eoi(uint8_t *pq) 839 { 840 uint8_t old_pq = *pq & 0x3; 841 842 switch (old_pq) { 843 case XIVE_ESB_RESET: 844 case XIVE_ESB_PENDING: 845 xive_esb_set(pq, XIVE_ESB_RESET); 846 return false; 847 case XIVE_ESB_QUEUED: 848 xive_esb_set(pq, XIVE_ESB_PENDING); 849 return true; 850 case XIVE_ESB_OFF: 851 xive_esb_set(pq, XIVE_ESB_OFF); 852 return false; 853 default: 854 g_assert_not_reached(); 855 } 856 } 857 858 /* 859 * XIVE Interrupt Source (or IVSE) 860 */ 861 862 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 863 { 864 assert(srcno < xsrc->nr_irqs); 865 866 return xsrc->status[srcno] & 0x3; 867 } 868 869 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 870 { 871 assert(srcno < xsrc->nr_irqs); 872 873 return xive_esb_set(&xsrc->status[srcno], pq); 874 } 875 876 /* 877 * Returns whether the event notification should be forwarded. 878 */ 879 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 880 { 881 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 882 883 xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; 884 885 switch (old_pq) { 886 case XIVE_ESB_RESET: 887 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 888 return true; 889 default: 890 return false; 891 } 892 } 893 894 /* 895 * Returns whether the event notification should be forwarded. 896 */ 897 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 898 { 899 bool ret; 900 901 assert(srcno < xsrc->nr_irqs); 902 903 ret = xive_esb_trigger(&xsrc->status[srcno]); 904 905 if (xive_source_irq_is_lsi(xsrc, srcno) && 906 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 907 qemu_log_mask(LOG_GUEST_ERROR, 908 "XIVE: queued an event on LSI IRQ %d\n", srcno); 909 } 910 911 return ret; 912 } 913 914 /* 915 * Returns whether the event notification should be forwarded. 916 */ 917 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 918 { 919 bool ret; 920 921 assert(srcno < xsrc->nr_irqs); 922 923 ret = xive_esb_eoi(&xsrc->status[srcno]); 924 925 /* 926 * LSI sources do not set the Q bit but they can still be 927 * asserted, in which case we should forward a new event 928 * notification 929 */ 930 if (xive_source_irq_is_lsi(xsrc, srcno) && 931 xsrc->status[srcno] & XIVE_STATUS_ASSERTED) { 932 ret = xive_source_lsi_trigger(xsrc, srcno); 933 } 934 935 return ret; 936 } 937 938 /* 939 * Forward the source event notification to the Router 940 */ 941 static void xive_source_notify(XiveSource *xsrc, int srcno) 942 { 943 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 944 945 if (xnc->notify) { 946 xnc->notify(xsrc->xive, srcno); 947 } 948 } 949 950 /* 951 * In a two pages ESB MMIO setting, even page is the trigger page, odd 952 * page is for management 953 */ 954 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 955 { 956 return !((addr >> shift) & 1); 957 } 958 959 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 960 { 961 return xive_source_esb_has_2page(xsrc) && 962 addr_is_even(addr, xsrc->esb_shift - 1); 963 } 964 965 /* 966 * ESB MMIO loads 967 * Trigger page Management/EOI page 968 * 969 * ESB MMIO setting 2 pages 1 or 2 pages 970 * 971 * 0x000 .. 0x3FF -1 EOI and return 0|1 972 * 0x400 .. 0x7FF -1 EOI and return 0|1 973 * 0x800 .. 0xBFF -1 return PQ 974 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 975 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 976 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 977 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 978 */ 979 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 980 { 981 XiveSource *xsrc = XIVE_SOURCE(opaque); 982 uint32_t offset = addr & 0xFFF; 983 uint32_t srcno = addr >> xsrc->esb_shift; 984 uint64_t ret = -1; 985 986 /* In a two pages ESB MMIO setting, trigger page should not be read */ 987 if (xive_source_is_trigger_page(xsrc, addr)) { 988 qemu_log_mask(LOG_GUEST_ERROR, 989 "XIVE: invalid load on IRQ %d trigger page at " 990 "0x%"HWADDR_PRIx"\n", srcno, addr); 991 return -1; 992 } 993 994 switch (offset) { 995 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 996 ret = xive_source_esb_eoi(xsrc, srcno); 997 998 /* Forward the source event notification for routing */ 999 if (ret) { 1000 xive_source_notify(xsrc, srcno); 1001 } 1002 break; 1003 1004 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1005 ret = xive_source_esb_get(xsrc, srcno); 1006 break; 1007 1008 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1009 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1010 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1011 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1012 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1013 break; 1014 default: 1015 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 1016 offset); 1017 } 1018 1019 trace_xive_source_esb_read(addr, srcno, ret); 1020 1021 return ret; 1022 } 1023 1024 /* 1025 * ESB MMIO stores 1026 * Trigger page Management/EOI page 1027 * 1028 * ESB MMIO setting 2 pages 1 or 2 pages 1029 * 1030 * 0x000 .. 0x3FF Trigger Trigger 1031 * 0x400 .. 0x7FF Trigger EOI 1032 * 0x800 .. 0xBFF Trigger undefined 1033 * 0xC00 .. 0xCFF Trigger PQ=00 1034 * 0xD00 .. 0xDFF Trigger PQ=01 1035 * 0xE00 .. 0xDFF Trigger PQ=10 1036 * 0xF00 .. 0xDFF Trigger PQ=11 1037 */ 1038 static void xive_source_esb_write(void *opaque, hwaddr addr, 1039 uint64_t value, unsigned size) 1040 { 1041 XiveSource *xsrc = XIVE_SOURCE(opaque); 1042 uint32_t offset = addr & 0xFFF; 1043 uint32_t srcno = addr >> xsrc->esb_shift; 1044 bool notify = false; 1045 1046 trace_xive_source_esb_write(addr, srcno, value); 1047 1048 /* In a two pages ESB MMIO setting, trigger page only triggers */ 1049 if (xive_source_is_trigger_page(xsrc, addr)) { 1050 notify = xive_source_esb_trigger(xsrc, srcno); 1051 goto out; 1052 } 1053 1054 switch (offset) { 1055 case 0 ... 0x3FF: 1056 notify = xive_source_esb_trigger(xsrc, srcno); 1057 break; 1058 1059 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 1060 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 1061 qemu_log_mask(LOG_GUEST_ERROR, 1062 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 1063 return; 1064 } 1065 1066 notify = xive_source_esb_eoi(xsrc, srcno); 1067 break; 1068 1069 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1070 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1071 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1072 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1073 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1074 break; 1075 1076 default: 1077 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 1078 offset); 1079 return; 1080 } 1081 1082 out: 1083 /* Forward the source event notification for routing */ 1084 if (notify) { 1085 xive_source_notify(xsrc, srcno); 1086 } 1087 } 1088 1089 static const MemoryRegionOps xive_source_esb_ops = { 1090 .read = xive_source_esb_read, 1091 .write = xive_source_esb_write, 1092 .endianness = DEVICE_BIG_ENDIAN, 1093 .valid = { 1094 .min_access_size = 8, 1095 .max_access_size = 8, 1096 }, 1097 .impl = { 1098 .min_access_size = 8, 1099 .max_access_size = 8, 1100 }, 1101 }; 1102 1103 void xive_source_set_irq(void *opaque, int srcno, int val) 1104 { 1105 XiveSource *xsrc = XIVE_SOURCE(opaque); 1106 bool notify = false; 1107 1108 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1109 if (val) { 1110 notify = xive_source_lsi_trigger(xsrc, srcno); 1111 } else { 1112 xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; 1113 } 1114 } else { 1115 if (val) { 1116 notify = xive_source_esb_trigger(xsrc, srcno); 1117 } 1118 } 1119 1120 /* Forward the source event notification for routing */ 1121 if (notify) { 1122 xive_source_notify(xsrc, srcno); 1123 } 1124 } 1125 1126 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 1127 { 1128 int i; 1129 1130 for (i = 0; i < xsrc->nr_irqs; i++) { 1131 uint8_t pq = xive_source_esb_get(xsrc, i); 1132 1133 if (pq == XIVE_ESB_OFF) { 1134 continue; 1135 } 1136 1137 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 1138 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1139 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1140 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1141 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' '); 1142 } 1143 } 1144 1145 static void xive_source_reset(void *dev) 1146 { 1147 XiveSource *xsrc = XIVE_SOURCE(dev); 1148 1149 /* Do not clear the LSI bitmap */ 1150 1151 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 1152 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 1153 } 1154 1155 static void xive_source_realize(DeviceState *dev, Error **errp) 1156 { 1157 XiveSource *xsrc = XIVE_SOURCE(dev); 1158 size_t esb_len = xive_source_esb_len(xsrc); 1159 1160 assert(xsrc->xive); 1161 1162 if (!xsrc->nr_irqs) { 1163 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1164 return; 1165 } 1166 1167 if (xsrc->esb_shift != XIVE_ESB_4K && 1168 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1169 xsrc->esb_shift != XIVE_ESB_64K && 1170 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1171 error_setg(errp, "Invalid ESB shift setting"); 1172 return; 1173 } 1174 1175 xsrc->status = g_malloc0(xsrc->nr_irqs); 1176 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1177 1178 memory_region_init(&xsrc->esb_mmio, OBJECT(xsrc), "xive.esb", esb_len); 1179 memory_region_init_io(&xsrc->esb_mmio_emulated, OBJECT(xsrc), 1180 &xive_source_esb_ops, xsrc, "xive.esb-emulated", 1181 esb_len); 1182 memory_region_add_subregion(&xsrc->esb_mmio, 0, &xsrc->esb_mmio_emulated); 1183 1184 qemu_register_reset(xive_source_reset, dev); 1185 } 1186 1187 static const VMStateDescription vmstate_xive_source = { 1188 .name = TYPE_XIVE_SOURCE, 1189 .version_id = 1, 1190 .minimum_version_id = 1, 1191 .fields = (VMStateField[]) { 1192 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1193 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1194 VMSTATE_END_OF_LIST() 1195 }, 1196 }; 1197 1198 /* 1199 * The default XIVE interrupt source setting for the ESB MMIOs is two 1200 * 64k pages without Store EOI, to be in sync with KVM. 1201 */ 1202 static Property xive_source_properties[] = { 1203 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1204 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1205 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1206 DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, 1207 XiveNotifier *), 1208 DEFINE_PROP_END_OF_LIST(), 1209 }; 1210 1211 static void xive_source_class_init(ObjectClass *klass, void *data) 1212 { 1213 DeviceClass *dc = DEVICE_CLASS(klass); 1214 1215 dc->desc = "XIVE Interrupt Source"; 1216 device_class_set_props(dc, xive_source_properties); 1217 dc->realize = xive_source_realize; 1218 dc->vmsd = &vmstate_xive_source; 1219 /* 1220 * Reason: part of XIVE interrupt controller, needs to be wired up, 1221 * e.g. by spapr_xive_instance_init(). 1222 */ 1223 dc->user_creatable = false; 1224 } 1225 1226 static const TypeInfo xive_source_info = { 1227 .name = TYPE_XIVE_SOURCE, 1228 .parent = TYPE_DEVICE, 1229 .instance_size = sizeof(XiveSource), 1230 .class_init = xive_source_class_init, 1231 }; 1232 1233 /* 1234 * XiveEND helpers 1235 */ 1236 1237 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1238 { 1239 uint64_t qaddr_base = xive_end_qaddr(end); 1240 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1241 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1242 uint32_t qentries = 1 << (qsize + 10); 1243 int i; 1244 1245 /* 1246 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1247 */ 1248 monitor_printf(mon, " [ "); 1249 qindex = (qindex - (width - 1)) & (qentries - 1); 1250 for (i = 0; i < width; i++) { 1251 uint64_t qaddr = qaddr_base + (qindex << 2); 1252 uint32_t qdata = -1; 1253 1254 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 1255 sizeof(qdata))) { 1256 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1257 HWADDR_PRIx "\n", qaddr); 1258 return; 1259 } 1260 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1261 be32_to_cpu(qdata)); 1262 qindex = (qindex + 1) & (qentries - 1); 1263 } 1264 monitor_printf(mon, "]"); 1265 } 1266 1267 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1268 { 1269 uint64_t qaddr_base = xive_end_qaddr(end); 1270 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1271 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1272 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1273 uint32_t qentries = 1 << (qsize + 10); 1274 1275 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1276 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1277 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1278 uint8_t pq; 1279 1280 if (!xive_end_is_valid(end)) { 1281 return; 1282 } 1283 1284 pq = xive_get_field32(END_W1_ESn, end->w1); 1285 1286 monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1287 end_idx, 1288 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1289 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1290 xive_end_is_valid(end) ? 'v' : '-', 1291 xive_end_is_enqueue(end) ? 'q' : '-', 1292 xive_end_is_notify(end) ? 'n' : '-', 1293 xive_end_is_backlog(end) ? 'b' : '-', 1294 xive_end_is_escalate(end) ? 'e' : '-', 1295 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1296 xive_end_is_silent_escalation(end) ? 's' : '-', 1297 xive_end_is_firmware(end) ? 'f' : '-', 1298 priority, nvt_blk, nvt_idx); 1299 1300 if (qaddr_base) { 1301 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1302 qaddr_base, qindex, qentries, qgen); 1303 xive_end_queue_pic_print_info(end, 6, mon); 1304 } 1305 monitor_printf(mon, "\n"); 1306 } 1307 1308 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1309 { 1310 uint64_t qaddr_base = xive_end_qaddr(end); 1311 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1312 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1313 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1314 1315 uint64_t qaddr = qaddr_base + (qindex << 2); 1316 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1317 uint32_t qentries = 1 << (qsize + 10); 1318 1319 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) { 1320 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1321 HWADDR_PRIx "\n", qaddr); 1322 return; 1323 } 1324 1325 qindex = (qindex + 1) & (qentries - 1); 1326 if (qindex == 0) { 1327 qgen ^= 1; 1328 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1329 } 1330 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1331 } 1332 1333 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, 1334 Monitor *mon) 1335 { 1336 XiveEAS *eas = (XiveEAS *) &end->w4; 1337 uint8_t pq; 1338 1339 if (!xive_end_is_escalate(end)) { 1340 return; 1341 } 1342 1343 pq = xive_get_field32(END_W1_ESe, end->w1); 1344 1345 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1346 end_idx, 1347 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1348 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1349 xive_eas_is_valid(eas) ? 'V' : ' ', 1350 xive_eas_is_masked(eas) ? 'M' : ' ', 1351 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1352 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1353 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1354 } 1355 1356 /* 1357 * XIVE Router (aka. Virtualization Controller or IVRE) 1358 */ 1359 1360 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1361 XiveEAS *eas) 1362 { 1363 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1364 1365 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1366 } 1367 1368 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1369 XiveEND *end) 1370 { 1371 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1372 1373 return xrc->get_end(xrtr, end_blk, end_idx, end); 1374 } 1375 1376 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1377 XiveEND *end, uint8_t word_number) 1378 { 1379 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1380 1381 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1382 } 1383 1384 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1385 XiveNVT *nvt) 1386 { 1387 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1388 1389 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1390 } 1391 1392 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1393 XiveNVT *nvt, uint8_t word_number) 1394 { 1395 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1396 1397 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1398 } 1399 1400 static int xive_router_get_block_id(XiveRouter *xrtr) 1401 { 1402 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1403 1404 return xrc->get_block_id(xrtr); 1405 } 1406 1407 static void xive_router_realize(DeviceState *dev, Error **errp) 1408 { 1409 XiveRouter *xrtr = XIVE_ROUTER(dev); 1410 1411 assert(xrtr->xfb); 1412 } 1413 1414 /* 1415 * Encode the HW CAM line in the block group mode format : 1416 * 1417 * chip << 19 | 0000000 0 0001 thread (7Bit) 1418 */ 1419 static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 1420 { 1421 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1422 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1423 uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr)); 1424 1425 return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); 1426 } 1427 1428 /* 1429 * The thread context register words are in big-endian format. 1430 */ 1431 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1432 uint8_t format, 1433 uint8_t nvt_blk, uint32_t nvt_idx, 1434 bool cam_ignore, uint32_t logic_serv) 1435 { 1436 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1437 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1438 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1439 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1440 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1441 1442 /* 1443 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1444 * identifier are ignored in the "CAM" match. 1445 */ 1446 1447 if (format == 0) { 1448 if (cam_ignore == true) { 1449 /* 1450 * F=0 & i=1: Logical server notification (bits ignored at 1451 * the end of the NVT identifier) 1452 */ 1453 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1454 nvt_blk, nvt_idx); 1455 return -1; 1456 } 1457 1458 /* F=0 & i=0: Specific NVT notification */ 1459 1460 /* PHYS ring */ 1461 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1462 cam == xive_tctx_hw_cam_line(xptr, tctx)) { 1463 return TM_QW3_HV_PHYS; 1464 } 1465 1466 /* HV POOL ring */ 1467 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1468 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1469 return TM_QW2_HV_POOL; 1470 } 1471 1472 /* OS ring */ 1473 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1474 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1475 return TM_QW1_OS; 1476 } 1477 } else { 1478 /* F=1 : User level Event-Based Branch (EBB) notification */ 1479 1480 /* USER ring */ 1481 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1482 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1483 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1484 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1485 return TM_QW0_USER; 1486 } 1487 } 1488 return -1; 1489 } 1490 1491 /* 1492 * This is our simple Xive Presenter Engine model. It is merged in the 1493 * Router as it does not require an extra object. 1494 * 1495 * It receives notification requests sent by the IVRE to find one 1496 * matching NVT (or more) dispatched on the processor threads. In case 1497 * of a single NVT notification, the process is abreviated and the 1498 * thread is signaled if a match is found. In case of a logical server 1499 * notification (bits ignored at the end of the NVT identifier), the 1500 * IVPE and IVRE select a winning thread using different filters. This 1501 * involves 2 or 3 exchanges on the PowerBus that the model does not 1502 * support. 1503 * 1504 * The parameters represent what is sent on the PowerBus 1505 */ 1506 bool xive_presenter_notify(XiveFabric *xfb, uint8_t format, 1507 uint8_t nvt_blk, uint32_t nvt_idx, 1508 bool cam_ignore, uint8_t priority, 1509 uint32_t logic_serv) 1510 { 1511 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb); 1512 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1513 int count; 1514 1515 /* 1516 * Ask the machine to scan the interrupt controllers for a match 1517 */ 1518 count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore, 1519 priority, logic_serv, &match); 1520 if (count < 0) { 1521 return false; 1522 } 1523 1524 /* handle CPU exception delivery */ 1525 if (count) { 1526 trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring); 1527 xive_tctx_ipb_update(match.tctx, match.ring, 1528 xive_priority_to_ipb(priority)); 1529 } 1530 1531 return !!count; 1532 } 1533 1534 /* 1535 * Notification using the END ESe/ESn bit (Event State Buffer for 1536 * escalation and notification). Provide further coalescing in the 1537 * Router. 1538 */ 1539 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1540 uint32_t end_idx, XiveEND *end, 1541 uint32_t end_esmask) 1542 { 1543 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1544 bool notify = xive_esb_trigger(&pq); 1545 1546 if (pq != xive_get_field32(end_esmask, end->w1)) { 1547 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1548 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1549 } 1550 1551 /* ESe/n[Q]=1 : end of notification */ 1552 return notify; 1553 } 1554 1555 /* 1556 * An END trigger can come from an event trigger (IPI or HW) or from 1557 * another chip. We don't model the PowerBus but the END trigger 1558 * message has the same parameters than in the function below. 1559 */ 1560 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1561 uint32_t end_idx, uint32_t end_data) 1562 { 1563 XiveEND end; 1564 uint8_t priority; 1565 uint8_t format; 1566 uint8_t nvt_blk; 1567 uint32_t nvt_idx; 1568 XiveNVT nvt; 1569 bool found; 1570 1571 /* END cache lookup */ 1572 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1573 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1574 end_idx); 1575 return; 1576 } 1577 1578 if (!xive_end_is_valid(&end)) { 1579 trace_xive_router_end_notify(end_blk, end_idx, end_data); 1580 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1581 end_blk, end_idx); 1582 return; 1583 } 1584 1585 if (xive_end_is_enqueue(&end)) { 1586 xive_end_enqueue(&end, end_data); 1587 /* Enqueuing event data modifies the EQ toggle and index */ 1588 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1589 } 1590 1591 /* 1592 * When the END is silent, we skip the notification part. 1593 */ 1594 if (xive_end_is_silent_escalation(&end)) { 1595 goto do_escalation; 1596 } 1597 1598 /* 1599 * The W7 format depends on the F bit in W6. It defines the type 1600 * of the notification : 1601 * 1602 * F=0 : single or multiple NVT notification 1603 * F=1 : User level Event-Based Branch (EBB) notification, no 1604 * priority 1605 */ 1606 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1607 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1608 1609 /* The END is masked */ 1610 if (format == 0 && priority == 0xff) { 1611 return; 1612 } 1613 1614 /* 1615 * Check the END ESn (Event State Buffer for notification) for 1616 * even further coalescing in the Router 1617 */ 1618 if (!xive_end_is_notify(&end)) { 1619 /* ESn[Q]=1 : end of notification */ 1620 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1621 &end, END_W1_ESn)) { 1622 return; 1623 } 1624 } 1625 1626 /* 1627 * Follows IVPE notification 1628 */ 1629 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1630 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1631 1632 /* NVT cache lookup */ 1633 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1634 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1635 nvt_blk, nvt_idx); 1636 return; 1637 } 1638 1639 if (!xive_nvt_is_valid(&nvt)) { 1640 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1641 nvt_blk, nvt_idx); 1642 return; 1643 } 1644 1645 found = xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx, 1646 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1647 priority, 1648 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1649 1650 /* TODO: Auto EOI. */ 1651 1652 if (found) { 1653 return; 1654 } 1655 1656 /* 1657 * If no matching NVT is dispatched on a HW thread : 1658 * - specific VP: update the NVT structure if backlog is activated 1659 * - logical server : forward request to IVPE (not supported) 1660 */ 1661 if (xive_end_is_backlog(&end)) { 1662 uint8_t ipb; 1663 1664 if (format == 1) { 1665 qemu_log_mask(LOG_GUEST_ERROR, 1666 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1667 end_blk, end_idx); 1668 return; 1669 } 1670 /* 1671 * Record the IPB in the associated NVT structure for later 1672 * use. The presenter will resend the interrupt when the vCPU 1673 * is dispatched again on a HW thread. 1674 */ 1675 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | 1676 xive_priority_to_ipb(priority); 1677 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); 1678 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1679 1680 /* 1681 * On HW, follows a "Broadcast Backlog" to IVPEs 1682 */ 1683 } 1684 1685 do_escalation: 1686 /* 1687 * If activated, escalate notification using the ESe PQ bits and 1688 * the EAS in w4-5 1689 */ 1690 if (!xive_end_is_escalate(&end)) { 1691 return; 1692 } 1693 1694 /* 1695 * Check the END ESe (Event State Buffer for escalation) for even 1696 * further coalescing in the Router 1697 */ 1698 if (!xive_end_is_uncond_escalation(&end)) { 1699 /* ESe[Q]=1 : end of notification */ 1700 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1701 &end, END_W1_ESe)) { 1702 return; 1703 } 1704 } 1705 1706 trace_xive_router_end_escalate(end_blk, end_idx, 1707 (uint8_t) xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1708 (uint32_t) xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1709 (uint32_t) xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1710 /* 1711 * The END trigger becomes an Escalation trigger 1712 */ 1713 xive_router_end_notify(xrtr, 1714 xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1715 xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1716 xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1717 } 1718 1719 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 1720 { 1721 XiveRouter *xrtr = XIVE_ROUTER(xn); 1722 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1723 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1724 XiveEAS eas; 1725 1726 /* EAS cache lookup */ 1727 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1728 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1729 return; 1730 } 1731 1732 /* 1733 * The IVRE checks the State Bit Cache at this point. We skip the 1734 * SBC lookup because the state bits of the sources are modeled 1735 * internally in QEMU. 1736 */ 1737 1738 if (!xive_eas_is_valid(&eas)) { 1739 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1740 return; 1741 } 1742 1743 if (xive_eas_is_masked(&eas)) { 1744 /* Notification completed */ 1745 return; 1746 } 1747 1748 /* 1749 * The event trigger becomes an END trigger 1750 */ 1751 xive_router_end_notify(xrtr, 1752 xive_get_field64(EAS_END_BLOCK, eas.w), 1753 xive_get_field64(EAS_END_INDEX, eas.w), 1754 xive_get_field64(EAS_END_DATA, eas.w)); 1755 } 1756 1757 static Property xive_router_properties[] = { 1758 DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb, 1759 TYPE_XIVE_FABRIC, XiveFabric *), 1760 DEFINE_PROP_END_OF_LIST(), 1761 }; 1762 1763 static void xive_router_class_init(ObjectClass *klass, void *data) 1764 { 1765 DeviceClass *dc = DEVICE_CLASS(klass); 1766 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1767 1768 dc->desc = "XIVE Router Engine"; 1769 device_class_set_props(dc, xive_router_properties); 1770 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 1771 dc->realize = xive_router_realize; 1772 xnc->notify = xive_router_notify; 1773 } 1774 1775 static const TypeInfo xive_router_info = { 1776 .name = TYPE_XIVE_ROUTER, 1777 .parent = TYPE_SYS_BUS_DEVICE, 1778 .abstract = true, 1779 .instance_size = sizeof(XiveRouter), 1780 .class_size = sizeof(XiveRouterClass), 1781 .class_init = xive_router_class_init, 1782 .interfaces = (InterfaceInfo[]) { 1783 { TYPE_XIVE_NOTIFIER }, 1784 { TYPE_XIVE_PRESENTER }, 1785 { } 1786 } 1787 }; 1788 1789 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1790 { 1791 if (!xive_eas_is_valid(eas)) { 1792 return; 1793 } 1794 1795 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1796 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1797 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1798 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1799 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1800 } 1801 1802 /* 1803 * END ESB MMIO loads 1804 */ 1805 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1806 { 1807 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1808 uint32_t offset = addr & 0xFFF; 1809 uint8_t end_blk; 1810 uint32_t end_idx; 1811 XiveEND end; 1812 uint32_t end_esmask; 1813 uint8_t pq; 1814 uint64_t ret = -1; 1815 1816 /* 1817 * The block id should be deduced from the load address on the END 1818 * ESB MMIO but our model only supports a single block per XIVE chip. 1819 */ 1820 end_blk = xive_router_get_block_id(xsrc->xrtr); 1821 end_idx = addr >> (xsrc->esb_shift + 1); 1822 1823 trace_xive_end_source_read(end_blk, end_idx, addr); 1824 1825 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1826 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1827 end_idx); 1828 return -1; 1829 } 1830 1831 if (!xive_end_is_valid(&end)) { 1832 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1833 end_blk, end_idx); 1834 return -1; 1835 } 1836 1837 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1838 pq = xive_get_field32(end_esmask, end.w1); 1839 1840 switch (offset) { 1841 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1842 ret = xive_esb_eoi(&pq); 1843 1844 /* Forward the source event notification for routing ?? */ 1845 break; 1846 1847 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1848 ret = pq; 1849 break; 1850 1851 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1852 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1853 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1854 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1855 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1856 break; 1857 default: 1858 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1859 offset); 1860 return -1; 1861 } 1862 1863 if (pq != xive_get_field32(end_esmask, end.w1)) { 1864 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1865 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1866 } 1867 1868 return ret; 1869 } 1870 1871 /* 1872 * END ESB MMIO stores are invalid 1873 */ 1874 static void xive_end_source_write(void *opaque, hwaddr addr, 1875 uint64_t value, unsigned size) 1876 { 1877 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1878 HWADDR_PRIx"\n", addr); 1879 } 1880 1881 static const MemoryRegionOps xive_end_source_ops = { 1882 .read = xive_end_source_read, 1883 .write = xive_end_source_write, 1884 .endianness = DEVICE_BIG_ENDIAN, 1885 .valid = { 1886 .min_access_size = 8, 1887 .max_access_size = 8, 1888 }, 1889 .impl = { 1890 .min_access_size = 8, 1891 .max_access_size = 8, 1892 }, 1893 }; 1894 1895 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1896 { 1897 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1898 1899 assert(xsrc->xrtr); 1900 1901 if (!xsrc->nr_ends) { 1902 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1903 return; 1904 } 1905 1906 if (xsrc->esb_shift != XIVE_ESB_4K && 1907 xsrc->esb_shift != XIVE_ESB_64K) { 1908 error_setg(errp, "Invalid ESB shift setting"); 1909 return; 1910 } 1911 1912 /* 1913 * Each END is assigned an even/odd pair of MMIO pages, the even page 1914 * manages the ESn field while the odd page manages the ESe field. 1915 */ 1916 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1917 &xive_end_source_ops, xsrc, "xive.end", 1918 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1919 } 1920 1921 static Property xive_end_source_properties[] = { 1922 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1923 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1924 DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, 1925 XiveRouter *), 1926 DEFINE_PROP_END_OF_LIST(), 1927 }; 1928 1929 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1930 { 1931 DeviceClass *dc = DEVICE_CLASS(klass); 1932 1933 dc->desc = "XIVE END Source"; 1934 device_class_set_props(dc, xive_end_source_properties); 1935 dc->realize = xive_end_source_realize; 1936 /* 1937 * Reason: part of XIVE interrupt controller, needs to be wired up, 1938 * e.g. by spapr_xive_instance_init(). 1939 */ 1940 dc->user_creatable = false; 1941 } 1942 1943 static const TypeInfo xive_end_source_info = { 1944 .name = TYPE_XIVE_END_SOURCE, 1945 .parent = TYPE_DEVICE, 1946 .instance_size = sizeof(XiveENDSource), 1947 .class_init = xive_end_source_class_init, 1948 }; 1949 1950 /* 1951 * XIVE Notifier 1952 */ 1953 static const TypeInfo xive_notifier_info = { 1954 .name = TYPE_XIVE_NOTIFIER, 1955 .parent = TYPE_INTERFACE, 1956 .class_size = sizeof(XiveNotifierClass), 1957 }; 1958 1959 /* 1960 * XIVE Presenter 1961 */ 1962 static const TypeInfo xive_presenter_info = { 1963 .name = TYPE_XIVE_PRESENTER, 1964 .parent = TYPE_INTERFACE, 1965 .class_size = sizeof(XivePresenterClass), 1966 }; 1967 1968 /* 1969 * XIVE Fabric 1970 */ 1971 static const TypeInfo xive_fabric_info = { 1972 .name = TYPE_XIVE_FABRIC, 1973 .parent = TYPE_INTERFACE, 1974 .class_size = sizeof(XiveFabricClass), 1975 }; 1976 1977 static void xive_register_types(void) 1978 { 1979 type_register_static(&xive_fabric_info); 1980 type_register_static(&xive_source_info); 1981 type_register_static(&xive_notifier_info); 1982 type_register_static(&xive_presenter_info); 1983 type_register_static(&xive_router_info); 1984 type_register_static(&xive_end_source_info); 1985 type_register_static(&xive_tctx_info); 1986 } 1987 1988 type_init(xive_register_types) 1989