1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "monitor/monitor.h" 21 #include "hw/irq.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive_regs.h" 24 25 /* 26 * XIVE Thread Interrupt Management context 27 */ 28 29 /* 30 * Convert a priority number to an Interrupt Pending Buffer (IPB) 31 * register, which indicates a pending interrupt at the priority 32 * corresponding to the bit number 33 */ 34 static uint8_t priority_to_ipb(uint8_t priority) 35 { 36 return priority > XIVE_PRIORITY_MAX ? 37 0 : 1 << (XIVE_PRIORITY_MAX - priority); 38 } 39 40 /* 41 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 42 * Interrupt Priority Register (PIPR), which contains the priority of 43 * the most favored pending notification. 44 */ 45 static uint8_t ipb_to_pipr(uint8_t ibp) 46 { 47 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 48 } 49 50 static uint8_t exception_mask(uint8_t ring) 51 { 52 switch (ring) { 53 case TM_QW1_OS: 54 return TM_QW1_NSR_EO; 55 case TM_QW3_HV_PHYS: 56 return TM_QW3_NSR_HE; 57 default: 58 g_assert_not_reached(); 59 } 60 } 61 62 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 63 { 64 switch (ring) { 65 case TM_QW0_USER: 66 return 0; /* Not supported */ 67 case TM_QW1_OS: 68 return tctx->os_output; 69 case TM_QW2_HV_POOL: 70 case TM_QW3_HV_PHYS: 71 return tctx->hv_output; 72 default: 73 return 0; 74 } 75 } 76 77 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 78 { 79 uint8_t *regs = &tctx->regs[ring]; 80 uint8_t nsr = regs[TM_NSR]; 81 uint8_t mask = exception_mask(ring); 82 83 qemu_irq_lower(xive_tctx_output(tctx, ring)); 84 85 if (regs[TM_NSR] & mask) { 86 uint8_t cppr = regs[TM_PIPR]; 87 88 regs[TM_CPPR] = cppr; 89 90 /* Reset the pending buffer bit */ 91 regs[TM_IPB] &= ~priority_to_ipb(cppr); 92 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 93 94 /* Drop Exception bit */ 95 regs[TM_NSR] &= ~mask; 96 } 97 98 return (nsr << 8) | regs[TM_CPPR]; 99 } 100 101 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 102 { 103 uint8_t *regs = &tctx->regs[ring]; 104 105 if (regs[TM_PIPR] < regs[TM_CPPR]) { 106 switch (ring) { 107 case TM_QW1_OS: 108 regs[TM_NSR] |= TM_QW1_NSR_EO; 109 break; 110 case TM_QW3_HV_PHYS: 111 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 112 break; 113 default: 114 g_assert_not_reached(); 115 } 116 qemu_irq_raise(xive_tctx_output(tctx, ring)); 117 } 118 } 119 120 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 121 { 122 if (cppr > XIVE_PRIORITY_MAX) { 123 cppr = 0xff; 124 } 125 126 tctx->regs[ring + TM_CPPR] = cppr; 127 128 /* CPPR has changed, check if we need to raise a pending exception */ 129 xive_tctx_notify(tctx, ring); 130 } 131 132 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) 133 { 134 uint8_t *regs = &tctx->regs[ring]; 135 136 regs[TM_IPB] |= ipb; 137 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 138 xive_tctx_notify(tctx, ring); 139 } 140 141 static inline uint32_t xive_tctx_word2(uint8_t *ring) 142 { 143 return *((uint32_t *) &ring[TM_WORD2]); 144 } 145 146 /* 147 * XIVE Thread Interrupt Management Area (TIMA) 148 */ 149 150 static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 151 hwaddr offset, uint64_t value, unsigned size) 152 { 153 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 154 } 155 156 static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx, 157 hwaddr offset, unsigned size) 158 { 159 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 160 } 161 162 static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 163 hwaddr offset, unsigned size) 164 { 165 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 166 uint32_t qw2w2; 167 168 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 169 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 170 return qw2w2; 171 } 172 173 static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 174 uint64_t value, unsigned size) 175 { 176 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 177 } 178 179 static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, 180 hwaddr offset, unsigned size) 181 { 182 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 183 } 184 185 /* 186 * Define an access map for each page of the TIMA that we will use in 187 * the memory region ops to filter values when doing loads and stores 188 * of raw registers values 189 * 190 * Registers accessibility bits : 191 * 192 * 0x0 - no access 193 * 0x1 - write only 194 * 0x2 - read only 195 * 0x3 - read/write 196 */ 197 198 static const uint8_t xive_tm_hw_view[] = { 199 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 200 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 201 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 202 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 203 }; 204 205 static const uint8_t xive_tm_hv_view[] = { 206 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 207 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 208 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 209 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 210 }; 211 212 static const uint8_t xive_tm_os_view[] = { 213 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 214 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 215 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 217 }; 218 219 static const uint8_t xive_tm_user_view[] = { 220 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 223 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 224 }; 225 226 /* 227 * Overall TIMA access map for the thread interrupt management context 228 * registers 229 */ 230 static const uint8_t *xive_tm_views[] = { 231 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 232 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 233 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 234 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 235 }; 236 237 /* 238 * Computes a register access mask for a given offset in the TIMA 239 */ 240 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 241 { 242 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 243 uint8_t reg_offset = offset & 0x3F; 244 uint8_t reg_mask = write ? 0x1 : 0x2; 245 uint64_t mask = 0x0; 246 int i; 247 248 for (i = 0; i < size; i++) { 249 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 250 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 251 } 252 } 253 254 return mask; 255 } 256 257 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 258 unsigned size) 259 { 260 uint8_t ring_offset = offset & 0x30; 261 uint8_t reg_offset = offset & 0x3F; 262 uint64_t mask = xive_tm_mask(offset, size, true); 263 int i; 264 265 /* 266 * Only 4 or 8 bytes stores are allowed and the User ring is 267 * excluded 268 */ 269 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 270 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 271 HWADDR_PRIx"\n", offset); 272 return; 273 } 274 275 /* 276 * Use the register offset for the raw values and filter out 277 * reserved values 278 */ 279 for (i = 0; i < size; i++) { 280 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 281 if (byte_mask) { 282 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 283 byte_mask; 284 } 285 } 286 } 287 288 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 289 { 290 uint8_t ring_offset = offset & 0x30; 291 uint8_t reg_offset = offset & 0x3F; 292 uint64_t mask = xive_tm_mask(offset, size, false); 293 uint64_t ret; 294 int i; 295 296 /* 297 * Only 4 or 8 bytes loads are allowed and the User ring is 298 * excluded 299 */ 300 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 301 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 302 HWADDR_PRIx"\n", offset); 303 return -1; 304 } 305 306 /* Use the register offset for the raw values */ 307 ret = 0; 308 for (i = 0; i < size; i++) { 309 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 310 } 311 312 /* filter out reserved values */ 313 return ret & mask; 314 } 315 316 /* 317 * The TM context is mapped twice within each page. Stores and loads 318 * to the first mapping below 2K write and read the specified values 319 * without modification. The second mapping above 2K performs specific 320 * state changes (side effects) in addition to setting/returning the 321 * interrupt management area context of the processor thread. 322 */ 323 static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx, 324 hwaddr offset, unsigned size) 325 { 326 return xive_tctx_accept(tctx, TM_QW1_OS); 327 } 328 329 static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 330 hwaddr offset, uint64_t value, unsigned size) 331 { 332 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 333 } 334 335 /* 336 * Adjust the IPB to allow a CPU to process event queues of other 337 * priorities during one physical interrupt cycle. 338 */ 339 static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, 340 hwaddr offset, uint64_t value, unsigned size) 341 { 342 xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff)); 343 } 344 345 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, 346 uint32_t *nvt_idx, bool *vo) 347 { 348 if (nvt_blk) { 349 *nvt_blk = xive_nvt_blk(cam); 350 } 351 if (nvt_idx) { 352 *nvt_idx = xive_nvt_idx(cam); 353 } 354 if (vo) { 355 *vo = !!(cam & TM_QW1W2_VO); 356 } 357 } 358 359 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk, 360 uint32_t *nvt_idx, bool *vo) 361 { 362 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 363 uint32_t cam = be32_to_cpu(qw1w2); 364 365 xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo); 366 return qw1w2; 367 } 368 369 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) 370 { 371 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 372 } 373 374 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 375 hwaddr offset, unsigned size) 376 { 377 uint32_t qw1w2; 378 uint32_t qw1w2_new; 379 uint8_t nvt_blk; 380 uint32_t nvt_idx; 381 bool vo; 382 383 qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); 384 385 if (!vo) { 386 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n", 387 nvt_blk, nvt_idx); 388 } 389 390 /* Invalidate CAM line */ 391 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); 392 xive_tctx_set_os_cam(tctx, qw1w2_new); 393 return qw1w2; 394 } 395 396 static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx, 397 uint8_t nvt_blk, uint32_t nvt_idx) 398 { 399 XiveNVT nvt; 400 uint8_t ipb; 401 402 /* 403 * Grab the associated NVT to pull the pending bits, and merge 404 * them with the IPB of the thread interrupt context registers 405 */ 406 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 407 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n", 408 nvt_blk, nvt_idx); 409 return; 410 } 411 412 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4); 413 414 if (ipb) { 415 /* Reset the NVT value */ 416 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0); 417 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 418 419 /* Merge in current context */ 420 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); 421 } 422 } 423 424 /* 425 * Updating the OS CAM line can trigger a resend of interrupt 426 */ 427 static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 428 hwaddr offset, uint64_t value, unsigned size) 429 { 430 uint32_t cam = value; 431 uint32_t qw1w2 = cpu_to_be32(cam); 432 uint8_t nvt_blk; 433 uint32_t nvt_idx; 434 bool vo; 435 436 xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); 437 438 /* First update the registers */ 439 xive_tctx_set_os_cam(tctx, qw1w2); 440 441 /* Check the interrupt pending bits */ 442 if (vo) { 443 xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); 444 } 445 } 446 447 /* 448 * Define a mapping of "special" operations depending on the TIMA page 449 * offset and the size of the operation. 450 */ 451 typedef struct XiveTmOp { 452 uint8_t page_offset; 453 uint32_t op_offset; 454 unsigned size; 455 void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, 456 hwaddr offset, 457 uint64_t value, unsigned size); 458 uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 459 unsigned size); 460 } XiveTmOp; 461 462 static const XiveTmOp xive_tm_operations[] = { 463 /* 464 * MMIOs below 2K : raw values and special operations without side 465 * effects 466 */ 467 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 468 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, NULL }, 469 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 470 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 471 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 472 473 /* MMIOs above 2K : special operations with side effects */ 474 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 475 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 476 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, 477 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, 478 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 479 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 480 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 481 }; 482 483 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 484 { 485 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 486 uint32_t op_offset = offset & 0xFFF; 487 int i; 488 489 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 490 const XiveTmOp *xto = &xive_tm_operations[i]; 491 492 /* Accesses done from a more privileged TIMA page is allowed */ 493 if (xto->page_offset >= page_offset && 494 xto->op_offset == op_offset && 495 xto->size == size && 496 ((write && xto->write_handler) || (!write && xto->read_handler))) { 497 return xto; 498 } 499 } 500 return NULL; 501 } 502 503 /* 504 * TIMA MMIO handlers 505 */ 506 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 507 uint64_t value, unsigned size) 508 { 509 const XiveTmOp *xto; 510 511 /* 512 * TODO: check V bit in Q[0-3]W2 513 */ 514 515 /* 516 * First, check for special operations in the 2K region 517 */ 518 if (offset & 0x800) { 519 xto = xive_tm_find_op(offset, size, true); 520 if (!xto) { 521 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 522 "@%"HWADDR_PRIx"\n", offset); 523 } else { 524 xto->write_handler(xptr, tctx, offset, value, size); 525 } 526 return; 527 } 528 529 /* 530 * Then, for special operations in the region below 2K. 531 */ 532 xto = xive_tm_find_op(offset, size, true); 533 if (xto) { 534 xto->write_handler(xptr, tctx, offset, value, size); 535 return; 536 } 537 538 /* 539 * Finish with raw access to the register values 540 */ 541 xive_tm_raw_write(tctx, offset, value, size); 542 } 543 544 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 545 unsigned size) 546 { 547 const XiveTmOp *xto; 548 549 /* 550 * TODO: check V bit in Q[0-3]W2 551 */ 552 553 /* 554 * First, check for special operations in the 2K region 555 */ 556 if (offset & 0x800) { 557 xto = xive_tm_find_op(offset, size, false); 558 if (!xto) { 559 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 560 "@%"HWADDR_PRIx"\n", offset); 561 return -1; 562 } 563 return xto->read_handler(xptr, tctx, offset, size); 564 } 565 566 /* 567 * Then, for special operations in the region below 2K. 568 */ 569 xto = xive_tm_find_op(offset, size, false); 570 if (xto) { 571 return xto->read_handler(xptr, tctx, offset, size); 572 } 573 574 /* 575 * Finish with raw access to the register values 576 */ 577 return xive_tm_raw_read(tctx, offset, size); 578 } 579 580 static char *xive_tctx_ring_print(uint8_t *ring) 581 { 582 uint32_t w2 = xive_tctx_word2(ring); 583 584 return g_strdup_printf("%02x %02x %02x %02x %02x " 585 "%02x %02x %02x %08x", 586 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 587 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 588 be32_to_cpu(w2)); 589 } 590 591 static const char * const xive_tctx_ring_names[] = { 592 "USER", "OS", "POOL", "PHYS", 593 }; 594 595 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 596 { 597 int cpu_index; 598 int i; 599 600 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs 601 * are hot plugged or unplugged. 602 */ 603 if (!tctx) { 604 return; 605 } 606 607 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 608 609 if (kvm_irqchip_in_kernel()) { 610 Error *local_err = NULL; 611 612 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 613 if (local_err) { 614 error_report_err(local_err); 615 return; 616 } 617 } 618 619 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 620 " W2\n", cpu_index); 621 622 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 623 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 624 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 625 xive_tctx_ring_names[i], s); 626 g_free(s); 627 } 628 } 629 630 void xive_tctx_reset(XiveTCTX *tctx) 631 { 632 memset(tctx->regs, 0, sizeof(tctx->regs)); 633 634 /* Set some defaults */ 635 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 636 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 637 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 638 639 /* 640 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 641 * CPPR is first set. 642 */ 643 tctx->regs[TM_QW1_OS + TM_PIPR] = 644 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 645 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 646 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 647 } 648 649 static void xive_tctx_realize(DeviceState *dev, Error **errp) 650 { 651 XiveTCTX *tctx = XIVE_TCTX(dev); 652 PowerPCCPU *cpu; 653 CPUPPCState *env; 654 Error *local_err = NULL; 655 656 assert(tctx->cs); 657 658 cpu = POWERPC_CPU(tctx->cs); 659 env = &cpu->env; 660 switch (PPC_INPUT(env)) { 661 case PPC_FLAGS_INPUT_POWER9: 662 tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT]; 663 tctx->os_output = env->irq_inputs[POWER9_INPUT_INT]; 664 break; 665 666 default: 667 error_setg(errp, "XIVE interrupt controller does not support " 668 "this CPU bus model"); 669 return; 670 } 671 672 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 673 if (kvm_irqchip_in_kernel()) { 674 kvmppc_xive_cpu_connect(tctx, &local_err); 675 if (local_err) { 676 error_propagate(errp, local_err); 677 return; 678 } 679 } 680 } 681 682 static int vmstate_xive_tctx_pre_save(void *opaque) 683 { 684 Error *local_err = NULL; 685 686 if (kvm_irqchip_in_kernel()) { 687 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque), &local_err); 688 if (local_err) { 689 error_report_err(local_err); 690 return -1; 691 } 692 } 693 694 return 0; 695 } 696 697 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 698 { 699 Error *local_err = NULL; 700 701 if (kvm_irqchip_in_kernel()) { 702 /* 703 * Required for hotplugged CPU, for which the state comes 704 * after all states of the machine. 705 */ 706 kvmppc_xive_cpu_set_state(XIVE_TCTX(opaque), &local_err); 707 if (local_err) { 708 error_report_err(local_err); 709 return -1; 710 } 711 } 712 713 return 0; 714 } 715 716 static const VMStateDescription vmstate_xive_tctx = { 717 .name = TYPE_XIVE_TCTX, 718 .version_id = 1, 719 .minimum_version_id = 1, 720 .pre_save = vmstate_xive_tctx_pre_save, 721 .post_load = vmstate_xive_tctx_post_load, 722 .fields = (VMStateField[]) { 723 VMSTATE_BUFFER(regs, XiveTCTX), 724 VMSTATE_END_OF_LIST() 725 }, 726 }; 727 728 static Property xive_tctx_properties[] = { 729 DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), 730 DEFINE_PROP_END_OF_LIST(), 731 }; 732 733 static void xive_tctx_class_init(ObjectClass *klass, void *data) 734 { 735 DeviceClass *dc = DEVICE_CLASS(klass); 736 737 dc->desc = "XIVE Interrupt Thread Context"; 738 dc->realize = xive_tctx_realize; 739 dc->vmsd = &vmstate_xive_tctx; 740 dc->props = xive_tctx_properties; 741 /* 742 * Reason: part of XIVE interrupt controller, needs to be wired up 743 * by xive_tctx_create(). 744 */ 745 dc->user_creatable = false; 746 } 747 748 static const TypeInfo xive_tctx_info = { 749 .name = TYPE_XIVE_TCTX, 750 .parent = TYPE_DEVICE, 751 .instance_size = sizeof(XiveTCTX), 752 .class_init = xive_tctx_class_init, 753 }; 754 755 Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) 756 { 757 Error *local_err = NULL; 758 Object *obj; 759 760 obj = object_new(TYPE_XIVE_TCTX); 761 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); 762 object_unref(obj); 763 object_property_set_link(obj, cpu, "cpu", &error_abort); 764 object_property_set_bool(obj, true, "realized", &local_err); 765 if (local_err) { 766 goto error; 767 } 768 769 return obj; 770 771 error: 772 object_unparent(obj); 773 error_propagate(errp, local_err); 774 return NULL; 775 } 776 777 void xive_tctx_destroy(XiveTCTX *tctx) 778 { 779 Object *obj = OBJECT(tctx); 780 781 object_unparent(obj); 782 } 783 784 /* 785 * XIVE ESB helpers 786 */ 787 788 static uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 789 { 790 uint8_t old_pq = *pq & 0x3; 791 792 *pq &= ~0x3; 793 *pq |= value & 0x3; 794 795 return old_pq; 796 } 797 798 static bool xive_esb_trigger(uint8_t *pq) 799 { 800 uint8_t old_pq = *pq & 0x3; 801 802 switch (old_pq) { 803 case XIVE_ESB_RESET: 804 xive_esb_set(pq, XIVE_ESB_PENDING); 805 return true; 806 case XIVE_ESB_PENDING: 807 case XIVE_ESB_QUEUED: 808 xive_esb_set(pq, XIVE_ESB_QUEUED); 809 return false; 810 case XIVE_ESB_OFF: 811 xive_esb_set(pq, XIVE_ESB_OFF); 812 return false; 813 default: 814 g_assert_not_reached(); 815 } 816 } 817 818 static bool xive_esb_eoi(uint8_t *pq) 819 { 820 uint8_t old_pq = *pq & 0x3; 821 822 switch (old_pq) { 823 case XIVE_ESB_RESET: 824 case XIVE_ESB_PENDING: 825 xive_esb_set(pq, XIVE_ESB_RESET); 826 return false; 827 case XIVE_ESB_QUEUED: 828 xive_esb_set(pq, XIVE_ESB_PENDING); 829 return true; 830 case XIVE_ESB_OFF: 831 xive_esb_set(pq, XIVE_ESB_OFF); 832 return false; 833 default: 834 g_assert_not_reached(); 835 } 836 } 837 838 /* 839 * XIVE Interrupt Source (or IVSE) 840 */ 841 842 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 843 { 844 assert(srcno < xsrc->nr_irqs); 845 846 return xsrc->status[srcno] & 0x3; 847 } 848 849 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 850 { 851 assert(srcno < xsrc->nr_irqs); 852 853 return xive_esb_set(&xsrc->status[srcno], pq); 854 } 855 856 /* 857 * Returns whether the event notification should be forwarded. 858 */ 859 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 860 { 861 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 862 863 xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; 864 865 switch (old_pq) { 866 case XIVE_ESB_RESET: 867 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 868 return true; 869 default: 870 return false; 871 } 872 } 873 874 /* 875 * Returns whether the event notification should be forwarded. 876 */ 877 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 878 { 879 bool ret; 880 881 assert(srcno < xsrc->nr_irqs); 882 883 ret = xive_esb_trigger(&xsrc->status[srcno]); 884 885 if (xive_source_irq_is_lsi(xsrc, srcno) && 886 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 887 qemu_log_mask(LOG_GUEST_ERROR, 888 "XIVE: queued an event on LSI IRQ %d\n", srcno); 889 } 890 891 return ret; 892 } 893 894 /* 895 * Returns whether the event notification should be forwarded. 896 */ 897 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 898 { 899 bool ret; 900 901 assert(srcno < xsrc->nr_irqs); 902 903 ret = xive_esb_eoi(&xsrc->status[srcno]); 904 905 /* 906 * LSI sources do not set the Q bit but they can still be 907 * asserted, in which case we should forward a new event 908 * notification 909 */ 910 if (xive_source_irq_is_lsi(xsrc, srcno) && 911 xsrc->status[srcno] & XIVE_STATUS_ASSERTED) { 912 ret = xive_source_lsi_trigger(xsrc, srcno); 913 } 914 915 return ret; 916 } 917 918 /* 919 * Forward the source event notification to the Router 920 */ 921 static void xive_source_notify(XiveSource *xsrc, int srcno) 922 { 923 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 924 925 if (xnc->notify) { 926 xnc->notify(xsrc->xive, srcno); 927 } 928 } 929 930 /* 931 * In a two pages ESB MMIO setting, even page is the trigger page, odd 932 * page is for management 933 */ 934 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 935 { 936 return !((addr >> shift) & 1); 937 } 938 939 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 940 { 941 return xive_source_esb_has_2page(xsrc) && 942 addr_is_even(addr, xsrc->esb_shift - 1); 943 } 944 945 /* 946 * ESB MMIO loads 947 * Trigger page Management/EOI page 948 * 949 * ESB MMIO setting 2 pages 1 or 2 pages 950 * 951 * 0x000 .. 0x3FF -1 EOI and return 0|1 952 * 0x400 .. 0x7FF -1 EOI and return 0|1 953 * 0x800 .. 0xBFF -1 return PQ 954 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 955 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 956 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 957 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 958 */ 959 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 960 { 961 XiveSource *xsrc = XIVE_SOURCE(opaque); 962 uint32_t offset = addr & 0xFFF; 963 uint32_t srcno = addr >> xsrc->esb_shift; 964 uint64_t ret = -1; 965 966 /* In a two pages ESB MMIO setting, trigger page should not be read */ 967 if (xive_source_is_trigger_page(xsrc, addr)) { 968 qemu_log_mask(LOG_GUEST_ERROR, 969 "XIVE: invalid load on IRQ %d trigger page at " 970 "0x%"HWADDR_PRIx"\n", srcno, addr); 971 return -1; 972 } 973 974 switch (offset) { 975 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 976 ret = xive_source_esb_eoi(xsrc, srcno); 977 978 /* Forward the source event notification for routing */ 979 if (ret) { 980 xive_source_notify(xsrc, srcno); 981 } 982 break; 983 984 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 985 ret = xive_source_esb_get(xsrc, srcno); 986 break; 987 988 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 989 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 990 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 991 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 992 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 993 break; 994 default: 995 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 996 offset); 997 } 998 999 return ret; 1000 } 1001 1002 /* 1003 * ESB MMIO stores 1004 * Trigger page Management/EOI page 1005 * 1006 * ESB MMIO setting 2 pages 1 or 2 pages 1007 * 1008 * 0x000 .. 0x3FF Trigger Trigger 1009 * 0x400 .. 0x7FF Trigger EOI 1010 * 0x800 .. 0xBFF Trigger undefined 1011 * 0xC00 .. 0xCFF Trigger PQ=00 1012 * 0xD00 .. 0xDFF Trigger PQ=01 1013 * 0xE00 .. 0xDFF Trigger PQ=10 1014 * 0xF00 .. 0xDFF Trigger PQ=11 1015 */ 1016 static void xive_source_esb_write(void *opaque, hwaddr addr, 1017 uint64_t value, unsigned size) 1018 { 1019 XiveSource *xsrc = XIVE_SOURCE(opaque); 1020 uint32_t offset = addr & 0xFFF; 1021 uint32_t srcno = addr >> xsrc->esb_shift; 1022 bool notify = false; 1023 1024 /* In a two pages ESB MMIO setting, trigger page only triggers */ 1025 if (xive_source_is_trigger_page(xsrc, addr)) { 1026 notify = xive_source_esb_trigger(xsrc, srcno); 1027 goto out; 1028 } 1029 1030 switch (offset) { 1031 case 0 ... 0x3FF: 1032 notify = xive_source_esb_trigger(xsrc, srcno); 1033 break; 1034 1035 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 1036 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 1037 qemu_log_mask(LOG_GUEST_ERROR, 1038 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 1039 return; 1040 } 1041 1042 notify = xive_source_esb_eoi(xsrc, srcno); 1043 break; 1044 1045 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1046 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1047 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1048 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1049 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1050 break; 1051 1052 default: 1053 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 1054 offset); 1055 return; 1056 } 1057 1058 out: 1059 /* Forward the source event notification for routing */ 1060 if (notify) { 1061 xive_source_notify(xsrc, srcno); 1062 } 1063 } 1064 1065 static const MemoryRegionOps xive_source_esb_ops = { 1066 .read = xive_source_esb_read, 1067 .write = xive_source_esb_write, 1068 .endianness = DEVICE_BIG_ENDIAN, 1069 .valid = { 1070 .min_access_size = 8, 1071 .max_access_size = 8, 1072 }, 1073 .impl = { 1074 .min_access_size = 8, 1075 .max_access_size = 8, 1076 }, 1077 }; 1078 1079 void xive_source_set_irq(void *opaque, int srcno, int val) 1080 { 1081 XiveSource *xsrc = XIVE_SOURCE(opaque); 1082 bool notify = false; 1083 1084 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1085 if (val) { 1086 notify = xive_source_lsi_trigger(xsrc, srcno); 1087 } else { 1088 xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; 1089 } 1090 } else { 1091 if (val) { 1092 notify = xive_source_esb_trigger(xsrc, srcno); 1093 } 1094 } 1095 1096 /* Forward the source event notification for routing */ 1097 if (notify) { 1098 xive_source_notify(xsrc, srcno); 1099 } 1100 } 1101 1102 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 1103 { 1104 int i; 1105 1106 for (i = 0; i < xsrc->nr_irqs; i++) { 1107 uint8_t pq = xive_source_esb_get(xsrc, i); 1108 1109 if (pq == XIVE_ESB_OFF) { 1110 continue; 1111 } 1112 1113 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 1114 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1115 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1116 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1117 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' '); 1118 } 1119 } 1120 1121 static void xive_source_reset(void *dev) 1122 { 1123 XiveSource *xsrc = XIVE_SOURCE(dev); 1124 1125 /* Do not clear the LSI bitmap */ 1126 1127 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 1128 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 1129 } 1130 1131 static void xive_source_realize(DeviceState *dev, Error **errp) 1132 { 1133 XiveSource *xsrc = XIVE_SOURCE(dev); 1134 1135 assert(xsrc->xive); 1136 1137 if (!xsrc->nr_irqs) { 1138 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1139 return; 1140 } 1141 1142 if (xsrc->esb_shift != XIVE_ESB_4K && 1143 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1144 xsrc->esb_shift != XIVE_ESB_64K && 1145 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1146 error_setg(errp, "Invalid ESB shift setting"); 1147 return; 1148 } 1149 1150 xsrc->status = g_malloc0(xsrc->nr_irqs); 1151 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1152 1153 if (!kvm_irqchip_in_kernel()) { 1154 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1155 &xive_source_esb_ops, xsrc, "xive.esb", 1156 (1ull << xsrc->esb_shift) * xsrc->nr_irqs); 1157 } 1158 1159 qemu_register_reset(xive_source_reset, dev); 1160 } 1161 1162 static const VMStateDescription vmstate_xive_source = { 1163 .name = TYPE_XIVE_SOURCE, 1164 .version_id = 1, 1165 .minimum_version_id = 1, 1166 .fields = (VMStateField[]) { 1167 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1168 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1169 VMSTATE_END_OF_LIST() 1170 }, 1171 }; 1172 1173 /* 1174 * The default XIVE interrupt source setting for the ESB MMIOs is two 1175 * 64k pages without Store EOI, to be in sync with KVM. 1176 */ 1177 static Property xive_source_properties[] = { 1178 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1179 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1180 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1181 DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, 1182 XiveNotifier *), 1183 DEFINE_PROP_END_OF_LIST(), 1184 }; 1185 1186 static void xive_source_class_init(ObjectClass *klass, void *data) 1187 { 1188 DeviceClass *dc = DEVICE_CLASS(klass); 1189 1190 dc->desc = "XIVE Interrupt Source"; 1191 dc->props = xive_source_properties; 1192 dc->realize = xive_source_realize; 1193 dc->vmsd = &vmstate_xive_source; 1194 /* 1195 * Reason: part of XIVE interrupt controller, needs to be wired up, 1196 * e.g. by spapr_xive_instance_init(). 1197 */ 1198 dc->user_creatable = false; 1199 } 1200 1201 static const TypeInfo xive_source_info = { 1202 .name = TYPE_XIVE_SOURCE, 1203 .parent = TYPE_DEVICE, 1204 .instance_size = sizeof(XiveSource), 1205 .class_init = xive_source_class_init, 1206 }; 1207 1208 /* 1209 * XiveEND helpers 1210 */ 1211 1212 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1213 { 1214 uint64_t qaddr_base = xive_end_qaddr(end); 1215 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1216 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1217 uint32_t qentries = 1 << (qsize + 10); 1218 int i; 1219 1220 /* 1221 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1222 */ 1223 monitor_printf(mon, " [ "); 1224 qindex = (qindex - (width - 1)) & (qentries - 1); 1225 for (i = 0; i < width; i++) { 1226 uint64_t qaddr = qaddr_base + (qindex << 2); 1227 uint32_t qdata = -1; 1228 1229 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 1230 sizeof(qdata))) { 1231 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1232 HWADDR_PRIx "\n", qaddr); 1233 return; 1234 } 1235 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1236 be32_to_cpu(qdata)); 1237 qindex = (qindex + 1) & (qentries - 1); 1238 } 1239 monitor_printf(mon, "]"); 1240 } 1241 1242 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1243 { 1244 uint64_t qaddr_base = xive_end_qaddr(end); 1245 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1246 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1247 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1248 uint32_t qentries = 1 << (qsize + 10); 1249 1250 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1251 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1252 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1253 uint8_t pq; 1254 1255 if (!xive_end_is_valid(end)) { 1256 return; 1257 } 1258 1259 pq = xive_get_field32(END_W1_ESn, end->w1); 1260 1261 monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1262 end_idx, 1263 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1264 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1265 xive_end_is_valid(end) ? 'v' : '-', 1266 xive_end_is_enqueue(end) ? 'q' : '-', 1267 xive_end_is_notify(end) ? 'n' : '-', 1268 xive_end_is_backlog(end) ? 'b' : '-', 1269 xive_end_is_escalate(end) ? 'e' : '-', 1270 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1271 xive_end_is_silent_escalation(end) ? 's' : '-', 1272 priority, nvt_blk, nvt_idx); 1273 1274 if (qaddr_base) { 1275 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1276 qaddr_base, qindex, qentries, qgen); 1277 xive_end_queue_pic_print_info(end, 6, mon); 1278 } 1279 monitor_printf(mon, "\n"); 1280 } 1281 1282 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1283 { 1284 uint64_t qaddr_base = xive_end_qaddr(end); 1285 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1286 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1287 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1288 1289 uint64_t qaddr = qaddr_base + (qindex << 2); 1290 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1291 uint32_t qentries = 1 << (qsize + 10); 1292 1293 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) { 1294 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1295 HWADDR_PRIx "\n", qaddr); 1296 return; 1297 } 1298 1299 qindex = (qindex + 1) & (qentries - 1); 1300 if (qindex == 0) { 1301 qgen ^= 1; 1302 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1303 } 1304 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1305 } 1306 1307 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, 1308 Monitor *mon) 1309 { 1310 XiveEAS *eas = (XiveEAS *) &end->w4; 1311 uint8_t pq; 1312 1313 if (!xive_end_is_escalate(end)) { 1314 return; 1315 } 1316 1317 pq = xive_get_field32(END_W1_ESe, end->w1); 1318 1319 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1320 end_idx, 1321 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1322 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1323 xive_eas_is_valid(eas) ? 'V' : ' ', 1324 xive_eas_is_masked(eas) ? 'M' : ' ', 1325 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1326 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1327 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1328 } 1329 1330 /* 1331 * XIVE Router (aka. Virtualization Controller or IVRE) 1332 */ 1333 1334 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1335 XiveEAS *eas) 1336 { 1337 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1338 1339 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1340 } 1341 1342 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1343 XiveEND *end) 1344 { 1345 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1346 1347 return xrc->get_end(xrtr, end_blk, end_idx, end); 1348 } 1349 1350 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1351 XiveEND *end, uint8_t word_number) 1352 { 1353 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1354 1355 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1356 } 1357 1358 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1359 XiveNVT *nvt) 1360 { 1361 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1362 1363 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1364 } 1365 1366 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1367 XiveNVT *nvt, uint8_t word_number) 1368 { 1369 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1370 1371 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1372 } 1373 1374 static int xive_router_get_block_id(XiveRouter *xrtr) 1375 { 1376 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1377 1378 return xrc->get_block_id(xrtr); 1379 } 1380 1381 /* 1382 * Encode the HW CAM line in the block group mode format : 1383 * 1384 * chip << 19 | 0000000 0 0001 thread (7Bit) 1385 */ 1386 static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 1387 { 1388 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1389 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1390 uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr)); 1391 1392 return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); 1393 } 1394 1395 /* 1396 * The thread context register words are in big-endian format. 1397 */ 1398 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1399 uint8_t format, 1400 uint8_t nvt_blk, uint32_t nvt_idx, 1401 bool cam_ignore, uint32_t logic_serv) 1402 { 1403 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1404 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1405 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1406 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1407 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1408 1409 /* 1410 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1411 * identifier are ignored in the "CAM" match. 1412 */ 1413 1414 if (format == 0) { 1415 if (cam_ignore == true) { 1416 /* 1417 * F=0 & i=1: Logical server notification (bits ignored at 1418 * the end of the NVT identifier) 1419 */ 1420 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1421 nvt_blk, nvt_idx); 1422 return -1; 1423 } 1424 1425 /* F=0 & i=0: Specific NVT notification */ 1426 1427 /* PHYS ring */ 1428 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1429 cam == xive_tctx_hw_cam_line(xptr, tctx)) { 1430 return TM_QW3_HV_PHYS; 1431 } 1432 1433 /* HV POOL ring */ 1434 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1435 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1436 return TM_QW2_HV_POOL; 1437 } 1438 1439 /* OS ring */ 1440 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1441 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1442 return TM_QW1_OS; 1443 } 1444 } else { 1445 /* F=1 : User level Event-Based Branch (EBB) notification */ 1446 1447 /* USER ring */ 1448 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1449 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1450 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1451 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1452 return TM_QW0_USER; 1453 } 1454 } 1455 return -1; 1456 } 1457 1458 /* 1459 * This is our simple Xive Presenter Engine model. It is merged in the 1460 * Router as it does not require an extra object. 1461 * 1462 * It receives notification requests sent by the IVRE to find one 1463 * matching NVT (or more) dispatched on the processor threads. In case 1464 * of a single NVT notification, the process is abreviated and the 1465 * thread is signaled if a match is found. In case of a logical server 1466 * notification (bits ignored at the end of the NVT identifier), the 1467 * IVPE and IVRE select a winning thread using different filters. This 1468 * involves 2 or 3 exchanges on the PowerBus that the model does not 1469 * support. 1470 * 1471 * The parameters represent what is sent on the PowerBus 1472 */ 1473 static bool xive_presenter_notify(uint8_t format, 1474 uint8_t nvt_blk, uint32_t nvt_idx, 1475 bool cam_ignore, uint8_t priority, 1476 uint32_t logic_serv) 1477 { 1478 XiveFabric *xfb = XIVE_FABRIC(qdev_get_machine()); 1479 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb); 1480 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1481 int count; 1482 1483 /* 1484 * Ask the machine to scan the interrupt controllers for a match 1485 */ 1486 count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore, 1487 priority, logic_serv, &match); 1488 if (count < 0) { 1489 return false; 1490 } 1491 1492 /* handle CPU exception delivery */ 1493 if (count) { 1494 xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(priority)); 1495 } 1496 1497 return !!count; 1498 } 1499 1500 /* 1501 * Notification using the END ESe/ESn bit (Event State Buffer for 1502 * escalation and notification). Profide futher coalescing in the 1503 * Router. 1504 */ 1505 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1506 uint32_t end_idx, XiveEND *end, 1507 uint32_t end_esmask) 1508 { 1509 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1510 bool notify = xive_esb_trigger(&pq); 1511 1512 if (pq != xive_get_field32(end_esmask, end->w1)) { 1513 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1514 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1515 } 1516 1517 /* ESe/n[Q]=1 : end of notification */ 1518 return notify; 1519 } 1520 1521 /* 1522 * An END trigger can come from an event trigger (IPI or HW) or from 1523 * another chip. We don't model the PowerBus but the END trigger 1524 * message has the same parameters than in the function below. 1525 */ 1526 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1527 uint32_t end_idx, uint32_t end_data) 1528 { 1529 XiveEND end; 1530 uint8_t priority; 1531 uint8_t format; 1532 uint8_t nvt_blk; 1533 uint32_t nvt_idx; 1534 XiveNVT nvt; 1535 bool found; 1536 1537 /* END cache lookup */ 1538 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1539 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1540 end_idx); 1541 return; 1542 } 1543 1544 if (!xive_end_is_valid(&end)) { 1545 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1546 end_blk, end_idx); 1547 return; 1548 } 1549 1550 if (xive_end_is_enqueue(&end)) { 1551 xive_end_enqueue(&end, end_data); 1552 /* Enqueuing event data modifies the EQ toggle and index */ 1553 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1554 } 1555 1556 /* 1557 * When the END is silent, we skip the notification part. 1558 */ 1559 if (xive_end_is_silent_escalation(&end)) { 1560 goto do_escalation; 1561 } 1562 1563 /* 1564 * The W7 format depends on the F bit in W6. It defines the type 1565 * of the notification : 1566 * 1567 * F=0 : single or multiple NVT notification 1568 * F=1 : User level Event-Based Branch (EBB) notification, no 1569 * priority 1570 */ 1571 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1572 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1573 1574 /* The END is masked */ 1575 if (format == 0 && priority == 0xff) { 1576 return; 1577 } 1578 1579 /* 1580 * Check the END ESn (Event State Buffer for notification) for 1581 * even futher coalescing in the Router 1582 */ 1583 if (!xive_end_is_notify(&end)) { 1584 /* ESn[Q]=1 : end of notification */ 1585 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1586 &end, END_W1_ESn)) { 1587 return; 1588 } 1589 } 1590 1591 /* 1592 * Follows IVPE notification 1593 */ 1594 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1595 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1596 1597 /* NVT cache lookup */ 1598 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1599 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1600 nvt_blk, nvt_idx); 1601 return; 1602 } 1603 1604 if (!xive_nvt_is_valid(&nvt)) { 1605 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1606 nvt_blk, nvt_idx); 1607 return; 1608 } 1609 1610 found = xive_presenter_notify(format, nvt_blk, nvt_idx, 1611 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1612 priority, 1613 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1614 1615 /* TODO: Auto EOI. */ 1616 1617 if (found) { 1618 return; 1619 } 1620 1621 /* 1622 * If no matching NVT is dispatched on a HW thread : 1623 * - specific VP: update the NVT structure if backlog is activated 1624 * - logical server : forward request to IVPE (not supported) 1625 */ 1626 if (xive_end_is_backlog(&end)) { 1627 uint8_t ipb; 1628 1629 if (format == 1) { 1630 qemu_log_mask(LOG_GUEST_ERROR, 1631 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1632 end_blk, end_idx); 1633 return; 1634 } 1635 /* 1636 * Record the IPB in the associated NVT structure for later 1637 * use. The presenter will resend the interrupt when the vCPU 1638 * is dispatched again on a HW thread. 1639 */ 1640 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priority); 1641 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); 1642 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1643 1644 /* 1645 * On HW, follows a "Broadcast Backlog" to IVPEs 1646 */ 1647 } 1648 1649 do_escalation: 1650 /* 1651 * If activated, escalate notification using the ESe PQ bits and 1652 * the EAS in w4-5 1653 */ 1654 if (!xive_end_is_escalate(&end)) { 1655 return; 1656 } 1657 1658 /* 1659 * Check the END ESe (Event State Buffer for escalation) for even 1660 * futher coalescing in the Router 1661 */ 1662 if (!xive_end_is_uncond_escalation(&end)) { 1663 /* ESe[Q]=1 : end of notification */ 1664 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1665 &end, END_W1_ESe)) { 1666 return; 1667 } 1668 } 1669 1670 /* 1671 * The END trigger becomes an Escalation trigger 1672 */ 1673 xive_router_end_notify(xrtr, 1674 xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1675 xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1676 xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1677 } 1678 1679 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 1680 { 1681 XiveRouter *xrtr = XIVE_ROUTER(xn); 1682 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1683 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1684 XiveEAS eas; 1685 1686 /* EAS cache lookup */ 1687 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1688 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1689 return; 1690 } 1691 1692 /* 1693 * The IVRE checks the State Bit Cache at this point. We skip the 1694 * SBC lookup because the state bits of the sources are modeled 1695 * internally in QEMU. 1696 */ 1697 1698 if (!xive_eas_is_valid(&eas)) { 1699 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1700 return; 1701 } 1702 1703 if (xive_eas_is_masked(&eas)) { 1704 /* Notification completed */ 1705 return; 1706 } 1707 1708 /* 1709 * The event trigger becomes an END trigger 1710 */ 1711 xive_router_end_notify(xrtr, 1712 xive_get_field64(EAS_END_BLOCK, eas.w), 1713 xive_get_field64(EAS_END_INDEX, eas.w), 1714 xive_get_field64(EAS_END_DATA, eas.w)); 1715 } 1716 1717 static void xive_router_class_init(ObjectClass *klass, void *data) 1718 { 1719 DeviceClass *dc = DEVICE_CLASS(klass); 1720 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1721 1722 dc->desc = "XIVE Router Engine"; 1723 xnc->notify = xive_router_notify; 1724 } 1725 1726 static const TypeInfo xive_router_info = { 1727 .name = TYPE_XIVE_ROUTER, 1728 .parent = TYPE_SYS_BUS_DEVICE, 1729 .abstract = true, 1730 .class_size = sizeof(XiveRouterClass), 1731 .class_init = xive_router_class_init, 1732 .interfaces = (InterfaceInfo[]) { 1733 { TYPE_XIVE_NOTIFIER }, 1734 { TYPE_XIVE_PRESENTER }, 1735 { } 1736 } 1737 }; 1738 1739 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1740 { 1741 if (!xive_eas_is_valid(eas)) { 1742 return; 1743 } 1744 1745 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1746 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1747 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1748 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1749 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1750 } 1751 1752 /* 1753 * END ESB MMIO loads 1754 */ 1755 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1756 { 1757 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1758 uint32_t offset = addr & 0xFFF; 1759 uint8_t end_blk; 1760 uint32_t end_idx; 1761 XiveEND end; 1762 uint32_t end_esmask; 1763 uint8_t pq; 1764 uint64_t ret = -1; 1765 1766 /* 1767 * The block id should be deduced from the load address on the END 1768 * ESB MMIO but our model only supports a single block per XIVE chip. 1769 */ 1770 end_blk = xive_router_get_block_id(xsrc->xrtr); 1771 end_idx = addr >> (xsrc->esb_shift + 1); 1772 1773 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1774 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1775 end_idx); 1776 return -1; 1777 } 1778 1779 if (!xive_end_is_valid(&end)) { 1780 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1781 end_blk, end_idx); 1782 return -1; 1783 } 1784 1785 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1786 pq = xive_get_field32(end_esmask, end.w1); 1787 1788 switch (offset) { 1789 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1790 ret = xive_esb_eoi(&pq); 1791 1792 /* Forward the source event notification for routing ?? */ 1793 break; 1794 1795 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1796 ret = pq; 1797 break; 1798 1799 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1800 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1801 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1802 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1803 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1804 break; 1805 default: 1806 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1807 offset); 1808 return -1; 1809 } 1810 1811 if (pq != xive_get_field32(end_esmask, end.w1)) { 1812 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1813 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1814 } 1815 1816 return ret; 1817 } 1818 1819 /* 1820 * END ESB MMIO stores are invalid 1821 */ 1822 static void xive_end_source_write(void *opaque, hwaddr addr, 1823 uint64_t value, unsigned size) 1824 { 1825 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1826 HWADDR_PRIx"\n", addr); 1827 } 1828 1829 static const MemoryRegionOps xive_end_source_ops = { 1830 .read = xive_end_source_read, 1831 .write = xive_end_source_write, 1832 .endianness = DEVICE_BIG_ENDIAN, 1833 .valid = { 1834 .min_access_size = 8, 1835 .max_access_size = 8, 1836 }, 1837 .impl = { 1838 .min_access_size = 8, 1839 .max_access_size = 8, 1840 }, 1841 }; 1842 1843 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1844 { 1845 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1846 1847 assert(xsrc->xrtr); 1848 1849 if (!xsrc->nr_ends) { 1850 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1851 return; 1852 } 1853 1854 if (xsrc->esb_shift != XIVE_ESB_4K && 1855 xsrc->esb_shift != XIVE_ESB_64K) { 1856 error_setg(errp, "Invalid ESB shift setting"); 1857 return; 1858 } 1859 1860 /* 1861 * Each END is assigned an even/odd pair of MMIO pages, the even page 1862 * manages the ESn field while the odd page manages the ESe field. 1863 */ 1864 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1865 &xive_end_source_ops, xsrc, "xive.end", 1866 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1867 } 1868 1869 static Property xive_end_source_properties[] = { 1870 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1871 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1872 DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, 1873 XiveRouter *), 1874 DEFINE_PROP_END_OF_LIST(), 1875 }; 1876 1877 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1878 { 1879 DeviceClass *dc = DEVICE_CLASS(klass); 1880 1881 dc->desc = "XIVE END Source"; 1882 dc->props = xive_end_source_properties; 1883 dc->realize = xive_end_source_realize; 1884 /* 1885 * Reason: part of XIVE interrupt controller, needs to be wired up, 1886 * e.g. by spapr_xive_instance_init(). 1887 */ 1888 dc->user_creatable = false; 1889 } 1890 1891 static const TypeInfo xive_end_source_info = { 1892 .name = TYPE_XIVE_END_SOURCE, 1893 .parent = TYPE_DEVICE, 1894 .instance_size = sizeof(XiveENDSource), 1895 .class_init = xive_end_source_class_init, 1896 }; 1897 1898 /* 1899 * XIVE Notifier 1900 */ 1901 static const TypeInfo xive_notifier_info = { 1902 .name = TYPE_XIVE_NOTIFIER, 1903 .parent = TYPE_INTERFACE, 1904 .class_size = sizeof(XiveNotifierClass), 1905 }; 1906 1907 /* 1908 * XIVE Presenter 1909 */ 1910 static const TypeInfo xive_presenter_info = { 1911 .name = TYPE_XIVE_PRESENTER, 1912 .parent = TYPE_INTERFACE, 1913 .class_size = sizeof(XivePresenterClass), 1914 }; 1915 1916 /* 1917 * XIVE Fabric 1918 */ 1919 static const TypeInfo xive_fabric_info = { 1920 .name = TYPE_XIVE_FABRIC, 1921 .parent = TYPE_INTERFACE, 1922 .class_size = sizeof(XiveFabricClass), 1923 }; 1924 1925 static void xive_register_types(void) 1926 { 1927 type_register_static(&xive_fabric_info); 1928 type_register_static(&xive_source_info); 1929 type_register_static(&xive_notifier_info); 1930 type_register_static(&xive_presenter_info); 1931 type_register_static(&xive_router_info); 1932 type_register_static(&xive_end_source_info); 1933 type_register_static(&xive_tctx_info); 1934 } 1935 1936 type_init(xive_register_types) 1937