1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "monitor/monitor.h" 21 #include "hw/irq.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive_regs.h" 24 25 /* 26 * XIVE Thread Interrupt Management context 27 */ 28 29 /* 30 * Convert a priority number to an Interrupt Pending Buffer (IPB) 31 * register, which indicates a pending interrupt at the priority 32 * corresponding to the bit number 33 */ 34 static uint8_t priority_to_ipb(uint8_t priority) 35 { 36 return priority > XIVE_PRIORITY_MAX ? 37 0 : 1 << (XIVE_PRIORITY_MAX - priority); 38 } 39 40 /* 41 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 42 * Interrupt Priority Register (PIPR), which contains the priority of 43 * the most favored pending notification. 44 */ 45 static uint8_t ipb_to_pipr(uint8_t ibp) 46 { 47 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 48 } 49 50 static void ipb_update(uint8_t *regs, uint8_t priority) 51 { 52 regs[TM_IPB] |= priority_to_ipb(priority); 53 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 54 } 55 56 static uint8_t exception_mask(uint8_t ring) 57 { 58 switch (ring) { 59 case TM_QW1_OS: 60 return TM_QW1_NSR_EO; 61 case TM_QW3_HV_PHYS: 62 return TM_QW3_NSR_HE; 63 default: 64 g_assert_not_reached(); 65 } 66 } 67 68 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 69 { 70 switch (ring) { 71 case TM_QW0_USER: 72 return 0; /* Not supported */ 73 case TM_QW1_OS: 74 return tctx->os_output; 75 case TM_QW2_HV_POOL: 76 case TM_QW3_HV_PHYS: 77 return tctx->hv_output; 78 default: 79 return 0; 80 } 81 } 82 83 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 84 { 85 uint8_t *regs = &tctx->regs[ring]; 86 uint8_t nsr = regs[TM_NSR]; 87 uint8_t mask = exception_mask(ring); 88 89 qemu_irq_lower(xive_tctx_output(tctx, ring)); 90 91 if (regs[TM_NSR] & mask) { 92 uint8_t cppr = regs[TM_PIPR]; 93 94 regs[TM_CPPR] = cppr; 95 96 /* Reset the pending buffer bit */ 97 regs[TM_IPB] &= ~priority_to_ipb(cppr); 98 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 99 100 /* Drop Exception bit */ 101 regs[TM_NSR] &= ~mask; 102 } 103 104 return (nsr << 8) | regs[TM_CPPR]; 105 } 106 107 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 108 { 109 uint8_t *regs = &tctx->regs[ring]; 110 111 if (regs[TM_PIPR] < regs[TM_CPPR]) { 112 switch (ring) { 113 case TM_QW1_OS: 114 regs[TM_NSR] |= TM_QW1_NSR_EO; 115 break; 116 case TM_QW3_HV_PHYS: 117 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 118 break; 119 default: 120 g_assert_not_reached(); 121 } 122 qemu_irq_raise(xive_tctx_output(tctx, ring)); 123 } 124 } 125 126 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 127 { 128 if (cppr > XIVE_PRIORITY_MAX) { 129 cppr = 0xff; 130 } 131 132 tctx->regs[ring + TM_CPPR] = cppr; 133 134 /* CPPR has changed, check if we need to raise a pending exception */ 135 xive_tctx_notify(tctx, ring); 136 } 137 138 static inline uint32_t xive_tctx_word2(uint8_t *ring) 139 { 140 return *((uint32_t *) &ring[TM_WORD2]); 141 } 142 143 /* 144 * XIVE Thread Interrupt Management Area (TIMA) 145 */ 146 147 static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset, 148 uint64_t value, unsigned size) 149 { 150 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 151 } 152 153 static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) 154 { 155 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 156 } 157 158 static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, 159 unsigned size) 160 { 161 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 162 uint32_t qw2w2; 163 164 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 165 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 166 return qw2w2; 167 } 168 169 static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset, 170 uint64_t value, unsigned size) 171 { 172 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 173 } 174 175 static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned size) 176 { 177 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 178 } 179 180 /* 181 * Define an access map for each page of the TIMA that we will use in 182 * the memory region ops to filter values when doing loads and stores 183 * of raw registers values 184 * 185 * Registers accessibility bits : 186 * 187 * 0x0 - no access 188 * 0x1 - write only 189 * 0x2 - read only 190 * 0x3 - read/write 191 */ 192 193 static const uint8_t xive_tm_hw_view[] = { 194 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 195 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 196 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 197 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 198 }; 199 200 static const uint8_t xive_tm_hv_view[] = { 201 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 202 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 203 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 204 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 205 }; 206 207 static const uint8_t xive_tm_os_view[] = { 208 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 209 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 210 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 211 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 212 }; 213 214 static const uint8_t xive_tm_user_view[] = { 215 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 219 }; 220 221 /* 222 * Overall TIMA access map for the thread interrupt management context 223 * registers 224 */ 225 static const uint8_t *xive_tm_views[] = { 226 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 227 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 228 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 229 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 230 }; 231 232 /* 233 * Computes a register access mask for a given offset in the TIMA 234 */ 235 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 236 { 237 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 238 uint8_t reg_offset = offset & 0x3F; 239 uint8_t reg_mask = write ? 0x1 : 0x2; 240 uint64_t mask = 0x0; 241 int i; 242 243 for (i = 0; i < size; i++) { 244 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 245 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 246 } 247 } 248 249 return mask; 250 } 251 252 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 253 unsigned size) 254 { 255 uint8_t ring_offset = offset & 0x30; 256 uint8_t reg_offset = offset & 0x3F; 257 uint64_t mask = xive_tm_mask(offset, size, true); 258 int i; 259 260 /* 261 * Only 4 or 8 bytes stores are allowed and the User ring is 262 * excluded 263 */ 264 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 265 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 266 HWADDR_PRIx"\n", offset); 267 return; 268 } 269 270 /* 271 * Use the register offset for the raw values and filter out 272 * reserved values 273 */ 274 for (i = 0; i < size; i++) { 275 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 276 if (byte_mask) { 277 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 278 byte_mask; 279 } 280 } 281 } 282 283 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 284 { 285 uint8_t ring_offset = offset & 0x30; 286 uint8_t reg_offset = offset & 0x3F; 287 uint64_t mask = xive_tm_mask(offset, size, false); 288 uint64_t ret; 289 int i; 290 291 /* 292 * Only 4 or 8 bytes loads are allowed and the User ring is 293 * excluded 294 */ 295 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 296 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 297 HWADDR_PRIx"\n", offset); 298 return -1; 299 } 300 301 /* Use the register offset for the raw values */ 302 ret = 0; 303 for (i = 0; i < size; i++) { 304 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 305 } 306 307 /* filter out reserved values */ 308 return ret & mask; 309 } 310 311 /* 312 * The TM context is mapped twice within each page. Stores and loads 313 * to the first mapping below 2K write and read the specified values 314 * without modification. The second mapping above 2K performs specific 315 * state changes (side effects) in addition to setting/returning the 316 * interrupt management area context of the processor thread. 317 */ 318 static uint64_t xive_tm_ack_os_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) 319 { 320 return xive_tctx_accept(tctx, TM_QW1_OS); 321 } 322 323 static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset, 324 uint64_t value, unsigned size) 325 { 326 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 327 } 328 329 /* 330 * Adjust the IPB to allow a CPU to process event queues of other 331 * priorities during one physical interrupt cycle. 332 */ 333 static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset, 334 uint64_t value, unsigned size) 335 { 336 ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff); 337 xive_tctx_notify(tctx, TM_QW1_OS); 338 } 339 340 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, 341 uint32_t *nvt_idx, bool *vo) 342 { 343 if (nvt_blk) { 344 *nvt_blk = xive_nvt_blk(cam); 345 } 346 if (nvt_idx) { 347 *nvt_idx = xive_nvt_idx(cam); 348 } 349 if (vo) { 350 *vo = !!(cam & TM_QW1W2_VO); 351 } 352 } 353 354 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk, 355 uint32_t *nvt_idx, bool *vo) 356 { 357 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 358 uint32_t cam = be32_to_cpu(qw1w2); 359 360 xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo); 361 return qw1w2; 362 } 363 364 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) 365 { 366 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 367 } 368 369 static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset, 370 unsigned size) 371 { 372 uint32_t qw1w2; 373 uint32_t qw1w2_new; 374 uint8_t nvt_blk; 375 uint32_t nvt_idx; 376 bool vo; 377 378 qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); 379 380 /* Invalidate CAM line */ 381 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); 382 xive_tctx_set_os_cam(tctx, qw1w2_new); 383 return qw1w2; 384 } 385 386 /* 387 * Define a mapping of "special" operations depending on the TIMA page 388 * offset and the size of the operation. 389 */ 390 typedef struct XiveTmOp { 391 uint8_t page_offset; 392 uint32_t op_offset; 393 unsigned size; 394 void (*write_handler)(XiveTCTX *tctx, hwaddr offset, uint64_t value, 395 unsigned size); 396 uint64_t (*read_handler)(XiveTCTX *tctx, hwaddr offset, unsigned size); 397 } XiveTmOp; 398 399 static const XiveTmOp xive_tm_operations[] = { 400 /* 401 * MMIOs below 2K : raw values and special operations without side 402 * effects 403 */ 404 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 405 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 406 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 407 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 408 409 /* MMIOs above 2K : special operations with side effects */ 410 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 411 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 412 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, 413 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, 414 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 415 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 416 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 417 }; 418 419 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 420 { 421 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 422 uint32_t op_offset = offset & 0xFFF; 423 int i; 424 425 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 426 const XiveTmOp *xto = &xive_tm_operations[i]; 427 428 /* Accesses done from a more privileged TIMA page is allowed */ 429 if (xto->page_offset >= page_offset && 430 xto->op_offset == op_offset && 431 xto->size == size && 432 ((write && xto->write_handler) || (!write && xto->read_handler))) { 433 return xto; 434 } 435 } 436 return NULL; 437 } 438 439 /* 440 * TIMA MMIO handlers 441 */ 442 void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 443 unsigned size) 444 { 445 const XiveTmOp *xto; 446 447 /* 448 * TODO: check V bit in Q[0-3]W2 449 */ 450 451 /* 452 * First, check for special operations in the 2K region 453 */ 454 if (offset & 0x800) { 455 xto = xive_tm_find_op(offset, size, true); 456 if (!xto) { 457 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 458 "@%"HWADDR_PRIx"\n", offset); 459 } else { 460 xto->write_handler(tctx, offset, value, size); 461 } 462 return; 463 } 464 465 /* 466 * Then, for special operations in the region below 2K. 467 */ 468 xto = xive_tm_find_op(offset, size, true); 469 if (xto) { 470 xto->write_handler(tctx, offset, value, size); 471 return; 472 } 473 474 /* 475 * Finish with raw access to the register values 476 */ 477 xive_tm_raw_write(tctx, offset, value, size); 478 } 479 480 uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 481 { 482 const XiveTmOp *xto; 483 484 /* 485 * TODO: check V bit in Q[0-3]W2 486 */ 487 488 /* 489 * First, check for special operations in the 2K region 490 */ 491 if (offset & 0x800) { 492 xto = xive_tm_find_op(offset, size, false); 493 if (!xto) { 494 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 495 "@%"HWADDR_PRIx"\n", offset); 496 return -1; 497 } 498 return xto->read_handler(tctx, offset, size); 499 } 500 501 /* 502 * Then, for special operations in the region below 2K. 503 */ 504 xto = xive_tm_find_op(offset, size, false); 505 if (xto) { 506 return xto->read_handler(tctx, offset, size); 507 } 508 509 /* 510 * Finish with raw access to the register values 511 */ 512 return xive_tm_raw_read(tctx, offset, size); 513 } 514 515 static void xive_tm_write(void *opaque, hwaddr offset, 516 uint64_t value, unsigned size) 517 { 518 XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); 519 520 xive_tctx_tm_write(tctx, offset, value, size); 521 } 522 523 static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) 524 { 525 XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); 526 527 return xive_tctx_tm_read(tctx, offset, size); 528 } 529 530 const MemoryRegionOps xive_tm_ops = { 531 .read = xive_tm_read, 532 .write = xive_tm_write, 533 .endianness = DEVICE_BIG_ENDIAN, 534 .valid = { 535 .min_access_size = 1, 536 .max_access_size = 8, 537 }, 538 .impl = { 539 .min_access_size = 1, 540 .max_access_size = 8, 541 }, 542 }; 543 544 static char *xive_tctx_ring_print(uint8_t *ring) 545 { 546 uint32_t w2 = xive_tctx_word2(ring); 547 548 return g_strdup_printf("%02x %02x %02x %02x %02x " 549 "%02x %02x %02x %08x", 550 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 551 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 552 be32_to_cpu(w2)); 553 } 554 555 static const char * const xive_tctx_ring_names[] = { 556 "USER", "OS", "POOL", "PHYS", 557 }; 558 559 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 560 { 561 int cpu_index; 562 int i; 563 564 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs 565 * are hot plugged or unplugged. 566 */ 567 if (!tctx) { 568 return; 569 } 570 571 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 572 573 if (kvm_irqchip_in_kernel()) { 574 Error *local_err = NULL; 575 576 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 577 if (local_err) { 578 error_report_err(local_err); 579 return; 580 } 581 } 582 583 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 584 " W2\n", cpu_index); 585 586 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 587 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 588 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 589 xive_tctx_ring_names[i], s); 590 g_free(s); 591 } 592 } 593 594 void xive_tctx_reset(XiveTCTX *tctx) 595 { 596 memset(tctx->regs, 0, sizeof(tctx->regs)); 597 598 /* Set some defaults */ 599 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 600 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 601 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 602 603 /* 604 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 605 * CPPR is first set. 606 */ 607 tctx->regs[TM_QW1_OS + TM_PIPR] = 608 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 609 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 610 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 611 } 612 613 static void xive_tctx_realize(DeviceState *dev, Error **errp) 614 { 615 XiveTCTX *tctx = XIVE_TCTX(dev); 616 PowerPCCPU *cpu; 617 CPUPPCState *env; 618 Error *local_err = NULL; 619 620 assert(tctx->cs); 621 622 cpu = POWERPC_CPU(tctx->cs); 623 env = &cpu->env; 624 switch (PPC_INPUT(env)) { 625 case PPC_FLAGS_INPUT_POWER9: 626 tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT]; 627 tctx->os_output = env->irq_inputs[POWER9_INPUT_INT]; 628 break; 629 630 default: 631 error_setg(errp, "XIVE interrupt controller does not support " 632 "this CPU bus model"); 633 return; 634 } 635 636 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 637 if (kvm_irqchip_in_kernel()) { 638 kvmppc_xive_cpu_connect(tctx, &local_err); 639 if (local_err) { 640 error_propagate(errp, local_err); 641 return; 642 } 643 } 644 } 645 646 static int vmstate_xive_tctx_pre_save(void *opaque) 647 { 648 Error *local_err = NULL; 649 650 if (kvm_irqchip_in_kernel()) { 651 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque), &local_err); 652 if (local_err) { 653 error_report_err(local_err); 654 return -1; 655 } 656 } 657 658 return 0; 659 } 660 661 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 662 { 663 Error *local_err = NULL; 664 665 if (kvm_irqchip_in_kernel()) { 666 /* 667 * Required for hotplugged CPU, for which the state comes 668 * after all states of the machine. 669 */ 670 kvmppc_xive_cpu_set_state(XIVE_TCTX(opaque), &local_err); 671 if (local_err) { 672 error_report_err(local_err); 673 return -1; 674 } 675 } 676 677 return 0; 678 } 679 680 static const VMStateDescription vmstate_xive_tctx = { 681 .name = TYPE_XIVE_TCTX, 682 .version_id = 1, 683 .minimum_version_id = 1, 684 .pre_save = vmstate_xive_tctx_pre_save, 685 .post_load = vmstate_xive_tctx_post_load, 686 .fields = (VMStateField[]) { 687 VMSTATE_BUFFER(regs, XiveTCTX), 688 VMSTATE_END_OF_LIST() 689 }, 690 }; 691 692 static Property xive_tctx_properties[] = { 693 DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), 694 DEFINE_PROP_END_OF_LIST(), 695 }; 696 697 static void xive_tctx_class_init(ObjectClass *klass, void *data) 698 { 699 DeviceClass *dc = DEVICE_CLASS(klass); 700 701 dc->desc = "XIVE Interrupt Thread Context"; 702 dc->realize = xive_tctx_realize; 703 dc->vmsd = &vmstate_xive_tctx; 704 dc->props = xive_tctx_properties; 705 /* 706 * Reason: part of XIVE interrupt controller, needs to be wired up 707 * by xive_tctx_create(). 708 */ 709 dc->user_creatable = false; 710 } 711 712 static const TypeInfo xive_tctx_info = { 713 .name = TYPE_XIVE_TCTX, 714 .parent = TYPE_DEVICE, 715 .instance_size = sizeof(XiveTCTX), 716 .class_init = xive_tctx_class_init, 717 }; 718 719 Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) 720 { 721 Error *local_err = NULL; 722 Object *obj; 723 724 obj = object_new(TYPE_XIVE_TCTX); 725 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); 726 object_unref(obj); 727 object_property_set_link(obj, cpu, "cpu", &error_abort); 728 object_property_set_bool(obj, true, "realized", &local_err); 729 if (local_err) { 730 goto error; 731 } 732 733 return obj; 734 735 error: 736 object_unparent(obj); 737 error_propagate(errp, local_err); 738 return NULL; 739 } 740 741 void xive_tctx_destroy(XiveTCTX *tctx) 742 { 743 Object *obj = OBJECT(tctx); 744 745 object_unparent(obj); 746 } 747 748 /* 749 * XIVE ESB helpers 750 */ 751 752 static uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 753 { 754 uint8_t old_pq = *pq & 0x3; 755 756 *pq &= ~0x3; 757 *pq |= value & 0x3; 758 759 return old_pq; 760 } 761 762 static bool xive_esb_trigger(uint8_t *pq) 763 { 764 uint8_t old_pq = *pq & 0x3; 765 766 switch (old_pq) { 767 case XIVE_ESB_RESET: 768 xive_esb_set(pq, XIVE_ESB_PENDING); 769 return true; 770 case XIVE_ESB_PENDING: 771 case XIVE_ESB_QUEUED: 772 xive_esb_set(pq, XIVE_ESB_QUEUED); 773 return false; 774 case XIVE_ESB_OFF: 775 xive_esb_set(pq, XIVE_ESB_OFF); 776 return false; 777 default: 778 g_assert_not_reached(); 779 } 780 } 781 782 static bool xive_esb_eoi(uint8_t *pq) 783 { 784 uint8_t old_pq = *pq & 0x3; 785 786 switch (old_pq) { 787 case XIVE_ESB_RESET: 788 case XIVE_ESB_PENDING: 789 xive_esb_set(pq, XIVE_ESB_RESET); 790 return false; 791 case XIVE_ESB_QUEUED: 792 xive_esb_set(pq, XIVE_ESB_PENDING); 793 return true; 794 case XIVE_ESB_OFF: 795 xive_esb_set(pq, XIVE_ESB_OFF); 796 return false; 797 default: 798 g_assert_not_reached(); 799 } 800 } 801 802 /* 803 * XIVE Interrupt Source (or IVSE) 804 */ 805 806 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 807 { 808 assert(srcno < xsrc->nr_irqs); 809 810 return xsrc->status[srcno] & 0x3; 811 } 812 813 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 814 { 815 assert(srcno < xsrc->nr_irqs); 816 817 return xive_esb_set(&xsrc->status[srcno], pq); 818 } 819 820 /* 821 * Returns whether the event notification should be forwarded. 822 */ 823 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 824 { 825 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 826 827 xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; 828 829 switch (old_pq) { 830 case XIVE_ESB_RESET: 831 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 832 return true; 833 default: 834 return false; 835 } 836 } 837 838 /* 839 * Returns whether the event notification should be forwarded. 840 */ 841 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 842 { 843 bool ret; 844 845 assert(srcno < xsrc->nr_irqs); 846 847 ret = xive_esb_trigger(&xsrc->status[srcno]); 848 849 if (xive_source_irq_is_lsi(xsrc, srcno) && 850 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 851 qemu_log_mask(LOG_GUEST_ERROR, 852 "XIVE: queued an event on LSI IRQ %d\n", srcno); 853 } 854 855 return ret; 856 } 857 858 /* 859 * Returns whether the event notification should be forwarded. 860 */ 861 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 862 { 863 bool ret; 864 865 assert(srcno < xsrc->nr_irqs); 866 867 ret = xive_esb_eoi(&xsrc->status[srcno]); 868 869 /* 870 * LSI sources do not set the Q bit but they can still be 871 * asserted, in which case we should forward a new event 872 * notification 873 */ 874 if (xive_source_irq_is_lsi(xsrc, srcno) && 875 xsrc->status[srcno] & XIVE_STATUS_ASSERTED) { 876 ret = xive_source_lsi_trigger(xsrc, srcno); 877 } 878 879 return ret; 880 } 881 882 /* 883 * Forward the source event notification to the Router 884 */ 885 static void xive_source_notify(XiveSource *xsrc, int srcno) 886 { 887 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 888 889 if (xnc->notify) { 890 xnc->notify(xsrc->xive, srcno); 891 } 892 } 893 894 /* 895 * In a two pages ESB MMIO setting, even page is the trigger page, odd 896 * page is for management 897 */ 898 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 899 { 900 return !((addr >> shift) & 1); 901 } 902 903 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 904 { 905 return xive_source_esb_has_2page(xsrc) && 906 addr_is_even(addr, xsrc->esb_shift - 1); 907 } 908 909 /* 910 * ESB MMIO loads 911 * Trigger page Management/EOI page 912 * 913 * ESB MMIO setting 2 pages 1 or 2 pages 914 * 915 * 0x000 .. 0x3FF -1 EOI and return 0|1 916 * 0x400 .. 0x7FF -1 EOI and return 0|1 917 * 0x800 .. 0xBFF -1 return PQ 918 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 919 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 920 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 921 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 922 */ 923 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 924 { 925 XiveSource *xsrc = XIVE_SOURCE(opaque); 926 uint32_t offset = addr & 0xFFF; 927 uint32_t srcno = addr >> xsrc->esb_shift; 928 uint64_t ret = -1; 929 930 /* In a two pages ESB MMIO setting, trigger page should not be read */ 931 if (xive_source_is_trigger_page(xsrc, addr)) { 932 qemu_log_mask(LOG_GUEST_ERROR, 933 "XIVE: invalid load on IRQ %d trigger page at " 934 "0x%"HWADDR_PRIx"\n", srcno, addr); 935 return -1; 936 } 937 938 switch (offset) { 939 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 940 ret = xive_source_esb_eoi(xsrc, srcno); 941 942 /* Forward the source event notification for routing */ 943 if (ret) { 944 xive_source_notify(xsrc, srcno); 945 } 946 break; 947 948 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 949 ret = xive_source_esb_get(xsrc, srcno); 950 break; 951 952 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 953 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 954 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 955 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 956 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 957 break; 958 default: 959 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 960 offset); 961 } 962 963 return ret; 964 } 965 966 /* 967 * ESB MMIO stores 968 * Trigger page Management/EOI page 969 * 970 * ESB MMIO setting 2 pages 1 or 2 pages 971 * 972 * 0x000 .. 0x3FF Trigger Trigger 973 * 0x400 .. 0x7FF Trigger EOI 974 * 0x800 .. 0xBFF Trigger undefined 975 * 0xC00 .. 0xCFF Trigger PQ=00 976 * 0xD00 .. 0xDFF Trigger PQ=01 977 * 0xE00 .. 0xDFF Trigger PQ=10 978 * 0xF00 .. 0xDFF Trigger PQ=11 979 */ 980 static void xive_source_esb_write(void *opaque, hwaddr addr, 981 uint64_t value, unsigned size) 982 { 983 XiveSource *xsrc = XIVE_SOURCE(opaque); 984 uint32_t offset = addr & 0xFFF; 985 uint32_t srcno = addr >> xsrc->esb_shift; 986 bool notify = false; 987 988 /* In a two pages ESB MMIO setting, trigger page only triggers */ 989 if (xive_source_is_trigger_page(xsrc, addr)) { 990 notify = xive_source_esb_trigger(xsrc, srcno); 991 goto out; 992 } 993 994 switch (offset) { 995 case 0 ... 0x3FF: 996 notify = xive_source_esb_trigger(xsrc, srcno); 997 break; 998 999 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 1000 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 1001 qemu_log_mask(LOG_GUEST_ERROR, 1002 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 1003 return; 1004 } 1005 1006 notify = xive_source_esb_eoi(xsrc, srcno); 1007 break; 1008 1009 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1010 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1011 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1012 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1013 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1014 break; 1015 1016 default: 1017 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 1018 offset); 1019 return; 1020 } 1021 1022 out: 1023 /* Forward the source event notification for routing */ 1024 if (notify) { 1025 xive_source_notify(xsrc, srcno); 1026 } 1027 } 1028 1029 static const MemoryRegionOps xive_source_esb_ops = { 1030 .read = xive_source_esb_read, 1031 .write = xive_source_esb_write, 1032 .endianness = DEVICE_BIG_ENDIAN, 1033 .valid = { 1034 .min_access_size = 8, 1035 .max_access_size = 8, 1036 }, 1037 .impl = { 1038 .min_access_size = 8, 1039 .max_access_size = 8, 1040 }, 1041 }; 1042 1043 void xive_source_set_irq(void *opaque, int srcno, int val) 1044 { 1045 XiveSource *xsrc = XIVE_SOURCE(opaque); 1046 bool notify = false; 1047 1048 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1049 if (val) { 1050 notify = xive_source_lsi_trigger(xsrc, srcno); 1051 } else { 1052 xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; 1053 } 1054 } else { 1055 if (val) { 1056 notify = xive_source_esb_trigger(xsrc, srcno); 1057 } 1058 } 1059 1060 /* Forward the source event notification for routing */ 1061 if (notify) { 1062 xive_source_notify(xsrc, srcno); 1063 } 1064 } 1065 1066 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 1067 { 1068 int i; 1069 1070 for (i = 0; i < xsrc->nr_irqs; i++) { 1071 uint8_t pq = xive_source_esb_get(xsrc, i); 1072 1073 if (pq == XIVE_ESB_OFF) { 1074 continue; 1075 } 1076 1077 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 1078 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1079 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1080 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1081 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' '); 1082 } 1083 } 1084 1085 static void xive_source_reset(void *dev) 1086 { 1087 XiveSource *xsrc = XIVE_SOURCE(dev); 1088 1089 /* Do not clear the LSI bitmap */ 1090 1091 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 1092 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 1093 } 1094 1095 static void xive_source_realize(DeviceState *dev, Error **errp) 1096 { 1097 XiveSource *xsrc = XIVE_SOURCE(dev); 1098 1099 assert(xsrc->xive); 1100 1101 if (!xsrc->nr_irqs) { 1102 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1103 return; 1104 } 1105 1106 if (xsrc->esb_shift != XIVE_ESB_4K && 1107 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1108 xsrc->esb_shift != XIVE_ESB_64K && 1109 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1110 error_setg(errp, "Invalid ESB shift setting"); 1111 return; 1112 } 1113 1114 xsrc->status = g_malloc0(xsrc->nr_irqs); 1115 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1116 1117 if (!kvm_irqchip_in_kernel()) { 1118 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1119 &xive_source_esb_ops, xsrc, "xive.esb", 1120 (1ull << xsrc->esb_shift) * xsrc->nr_irqs); 1121 } 1122 1123 qemu_register_reset(xive_source_reset, dev); 1124 } 1125 1126 static const VMStateDescription vmstate_xive_source = { 1127 .name = TYPE_XIVE_SOURCE, 1128 .version_id = 1, 1129 .minimum_version_id = 1, 1130 .fields = (VMStateField[]) { 1131 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1132 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1133 VMSTATE_END_OF_LIST() 1134 }, 1135 }; 1136 1137 /* 1138 * The default XIVE interrupt source setting for the ESB MMIOs is two 1139 * 64k pages without Store EOI, to be in sync with KVM. 1140 */ 1141 static Property xive_source_properties[] = { 1142 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1143 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1144 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1145 DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, 1146 XiveNotifier *), 1147 DEFINE_PROP_END_OF_LIST(), 1148 }; 1149 1150 static void xive_source_class_init(ObjectClass *klass, void *data) 1151 { 1152 DeviceClass *dc = DEVICE_CLASS(klass); 1153 1154 dc->desc = "XIVE Interrupt Source"; 1155 dc->props = xive_source_properties; 1156 dc->realize = xive_source_realize; 1157 dc->vmsd = &vmstate_xive_source; 1158 /* 1159 * Reason: part of XIVE interrupt controller, needs to be wired up, 1160 * e.g. by spapr_xive_instance_init(). 1161 */ 1162 dc->user_creatable = false; 1163 } 1164 1165 static const TypeInfo xive_source_info = { 1166 .name = TYPE_XIVE_SOURCE, 1167 .parent = TYPE_DEVICE, 1168 .instance_size = sizeof(XiveSource), 1169 .class_init = xive_source_class_init, 1170 }; 1171 1172 /* 1173 * XiveEND helpers 1174 */ 1175 1176 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1177 { 1178 uint64_t qaddr_base = xive_end_qaddr(end); 1179 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1180 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1181 uint32_t qentries = 1 << (qsize + 10); 1182 int i; 1183 1184 /* 1185 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1186 */ 1187 monitor_printf(mon, " [ "); 1188 qindex = (qindex - (width - 1)) & (qentries - 1); 1189 for (i = 0; i < width; i++) { 1190 uint64_t qaddr = qaddr_base + (qindex << 2); 1191 uint32_t qdata = -1; 1192 1193 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 1194 sizeof(qdata))) { 1195 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1196 HWADDR_PRIx "\n", qaddr); 1197 return; 1198 } 1199 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1200 be32_to_cpu(qdata)); 1201 qindex = (qindex + 1) & (qentries - 1); 1202 } 1203 monitor_printf(mon, "]"); 1204 } 1205 1206 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1207 { 1208 uint64_t qaddr_base = xive_end_qaddr(end); 1209 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1210 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1211 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1212 uint32_t qentries = 1 << (qsize + 10); 1213 1214 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1215 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1216 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1217 uint8_t pq; 1218 1219 if (!xive_end_is_valid(end)) { 1220 return; 1221 } 1222 1223 pq = xive_get_field32(END_W1_ESn, end->w1); 1224 1225 monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1226 end_idx, 1227 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1228 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1229 xive_end_is_valid(end) ? 'v' : '-', 1230 xive_end_is_enqueue(end) ? 'q' : '-', 1231 xive_end_is_notify(end) ? 'n' : '-', 1232 xive_end_is_backlog(end) ? 'b' : '-', 1233 xive_end_is_escalate(end) ? 'e' : '-', 1234 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1235 xive_end_is_silent_escalation(end) ? 's' : '-', 1236 priority, nvt_blk, nvt_idx); 1237 1238 if (qaddr_base) { 1239 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1240 qaddr_base, qindex, qentries, qgen); 1241 xive_end_queue_pic_print_info(end, 6, mon); 1242 } 1243 monitor_printf(mon, "\n"); 1244 } 1245 1246 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1247 { 1248 uint64_t qaddr_base = xive_end_qaddr(end); 1249 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1250 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1251 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1252 1253 uint64_t qaddr = qaddr_base + (qindex << 2); 1254 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1255 uint32_t qentries = 1 << (qsize + 10); 1256 1257 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) { 1258 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1259 HWADDR_PRIx "\n", qaddr); 1260 return; 1261 } 1262 1263 qindex = (qindex + 1) & (qentries - 1); 1264 if (qindex == 0) { 1265 qgen ^= 1; 1266 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1267 } 1268 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1269 } 1270 1271 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, 1272 Monitor *mon) 1273 { 1274 XiveEAS *eas = (XiveEAS *) &end->w4; 1275 uint8_t pq; 1276 1277 if (!xive_end_is_escalate(end)) { 1278 return; 1279 } 1280 1281 pq = xive_get_field32(END_W1_ESe, end->w1); 1282 1283 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1284 end_idx, 1285 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1286 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1287 xive_eas_is_valid(eas) ? 'V' : ' ', 1288 xive_eas_is_masked(eas) ? 'M' : ' ', 1289 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1290 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1291 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1292 } 1293 1294 /* 1295 * XIVE Router (aka. Virtualization Controller or IVRE) 1296 */ 1297 1298 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1299 XiveEAS *eas) 1300 { 1301 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1302 1303 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1304 } 1305 1306 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1307 XiveEND *end) 1308 { 1309 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1310 1311 return xrc->get_end(xrtr, end_blk, end_idx, end); 1312 } 1313 1314 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1315 XiveEND *end, uint8_t word_number) 1316 { 1317 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1318 1319 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1320 } 1321 1322 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1323 XiveNVT *nvt) 1324 { 1325 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1326 1327 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1328 } 1329 1330 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1331 XiveNVT *nvt, uint8_t word_number) 1332 { 1333 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1334 1335 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1336 } 1337 1338 XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) 1339 { 1340 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1341 1342 return xrc->get_tctx(xrtr, cs); 1343 } 1344 1345 /* 1346 * Encode the HW CAM line in the block group mode format : 1347 * 1348 * chip << 19 | 0000000 0 0001 thread (7Bit) 1349 */ 1350 static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) 1351 { 1352 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1353 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1354 1355 return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f)); 1356 } 1357 1358 /* 1359 * The thread context register words are in big-endian format. 1360 */ 1361 static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format, 1362 uint8_t nvt_blk, uint32_t nvt_idx, 1363 bool cam_ignore, uint32_t logic_serv) 1364 { 1365 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1366 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1367 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1368 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1369 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1370 1371 /* 1372 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1373 * identifier are ignored in the "CAM" match. 1374 */ 1375 1376 if (format == 0) { 1377 if (cam_ignore == true) { 1378 /* 1379 * F=0 & i=1: Logical server notification (bits ignored at 1380 * the end of the NVT identifier) 1381 */ 1382 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1383 nvt_blk, nvt_idx); 1384 return -1; 1385 } 1386 1387 /* F=0 & i=0: Specific NVT notification */ 1388 1389 /* PHYS ring */ 1390 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1391 cam == xive_tctx_hw_cam_line(tctx)) { 1392 return TM_QW3_HV_PHYS; 1393 } 1394 1395 /* HV POOL ring */ 1396 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1397 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1398 return TM_QW2_HV_POOL; 1399 } 1400 1401 /* OS ring */ 1402 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1403 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1404 return TM_QW1_OS; 1405 } 1406 } else { 1407 /* F=1 : User level Event-Based Branch (EBB) notification */ 1408 1409 /* USER ring */ 1410 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1411 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1412 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1413 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1414 return TM_QW0_USER; 1415 } 1416 } 1417 return -1; 1418 } 1419 1420 typedef struct XiveTCTXMatch { 1421 XiveTCTX *tctx; 1422 uint8_t ring; 1423 } XiveTCTXMatch; 1424 1425 static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, 1426 uint8_t nvt_blk, uint32_t nvt_idx, 1427 bool cam_ignore, uint8_t priority, 1428 uint32_t logic_serv, XiveTCTXMatch *match) 1429 { 1430 CPUState *cs; 1431 1432 /* 1433 * TODO (PowerNV): handle chip_id overwrite of block field for 1434 * hardwired CAM compares 1435 */ 1436 1437 CPU_FOREACH(cs) { 1438 XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs); 1439 int ring; 1440 1441 /* 1442 * Skip partially initialized vCPUs. This can happen when 1443 * vCPUs are hotplugged. 1444 */ 1445 if (!tctx) { 1446 continue; 1447 } 1448 1449 /* 1450 * HW checks that the CPU is enabled in the Physical Thread 1451 * Enable Register (PTER). 1452 */ 1453 1454 /* 1455 * Check the thread context CAM lines and record matches. We 1456 * will handle CPU exception delivery later 1457 */ 1458 ring = xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx, 1459 cam_ignore, logic_serv); 1460 /* 1461 * Save the context and follow on to catch duplicates, that we 1462 * don't support yet. 1463 */ 1464 if (ring != -1) { 1465 if (match->tctx) { 1466 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread " 1467 "context NVT %x/%x\n", nvt_blk, nvt_idx); 1468 return false; 1469 } 1470 1471 match->ring = ring; 1472 match->tctx = tctx; 1473 } 1474 } 1475 1476 if (!match->tctx) { 1477 qemu_log_mask(LOG_UNIMP, "XIVE: NVT %x/%x is not dispatched\n", 1478 nvt_blk, nvt_idx); 1479 return false; 1480 } 1481 1482 return true; 1483 } 1484 1485 /* 1486 * This is our simple Xive Presenter Engine model. It is merged in the 1487 * Router as it does not require an extra object. 1488 * 1489 * It receives notification requests sent by the IVRE to find one 1490 * matching NVT (or more) dispatched on the processor threads. In case 1491 * of a single NVT notification, the process is abreviated and the 1492 * thread is signaled if a match is found. In case of a logical server 1493 * notification (bits ignored at the end of the NVT identifier), the 1494 * IVPE and IVRE select a winning thread using different filters. This 1495 * involves 2 or 3 exchanges on the PowerBus that the model does not 1496 * support. 1497 * 1498 * The parameters represent what is sent on the PowerBus 1499 */ 1500 static bool xive_presenter_notify(XiveRouter *xrtr, uint8_t format, 1501 uint8_t nvt_blk, uint32_t nvt_idx, 1502 bool cam_ignore, uint8_t priority, 1503 uint32_t logic_serv) 1504 { 1505 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1506 bool found; 1507 1508 found = xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ignore, 1509 priority, logic_serv, &match); 1510 if (found) { 1511 ipb_update(&match.tctx->regs[match.ring], priority); 1512 xive_tctx_notify(match.tctx, match.ring); 1513 } 1514 1515 return found; 1516 } 1517 1518 /* 1519 * Notification using the END ESe/ESn bit (Event State Buffer for 1520 * escalation and notification). Profide futher coalescing in the 1521 * Router. 1522 */ 1523 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1524 uint32_t end_idx, XiveEND *end, 1525 uint32_t end_esmask) 1526 { 1527 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1528 bool notify = xive_esb_trigger(&pq); 1529 1530 if (pq != xive_get_field32(end_esmask, end->w1)) { 1531 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1532 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1533 } 1534 1535 /* ESe/n[Q]=1 : end of notification */ 1536 return notify; 1537 } 1538 1539 /* 1540 * An END trigger can come from an event trigger (IPI or HW) or from 1541 * another chip. We don't model the PowerBus but the END trigger 1542 * message has the same parameters than in the function below. 1543 */ 1544 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1545 uint32_t end_idx, uint32_t end_data) 1546 { 1547 XiveEND end; 1548 uint8_t priority; 1549 uint8_t format; 1550 uint8_t nvt_blk; 1551 uint32_t nvt_idx; 1552 XiveNVT nvt; 1553 bool found; 1554 1555 /* END cache lookup */ 1556 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1557 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1558 end_idx); 1559 return; 1560 } 1561 1562 if (!xive_end_is_valid(&end)) { 1563 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1564 end_blk, end_idx); 1565 return; 1566 } 1567 1568 if (xive_end_is_enqueue(&end)) { 1569 xive_end_enqueue(&end, end_data); 1570 /* Enqueuing event data modifies the EQ toggle and index */ 1571 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1572 } 1573 1574 /* 1575 * When the END is silent, we skip the notification part. 1576 */ 1577 if (xive_end_is_silent_escalation(&end)) { 1578 goto do_escalation; 1579 } 1580 1581 /* 1582 * The W7 format depends on the F bit in W6. It defines the type 1583 * of the notification : 1584 * 1585 * F=0 : single or multiple NVT notification 1586 * F=1 : User level Event-Based Branch (EBB) notification, no 1587 * priority 1588 */ 1589 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1590 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1591 1592 /* The END is masked */ 1593 if (format == 0 && priority == 0xff) { 1594 return; 1595 } 1596 1597 /* 1598 * Check the END ESn (Event State Buffer for notification) for 1599 * even futher coalescing in the Router 1600 */ 1601 if (!xive_end_is_notify(&end)) { 1602 /* ESn[Q]=1 : end of notification */ 1603 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1604 &end, END_W1_ESn)) { 1605 return; 1606 } 1607 } 1608 1609 /* 1610 * Follows IVPE notification 1611 */ 1612 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1613 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1614 1615 /* NVT cache lookup */ 1616 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1617 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1618 nvt_blk, nvt_idx); 1619 return; 1620 } 1621 1622 if (!xive_nvt_is_valid(&nvt)) { 1623 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1624 nvt_blk, nvt_idx); 1625 return; 1626 } 1627 1628 found = xive_presenter_notify(xrtr, format, nvt_blk, nvt_idx, 1629 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1630 priority, 1631 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1632 1633 /* TODO: Auto EOI. */ 1634 1635 if (found) { 1636 return; 1637 } 1638 1639 /* 1640 * If no matching NVT is dispatched on a HW thread : 1641 * - specific VP: update the NVT structure if backlog is activated 1642 * - logical server : forward request to IVPE (not supported) 1643 */ 1644 if (xive_end_is_backlog(&end)) { 1645 uint8_t ipb; 1646 1647 if (format == 1) { 1648 qemu_log_mask(LOG_GUEST_ERROR, 1649 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1650 end_blk, end_idx); 1651 return; 1652 } 1653 /* 1654 * Record the IPB in the associated NVT structure for later 1655 * use. The presenter will resend the interrupt when the vCPU 1656 * is dispatched again on a HW thread. 1657 */ 1658 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priority); 1659 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); 1660 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1661 1662 /* 1663 * On HW, follows a "Broadcast Backlog" to IVPEs 1664 */ 1665 } 1666 1667 do_escalation: 1668 /* 1669 * If activated, escalate notification using the ESe PQ bits and 1670 * the EAS in w4-5 1671 */ 1672 if (!xive_end_is_escalate(&end)) { 1673 return; 1674 } 1675 1676 /* 1677 * Check the END ESe (Event State Buffer for escalation) for even 1678 * futher coalescing in the Router 1679 */ 1680 if (!xive_end_is_uncond_escalation(&end)) { 1681 /* ESe[Q]=1 : end of notification */ 1682 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1683 &end, END_W1_ESe)) { 1684 return; 1685 } 1686 } 1687 1688 /* 1689 * The END trigger becomes an Escalation trigger 1690 */ 1691 xive_router_end_notify(xrtr, 1692 xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1693 xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1694 xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1695 } 1696 1697 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 1698 { 1699 XiveRouter *xrtr = XIVE_ROUTER(xn); 1700 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1701 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1702 XiveEAS eas; 1703 1704 /* EAS cache lookup */ 1705 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1706 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1707 return; 1708 } 1709 1710 /* 1711 * The IVRE checks the State Bit Cache at this point. We skip the 1712 * SBC lookup because the state bits of the sources are modeled 1713 * internally in QEMU. 1714 */ 1715 1716 if (!xive_eas_is_valid(&eas)) { 1717 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1718 return; 1719 } 1720 1721 if (xive_eas_is_masked(&eas)) { 1722 /* Notification completed */ 1723 return; 1724 } 1725 1726 /* 1727 * The event trigger becomes an END trigger 1728 */ 1729 xive_router_end_notify(xrtr, 1730 xive_get_field64(EAS_END_BLOCK, eas.w), 1731 xive_get_field64(EAS_END_INDEX, eas.w), 1732 xive_get_field64(EAS_END_DATA, eas.w)); 1733 } 1734 1735 static void xive_router_class_init(ObjectClass *klass, void *data) 1736 { 1737 DeviceClass *dc = DEVICE_CLASS(klass); 1738 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1739 1740 dc->desc = "XIVE Router Engine"; 1741 xnc->notify = xive_router_notify; 1742 } 1743 1744 static const TypeInfo xive_router_info = { 1745 .name = TYPE_XIVE_ROUTER, 1746 .parent = TYPE_SYS_BUS_DEVICE, 1747 .abstract = true, 1748 .class_size = sizeof(XiveRouterClass), 1749 .class_init = xive_router_class_init, 1750 .interfaces = (InterfaceInfo[]) { 1751 { TYPE_XIVE_NOTIFIER }, 1752 { } 1753 } 1754 }; 1755 1756 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1757 { 1758 if (!xive_eas_is_valid(eas)) { 1759 return; 1760 } 1761 1762 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1763 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1764 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1765 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1766 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1767 } 1768 1769 /* 1770 * END ESB MMIO loads 1771 */ 1772 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1773 { 1774 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1775 uint32_t offset = addr & 0xFFF; 1776 uint8_t end_blk; 1777 uint32_t end_idx; 1778 XiveEND end; 1779 uint32_t end_esmask; 1780 uint8_t pq; 1781 uint64_t ret = -1; 1782 1783 end_blk = xsrc->block_id; 1784 end_idx = addr >> (xsrc->esb_shift + 1); 1785 1786 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1787 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1788 end_idx); 1789 return -1; 1790 } 1791 1792 if (!xive_end_is_valid(&end)) { 1793 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1794 end_blk, end_idx); 1795 return -1; 1796 } 1797 1798 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1799 pq = xive_get_field32(end_esmask, end.w1); 1800 1801 switch (offset) { 1802 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1803 ret = xive_esb_eoi(&pq); 1804 1805 /* Forward the source event notification for routing ?? */ 1806 break; 1807 1808 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1809 ret = pq; 1810 break; 1811 1812 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1813 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1814 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1815 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1816 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1817 break; 1818 default: 1819 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1820 offset); 1821 return -1; 1822 } 1823 1824 if (pq != xive_get_field32(end_esmask, end.w1)) { 1825 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1826 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1827 } 1828 1829 return ret; 1830 } 1831 1832 /* 1833 * END ESB MMIO stores are invalid 1834 */ 1835 static void xive_end_source_write(void *opaque, hwaddr addr, 1836 uint64_t value, unsigned size) 1837 { 1838 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1839 HWADDR_PRIx"\n", addr); 1840 } 1841 1842 static const MemoryRegionOps xive_end_source_ops = { 1843 .read = xive_end_source_read, 1844 .write = xive_end_source_write, 1845 .endianness = DEVICE_BIG_ENDIAN, 1846 .valid = { 1847 .min_access_size = 8, 1848 .max_access_size = 8, 1849 }, 1850 .impl = { 1851 .min_access_size = 8, 1852 .max_access_size = 8, 1853 }, 1854 }; 1855 1856 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1857 { 1858 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1859 1860 assert(xsrc->xrtr); 1861 1862 if (!xsrc->nr_ends) { 1863 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1864 return; 1865 } 1866 1867 if (xsrc->esb_shift != XIVE_ESB_4K && 1868 xsrc->esb_shift != XIVE_ESB_64K) { 1869 error_setg(errp, "Invalid ESB shift setting"); 1870 return; 1871 } 1872 1873 /* 1874 * Each END is assigned an even/odd pair of MMIO pages, the even page 1875 * manages the ESn field while the odd page manages the ESe field. 1876 */ 1877 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1878 &xive_end_source_ops, xsrc, "xive.end", 1879 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1880 } 1881 1882 static Property xive_end_source_properties[] = { 1883 DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0), 1884 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1885 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1886 DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, 1887 XiveRouter *), 1888 DEFINE_PROP_END_OF_LIST(), 1889 }; 1890 1891 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1892 { 1893 DeviceClass *dc = DEVICE_CLASS(klass); 1894 1895 dc->desc = "XIVE END Source"; 1896 dc->props = xive_end_source_properties; 1897 dc->realize = xive_end_source_realize; 1898 /* 1899 * Reason: part of XIVE interrupt controller, needs to be wired up, 1900 * e.g. by spapr_xive_instance_init(). 1901 */ 1902 dc->user_creatable = false; 1903 } 1904 1905 static const TypeInfo xive_end_source_info = { 1906 .name = TYPE_XIVE_END_SOURCE, 1907 .parent = TYPE_DEVICE, 1908 .instance_size = sizeof(XiveENDSource), 1909 .class_init = xive_end_source_class_init, 1910 }; 1911 1912 /* 1913 * XIVE Notifier 1914 */ 1915 static const TypeInfo xive_notifier_info = { 1916 .name = TYPE_XIVE_NOTIFIER, 1917 .parent = TYPE_INTERFACE, 1918 .class_size = sizeof(XiveNotifierClass), 1919 }; 1920 1921 static void xive_register_types(void) 1922 { 1923 type_register_static(&xive_source_info); 1924 type_register_static(&xive_notifier_info); 1925 type_register_static(&xive_router_info); 1926 type_register_static(&xive_end_source_info); 1927 type_register_static(&xive_tctx_info); 1928 } 1929 1930 type_init(xive_register_types) 1931