1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "hw/qdev-properties.h" 18 #include "monitor/monitor.h" 19 #include "hw/ppc/xive.h" 20 #include "hw/ppc/xive_regs.h" 21 22 /* 23 * XIVE Thread Interrupt Management context 24 */ 25 26 /* 27 * Convert a priority number to an Interrupt Pending Buffer (IPB) 28 * register, which indicates a pending interrupt at the priority 29 * corresponding to the bit number 30 */ 31 static uint8_t priority_to_ipb(uint8_t priority) 32 { 33 return priority > XIVE_PRIORITY_MAX ? 34 0 : 1 << (XIVE_PRIORITY_MAX - priority); 35 } 36 37 /* 38 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 39 * Interrupt Priority Register (PIPR), which contains the priority of 40 * the most favored pending notification. 41 */ 42 static uint8_t ipb_to_pipr(uint8_t ibp) 43 { 44 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 45 } 46 47 static void ipb_update(uint8_t *regs, uint8_t priority) 48 { 49 regs[TM_IPB] |= priority_to_ipb(priority); 50 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 51 } 52 53 static uint8_t exception_mask(uint8_t ring) 54 { 55 switch (ring) { 56 case TM_QW1_OS: 57 return TM_QW1_NSR_EO; 58 case TM_QW3_HV_PHYS: 59 return TM_QW3_NSR_HE; 60 default: 61 g_assert_not_reached(); 62 } 63 } 64 65 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 66 { 67 switch (ring) { 68 case TM_QW0_USER: 69 return 0; /* Not supported */ 70 case TM_QW1_OS: 71 return tctx->os_output; 72 case TM_QW2_HV_POOL: 73 case TM_QW3_HV_PHYS: 74 return tctx->hv_output; 75 default: 76 return 0; 77 } 78 } 79 80 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 81 { 82 uint8_t *regs = &tctx->regs[ring]; 83 uint8_t nsr = regs[TM_NSR]; 84 uint8_t mask = exception_mask(ring); 85 86 qemu_irq_lower(xive_tctx_output(tctx, ring)); 87 88 if (regs[TM_NSR] & mask) { 89 uint8_t cppr = regs[TM_PIPR]; 90 91 regs[TM_CPPR] = cppr; 92 93 /* Reset the pending buffer bit */ 94 regs[TM_IPB] &= ~priority_to_ipb(cppr); 95 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 96 97 /* Drop Exception bit */ 98 regs[TM_NSR] &= ~mask; 99 } 100 101 return (nsr << 8) | regs[TM_CPPR]; 102 } 103 104 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 105 { 106 uint8_t *regs = &tctx->regs[ring]; 107 108 if (regs[TM_PIPR] < regs[TM_CPPR]) { 109 switch (ring) { 110 case TM_QW1_OS: 111 regs[TM_NSR] |= TM_QW1_NSR_EO; 112 break; 113 case TM_QW3_HV_PHYS: 114 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 115 break; 116 default: 117 g_assert_not_reached(); 118 } 119 qemu_irq_raise(xive_tctx_output(tctx, ring)); 120 } 121 } 122 123 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 124 { 125 if (cppr > XIVE_PRIORITY_MAX) { 126 cppr = 0xff; 127 } 128 129 tctx->regs[ring + TM_CPPR] = cppr; 130 131 /* CPPR has changed, check if we need to raise a pending exception */ 132 xive_tctx_notify(tctx, ring); 133 } 134 135 static inline uint32_t xive_tctx_word2(uint8_t *ring) 136 { 137 return *((uint32_t *) &ring[TM_WORD2]); 138 } 139 140 /* 141 * XIVE Thread Interrupt Management Area (TIMA) 142 */ 143 144 static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset, 145 uint64_t value, unsigned size) 146 { 147 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 148 } 149 150 static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) 151 { 152 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 153 } 154 155 static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, 156 unsigned size) 157 { 158 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 159 uint32_t qw2w2; 160 161 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 162 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 163 return qw2w2; 164 } 165 166 static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset, 167 uint64_t value, unsigned size) 168 { 169 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 170 } 171 172 static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned size) 173 { 174 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 175 } 176 177 /* 178 * Define an access map for each page of the TIMA that we will use in 179 * the memory region ops to filter values when doing loads and stores 180 * of raw registers values 181 * 182 * Registers accessibility bits : 183 * 184 * 0x0 - no access 185 * 0x1 - write only 186 * 0x2 - read only 187 * 0x3 - read/write 188 */ 189 190 static const uint8_t xive_tm_hw_view[] = { 191 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 192 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 193 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 194 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 195 }; 196 197 static const uint8_t xive_tm_hv_view[] = { 198 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 199 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 200 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 201 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 202 }; 203 204 static const uint8_t xive_tm_os_view[] = { 205 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 206 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 208 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 209 }; 210 211 static const uint8_t xive_tm_user_view[] = { 212 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 213 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 214 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 215 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 216 }; 217 218 /* 219 * Overall TIMA access map for the thread interrupt management context 220 * registers 221 */ 222 static const uint8_t *xive_tm_views[] = { 223 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 224 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 225 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 226 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 227 }; 228 229 /* 230 * Computes a register access mask for a given offset in the TIMA 231 */ 232 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 233 { 234 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 235 uint8_t reg_offset = offset & 0x3F; 236 uint8_t reg_mask = write ? 0x1 : 0x2; 237 uint64_t mask = 0x0; 238 int i; 239 240 for (i = 0; i < size; i++) { 241 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 242 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 243 } 244 } 245 246 return mask; 247 } 248 249 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 250 unsigned size) 251 { 252 uint8_t ring_offset = offset & 0x30; 253 uint8_t reg_offset = offset & 0x3F; 254 uint64_t mask = xive_tm_mask(offset, size, true); 255 int i; 256 257 /* 258 * Only 4 or 8 bytes stores are allowed and the User ring is 259 * excluded 260 */ 261 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 262 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 263 HWADDR_PRIx"\n", offset); 264 return; 265 } 266 267 /* 268 * Use the register offset for the raw values and filter out 269 * reserved values 270 */ 271 for (i = 0; i < size; i++) { 272 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 273 if (byte_mask) { 274 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 275 byte_mask; 276 } 277 } 278 } 279 280 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 281 { 282 uint8_t ring_offset = offset & 0x30; 283 uint8_t reg_offset = offset & 0x3F; 284 uint64_t mask = xive_tm_mask(offset, size, false); 285 uint64_t ret; 286 int i; 287 288 /* 289 * Only 4 or 8 bytes loads are allowed and the User ring is 290 * excluded 291 */ 292 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 293 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 294 HWADDR_PRIx"\n", offset); 295 return -1; 296 } 297 298 /* Use the register offset for the raw values */ 299 ret = 0; 300 for (i = 0; i < size; i++) { 301 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 302 } 303 304 /* filter out reserved values */ 305 return ret & mask; 306 } 307 308 /* 309 * The TM context is mapped twice within each page. Stores and loads 310 * to the first mapping below 2K write and read the specified values 311 * without modification. The second mapping above 2K performs specific 312 * state changes (side effects) in addition to setting/returning the 313 * interrupt management area context of the processor thread. 314 */ 315 static uint64_t xive_tm_ack_os_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) 316 { 317 return xive_tctx_accept(tctx, TM_QW1_OS); 318 } 319 320 static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset, 321 uint64_t value, unsigned size) 322 { 323 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 324 } 325 326 /* 327 * Adjust the IPB to allow a CPU to process event queues of other 328 * priorities during one physical interrupt cycle. 329 */ 330 static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset, 331 uint64_t value, unsigned size) 332 { 333 ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff); 334 xive_tctx_notify(tctx, TM_QW1_OS); 335 } 336 337 /* 338 * Define a mapping of "special" operations depending on the TIMA page 339 * offset and the size of the operation. 340 */ 341 typedef struct XiveTmOp { 342 uint8_t page_offset; 343 uint32_t op_offset; 344 unsigned size; 345 void (*write_handler)(XiveTCTX *tctx, hwaddr offset, uint64_t value, 346 unsigned size); 347 uint64_t (*read_handler)(XiveTCTX *tctx, hwaddr offset, unsigned size); 348 } XiveTmOp; 349 350 static const XiveTmOp xive_tm_operations[] = { 351 /* 352 * MMIOs below 2K : raw values and special operations without side 353 * effects 354 */ 355 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 356 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 357 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 358 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 359 360 /* MMIOs above 2K : special operations with side effects */ 361 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 362 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 363 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 364 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 365 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 366 }; 367 368 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 369 { 370 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 371 uint32_t op_offset = offset & 0xFFF; 372 int i; 373 374 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 375 const XiveTmOp *xto = &xive_tm_operations[i]; 376 377 /* Accesses done from a more privileged TIMA page is allowed */ 378 if (xto->page_offset >= page_offset && 379 xto->op_offset == op_offset && 380 xto->size == size && 381 ((write && xto->write_handler) || (!write && xto->read_handler))) { 382 return xto; 383 } 384 } 385 return NULL; 386 } 387 388 /* 389 * TIMA MMIO handlers 390 */ 391 void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 392 unsigned size) 393 { 394 const XiveTmOp *xto; 395 396 /* 397 * TODO: check V bit in Q[0-3]W2 398 */ 399 400 /* 401 * First, check for special operations in the 2K region 402 */ 403 if (offset & 0x800) { 404 xto = xive_tm_find_op(offset, size, true); 405 if (!xto) { 406 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA" 407 "@%"HWADDR_PRIx"\n", offset); 408 } else { 409 xto->write_handler(tctx, offset, value, size); 410 } 411 return; 412 } 413 414 /* 415 * Then, for special operations in the region below 2K. 416 */ 417 xto = xive_tm_find_op(offset, size, true); 418 if (xto) { 419 xto->write_handler(tctx, offset, value, size); 420 return; 421 } 422 423 /* 424 * Finish with raw access to the register values 425 */ 426 xive_tm_raw_write(tctx, offset, value, size); 427 } 428 429 uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 430 { 431 const XiveTmOp *xto; 432 433 /* 434 * TODO: check V bit in Q[0-3]W2 435 */ 436 437 /* 438 * First, check for special operations in the 2K region 439 */ 440 if (offset & 0x800) { 441 xto = xive_tm_find_op(offset, size, false); 442 if (!xto) { 443 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 444 "@%"HWADDR_PRIx"\n", offset); 445 return -1; 446 } 447 return xto->read_handler(tctx, offset, size); 448 } 449 450 /* 451 * Then, for special operations in the region below 2K. 452 */ 453 xto = xive_tm_find_op(offset, size, false); 454 if (xto) { 455 return xto->read_handler(tctx, offset, size); 456 } 457 458 /* 459 * Finish with raw access to the register values 460 */ 461 return xive_tm_raw_read(tctx, offset, size); 462 } 463 464 static void xive_tm_write(void *opaque, hwaddr offset, 465 uint64_t value, unsigned size) 466 { 467 XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); 468 469 xive_tctx_tm_write(tctx, offset, value, size); 470 } 471 472 static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) 473 { 474 XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); 475 476 return xive_tctx_tm_read(tctx, offset, size); 477 } 478 479 const MemoryRegionOps xive_tm_ops = { 480 .read = xive_tm_read, 481 .write = xive_tm_write, 482 .endianness = DEVICE_BIG_ENDIAN, 483 .valid = { 484 .min_access_size = 1, 485 .max_access_size = 8, 486 }, 487 .impl = { 488 .min_access_size = 1, 489 .max_access_size = 8, 490 }, 491 }; 492 493 static char *xive_tctx_ring_print(uint8_t *ring) 494 { 495 uint32_t w2 = xive_tctx_word2(ring); 496 497 return g_strdup_printf("%02x %02x %02x %02x %02x " 498 "%02x %02x %02x %08x", 499 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 500 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 501 be32_to_cpu(w2)); 502 } 503 504 static const char * const xive_tctx_ring_names[] = { 505 "USER", "OS", "POOL", "PHYS", 506 }; 507 508 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 509 { 510 int cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 511 int i; 512 513 if (kvm_irqchip_in_kernel()) { 514 Error *local_err = NULL; 515 516 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 517 if (local_err) { 518 error_report_err(local_err); 519 return; 520 } 521 } 522 523 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 524 " W2\n", cpu_index); 525 526 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 527 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 528 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 529 xive_tctx_ring_names[i], s); 530 g_free(s); 531 } 532 } 533 534 static void xive_tctx_reset(void *dev) 535 { 536 XiveTCTX *tctx = XIVE_TCTX(dev); 537 538 memset(tctx->regs, 0, sizeof(tctx->regs)); 539 540 /* Set some defaults */ 541 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 542 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 543 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 544 545 /* 546 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 547 * CPPR is first set. 548 */ 549 tctx->regs[TM_QW1_OS + TM_PIPR] = 550 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 551 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 552 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 553 } 554 555 static void xive_tctx_realize(DeviceState *dev, Error **errp) 556 { 557 XiveTCTX *tctx = XIVE_TCTX(dev); 558 PowerPCCPU *cpu; 559 CPUPPCState *env; 560 Object *obj; 561 Error *local_err = NULL; 562 563 obj = object_property_get_link(OBJECT(dev), "cpu", &local_err); 564 if (!obj) { 565 error_propagate(errp, local_err); 566 error_prepend(errp, "required link 'cpu' not found: "); 567 return; 568 } 569 570 cpu = POWERPC_CPU(obj); 571 tctx->cs = CPU(obj); 572 573 env = &cpu->env; 574 switch (PPC_INPUT(env)) { 575 case PPC_FLAGS_INPUT_POWER9: 576 tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT]; 577 tctx->os_output = env->irq_inputs[POWER9_INPUT_INT]; 578 break; 579 580 default: 581 error_setg(errp, "XIVE interrupt controller does not support " 582 "this CPU bus model"); 583 return; 584 } 585 586 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 587 if (kvm_irqchip_in_kernel()) { 588 kvmppc_xive_cpu_connect(tctx, &local_err); 589 if (local_err) { 590 error_propagate(errp, local_err); 591 return; 592 } 593 } 594 595 qemu_register_reset(xive_tctx_reset, dev); 596 } 597 598 static void xive_tctx_unrealize(DeviceState *dev, Error **errp) 599 { 600 qemu_unregister_reset(xive_tctx_reset, dev); 601 } 602 603 static int vmstate_xive_tctx_pre_save(void *opaque) 604 { 605 Error *local_err = NULL; 606 607 if (kvm_irqchip_in_kernel()) { 608 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque), &local_err); 609 if (local_err) { 610 error_report_err(local_err); 611 return -1; 612 } 613 } 614 615 return 0; 616 } 617 618 static const VMStateDescription vmstate_xive_tctx = { 619 .name = TYPE_XIVE_TCTX, 620 .version_id = 1, 621 .minimum_version_id = 1, 622 .pre_save = vmstate_xive_tctx_pre_save, 623 .post_load = NULL, /* handled by the sPAPRxive model */ 624 .fields = (VMStateField[]) { 625 VMSTATE_BUFFER(regs, XiveTCTX), 626 VMSTATE_END_OF_LIST() 627 }, 628 }; 629 630 static void xive_tctx_class_init(ObjectClass *klass, void *data) 631 { 632 DeviceClass *dc = DEVICE_CLASS(klass); 633 634 dc->desc = "XIVE Interrupt Thread Context"; 635 dc->realize = xive_tctx_realize; 636 dc->unrealize = xive_tctx_unrealize; 637 dc->vmsd = &vmstate_xive_tctx; 638 } 639 640 static const TypeInfo xive_tctx_info = { 641 .name = TYPE_XIVE_TCTX, 642 .parent = TYPE_DEVICE, 643 .instance_size = sizeof(XiveTCTX), 644 .class_init = xive_tctx_class_init, 645 }; 646 647 Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) 648 { 649 Error *local_err = NULL; 650 Object *obj; 651 652 obj = object_new(TYPE_XIVE_TCTX); 653 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); 654 object_unref(obj); 655 object_property_add_const_link(obj, "cpu", cpu, &error_abort); 656 object_property_set_bool(obj, true, "realized", &local_err); 657 if (local_err) { 658 goto error; 659 } 660 661 return obj; 662 663 error: 664 object_unparent(obj); 665 error_propagate(errp, local_err); 666 return NULL; 667 } 668 669 /* 670 * XIVE ESB helpers 671 */ 672 673 static uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 674 { 675 uint8_t old_pq = *pq & 0x3; 676 677 *pq &= ~0x3; 678 *pq |= value & 0x3; 679 680 return old_pq; 681 } 682 683 static bool xive_esb_trigger(uint8_t *pq) 684 { 685 uint8_t old_pq = *pq & 0x3; 686 687 switch (old_pq) { 688 case XIVE_ESB_RESET: 689 xive_esb_set(pq, XIVE_ESB_PENDING); 690 return true; 691 case XIVE_ESB_PENDING: 692 case XIVE_ESB_QUEUED: 693 xive_esb_set(pq, XIVE_ESB_QUEUED); 694 return false; 695 case XIVE_ESB_OFF: 696 xive_esb_set(pq, XIVE_ESB_OFF); 697 return false; 698 default: 699 g_assert_not_reached(); 700 } 701 } 702 703 static bool xive_esb_eoi(uint8_t *pq) 704 { 705 uint8_t old_pq = *pq & 0x3; 706 707 switch (old_pq) { 708 case XIVE_ESB_RESET: 709 case XIVE_ESB_PENDING: 710 xive_esb_set(pq, XIVE_ESB_RESET); 711 return false; 712 case XIVE_ESB_QUEUED: 713 xive_esb_set(pq, XIVE_ESB_PENDING); 714 return true; 715 case XIVE_ESB_OFF: 716 xive_esb_set(pq, XIVE_ESB_OFF); 717 return false; 718 default: 719 g_assert_not_reached(); 720 } 721 } 722 723 /* 724 * XIVE Interrupt Source (or IVSE) 725 */ 726 727 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 728 { 729 assert(srcno < xsrc->nr_irqs); 730 731 return xsrc->status[srcno] & 0x3; 732 } 733 734 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 735 { 736 assert(srcno < xsrc->nr_irqs); 737 738 return xive_esb_set(&xsrc->status[srcno], pq); 739 } 740 741 /* 742 * Returns whether the event notification should be forwarded. 743 */ 744 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 745 { 746 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 747 748 xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; 749 750 switch (old_pq) { 751 case XIVE_ESB_RESET: 752 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 753 return true; 754 default: 755 return false; 756 } 757 } 758 759 /* 760 * Returns whether the event notification should be forwarded. 761 */ 762 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 763 { 764 bool ret; 765 766 assert(srcno < xsrc->nr_irqs); 767 768 ret = xive_esb_trigger(&xsrc->status[srcno]); 769 770 if (xive_source_irq_is_lsi(xsrc, srcno) && 771 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 772 qemu_log_mask(LOG_GUEST_ERROR, 773 "XIVE: queued an event on LSI IRQ %d\n", srcno); 774 } 775 776 return ret; 777 } 778 779 /* 780 * Returns whether the event notification should be forwarded. 781 */ 782 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 783 { 784 bool ret; 785 786 assert(srcno < xsrc->nr_irqs); 787 788 ret = xive_esb_eoi(&xsrc->status[srcno]); 789 790 /* 791 * LSI sources do not set the Q bit but they can still be 792 * asserted, in which case we should forward a new event 793 * notification 794 */ 795 if (xive_source_irq_is_lsi(xsrc, srcno) && 796 xsrc->status[srcno] & XIVE_STATUS_ASSERTED) { 797 ret = xive_source_lsi_trigger(xsrc, srcno); 798 } 799 800 return ret; 801 } 802 803 /* 804 * Forward the source event notification to the Router 805 */ 806 static void xive_source_notify(XiveSource *xsrc, int srcno) 807 { 808 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 809 810 if (xnc->notify) { 811 xnc->notify(xsrc->xive, srcno); 812 } 813 } 814 815 /* 816 * In a two pages ESB MMIO setting, even page is the trigger page, odd 817 * page is for management 818 */ 819 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 820 { 821 return !((addr >> shift) & 1); 822 } 823 824 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 825 { 826 return xive_source_esb_has_2page(xsrc) && 827 addr_is_even(addr, xsrc->esb_shift - 1); 828 } 829 830 /* 831 * ESB MMIO loads 832 * Trigger page Management/EOI page 833 * 834 * ESB MMIO setting 2 pages 1 or 2 pages 835 * 836 * 0x000 .. 0x3FF -1 EOI and return 0|1 837 * 0x400 .. 0x7FF -1 EOI and return 0|1 838 * 0x800 .. 0xBFF -1 return PQ 839 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 840 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 841 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 842 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 843 */ 844 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 845 { 846 XiveSource *xsrc = XIVE_SOURCE(opaque); 847 uint32_t offset = addr & 0xFFF; 848 uint32_t srcno = addr >> xsrc->esb_shift; 849 uint64_t ret = -1; 850 851 /* In a two pages ESB MMIO setting, trigger page should not be read */ 852 if (xive_source_is_trigger_page(xsrc, addr)) { 853 qemu_log_mask(LOG_GUEST_ERROR, 854 "XIVE: invalid load on IRQ %d trigger page at " 855 "0x%"HWADDR_PRIx"\n", srcno, addr); 856 return -1; 857 } 858 859 switch (offset) { 860 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 861 ret = xive_source_esb_eoi(xsrc, srcno); 862 863 /* Forward the source event notification for routing */ 864 if (ret) { 865 xive_source_notify(xsrc, srcno); 866 } 867 break; 868 869 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 870 ret = xive_source_esb_get(xsrc, srcno); 871 break; 872 873 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 874 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 875 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 876 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 877 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 878 break; 879 default: 880 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 881 offset); 882 } 883 884 return ret; 885 } 886 887 /* 888 * ESB MMIO stores 889 * Trigger page Management/EOI page 890 * 891 * ESB MMIO setting 2 pages 1 or 2 pages 892 * 893 * 0x000 .. 0x3FF Trigger Trigger 894 * 0x400 .. 0x7FF Trigger EOI 895 * 0x800 .. 0xBFF Trigger undefined 896 * 0xC00 .. 0xCFF Trigger PQ=00 897 * 0xD00 .. 0xDFF Trigger PQ=01 898 * 0xE00 .. 0xDFF Trigger PQ=10 899 * 0xF00 .. 0xDFF Trigger PQ=11 900 */ 901 static void xive_source_esb_write(void *opaque, hwaddr addr, 902 uint64_t value, unsigned size) 903 { 904 XiveSource *xsrc = XIVE_SOURCE(opaque); 905 uint32_t offset = addr & 0xFFF; 906 uint32_t srcno = addr >> xsrc->esb_shift; 907 bool notify = false; 908 909 /* In a two pages ESB MMIO setting, trigger page only triggers */ 910 if (xive_source_is_trigger_page(xsrc, addr)) { 911 notify = xive_source_esb_trigger(xsrc, srcno); 912 goto out; 913 } 914 915 switch (offset) { 916 case 0 ... 0x3FF: 917 notify = xive_source_esb_trigger(xsrc, srcno); 918 break; 919 920 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 921 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 922 qemu_log_mask(LOG_GUEST_ERROR, 923 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 924 return; 925 } 926 927 notify = xive_source_esb_eoi(xsrc, srcno); 928 break; 929 930 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 931 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 932 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 933 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 934 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 935 break; 936 937 default: 938 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 939 offset); 940 return; 941 } 942 943 out: 944 /* Forward the source event notification for routing */ 945 if (notify) { 946 xive_source_notify(xsrc, srcno); 947 } 948 } 949 950 static const MemoryRegionOps xive_source_esb_ops = { 951 .read = xive_source_esb_read, 952 .write = xive_source_esb_write, 953 .endianness = DEVICE_BIG_ENDIAN, 954 .valid = { 955 .min_access_size = 8, 956 .max_access_size = 8, 957 }, 958 .impl = { 959 .min_access_size = 8, 960 .max_access_size = 8, 961 }, 962 }; 963 964 void xive_source_set_irq(void *opaque, int srcno, int val) 965 { 966 XiveSource *xsrc = XIVE_SOURCE(opaque); 967 bool notify = false; 968 969 if (xive_source_irq_is_lsi(xsrc, srcno)) { 970 if (val) { 971 notify = xive_source_lsi_trigger(xsrc, srcno); 972 } else { 973 xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; 974 } 975 } else { 976 if (val) { 977 notify = xive_source_esb_trigger(xsrc, srcno); 978 } 979 } 980 981 /* Forward the source event notification for routing */ 982 if (notify) { 983 xive_source_notify(xsrc, srcno); 984 } 985 } 986 987 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 988 { 989 int i; 990 991 for (i = 0; i < xsrc->nr_irqs; i++) { 992 uint8_t pq = xive_source_esb_get(xsrc, i); 993 994 if (pq == XIVE_ESB_OFF) { 995 continue; 996 } 997 998 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 999 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1000 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1001 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1002 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' '); 1003 } 1004 } 1005 1006 static void xive_source_reset(void *dev) 1007 { 1008 XiveSource *xsrc = XIVE_SOURCE(dev); 1009 1010 /* Do not clear the LSI bitmap */ 1011 1012 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 1013 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 1014 } 1015 1016 static void xive_source_realize(DeviceState *dev, Error **errp) 1017 { 1018 XiveSource *xsrc = XIVE_SOURCE(dev); 1019 Object *obj; 1020 Error *local_err = NULL; 1021 1022 obj = object_property_get_link(OBJECT(dev), "xive", &local_err); 1023 if (!obj) { 1024 error_propagate(errp, local_err); 1025 error_prepend(errp, "required link 'xive' not found: "); 1026 return; 1027 } 1028 1029 xsrc->xive = XIVE_NOTIFIER(obj); 1030 1031 if (!xsrc->nr_irqs) { 1032 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1033 return; 1034 } 1035 1036 if (xsrc->esb_shift != XIVE_ESB_4K && 1037 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1038 xsrc->esb_shift != XIVE_ESB_64K && 1039 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1040 error_setg(errp, "Invalid ESB shift setting"); 1041 return; 1042 } 1043 1044 xsrc->status = g_malloc0(xsrc->nr_irqs); 1045 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1046 1047 if (!kvm_irqchip_in_kernel()) { 1048 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1049 &xive_source_esb_ops, xsrc, "xive.esb", 1050 (1ull << xsrc->esb_shift) * xsrc->nr_irqs); 1051 } 1052 1053 qemu_register_reset(xive_source_reset, dev); 1054 } 1055 1056 static const VMStateDescription vmstate_xive_source = { 1057 .name = TYPE_XIVE_SOURCE, 1058 .version_id = 1, 1059 .minimum_version_id = 1, 1060 .fields = (VMStateField[]) { 1061 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1062 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1063 VMSTATE_END_OF_LIST() 1064 }, 1065 }; 1066 1067 /* 1068 * The default XIVE interrupt source setting for the ESB MMIOs is two 1069 * 64k pages without Store EOI, to be in sync with KVM. 1070 */ 1071 static Property xive_source_properties[] = { 1072 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1073 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1074 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1075 DEFINE_PROP_END_OF_LIST(), 1076 }; 1077 1078 static void xive_source_class_init(ObjectClass *klass, void *data) 1079 { 1080 DeviceClass *dc = DEVICE_CLASS(klass); 1081 1082 dc->desc = "XIVE Interrupt Source"; 1083 dc->props = xive_source_properties; 1084 dc->realize = xive_source_realize; 1085 dc->vmsd = &vmstate_xive_source; 1086 } 1087 1088 static const TypeInfo xive_source_info = { 1089 .name = TYPE_XIVE_SOURCE, 1090 .parent = TYPE_DEVICE, 1091 .instance_size = sizeof(XiveSource), 1092 .class_init = xive_source_class_init, 1093 }; 1094 1095 /* 1096 * XiveEND helpers 1097 */ 1098 1099 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1100 { 1101 uint64_t qaddr_base = xive_end_qaddr(end); 1102 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1103 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1104 uint32_t qentries = 1 << (qsize + 10); 1105 int i; 1106 1107 /* 1108 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1109 */ 1110 monitor_printf(mon, " [ "); 1111 qindex = (qindex - (width - 1)) & (qentries - 1); 1112 for (i = 0; i < width; i++) { 1113 uint64_t qaddr = qaddr_base + (qindex << 2); 1114 uint32_t qdata = -1; 1115 1116 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 1117 sizeof(qdata))) { 1118 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1119 HWADDR_PRIx "\n", qaddr); 1120 return; 1121 } 1122 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1123 be32_to_cpu(qdata)); 1124 qindex = (qindex + 1) & (qentries - 1); 1125 } 1126 } 1127 1128 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1129 { 1130 uint64_t qaddr_base = xive_end_qaddr(end); 1131 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1132 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1133 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1134 uint32_t qentries = 1 << (qsize + 10); 1135 1136 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1137 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1138 1139 if (!xive_end_is_valid(end)) { 1140 return; 1141 } 1142 1143 monitor_printf(mon, " %08x %c%c%c%c%c prio:%d nvt:%04x eq:@%08"PRIx64 1144 "% 6d/%5d ^%d", end_idx, 1145 xive_end_is_valid(end) ? 'v' : '-', 1146 xive_end_is_enqueue(end) ? 'q' : '-', 1147 xive_end_is_notify(end) ? 'n' : '-', 1148 xive_end_is_backlog(end) ? 'b' : '-', 1149 xive_end_is_escalate(end) ? 'e' : '-', 1150 priority, nvt, qaddr_base, qindex, qentries, qgen); 1151 1152 xive_end_queue_pic_print_info(end, 6, mon); 1153 monitor_printf(mon, "]\n"); 1154 } 1155 1156 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1157 { 1158 uint64_t qaddr_base = xive_end_qaddr(end); 1159 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1160 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1161 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1162 1163 uint64_t qaddr = qaddr_base + (qindex << 2); 1164 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1165 uint32_t qentries = 1 << (qsize + 10); 1166 1167 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) { 1168 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1169 HWADDR_PRIx "\n", qaddr); 1170 return; 1171 } 1172 1173 qindex = (qindex + 1) & (qentries - 1); 1174 if (qindex == 0) { 1175 qgen ^= 1; 1176 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1177 } 1178 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1179 } 1180 1181 /* 1182 * XIVE Router (aka. Virtualization Controller or IVRE) 1183 */ 1184 1185 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1186 XiveEAS *eas) 1187 { 1188 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1189 1190 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1191 } 1192 1193 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1194 XiveEND *end) 1195 { 1196 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1197 1198 return xrc->get_end(xrtr, end_blk, end_idx, end); 1199 } 1200 1201 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1202 XiveEND *end, uint8_t word_number) 1203 { 1204 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1205 1206 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1207 } 1208 1209 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1210 XiveNVT *nvt) 1211 { 1212 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1213 1214 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1215 } 1216 1217 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1218 XiveNVT *nvt, uint8_t word_number) 1219 { 1220 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1221 1222 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1223 } 1224 1225 XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) 1226 { 1227 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1228 1229 return xrc->get_tctx(xrtr, cs); 1230 } 1231 1232 /* 1233 * Encode the HW CAM line in the block group mode format : 1234 * 1235 * chip << 19 | 0000000 0 0001 thread (7Bit) 1236 */ 1237 static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) 1238 { 1239 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1240 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1241 1242 return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f)); 1243 } 1244 1245 /* 1246 * The thread context register words are in big-endian format. 1247 */ 1248 static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format, 1249 uint8_t nvt_blk, uint32_t nvt_idx, 1250 bool cam_ignore, uint32_t logic_serv) 1251 { 1252 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1253 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1254 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1255 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1256 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1257 1258 /* 1259 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1260 * identifier are ignored in the "CAM" match. 1261 */ 1262 1263 if (format == 0) { 1264 if (cam_ignore == true) { 1265 /* 1266 * F=0 & i=1: Logical server notification (bits ignored at 1267 * the end of the NVT identifier) 1268 */ 1269 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1270 nvt_blk, nvt_idx); 1271 return -1; 1272 } 1273 1274 /* F=0 & i=0: Specific NVT notification */ 1275 1276 /* PHYS ring */ 1277 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1278 cam == xive_tctx_hw_cam_line(tctx)) { 1279 return TM_QW3_HV_PHYS; 1280 } 1281 1282 /* HV POOL ring */ 1283 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1284 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1285 return TM_QW2_HV_POOL; 1286 } 1287 1288 /* OS ring */ 1289 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1290 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1291 return TM_QW1_OS; 1292 } 1293 } else { 1294 /* F=1 : User level Event-Based Branch (EBB) notification */ 1295 1296 /* USER ring */ 1297 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1298 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1299 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1300 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1301 return TM_QW0_USER; 1302 } 1303 } 1304 return -1; 1305 } 1306 1307 typedef struct XiveTCTXMatch { 1308 XiveTCTX *tctx; 1309 uint8_t ring; 1310 } XiveTCTXMatch; 1311 1312 static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, 1313 uint8_t nvt_blk, uint32_t nvt_idx, 1314 bool cam_ignore, uint8_t priority, 1315 uint32_t logic_serv, XiveTCTXMatch *match) 1316 { 1317 CPUState *cs; 1318 1319 /* 1320 * TODO (PowerNV): handle chip_id overwrite of block field for 1321 * hardwired CAM compares 1322 */ 1323 1324 CPU_FOREACH(cs) { 1325 XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs); 1326 int ring; 1327 1328 /* 1329 * HW checks that the CPU is enabled in the Physical Thread 1330 * Enable Register (PTER). 1331 */ 1332 1333 /* 1334 * Check the thread context CAM lines and record matches. We 1335 * will handle CPU exception delivery later 1336 */ 1337 ring = xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx, 1338 cam_ignore, logic_serv); 1339 /* 1340 * Save the context and follow on to catch duplicates, that we 1341 * don't support yet. 1342 */ 1343 if (ring != -1) { 1344 if (match->tctx) { 1345 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread " 1346 "context NVT %x/%x\n", nvt_blk, nvt_idx); 1347 return false; 1348 } 1349 1350 match->ring = ring; 1351 match->tctx = tctx; 1352 } 1353 } 1354 1355 if (!match->tctx) { 1356 qemu_log_mask(LOG_UNIMP, "XIVE: NVT %x/%x is not dispatched\n", 1357 nvt_blk, nvt_idx); 1358 return false; 1359 } 1360 1361 return true; 1362 } 1363 1364 /* 1365 * This is our simple Xive Presenter Engine model. It is merged in the 1366 * Router as it does not require an extra object. 1367 * 1368 * It receives notification requests sent by the IVRE to find one 1369 * matching NVT (or more) dispatched on the processor threads. In case 1370 * of a single NVT notification, the process is abreviated and the 1371 * thread is signaled if a match is found. In case of a logical server 1372 * notification (bits ignored at the end of the NVT identifier), the 1373 * IVPE and IVRE select a winning thread using different filters. This 1374 * involves 2 or 3 exchanges on the PowerBus that the model does not 1375 * support. 1376 * 1377 * The parameters represent what is sent on the PowerBus 1378 */ 1379 static void xive_presenter_notify(XiveRouter *xrtr, uint8_t format, 1380 uint8_t nvt_blk, uint32_t nvt_idx, 1381 bool cam_ignore, uint8_t priority, 1382 uint32_t logic_serv) 1383 { 1384 XiveNVT nvt; 1385 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1386 bool found; 1387 1388 /* NVT cache lookup */ 1389 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1390 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1391 nvt_blk, nvt_idx); 1392 return; 1393 } 1394 1395 if (!xive_nvt_is_valid(&nvt)) { 1396 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1397 nvt_blk, nvt_idx); 1398 return; 1399 } 1400 1401 found = xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ignore, 1402 priority, logic_serv, &match); 1403 if (found) { 1404 ipb_update(&match.tctx->regs[match.ring], priority); 1405 xive_tctx_notify(match.tctx, match.ring); 1406 return; 1407 } 1408 1409 /* Record the IPB in the associated NVT structure */ 1410 ipb_update((uint8_t *) &nvt.w4, priority); 1411 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1412 1413 /* 1414 * If no matching NVT is dispatched on a HW thread : 1415 * - update the NVT structure if backlog is activated 1416 * - escalate (ESe PQ bits and EAS in w4-5) if escalation is 1417 * activated 1418 */ 1419 } 1420 1421 /* 1422 * An END trigger can come from an event trigger (IPI or HW) or from 1423 * another chip. We don't model the PowerBus but the END trigger 1424 * message has the same parameters than in the function below. 1425 */ 1426 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1427 uint32_t end_idx, uint32_t end_data) 1428 { 1429 XiveEND end; 1430 uint8_t priority; 1431 uint8_t format; 1432 1433 /* END cache lookup */ 1434 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1435 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1436 end_idx); 1437 return; 1438 } 1439 1440 if (!xive_end_is_valid(&end)) { 1441 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1442 end_blk, end_idx); 1443 return; 1444 } 1445 1446 if (xive_end_is_enqueue(&end)) { 1447 xive_end_enqueue(&end, end_data); 1448 /* Enqueuing event data modifies the EQ toggle and index */ 1449 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1450 } 1451 1452 /* 1453 * The W7 format depends on the F bit in W6. It defines the type 1454 * of the notification : 1455 * 1456 * F=0 : single or multiple NVT notification 1457 * F=1 : User level Event-Based Branch (EBB) notification, no 1458 * priority 1459 */ 1460 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1461 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1462 1463 /* The END is masked */ 1464 if (format == 0 && priority == 0xff) { 1465 return; 1466 } 1467 1468 /* 1469 * Check the END ESn (Event State Buffer for notification) for 1470 * even futher coalescing in the Router 1471 */ 1472 if (!xive_end_is_notify(&end)) { 1473 uint8_t pq = xive_get_field32(END_W1_ESn, end.w1); 1474 bool notify = xive_esb_trigger(&pq); 1475 1476 if (pq != xive_get_field32(END_W1_ESn, end.w1)) { 1477 end.w1 = xive_set_field32(END_W1_ESn, end.w1, pq); 1478 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1479 } 1480 1481 /* ESn[Q]=1 : end of notification */ 1482 if (!notify) { 1483 return; 1484 } 1485 } 1486 1487 /* 1488 * Follows IVPE notification 1489 */ 1490 xive_presenter_notify(xrtr, format, 1491 xive_get_field32(END_W6_NVT_BLOCK, end.w6), 1492 xive_get_field32(END_W6_NVT_INDEX, end.w6), 1493 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1494 priority, 1495 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1496 1497 /* TODO: Auto EOI. */ 1498 } 1499 1500 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 1501 { 1502 XiveRouter *xrtr = XIVE_ROUTER(xn); 1503 uint8_t eas_blk = XIVE_SRCNO_BLOCK(lisn); 1504 uint32_t eas_idx = XIVE_SRCNO_INDEX(lisn); 1505 XiveEAS eas; 1506 1507 /* EAS cache lookup */ 1508 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1509 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1510 return; 1511 } 1512 1513 /* 1514 * The IVRE checks the State Bit Cache at this point. We skip the 1515 * SBC lookup because the state bits of the sources are modeled 1516 * internally in QEMU. 1517 */ 1518 1519 if (!xive_eas_is_valid(&eas)) { 1520 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1521 return; 1522 } 1523 1524 if (xive_eas_is_masked(&eas)) { 1525 /* Notification completed */ 1526 return; 1527 } 1528 1529 /* 1530 * The event trigger becomes an END trigger 1531 */ 1532 xive_router_end_notify(xrtr, 1533 xive_get_field64(EAS_END_BLOCK, eas.w), 1534 xive_get_field64(EAS_END_INDEX, eas.w), 1535 xive_get_field64(EAS_END_DATA, eas.w)); 1536 } 1537 1538 static void xive_router_class_init(ObjectClass *klass, void *data) 1539 { 1540 DeviceClass *dc = DEVICE_CLASS(klass); 1541 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1542 1543 dc->desc = "XIVE Router Engine"; 1544 xnc->notify = xive_router_notify; 1545 } 1546 1547 static const TypeInfo xive_router_info = { 1548 .name = TYPE_XIVE_ROUTER, 1549 .parent = TYPE_SYS_BUS_DEVICE, 1550 .abstract = true, 1551 .class_size = sizeof(XiveRouterClass), 1552 .class_init = xive_router_class_init, 1553 .interfaces = (InterfaceInfo[]) { 1554 { TYPE_XIVE_NOTIFIER }, 1555 { } 1556 } 1557 }; 1558 1559 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1560 { 1561 if (!xive_eas_is_valid(eas)) { 1562 return; 1563 } 1564 1565 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1566 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1567 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1568 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1569 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1570 } 1571 1572 /* 1573 * END ESB MMIO loads 1574 */ 1575 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1576 { 1577 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1578 uint32_t offset = addr & 0xFFF; 1579 uint8_t end_blk; 1580 uint32_t end_idx; 1581 XiveEND end; 1582 uint32_t end_esmask; 1583 uint8_t pq; 1584 uint64_t ret = -1; 1585 1586 end_blk = xsrc->block_id; 1587 end_idx = addr >> (xsrc->esb_shift + 1); 1588 1589 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1590 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1591 end_idx); 1592 return -1; 1593 } 1594 1595 if (!xive_end_is_valid(&end)) { 1596 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1597 end_blk, end_idx); 1598 return -1; 1599 } 1600 1601 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1602 pq = xive_get_field32(end_esmask, end.w1); 1603 1604 switch (offset) { 1605 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1606 ret = xive_esb_eoi(&pq); 1607 1608 /* Forward the source event notification for routing ?? */ 1609 break; 1610 1611 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1612 ret = pq; 1613 break; 1614 1615 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1616 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1617 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1618 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1619 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1620 break; 1621 default: 1622 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1623 offset); 1624 return -1; 1625 } 1626 1627 if (pq != xive_get_field32(end_esmask, end.w1)) { 1628 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1629 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1630 } 1631 1632 return ret; 1633 } 1634 1635 /* 1636 * END ESB MMIO stores are invalid 1637 */ 1638 static void xive_end_source_write(void *opaque, hwaddr addr, 1639 uint64_t value, unsigned size) 1640 { 1641 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1642 HWADDR_PRIx"\n", addr); 1643 } 1644 1645 static const MemoryRegionOps xive_end_source_ops = { 1646 .read = xive_end_source_read, 1647 .write = xive_end_source_write, 1648 .endianness = DEVICE_BIG_ENDIAN, 1649 .valid = { 1650 .min_access_size = 8, 1651 .max_access_size = 8, 1652 }, 1653 .impl = { 1654 .min_access_size = 8, 1655 .max_access_size = 8, 1656 }, 1657 }; 1658 1659 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1660 { 1661 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1662 Object *obj; 1663 Error *local_err = NULL; 1664 1665 obj = object_property_get_link(OBJECT(dev), "xive", &local_err); 1666 if (!obj) { 1667 error_propagate(errp, local_err); 1668 error_prepend(errp, "required link 'xive' not found: "); 1669 return; 1670 } 1671 1672 xsrc->xrtr = XIVE_ROUTER(obj); 1673 1674 if (!xsrc->nr_ends) { 1675 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1676 return; 1677 } 1678 1679 if (xsrc->esb_shift != XIVE_ESB_4K && 1680 xsrc->esb_shift != XIVE_ESB_64K) { 1681 error_setg(errp, "Invalid ESB shift setting"); 1682 return; 1683 } 1684 1685 /* 1686 * Each END is assigned an even/odd pair of MMIO pages, the even page 1687 * manages the ESn field while the odd page manages the ESe field. 1688 */ 1689 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1690 &xive_end_source_ops, xsrc, "xive.end", 1691 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1692 } 1693 1694 static Property xive_end_source_properties[] = { 1695 DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0), 1696 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1697 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1698 DEFINE_PROP_END_OF_LIST(), 1699 }; 1700 1701 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1702 { 1703 DeviceClass *dc = DEVICE_CLASS(klass); 1704 1705 dc->desc = "XIVE END Source"; 1706 dc->props = xive_end_source_properties; 1707 dc->realize = xive_end_source_realize; 1708 } 1709 1710 static const TypeInfo xive_end_source_info = { 1711 .name = TYPE_XIVE_END_SOURCE, 1712 .parent = TYPE_DEVICE, 1713 .instance_size = sizeof(XiveENDSource), 1714 .class_init = xive_end_source_class_init, 1715 }; 1716 1717 /* 1718 * XIVE Notifier 1719 */ 1720 static const TypeInfo xive_notifier_info = { 1721 .name = TYPE_XIVE_NOTIFIER, 1722 .parent = TYPE_INTERFACE, 1723 .class_size = sizeof(XiveNotifierClass), 1724 }; 1725 1726 static void xive_register_types(void) 1727 { 1728 type_register_static(&xive_source_info); 1729 type_register_static(&xive_notifier_info); 1730 type_register_static(&xive_router_info); 1731 type_register_static(&xive_end_source_info); 1732 type_register_static(&xive_tctx_info); 1733 } 1734 1735 type_init(xive_register_types) 1736