1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "hw/qdev-properties.h" 18 #include "monitor/monitor.h" 19 #include "hw/ppc/xive.h" 20 #include "hw/ppc/xive_regs.h" 21 22 /* 23 * XIVE Thread Interrupt Management context 24 */ 25 26 /* 27 * Convert a priority number to an Interrupt Pending Buffer (IPB) 28 * register, which indicates a pending interrupt at the priority 29 * corresponding to the bit number 30 */ 31 static uint8_t priority_to_ipb(uint8_t priority) 32 { 33 return priority > XIVE_PRIORITY_MAX ? 34 0 : 1 << (XIVE_PRIORITY_MAX - priority); 35 } 36 37 /* 38 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 39 * Interrupt Priority Register (PIPR), which contains the priority of 40 * the most favored pending notification. 41 */ 42 static uint8_t ipb_to_pipr(uint8_t ibp) 43 { 44 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 45 } 46 47 static void ipb_update(uint8_t *regs, uint8_t priority) 48 { 49 regs[TM_IPB] |= priority_to_ipb(priority); 50 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 51 } 52 53 static uint8_t exception_mask(uint8_t ring) 54 { 55 switch (ring) { 56 case TM_QW1_OS: 57 return TM_QW1_NSR_EO; 58 case TM_QW3_HV_PHYS: 59 return TM_QW3_NSR_HE; 60 default: 61 g_assert_not_reached(); 62 } 63 } 64 65 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 66 { 67 uint8_t *regs = &tctx->regs[ring]; 68 uint8_t nsr = regs[TM_NSR]; 69 uint8_t mask = exception_mask(ring); 70 71 qemu_irq_lower(tctx->output); 72 73 if (regs[TM_NSR] & mask) { 74 uint8_t cppr = regs[TM_PIPR]; 75 76 regs[TM_CPPR] = cppr; 77 78 /* Reset the pending buffer bit */ 79 regs[TM_IPB] &= ~priority_to_ipb(cppr); 80 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 81 82 /* Drop Exception bit */ 83 regs[TM_NSR] &= ~mask; 84 } 85 86 return (nsr << 8) | regs[TM_CPPR]; 87 } 88 89 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 90 { 91 uint8_t *regs = &tctx->regs[ring]; 92 93 if (regs[TM_PIPR] < regs[TM_CPPR]) { 94 switch (ring) { 95 case TM_QW1_OS: 96 regs[TM_NSR] |= TM_QW1_NSR_EO; 97 break; 98 case TM_QW3_HV_PHYS: 99 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 100 break; 101 default: 102 g_assert_not_reached(); 103 } 104 qemu_irq_raise(tctx->output); 105 } 106 } 107 108 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 109 { 110 if (cppr > XIVE_PRIORITY_MAX) { 111 cppr = 0xff; 112 } 113 114 tctx->regs[ring + TM_CPPR] = cppr; 115 116 /* CPPR has changed, check if we need to raise a pending exception */ 117 xive_tctx_notify(tctx, ring); 118 } 119 120 /* 121 * XIVE Thread Interrupt Management Area (TIMA) 122 */ 123 124 static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset, 125 uint64_t value, unsigned size) 126 { 127 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 128 } 129 130 static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) 131 { 132 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 133 } 134 135 static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, 136 unsigned size) 137 { 138 uint64_t ret; 139 140 ret = tctx->regs[TM_QW2_HV_POOL + TM_WORD2] & TM_QW2W2_POOL_CAM; 141 tctx->regs[TM_QW2_HV_POOL + TM_WORD2] &= ~TM_QW2W2_POOL_CAM; 142 return ret; 143 } 144 145 static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset, 146 uint64_t value, unsigned size) 147 { 148 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 149 } 150 151 static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned size) 152 { 153 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 154 } 155 156 /* 157 * Define an access map for each page of the TIMA that we will use in 158 * the memory region ops to filter values when doing loads and stores 159 * of raw registers values 160 * 161 * Registers accessibility bits : 162 * 163 * 0x0 - no access 164 * 0x1 - write only 165 * 0x2 - read only 166 * 0x3 - read/write 167 */ 168 169 static const uint8_t xive_tm_hw_view[] = { 170 /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, 171 /* QW-1 OS */ 3, 3, 3, 3, 3, 3, 0, 3, 3, 3, 3, 3, 0, 0, 0, 0, 172 /* QW-2 POOL */ 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, 173 /* QW-3 PHYS */ 3, 3, 3, 3, 0, 3, 0, 3, 3, 0, 0, 3, 3, 3, 3, 0, 174 }; 175 176 static const uint8_t xive_tm_hv_view[] = { 177 /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, 178 /* QW-1 OS */ 3, 3, 3, 3, 3, 3, 0, 3, 3, 3, 3, 3, 0, 0, 0, 0, 179 /* QW-2 POOL */ 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, 180 /* QW-3 PHYS */ 3, 3, 3, 3, 0, 3, 0, 3, 3, 0, 0, 3, 0, 0, 0, 0, 181 }; 182 183 static const uint8_t xive_tm_os_view[] = { 184 /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, 185 /* QW-1 OS */ 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 186 /* QW-2 POOL */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 187 /* QW-3 PHYS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 188 }; 189 190 static const uint8_t xive_tm_user_view[] = { 191 /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 192 /* QW-1 OS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 193 /* QW-2 POOL */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 194 /* QW-3 PHYS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 195 }; 196 197 /* 198 * Overall TIMA access map for the thread interrupt management context 199 * registers 200 */ 201 static const uint8_t *xive_tm_views[] = { 202 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 203 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 204 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 205 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 206 }; 207 208 /* 209 * Computes a register access mask for a given offset in the TIMA 210 */ 211 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 212 { 213 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 214 uint8_t reg_offset = offset & 0x3F; 215 uint8_t reg_mask = write ? 0x1 : 0x2; 216 uint64_t mask = 0x0; 217 int i; 218 219 for (i = 0; i < size; i++) { 220 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 221 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 222 } 223 } 224 225 return mask; 226 } 227 228 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 229 unsigned size) 230 { 231 uint8_t ring_offset = offset & 0x30; 232 uint8_t reg_offset = offset & 0x3F; 233 uint64_t mask = xive_tm_mask(offset, size, true); 234 int i; 235 236 /* 237 * Only 4 or 8 bytes stores are allowed and the User ring is 238 * excluded 239 */ 240 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 241 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 242 HWADDR_PRIx"\n", offset); 243 return; 244 } 245 246 /* 247 * Use the register offset for the raw values and filter out 248 * reserved values 249 */ 250 for (i = 0; i < size; i++) { 251 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 252 if (byte_mask) { 253 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 254 byte_mask; 255 } 256 } 257 } 258 259 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 260 { 261 uint8_t ring_offset = offset & 0x30; 262 uint8_t reg_offset = offset & 0x3F; 263 uint64_t mask = xive_tm_mask(offset, size, false); 264 uint64_t ret; 265 int i; 266 267 /* 268 * Only 4 or 8 bytes loads are allowed and the User ring is 269 * excluded 270 */ 271 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 272 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 273 HWADDR_PRIx"\n", offset); 274 return -1; 275 } 276 277 /* Use the register offset for the raw values */ 278 ret = 0; 279 for (i = 0; i < size; i++) { 280 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 281 } 282 283 /* filter out reserved values */ 284 return ret & mask; 285 } 286 287 /* 288 * The TM context is mapped twice within each page. Stores and loads 289 * to the first mapping below 2K write and read the specified values 290 * without modification. The second mapping above 2K performs specific 291 * state changes (side effects) in addition to setting/returning the 292 * interrupt management area context of the processor thread. 293 */ 294 static uint64_t xive_tm_ack_os_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) 295 { 296 return xive_tctx_accept(tctx, TM_QW1_OS); 297 } 298 299 static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset, 300 uint64_t value, unsigned size) 301 { 302 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 303 } 304 305 /* 306 * Adjust the IPB to allow a CPU to process event queues of other 307 * priorities during one physical interrupt cycle. 308 */ 309 static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset, 310 uint64_t value, unsigned size) 311 { 312 ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff); 313 xive_tctx_notify(tctx, TM_QW1_OS); 314 } 315 316 /* 317 * Define a mapping of "special" operations depending on the TIMA page 318 * offset and the size of the operation. 319 */ 320 typedef struct XiveTmOp { 321 uint8_t page_offset; 322 uint32_t op_offset; 323 unsigned size; 324 void (*write_handler)(XiveTCTX *tctx, hwaddr offset, uint64_t value, 325 unsigned size); 326 uint64_t (*read_handler)(XiveTCTX *tctx, hwaddr offset, unsigned size); 327 } XiveTmOp; 328 329 static const XiveTmOp xive_tm_operations[] = { 330 /* 331 * MMIOs below 2K : raw values and special operations without side 332 * effects 333 */ 334 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 335 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 336 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 337 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 338 339 /* MMIOs above 2K : special operations with side effects */ 340 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 341 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 342 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 343 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 344 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 345 }; 346 347 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 348 { 349 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 350 uint32_t op_offset = offset & 0xFFF; 351 int i; 352 353 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 354 const XiveTmOp *xto = &xive_tm_operations[i]; 355 356 /* Accesses done from a more privileged TIMA page is allowed */ 357 if (xto->page_offset >= page_offset && 358 xto->op_offset == op_offset && 359 xto->size == size && 360 ((write && xto->write_handler) || (!write && xto->read_handler))) { 361 return xto; 362 } 363 } 364 return NULL; 365 } 366 367 /* 368 * TIMA MMIO handlers 369 */ 370 void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 371 unsigned size) 372 { 373 const XiveTmOp *xto; 374 375 /* 376 * TODO: check V bit in Q[0-3]W2 377 */ 378 379 /* 380 * First, check for special operations in the 2K region 381 */ 382 if (offset & 0x800) { 383 xto = xive_tm_find_op(offset, size, true); 384 if (!xto) { 385 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA" 386 "@%"HWADDR_PRIx"\n", offset); 387 } else { 388 xto->write_handler(tctx, offset, value, size); 389 } 390 return; 391 } 392 393 /* 394 * Then, for special operations in the region below 2K. 395 */ 396 xto = xive_tm_find_op(offset, size, true); 397 if (xto) { 398 xto->write_handler(tctx, offset, value, size); 399 return; 400 } 401 402 /* 403 * Finish with raw access to the register values 404 */ 405 xive_tm_raw_write(tctx, offset, value, size); 406 } 407 408 uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 409 { 410 const XiveTmOp *xto; 411 412 /* 413 * TODO: check V bit in Q[0-3]W2 414 */ 415 416 /* 417 * First, check for special operations in the 2K region 418 */ 419 if (offset & 0x800) { 420 xto = xive_tm_find_op(offset, size, false); 421 if (!xto) { 422 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 423 "@%"HWADDR_PRIx"\n", offset); 424 return -1; 425 } 426 return xto->read_handler(tctx, offset, size); 427 } 428 429 /* 430 * Then, for special operations in the region below 2K. 431 */ 432 xto = xive_tm_find_op(offset, size, false); 433 if (xto) { 434 return xto->read_handler(tctx, offset, size); 435 } 436 437 /* 438 * Finish with raw access to the register values 439 */ 440 return xive_tm_raw_read(tctx, offset, size); 441 } 442 443 static void xive_tm_write(void *opaque, hwaddr offset, 444 uint64_t value, unsigned size) 445 { 446 XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); 447 448 xive_tctx_tm_write(tctx, offset, value, size); 449 } 450 451 static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) 452 { 453 XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); 454 455 return xive_tctx_tm_read(tctx, offset, size); 456 } 457 458 const MemoryRegionOps xive_tm_ops = { 459 .read = xive_tm_read, 460 .write = xive_tm_write, 461 .endianness = DEVICE_BIG_ENDIAN, 462 .valid = { 463 .min_access_size = 1, 464 .max_access_size = 8, 465 }, 466 .impl = { 467 .min_access_size = 1, 468 .max_access_size = 8, 469 }, 470 }; 471 472 static inline uint32_t xive_tctx_word2(uint8_t *ring) 473 { 474 return *((uint32_t *) &ring[TM_WORD2]); 475 } 476 477 static char *xive_tctx_ring_print(uint8_t *ring) 478 { 479 uint32_t w2 = xive_tctx_word2(ring); 480 481 return g_strdup_printf("%02x %02x %02x %02x %02x " 482 "%02x %02x %02x %08x", 483 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 484 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 485 be32_to_cpu(w2)); 486 } 487 488 static const char * const xive_tctx_ring_names[] = { 489 "USER", "OS", "POOL", "PHYS", 490 }; 491 492 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 493 { 494 int cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 495 int i; 496 497 if (kvm_irqchip_in_kernel()) { 498 Error *local_err = NULL; 499 500 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 501 if (local_err) { 502 error_report_err(local_err); 503 return; 504 } 505 } 506 507 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 508 " W2\n", cpu_index); 509 510 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 511 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 512 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 513 xive_tctx_ring_names[i], s); 514 g_free(s); 515 } 516 } 517 518 static void xive_tctx_reset(void *dev) 519 { 520 XiveTCTX *tctx = XIVE_TCTX(dev); 521 522 memset(tctx->regs, 0, sizeof(tctx->regs)); 523 524 /* Set some defaults */ 525 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 526 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 527 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 528 529 /* 530 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 531 * CPPR is first set. 532 */ 533 tctx->regs[TM_QW1_OS + TM_PIPR] = 534 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 535 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 536 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 537 } 538 539 static void xive_tctx_realize(DeviceState *dev, Error **errp) 540 { 541 XiveTCTX *tctx = XIVE_TCTX(dev); 542 PowerPCCPU *cpu; 543 CPUPPCState *env; 544 Object *obj; 545 Error *local_err = NULL; 546 547 obj = object_property_get_link(OBJECT(dev), "cpu", &local_err); 548 if (!obj) { 549 error_propagate(errp, local_err); 550 error_prepend(errp, "required link 'cpu' not found: "); 551 return; 552 } 553 554 cpu = POWERPC_CPU(obj); 555 tctx->cs = CPU(obj); 556 557 env = &cpu->env; 558 switch (PPC_INPUT(env)) { 559 case PPC_FLAGS_INPUT_POWER9: 560 tctx->output = env->irq_inputs[POWER9_INPUT_INT]; 561 break; 562 563 default: 564 error_setg(errp, "XIVE interrupt controller does not support " 565 "this CPU bus model"); 566 return; 567 } 568 569 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 570 if (kvm_irqchip_in_kernel()) { 571 kvmppc_xive_cpu_connect(tctx, &local_err); 572 if (local_err) { 573 error_propagate(errp, local_err); 574 return; 575 } 576 } 577 578 qemu_register_reset(xive_tctx_reset, dev); 579 } 580 581 static void xive_tctx_unrealize(DeviceState *dev, Error **errp) 582 { 583 qemu_unregister_reset(xive_tctx_reset, dev); 584 } 585 586 static int vmstate_xive_tctx_pre_save(void *opaque) 587 { 588 Error *local_err = NULL; 589 590 if (kvm_irqchip_in_kernel()) { 591 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque), &local_err); 592 if (local_err) { 593 error_report_err(local_err); 594 return -1; 595 } 596 } 597 598 return 0; 599 } 600 601 static const VMStateDescription vmstate_xive_tctx = { 602 .name = TYPE_XIVE_TCTX, 603 .version_id = 1, 604 .minimum_version_id = 1, 605 .pre_save = vmstate_xive_tctx_pre_save, 606 .post_load = NULL, /* handled by the sPAPRxive model */ 607 .fields = (VMStateField[]) { 608 VMSTATE_BUFFER(regs, XiveTCTX), 609 VMSTATE_END_OF_LIST() 610 }, 611 }; 612 613 static void xive_tctx_class_init(ObjectClass *klass, void *data) 614 { 615 DeviceClass *dc = DEVICE_CLASS(klass); 616 617 dc->desc = "XIVE Interrupt Thread Context"; 618 dc->realize = xive_tctx_realize; 619 dc->unrealize = xive_tctx_unrealize; 620 dc->vmsd = &vmstate_xive_tctx; 621 } 622 623 static const TypeInfo xive_tctx_info = { 624 .name = TYPE_XIVE_TCTX, 625 .parent = TYPE_DEVICE, 626 .instance_size = sizeof(XiveTCTX), 627 .class_init = xive_tctx_class_init, 628 }; 629 630 Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) 631 { 632 Error *local_err = NULL; 633 Object *obj; 634 635 obj = object_new(TYPE_XIVE_TCTX); 636 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); 637 object_unref(obj); 638 object_property_add_const_link(obj, "cpu", cpu, &error_abort); 639 object_property_set_bool(obj, true, "realized", &local_err); 640 if (local_err) { 641 goto error; 642 } 643 644 return obj; 645 646 error: 647 object_unparent(obj); 648 error_propagate(errp, local_err); 649 return NULL; 650 } 651 652 /* 653 * XIVE ESB helpers 654 */ 655 656 static uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 657 { 658 uint8_t old_pq = *pq & 0x3; 659 660 *pq &= ~0x3; 661 *pq |= value & 0x3; 662 663 return old_pq; 664 } 665 666 static bool xive_esb_trigger(uint8_t *pq) 667 { 668 uint8_t old_pq = *pq & 0x3; 669 670 switch (old_pq) { 671 case XIVE_ESB_RESET: 672 xive_esb_set(pq, XIVE_ESB_PENDING); 673 return true; 674 case XIVE_ESB_PENDING: 675 case XIVE_ESB_QUEUED: 676 xive_esb_set(pq, XIVE_ESB_QUEUED); 677 return false; 678 case XIVE_ESB_OFF: 679 xive_esb_set(pq, XIVE_ESB_OFF); 680 return false; 681 default: 682 g_assert_not_reached(); 683 } 684 } 685 686 static bool xive_esb_eoi(uint8_t *pq) 687 { 688 uint8_t old_pq = *pq & 0x3; 689 690 switch (old_pq) { 691 case XIVE_ESB_RESET: 692 case XIVE_ESB_PENDING: 693 xive_esb_set(pq, XIVE_ESB_RESET); 694 return false; 695 case XIVE_ESB_QUEUED: 696 xive_esb_set(pq, XIVE_ESB_PENDING); 697 return true; 698 case XIVE_ESB_OFF: 699 xive_esb_set(pq, XIVE_ESB_OFF); 700 return false; 701 default: 702 g_assert_not_reached(); 703 } 704 } 705 706 /* 707 * XIVE Interrupt Source (or IVSE) 708 */ 709 710 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 711 { 712 assert(srcno < xsrc->nr_irqs); 713 714 return xsrc->status[srcno] & 0x3; 715 } 716 717 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 718 { 719 assert(srcno < xsrc->nr_irqs); 720 721 return xive_esb_set(&xsrc->status[srcno], pq); 722 } 723 724 /* 725 * Returns whether the event notification should be forwarded. 726 */ 727 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 728 { 729 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 730 731 xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; 732 733 switch (old_pq) { 734 case XIVE_ESB_RESET: 735 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 736 return true; 737 default: 738 return false; 739 } 740 } 741 742 /* 743 * Returns whether the event notification should be forwarded. 744 */ 745 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 746 { 747 bool ret; 748 749 assert(srcno < xsrc->nr_irqs); 750 751 ret = xive_esb_trigger(&xsrc->status[srcno]); 752 753 if (xive_source_irq_is_lsi(xsrc, srcno) && 754 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 755 qemu_log_mask(LOG_GUEST_ERROR, 756 "XIVE: queued an event on LSI IRQ %d\n", srcno); 757 } 758 759 return ret; 760 } 761 762 /* 763 * Returns whether the event notification should be forwarded. 764 */ 765 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 766 { 767 bool ret; 768 769 assert(srcno < xsrc->nr_irqs); 770 771 ret = xive_esb_eoi(&xsrc->status[srcno]); 772 773 /* 774 * LSI sources do not set the Q bit but they can still be 775 * asserted, in which case we should forward a new event 776 * notification 777 */ 778 if (xive_source_irq_is_lsi(xsrc, srcno) && 779 xsrc->status[srcno] & XIVE_STATUS_ASSERTED) { 780 ret = xive_source_lsi_trigger(xsrc, srcno); 781 } 782 783 return ret; 784 } 785 786 /* 787 * Forward the source event notification to the Router 788 */ 789 static void xive_source_notify(XiveSource *xsrc, int srcno) 790 { 791 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 792 793 if (xnc->notify) { 794 xnc->notify(xsrc->xive, srcno); 795 } 796 } 797 798 /* 799 * In a two pages ESB MMIO setting, even page is the trigger page, odd 800 * page is for management 801 */ 802 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 803 { 804 return !((addr >> shift) & 1); 805 } 806 807 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 808 { 809 return xive_source_esb_has_2page(xsrc) && 810 addr_is_even(addr, xsrc->esb_shift - 1); 811 } 812 813 /* 814 * ESB MMIO loads 815 * Trigger page Management/EOI page 816 * 817 * ESB MMIO setting 2 pages 1 or 2 pages 818 * 819 * 0x000 .. 0x3FF -1 EOI and return 0|1 820 * 0x400 .. 0x7FF -1 EOI and return 0|1 821 * 0x800 .. 0xBFF -1 return PQ 822 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 823 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 824 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 825 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 826 */ 827 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 828 { 829 XiveSource *xsrc = XIVE_SOURCE(opaque); 830 uint32_t offset = addr & 0xFFF; 831 uint32_t srcno = addr >> xsrc->esb_shift; 832 uint64_t ret = -1; 833 834 /* In a two pages ESB MMIO setting, trigger page should not be read */ 835 if (xive_source_is_trigger_page(xsrc, addr)) { 836 qemu_log_mask(LOG_GUEST_ERROR, 837 "XIVE: invalid load on IRQ %d trigger page at " 838 "0x%"HWADDR_PRIx"\n", srcno, addr); 839 return -1; 840 } 841 842 switch (offset) { 843 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 844 ret = xive_source_esb_eoi(xsrc, srcno); 845 846 /* Forward the source event notification for routing */ 847 if (ret) { 848 xive_source_notify(xsrc, srcno); 849 } 850 break; 851 852 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 853 ret = xive_source_esb_get(xsrc, srcno); 854 break; 855 856 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 857 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 858 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 859 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 860 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 861 break; 862 default: 863 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 864 offset); 865 } 866 867 return ret; 868 } 869 870 /* 871 * ESB MMIO stores 872 * Trigger page Management/EOI page 873 * 874 * ESB MMIO setting 2 pages 1 or 2 pages 875 * 876 * 0x000 .. 0x3FF Trigger Trigger 877 * 0x400 .. 0x7FF Trigger EOI 878 * 0x800 .. 0xBFF Trigger undefined 879 * 0xC00 .. 0xCFF Trigger PQ=00 880 * 0xD00 .. 0xDFF Trigger PQ=01 881 * 0xE00 .. 0xDFF Trigger PQ=10 882 * 0xF00 .. 0xDFF Trigger PQ=11 883 */ 884 static void xive_source_esb_write(void *opaque, hwaddr addr, 885 uint64_t value, unsigned size) 886 { 887 XiveSource *xsrc = XIVE_SOURCE(opaque); 888 uint32_t offset = addr & 0xFFF; 889 uint32_t srcno = addr >> xsrc->esb_shift; 890 bool notify = false; 891 892 /* In a two pages ESB MMIO setting, trigger page only triggers */ 893 if (xive_source_is_trigger_page(xsrc, addr)) { 894 notify = xive_source_esb_trigger(xsrc, srcno); 895 goto out; 896 } 897 898 switch (offset) { 899 case 0 ... 0x3FF: 900 notify = xive_source_esb_trigger(xsrc, srcno); 901 break; 902 903 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 904 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 905 qemu_log_mask(LOG_GUEST_ERROR, 906 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 907 return; 908 } 909 910 notify = xive_source_esb_eoi(xsrc, srcno); 911 break; 912 913 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 914 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 915 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 916 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 917 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 918 break; 919 920 default: 921 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 922 offset); 923 return; 924 } 925 926 out: 927 /* Forward the source event notification for routing */ 928 if (notify) { 929 xive_source_notify(xsrc, srcno); 930 } 931 } 932 933 static const MemoryRegionOps xive_source_esb_ops = { 934 .read = xive_source_esb_read, 935 .write = xive_source_esb_write, 936 .endianness = DEVICE_BIG_ENDIAN, 937 .valid = { 938 .min_access_size = 8, 939 .max_access_size = 8, 940 }, 941 .impl = { 942 .min_access_size = 8, 943 .max_access_size = 8, 944 }, 945 }; 946 947 void xive_source_set_irq(void *opaque, int srcno, int val) 948 { 949 XiveSource *xsrc = XIVE_SOURCE(opaque); 950 bool notify = false; 951 952 if (xive_source_irq_is_lsi(xsrc, srcno)) { 953 if (val) { 954 notify = xive_source_lsi_trigger(xsrc, srcno); 955 } else { 956 xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; 957 } 958 } else { 959 if (val) { 960 notify = xive_source_esb_trigger(xsrc, srcno); 961 } 962 } 963 964 /* Forward the source event notification for routing */ 965 if (notify) { 966 xive_source_notify(xsrc, srcno); 967 } 968 } 969 970 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 971 { 972 int i; 973 974 for (i = 0; i < xsrc->nr_irqs; i++) { 975 uint8_t pq = xive_source_esb_get(xsrc, i); 976 977 if (pq == XIVE_ESB_OFF) { 978 continue; 979 } 980 981 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 982 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 983 pq & XIVE_ESB_VAL_P ? 'P' : '-', 984 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 985 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' '); 986 } 987 } 988 989 static void xive_source_reset(void *dev) 990 { 991 XiveSource *xsrc = XIVE_SOURCE(dev); 992 993 /* Do not clear the LSI bitmap */ 994 995 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 996 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 997 } 998 999 static void xive_source_realize(DeviceState *dev, Error **errp) 1000 { 1001 XiveSource *xsrc = XIVE_SOURCE(dev); 1002 Object *obj; 1003 Error *local_err = NULL; 1004 1005 obj = object_property_get_link(OBJECT(dev), "xive", &local_err); 1006 if (!obj) { 1007 error_propagate(errp, local_err); 1008 error_prepend(errp, "required link 'xive' not found: "); 1009 return; 1010 } 1011 1012 xsrc->xive = XIVE_NOTIFIER(obj); 1013 1014 if (!xsrc->nr_irqs) { 1015 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1016 return; 1017 } 1018 1019 if (xsrc->esb_shift != XIVE_ESB_4K && 1020 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1021 xsrc->esb_shift != XIVE_ESB_64K && 1022 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1023 error_setg(errp, "Invalid ESB shift setting"); 1024 return; 1025 } 1026 1027 xsrc->status = g_malloc0(xsrc->nr_irqs); 1028 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1029 1030 if (!kvm_irqchip_in_kernel()) { 1031 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1032 &xive_source_esb_ops, xsrc, "xive.esb", 1033 (1ull << xsrc->esb_shift) * xsrc->nr_irqs); 1034 } 1035 1036 qemu_register_reset(xive_source_reset, dev); 1037 } 1038 1039 static const VMStateDescription vmstate_xive_source = { 1040 .name = TYPE_XIVE_SOURCE, 1041 .version_id = 1, 1042 .minimum_version_id = 1, 1043 .fields = (VMStateField[]) { 1044 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1045 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1046 VMSTATE_END_OF_LIST() 1047 }, 1048 }; 1049 1050 /* 1051 * The default XIVE interrupt source setting for the ESB MMIOs is two 1052 * 64k pages without Store EOI, to be in sync with KVM. 1053 */ 1054 static Property xive_source_properties[] = { 1055 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1056 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1057 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1058 DEFINE_PROP_END_OF_LIST(), 1059 }; 1060 1061 static void xive_source_class_init(ObjectClass *klass, void *data) 1062 { 1063 DeviceClass *dc = DEVICE_CLASS(klass); 1064 1065 dc->desc = "XIVE Interrupt Source"; 1066 dc->props = xive_source_properties; 1067 dc->realize = xive_source_realize; 1068 dc->vmsd = &vmstate_xive_source; 1069 } 1070 1071 static const TypeInfo xive_source_info = { 1072 .name = TYPE_XIVE_SOURCE, 1073 .parent = TYPE_DEVICE, 1074 .instance_size = sizeof(XiveSource), 1075 .class_init = xive_source_class_init, 1076 }; 1077 1078 /* 1079 * XiveEND helpers 1080 */ 1081 1082 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1083 { 1084 uint64_t qaddr_base = xive_end_qaddr(end); 1085 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1086 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1087 uint32_t qentries = 1 << (qsize + 10); 1088 int i; 1089 1090 /* 1091 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1092 */ 1093 monitor_printf(mon, " [ "); 1094 qindex = (qindex - (width - 1)) & (qentries - 1); 1095 for (i = 0; i < width; i++) { 1096 uint64_t qaddr = qaddr_base + (qindex << 2); 1097 uint32_t qdata = -1; 1098 1099 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 1100 sizeof(qdata))) { 1101 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1102 HWADDR_PRIx "\n", qaddr); 1103 return; 1104 } 1105 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1106 be32_to_cpu(qdata)); 1107 qindex = (qindex + 1) & (qentries - 1); 1108 } 1109 } 1110 1111 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1112 { 1113 uint64_t qaddr_base = xive_end_qaddr(end); 1114 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1115 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1116 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1117 uint32_t qentries = 1 << (qsize + 10); 1118 1119 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1120 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1121 1122 if (!xive_end_is_valid(end)) { 1123 return; 1124 } 1125 1126 monitor_printf(mon, " %08x %c%c%c%c%c prio:%d nvt:%04x eq:@%08"PRIx64 1127 "% 6d/%5d ^%d", end_idx, 1128 xive_end_is_valid(end) ? 'v' : '-', 1129 xive_end_is_enqueue(end) ? 'q' : '-', 1130 xive_end_is_notify(end) ? 'n' : '-', 1131 xive_end_is_backlog(end) ? 'b' : '-', 1132 xive_end_is_escalate(end) ? 'e' : '-', 1133 priority, nvt, qaddr_base, qindex, qentries, qgen); 1134 1135 xive_end_queue_pic_print_info(end, 6, mon); 1136 monitor_printf(mon, "]\n"); 1137 } 1138 1139 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1140 { 1141 uint64_t qaddr_base = xive_end_qaddr(end); 1142 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1143 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1144 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1145 1146 uint64_t qaddr = qaddr_base + (qindex << 2); 1147 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1148 uint32_t qentries = 1 << (qsize + 10); 1149 1150 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) { 1151 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1152 HWADDR_PRIx "\n", qaddr); 1153 return; 1154 } 1155 1156 qindex = (qindex + 1) & (qentries - 1); 1157 if (qindex == 0) { 1158 qgen ^= 1; 1159 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1160 } 1161 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1162 } 1163 1164 /* 1165 * XIVE Router (aka. Virtualization Controller or IVRE) 1166 */ 1167 1168 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1169 XiveEAS *eas) 1170 { 1171 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1172 1173 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1174 } 1175 1176 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1177 XiveEND *end) 1178 { 1179 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1180 1181 return xrc->get_end(xrtr, end_blk, end_idx, end); 1182 } 1183 1184 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1185 XiveEND *end, uint8_t word_number) 1186 { 1187 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1188 1189 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1190 } 1191 1192 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1193 XiveNVT *nvt) 1194 { 1195 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1196 1197 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1198 } 1199 1200 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1201 XiveNVT *nvt, uint8_t word_number) 1202 { 1203 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1204 1205 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1206 } 1207 1208 XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) 1209 { 1210 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1211 1212 return xrc->get_tctx(xrtr, cs); 1213 } 1214 1215 /* 1216 * By default on P9, the HW CAM line (23bits) is hardwired to : 1217 * 1218 * 0x000||0b1||4Bit chip number||7Bit Thread number. 1219 * 1220 * When the block grouping is enabled, the CAM line is changed to : 1221 * 1222 * 4Bit chip number||0x001||7Bit Thread number. 1223 */ 1224 static uint32_t hw_cam_line(uint8_t chip_id, uint8_t tid) 1225 { 1226 return 1 << 11 | (chip_id & 0xf) << 7 | (tid & 0x7f); 1227 } 1228 1229 static bool xive_presenter_tctx_match_hw(XiveTCTX *tctx, 1230 uint8_t nvt_blk, uint32_t nvt_idx) 1231 { 1232 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1233 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1234 1235 return hw_cam_line((pir >> 8) & 0xf, pir & 0x7f) == 1236 hw_cam_line(nvt_blk, nvt_idx); 1237 } 1238 1239 /* 1240 * The thread context register words are in big-endian format. 1241 */ 1242 static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format, 1243 uint8_t nvt_blk, uint32_t nvt_idx, 1244 bool cam_ignore, uint32_t logic_serv) 1245 { 1246 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1247 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1248 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1249 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1250 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1251 1252 /* 1253 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1254 * identifier are ignored in the "CAM" match. 1255 */ 1256 1257 if (format == 0) { 1258 if (cam_ignore == true) { 1259 /* 1260 * F=0 & i=1: Logical server notification (bits ignored at 1261 * the end of the NVT identifier) 1262 */ 1263 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1264 nvt_blk, nvt_idx); 1265 return -1; 1266 } 1267 1268 /* F=0 & i=0: Specific NVT notification */ 1269 1270 /* PHYS ring */ 1271 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1272 xive_presenter_tctx_match_hw(tctx, nvt_blk, nvt_idx)) { 1273 return TM_QW3_HV_PHYS; 1274 } 1275 1276 /* HV POOL ring */ 1277 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1278 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1279 return TM_QW2_HV_POOL; 1280 } 1281 1282 /* OS ring */ 1283 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1284 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1285 return TM_QW1_OS; 1286 } 1287 } else { 1288 /* F=1 : User level Event-Based Branch (EBB) notification */ 1289 1290 /* USER ring */ 1291 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1292 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1293 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1294 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1295 return TM_QW0_USER; 1296 } 1297 } 1298 return -1; 1299 } 1300 1301 typedef struct XiveTCTXMatch { 1302 XiveTCTX *tctx; 1303 uint8_t ring; 1304 } XiveTCTXMatch; 1305 1306 static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, 1307 uint8_t nvt_blk, uint32_t nvt_idx, 1308 bool cam_ignore, uint8_t priority, 1309 uint32_t logic_serv, XiveTCTXMatch *match) 1310 { 1311 CPUState *cs; 1312 1313 /* 1314 * TODO (PowerNV): handle chip_id overwrite of block field for 1315 * hardwired CAM compares 1316 */ 1317 1318 CPU_FOREACH(cs) { 1319 XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs); 1320 int ring; 1321 1322 /* 1323 * HW checks that the CPU is enabled in the Physical Thread 1324 * Enable Register (PTER). 1325 */ 1326 1327 /* 1328 * Check the thread context CAM lines and record matches. We 1329 * will handle CPU exception delivery later 1330 */ 1331 ring = xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx, 1332 cam_ignore, logic_serv); 1333 /* 1334 * Save the context and follow on to catch duplicates, that we 1335 * don't support yet. 1336 */ 1337 if (ring != -1) { 1338 if (match->tctx) { 1339 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread " 1340 "context NVT %x/%x\n", nvt_blk, nvt_idx); 1341 return false; 1342 } 1343 1344 match->ring = ring; 1345 match->tctx = tctx; 1346 } 1347 } 1348 1349 if (!match->tctx) { 1350 qemu_log_mask(LOG_UNIMP, "XIVE: NVT %x/%x is not dispatched\n", 1351 nvt_blk, nvt_idx); 1352 return false; 1353 } 1354 1355 return true; 1356 } 1357 1358 /* 1359 * This is our simple Xive Presenter Engine model. It is merged in the 1360 * Router as it does not require an extra object. 1361 * 1362 * It receives notification requests sent by the IVRE to find one 1363 * matching NVT (or more) dispatched on the processor threads. In case 1364 * of a single NVT notification, the process is abreviated and the 1365 * thread is signaled if a match is found. In case of a logical server 1366 * notification (bits ignored at the end of the NVT identifier), the 1367 * IVPE and IVRE select a winning thread using different filters. This 1368 * involves 2 or 3 exchanges on the PowerBus that the model does not 1369 * support. 1370 * 1371 * The parameters represent what is sent on the PowerBus 1372 */ 1373 static void xive_presenter_notify(XiveRouter *xrtr, uint8_t format, 1374 uint8_t nvt_blk, uint32_t nvt_idx, 1375 bool cam_ignore, uint8_t priority, 1376 uint32_t logic_serv) 1377 { 1378 XiveNVT nvt; 1379 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1380 bool found; 1381 1382 /* NVT cache lookup */ 1383 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1384 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1385 nvt_blk, nvt_idx); 1386 return; 1387 } 1388 1389 if (!xive_nvt_is_valid(&nvt)) { 1390 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1391 nvt_blk, nvt_idx); 1392 return; 1393 } 1394 1395 found = xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ignore, 1396 priority, logic_serv, &match); 1397 if (found) { 1398 ipb_update(&match.tctx->regs[match.ring], priority); 1399 xive_tctx_notify(match.tctx, match.ring); 1400 return; 1401 } 1402 1403 /* Record the IPB in the associated NVT structure */ 1404 ipb_update((uint8_t *) &nvt.w4, priority); 1405 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1406 1407 /* 1408 * If no matching NVT is dispatched on a HW thread : 1409 * - update the NVT structure if backlog is activated 1410 * - escalate (ESe PQ bits and EAS in w4-5) if escalation is 1411 * activated 1412 */ 1413 } 1414 1415 /* 1416 * An END trigger can come from an event trigger (IPI or HW) or from 1417 * another chip. We don't model the PowerBus but the END trigger 1418 * message has the same parameters than in the function below. 1419 */ 1420 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1421 uint32_t end_idx, uint32_t end_data) 1422 { 1423 XiveEND end; 1424 uint8_t priority; 1425 uint8_t format; 1426 1427 /* END cache lookup */ 1428 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1429 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1430 end_idx); 1431 return; 1432 } 1433 1434 if (!xive_end_is_valid(&end)) { 1435 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1436 end_blk, end_idx); 1437 return; 1438 } 1439 1440 if (xive_end_is_enqueue(&end)) { 1441 xive_end_enqueue(&end, end_data); 1442 /* Enqueuing event data modifies the EQ toggle and index */ 1443 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1444 } 1445 1446 /* 1447 * The W7 format depends on the F bit in W6. It defines the type 1448 * of the notification : 1449 * 1450 * F=0 : single or multiple NVT notification 1451 * F=1 : User level Event-Based Branch (EBB) notification, no 1452 * priority 1453 */ 1454 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1455 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1456 1457 /* The END is masked */ 1458 if (format == 0 && priority == 0xff) { 1459 return; 1460 } 1461 1462 /* 1463 * Check the END ESn (Event State Buffer for notification) for 1464 * even futher coalescing in the Router 1465 */ 1466 if (!xive_end_is_notify(&end)) { 1467 uint8_t pq = xive_get_field32(END_W1_ESn, end.w1); 1468 bool notify = xive_esb_trigger(&pq); 1469 1470 if (pq != xive_get_field32(END_W1_ESn, end.w1)) { 1471 end.w1 = xive_set_field32(END_W1_ESn, end.w1, pq); 1472 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1473 } 1474 1475 /* ESn[Q]=1 : end of notification */ 1476 if (!notify) { 1477 return; 1478 } 1479 } 1480 1481 /* 1482 * Follows IVPE notification 1483 */ 1484 xive_presenter_notify(xrtr, format, 1485 xive_get_field32(END_W6_NVT_BLOCK, end.w6), 1486 xive_get_field32(END_W6_NVT_INDEX, end.w6), 1487 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1488 priority, 1489 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1490 1491 /* TODO: Auto EOI. */ 1492 } 1493 1494 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 1495 { 1496 XiveRouter *xrtr = XIVE_ROUTER(xn); 1497 uint8_t eas_blk = XIVE_SRCNO_BLOCK(lisn); 1498 uint32_t eas_idx = XIVE_SRCNO_INDEX(lisn); 1499 XiveEAS eas; 1500 1501 /* EAS cache lookup */ 1502 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1503 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1504 return; 1505 } 1506 1507 /* 1508 * The IVRE checks the State Bit Cache at this point. We skip the 1509 * SBC lookup because the state bits of the sources are modeled 1510 * internally in QEMU. 1511 */ 1512 1513 if (!xive_eas_is_valid(&eas)) { 1514 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1515 return; 1516 } 1517 1518 if (xive_eas_is_masked(&eas)) { 1519 /* Notification completed */ 1520 return; 1521 } 1522 1523 /* 1524 * The event trigger becomes an END trigger 1525 */ 1526 xive_router_end_notify(xrtr, 1527 xive_get_field64(EAS_END_BLOCK, eas.w), 1528 xive_get_field64(EAS_END_INDEX, eas.w), 1529 xive_get_field64(EAS_END_DATA, eas.w)); 1530 } 1531 1532 static void xive_router_class_init(ObjectClass *klass, void *data) 1533 { 1534 DeviceClass *dc = DEVICE_CLASS(klass); 1535 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1536 1537 dc->desc = "XIVE Router Engine"; 1538 xnc->notify = xive_router_notify; 1539 } 1540 1541 static const TypeInfo xive_router_info = { 1542 .name = TYPE_XIVE_ROUTER, 1543 .parent = TYPE_SYS_BUS_DEVICE, 1544 .abstract = true, 1545 .class_size = sizeof(XiveRouterClass), 1546 .class_init = xive_router_class_init, 1547 .interfaces = (InterfaceInfo[]) { 1548 { TYPE_XIVE_NOTIFIER }, 1549 { } 1550 } 1551 }; 1552 1553 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1554 { 1555 if (!xive_eas_is_valid(eas)) { 1556 return; 1557 } 1558 1559 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1560 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1561 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1562 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1563 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1564 } 1565 1566 /* 1567 * END ESB MMIO loads 1568 */ 1569 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1570 { 1571 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1572 uint32_t offset = addr & 0xFFF; 1573 uint8_t end_blk; 1574 uint32_t end_idx; 1575 XiveEND end; 1576 uint32_t end_esmask; 1577 uint8_t pq; 1578 uint64_t ret = -1; 1579 1580 end_blk = xsrc->block_id; 1581 end_idx = addr >> (xsrc->esb_shift + 1); 1582 1583 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1584 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1585 end_idx); 1586 return -1; 1587 } 1588 1589 if (!xive_end_is_valid(&end)) { 1590 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1591 end_blk, end_idx); 1592 return -1; 1593 } 1594 1595 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1596 pq = xive_get_field32(end_esmask, end.w1); 1597 1598 switch (offset) { 1599 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1600 ret = xive_esb_eoi(&pq); 1601 1602 /* Forward the source event notification for routing ?? */ 1603 break; 1604 1605 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1606 ret = pq; 1607 break; 1608 1609 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1610 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1611 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1612 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1613 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1614 break; 1615 default: 1616 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1617 offset); 1618 return -1; 1619 } 1620 1621 if (pq != xive_get_field32(end_esmask, end.w1)) { 1622 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1623 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1624 } 1625 1626 return ret; 1627 } 1628 1629 /* 1630 * END ESB MMIO stores are invalid 1631 */ 1632 static void xive_end_source_write(void *opaque, hwaddr addr, 1633 uint64_t value, unsigned size) 1634 { 1635 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1636 HWADDR_PRIx"\n", addr); 1637 } 1638 1639 static const MemoryRegionOps xive_end_source_ops = { 1640 .read = xive_end_source_read, 1641 .write = xive_end_source_write, 1642 .endianness = DEVICE_BIG_ENDIAN, 1643 .valid = { 1644 .min_access_size = 8, 1645 .max_access_size = 8, 1646 }, 1647 .impl = { 1648 .min_access_size = 8, 1649 .max_access_size = 8, 1650 }, 1651 }; 1652 1653 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1654 { 1655 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1656 Object *obj; 1657 Error *local_err = NULL; 1658 1659 obj = object_property_get_link(OBJECT(dev), "xive", &local_err); 1660 if (!obj) { 1661 error_propagate(errp, local_err); 1662 error_prepend(errp, "required link 'xive' not found: "); 1663 return; 1664 } 1665 1666 xsrc->xrtr = XIVE_ROUTER(obj); 1667 1668 if (!xsrc->nr_ends) { 1669 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1670 return; 1671 } 1672 1673 if (xsrc->esb_shift != XIVE_ESB_4K && 1674 xsrc->esb_shift != XIVE_ESB_64K) { 1675 error_setg(errp, "Invalid ESB shift setting"); 1676 return; 1677 } 1678 1679 /* 1680 * Each END is assigned an even/odd pair of MMIO pages, the even page 1681 * manages the ESn field while the odd page manages the ESe field. 1682 */ 1683 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1684 &xive_end_source_ops, xsrc, "xive.end", 1685 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1686 } 1687 1688 static Property xive_end_source_properties[] = { 1689 DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0), 1690 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1691 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1692 DEFINE_PROP_END_OF_LIST(), 1693 }; 1694 1695 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1696 { 1697 DeviceClass *dc = DEVICE_CLASS(klass); 1698 1699 dc->desc = "XIVE END Source"; 1700 dc->props = xive_end_source_properties; 1701 dc->realize = xive_end_source_realize; 1702 } 1703 1704 static const TypeInfo xive_end_source_info = { 1705 .name = TYPE_XIVE_END_SOURCE, 1706 .parent = TYPE_DEVICE, 1707 .instance_size = sizeof(XiveENDSource), 1708 .class_init = xive_end_source_class_init, 1709 }; 1710 1711 /* 1712 * XIVE Notifier 1713 */ 1714 static const TypeInfo xive_notifier_info = { 1715 .name = TYPE_XIVE_NOTIFIER, 1716 .parent = TYPE_INTERFACE, 1717 .class_size = sizeof(XiveNotifierClass), 1718 }; 1719 1720 static void xive_register_types(void) 1721 { 1722 type_register_static(&xive_source_info); 1723 type_register_static(&xive_notifier_info); 1724 type_register_static(&xive_router_info); 1725 type_register_static(&xive_end_source_info); 1726 type_register_static(&xive_tctx_info); 1727 } 1728 1729 type_init(xive_register_types) 1730