1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "monitor/monitor.h" 21 #include "hw/irq.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive_regs.h" 24 25 /* 26 * XIVE Thread Interrupt Management context 27 */ 28 29 /* 30 * Convert a priority number to an Interrupt Pending Buffer (IPB) 31 * register, which indicates a pending interrupt at the priority 32 * corresponding to the bit number 33 */ 34 static uint8_t priority_to_ipb(uint8_t priority) 35 { 36 return priority > XIVE_PRIORITY_MAX ? 37 0 : 1 << (XIVE_PRIORITY_MAX - priority); 38 } 39 40 /* 41 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 42 * Interrupt Priority Register (PIPR), which contains the priority of 43 * the most favored pending notification. 44 */ 45 static uint8_t ipb_to_pipr(uint8_t ibp) 46 { 47 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 48 } 49 50 static void ipb_update(uint8_t *regs, uint8_t priority) 51 { 52 regs[TM_IPB] |= priority_to_ipb(priority); 53 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 54 } 55 56 static uint8_t exception_mask(uint8_t ring) 57 { 58 switch (ring) { 59 case TM_QW1_OS: 60 return TM_QW1_NSR_EO; 61 case TM_QW3_HV_PHYS: 62 return TM_QW3_NSR_HE; 63 default: 64 g_assert_not_reached(); 65 } 66 } 67 68 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 69 { 70 switch (ring) { 71 case TM_QW0_USER: 72 return 0; /* Not supported */ 73 case TM_QW1_OS: 74 return tctx->os_output; 75 case TM_QW2_HV_POOL: 76 case TM_QW3_HV_PHYS: 77 return tctx->hv_output; 78 default: 79 return 0; 80 } 81 } 82 83 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 84 { 85 uint8_t *regs = &tctx->regs[ring]; 86 uint8_t nsr = regs[TM_NSR]; 87 uint8_t mask = exception_mask(ring); 88 89 qemu_irq_lower(xive_tctx_output(tctx, ring)); 90 91 if (regs[TM_NSR] & mask) { 92 uint8_t cppr = regs[TM_PIPR]; 93 94 regs[TM_CPPR] = cppr; 95 96 /* Reset the pending buffer bit */ 97 regs[TM_IPB] &= ~priority_to_ipb(cppr); 98 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 99 100 /* Drop Exception bit */ 101 regs[TM_NSR] &= ~mask; 102 } 103 104 return (nsr << 8) | regs[TM_CPPR]; 105 } 106 107 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 108 { 109 uint8_t *regs = &tctx->regs[ring]; 110 111 if (regs[TM_PIPR] < regs[TM_CPPR]) { 112 switch (ring) { 113 case TM_QW1_OS: 114 regs[TM_NSR] |= TM_QW1_NSR_EO; 115 break; 116 case TM_QW3_HV_PHYS: 117 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 118 break; 119 default: 120 g_assert_not_reached(); 121 } 122 qemu_irq_raise(xive_tctx_output(tctx, ring)); 123 } 124 } 125 126 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 127 { 128 if (cppr > XIVE_PRIORITY_MAX) { 129 cppr = 0xff; 130 } 131 132 tctx->regs[ring + TM_CPPR] = cppr; 133 134 /* CPPR has changed, check if we need to raise a pending exception */ 135 xive_tctx_notify(tctx, ring); 136 } 137 138 static inline uint32_t xive_tctx_word2(uint8_t *ring) 139 { 140 return *((uint32_t *) &ring[TM_WORD2]); 141 } 142 143 /* 144 * XIVE Thread Interrupt Management Area (TIMA) 145 */ 146 147 static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset, 148 uint64_t value, unsigned size) 149 { 150 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 151 } 152 153 static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) 154 { 155 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 156 } 157 158 static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, 159 unsigned size) 160 { 161 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 162 uint32_t qw2w2; 163 164 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 165 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 166 return qw2w2; 167 } 168 169 static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset, 170 uint64_t value, unsigned size) 171 { 172 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 173 } 174 175 static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned size) 176 { 177 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 178 } 179 180 /* 181 * Define an access map for each page of the TIMA that we will use in 182 * the memory region ops to filter values when doing loads and stores 183 * of raw registers values 184 * 185 * Registers accessibility bits : 186 * 187 * 0x0 - no access 188 * 0x1 - write only 189 * 0x2 - read only 190 * 0x3 - read/write 191 */ 192 193 static const uint8_t xive_tm_hw_view[] = { 194 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 195 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 196 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 197 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 198 }; 199 200 static const uint8_t xive_tm_hv_view[] = { 201 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 202 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 203 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 204 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 205 }; 206 207 static const uint8_t xive_tm_os_view[] = { 208 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 209 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 210 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 211 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 212 }; 213 214 static const uint8_t xive_tm_user_view[] = { 215 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 219 }; 220 221 /* 222 * Overall TIMA access map for the thread interrupt management context 223 * registers 224 */ 225 static const uint8_t *xive_tm_views[] = { 226 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 227 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 228 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 229 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 230 }; 231 232 /* 233 * Computes a register access mask for a given offset in the TIMA 234 */ 235 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 236 { 237 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 238 uint8_t reg_offset = offset & 0x3F; 239 uint8_t reg_mask = write ? 0x1 : 0x2; 240 uint64_t mask = 0x0; 241 int i; 242 243 for (i = 0; i < size; i++) { 244 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 245 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 246 } 247 } 248 249 return mask; 250 } 251 252 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 253 unsigned size) 254 { 255 uint8_t ring_offset = offset & 0x30; 256 uint8_t reg_offset = offset & 0x3F; 257 uint64_t mask = xive_tm_mask(offset, size, true); 258 int i; 259 260 /* 261 * Only 4 or 8 bytes stores are allowed and the User ring is 262 * excluded 263 */ 264 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 265 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 266 HWADDR_PRIx"\n", offset); 267 return; 268 } 269 270 /* 271 * Use the register offset for the raw values and filter out 272 * reserved values 273 */ 274 for (i = 0; i < size; i++) { 275 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 276 if (byte_mask) { 277 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 278 byte_mask; 279 } 280 } 281 } 282 283 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 284 { 285 uint8_t ring_offset = offset & 0x30; 286 uint8_t reg_offset = offset & 0x3F; 287 uint64_t mask = xive_tm_mask(offset, size, false); 288 uint64_t ret; 289 int i; 290 291 /* 292 * Only 4 or 8 bytes loads are allowed and the User ring is 293 * excluded 294 */ 295 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 296 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 297 HWADDR_PRIx"\n", offset); 298 return -1; 299 } 300 301 /* Use the register offset for the raw values */ 302 ret = 0; 303 for (i = 0; i < size; i++) { 304 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 305 } 306 307 /* filter out reserved values */ 308 return ret & mask; 309 } 310 311 /* 312 * The TM context is mapped twice within each page. Stores and loads 313 * to the first mapping below 2K write and read the specified values 314 * without modification. The second mapping above 2K performs specific 315 * state changes (side effects) in addition to setting/returning the 316 * interrupt management area context of the processor thread. 317 */ 318 static uint64_t xive_tm_ack_os_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) 319 { 320 return xive_tctx_accept(tctx, TM_QW1_OS); 321 } 322 323 static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset, 324 uint64_t value, unsigned size) 325 { 326 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 327 } 328 329 /* 330 * Adjust the IPB to allow a CPU to process event queues of other 331 * priorities during one physical interrupt cycle. 332 */ 333 static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset, 334 uint64_t value, unsigned size) 335 { 336 ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff); 337 xive_tctx_notify(tctx, TM_QW1_OS); 338 } 339 340 static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset, 341 unsigned size) 342 { 343 uint32_t qw1w2_prev = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 344 uint32_t qw1w2; 345 346 qw1w2 = xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0); 347 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 348 return qw1w2; 349 } 350 351 /* 352 * Define a mapping of "special" operations depending on the TIMA page 353 * offset and the size of the operation. 354 */ 355 typedef struct XiveTmOp { 356 uint8_t page_offset; 357 uint32_t op_offset; 358 unsigned size; 359 void (*write_handler)(XiveTCTX *tctx, hwaddr offset, uint64_t value, 360 unsigned size); 361 uint64_t (*read_handler)(XiveTCTX *tctx, hwaddr offset, unsigned size); 362 } XiveTmOp; 363 364 static const XiveTmOp xive_tm_operations[] = { 365 /* 366 * MMIOs below 2K : raw values and special operations without side 367 * effects 368 */ 369 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 370 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 371 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 372 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 373 374 /* MMIOs above 2K : special operations with side effects */ 375 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 376 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 377 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, 378 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, 379 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 380 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 381 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 382 }; 383 384 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 385 { 386 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 387 uint32_t op_offset = offset & 0xFFF; 388 int i; 389 390 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 391 const XiveTmOp *xto = &xive_tm_operations[i]; 392 393 /* Accesses done from a more privileged TIMA page is allowed */ 394 if (xto->page_offset >= page_offset && 395 xto->op_offset == op_offset && 396 xto->size == size && 397 ((write && xto->write_handler) || (!write && xto->read_handler))) { 398 return xto; 399 } 400 } 401 return NULL; 402 } 403 404 /* 405 * TIMA MMIO handlers 406 */ 407 void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 408 unsigned size) 409 { 410 const XiveTmOp *xto; 411 412 /* 413 * TODO: check V bit in Q[0-3]W2 414 */ 415 416 /* 417 * First, check for special operations in the 2K region 418 */ 419 if (offset & 0x800) { 420 xto = xive_tm_find_op(offset, size, true); 421 if (!xto) { 422 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 423 "@%"HWADDR_PRIx"\n", offset); 424 } else { 425 xto->write_handler(tctx, offset, value, size); 426 } 427 return; 428 } 429 430 /* 431 * Then, for special operations in the region below 2K. 432 */ 433 xto = xive_tm_find_op(offset, size, true); 434 if (xto) { 435 xto->write_handler(tctx, offset, value, size); 436 return; 437 } 438 439 /* 440 * Finish with raw access to the register values 441 */ 442 xive_tm_raw_write(tctx, offset, value, size); 443 } 444 445 uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 446 { 447 const XiveTmOp *xto; 448 449 /* 450 * TODO: check V bit in Q[0-3]W2 451 */ 452 453 /* 454 * First, check for special operations in the 2K region 455 */ 456 if (offset & 0x800) { 457 xto = xive_tm_find_op(offset, size, false); 458 if (!xto) { 459 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 460 "@%"HWADDR_PRIx"\n", offset); 461 return -1; 462 } 463 return xto->read_handler(tctx, offset, size); 464 } 465 466 /* 467 * Then, for special operations in the region below 2K. 468 */ 469 xto = xive_tm_find_op(offset, size, false); 470 if (xto) { 471 return xto->read_handler(tctx, offset, size); 472 } 473 474 /* 475 * Finish with raw access to the register values 476 */ 477 return xive_tm_raw_read(tctx, offset, size); 478 } 479 480 static void xive_tm_write(void *opaque, hwaddr offset, 481 uint64_t value, unsigned size) 482 { 483 XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); 484 485 xive_tctx_tm_write(tctx, offset, value, size); 486 } 487 488 static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) 489 { 490 XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); 491 492 return xive_tctx_tm_read(tctx, offset, size); 493 } 494 495 const MemoryRegionOps xive_tm_ops = { 496 .read = xive_tm_read, 497 .write = xive_tm_write, 498 .endianness = DEVICE_BIG_ENDIAN, 499 .valid = { 500 .min_access_size = 1, 501 .max_access_size = 8, 502 }, 503 .impl = { 504 .min_access_size = 1, 505 .max_access_size = 8, 506 }, 507 }; 508 509 static char *xive_tctx_ring_print(uint8_t *ring) 510 { 511 uint32_t w2 = xive_tctx_word2(ring); 512 513 return g_strdup_printf("%02x %02x %02x %02x %02x " 514 "%02x %02x %02x %08x", 515 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 516 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 517 be32_to_cpu(w2)); 518 } 519 520 static const char * const xive_tctx_ring_names[] = { 521 "USER", "OS", "POOL", "PHYS", 522 }; 523 524 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 525 { 526 int cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 527 int i; 528 529 if (kvm_irqchip_in_kernel()) { 530 Error *local_err = NULL; 531 532 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 533 if (local_err) { 534 error_report_err(local_err); 535 return; 536 } 537 } 538 539 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 540 " W2\n", cpu_index); 541 542 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 543 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 544 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 545 xive_tctx_ring_names[i], s); 546 g_free(s); 547 } 548 } 549 550 void xive_tctx_reset(XiveTCTX *tctx) 551 { 552 memset(tctx->regs, 0, sizeof(tctx->regs)); 553 554 /* Set some defaults */ 555 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 556 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 557 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 558 559 /* 560 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 561 * CPPR is first set. 562 */ 563 tctx->regs[TM_QW1_OS + TM_PIPR] = 564 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 565 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 566 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 567 } 568 569 static void xive_tctx_realize(DeviceState *dev, Error **errp) 570 { 571 XiveTCTX *tctx = XIVE_TCTX(dev); 572 PowerPCCPU *cpu; 573 CPUPPCState *env; 574 Object *obj; 575 Error *local_err = NULL; 576 577 obj = object_property_get_link(OBJECT(dev), "cpu", &local_err); 578 if (!obj) { 579 error_propagate(errp, local_err); 580 error_prepend(errp, "required link 'cpu' not found: "); 581 return; 582 } 583 584 cpu = POWERPC_CPU(obj); 585 tctx->cs = CPU(obj); 586 587 env = &cpu->env; 588 switch (PPC_INPUT(env)) { 589 case PPC_FLAGS_INPUT_POWER9: 590 tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT]; 591 tctx->os_output = env->irq_inputs[POWER9_INPUT_INT]; 592 break; 593 594 default: 595 error_setg(errp, "XIVE interrupt controller does not support " 596 "this CPU bus model"); 597 return; 598 } 599 600 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 601 if (kvm_irqchip_in_kernel()) { 602 kvmppc_xive_cpu_connect(tctx, &local_err); 603 if (local_err) { 604 error_propagate(errp, local_err); 605 return; 606 } 607 } 608 } 609 610 static int vmstate_xive_tctx_pre_save(void *opaque) 611 { 612 Error *local_err = NULL; 613 614 if (kvm_irqchip_in_kernel()) { 615 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque), &local_err); 616 if (local_err) { 617 error_report_err(local_err); 618 return -1; 619 } 620 } 621 622 return 0; 623 } 624 625 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 626 { 627 Error *local_err = NULL; 628 629 if (kvm_irqchip_in_kernel()) { 630 /* 631 * Required for hotplugged CPU, for which the state comes 632 * after all states of the machine. 633 */ 634 kvmppc_xive_cpu_set_state(XIVE_TCTX(opaque), &local_err); 635 if (local_err) { 636 error_report_err(local_err); 637 return -1; 638 } 639 } 640 641 return 0; 642 } 643 644 static const VMStateDescription vmstate_xive_tctx = { 645 .name = TYPE_XIVE_TCTX, 646 .version_id = 1, 647 .minimum_version_id = 1, 648 .pre_save = vmstate_xive_tctx_pre_save, 649 .post_load = vmstate_xive_tctx_post_load, 650 .fields = (VMStateField[]) { 651 VMSTATE_BUFFER(regs, XiveTCTX), 652 VMSTATE_END_OF_LIST() 653 }, 654 }; 655 656 static void xive_tctx_class_init(ObjectClass *klass, void *data) 657 { 658 DeviceClass *dc = DEVICE_CLASS(klass); 659 660 dc->desc = "XIVE Interrupt Thread Context"; 661 dc->realize = xive_tctx_realize; 662 dc->vmsd = &vmstate_xive_tctx; 663 /* 664 * Reason: part of XIVE interrupt controller, needs to be wired up 665 * by xive_tctx_create(). 666 */ 667 dc->user_creatable = false; 668 } 669 670 static const TypeInfo xive_tctx_info = { 671 .name = TYPE_XIVE_TCTX, 672 .parent = TYPE_DEVICE, 673 .instance_size = sizeof(XiveTCTX), 674 .class_init = xive_tctx_class_init, 675 }; 676 677 Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) 678 { 679 Error *local_err = NULL; 680 Object *obj; 681 682 obj = object_new(TYPE_XIVE_TCTX); 683 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); 684 object_unref(obj); 685 object_ref(cpu); 686 object_property_add_const_link(obj, "cpu", cpu, &error_abort); 687 object_property_set_bool(obj, true, "realized", &local_err); 688 if (local_err) { 689 goto error; 690 } 691 692 return obj; 693 694 error: 695 object_unparent(obj); 696 error_propagate(errp, local_err); 697 return NULL; 698 } 699 700 void xive_tctx_destroy(XiveTCTX *tctx) 701 { 702 Object *obj = OBJECT(tctx); 703 704 object_unref(object_property_get_link(obj, "cpu", &error_abort)); 705 object_unparent(obj); 706 } 707 708 /* 709 * XIVE ESB helpers 710 */ 711 712 static uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 713 { 714 uint8_t old_pq = *pq & 0x3; 715 716 *pq &= ~0x3; 717 *pq |= value & 0x3; 718 719 return old_pq; 720 } 721 722 static bool xive_esb_trigger(uint8_t *pq) 723 { 724 uint8_t old_pq = *pq & 0x3; 725 726 switch (old_pq) { 727 case XIVE_ESB_RESET: 728 xive_esb_set(pq, XIVE_ESB_PENDING); 729 return true; 730 case XIVE_ESB_PENDING: 731 case XIVE_ESB_QUEUED: 732 xive_esb_set(pq, XIVE_ESB_QUEUED); 733 return false; 734 case XIVE_ESB_OFF: 735 xive_esb_set(pq, XIVE_ESB_OFF); 736 return false; 737 default: 738 g_assert_not_reached(); 739 } 740 } 741 742 static bool xive_esb_eoi(uint8_t *pq) 743 { 744 uint8_t old_pq = *pq & 0x3; 745 746 switch (old_pq) { 747 case XIVE_ESB_RESET: 748 case XIVE_ESB_PENDING: 749 xive_esb_set(pq, XIVE_ESB_RESET); 750 return false; 751 case XIVE_ESB_QUEUED: 752 xive_esb_set(pq, XIVE_ESB_PENDING); 753 return true; 754 case XIVE_ESB_OFF: 755 xive_esb_set(pq, XIVE_ESB_OFF); 756 return false; 757 default: 758 g_assert_not_reached(); 759 } 760 } 761 762 /* 763 * XIVE Interrupt Source (or IVSE) 764 */ 765 766 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 767 { 768 assert(srcno < xsrc->nr_irqs); 769 770 return xsrc->status[srcno] & 0x3; 771 } 772 773 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 774 { 775 assert(srcno < xsrc->nr_irqs); 776 777 return xive_esb_set(&xsrc->status[srcno], pq); 778 } 779 780 /* 781 * Returns whether the event notification should be forwarded. 782 */ 783 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 784 { 785 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 786 787 xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; 788 789 switch (old_pq) { 790 case XIVE_ESB_RESET: 791 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 792 return true; 793 default: 794 return false; 795 } 796 } 797 798 /* 799 * Returns whether the event notification should be forwarded. 800 */ 801 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 802 { 803 bool ret; 804 805 assert(srcno < xsrc->nr_irqs); 806 807 ret = xive_esb_trigger(&xsrc->status[srcno]); 808 809 if (xive_source_irq_is_lsi(xsrc, srcno) && 810 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 811 qemu_log_mask(LOG_GUEST_ERROR, 812 "XIVE: queued an event on LSI IRQ %d\n", srcno); 813 } 814 815 return ret; 816 } 817 818 /* 819 * Returns whether the event notification should be forwarded. 820 */ 821 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 822 { 823 bool ret; 824 825 assert(srcno < xsrc->nr_irqs); 826 827 ret = xive_esb_eoi(&xsrc->status[srcno]); 828 829 /* 830 * LSI sources do not set the Q bit but they can still be 831 * asserted, in which case we should forward a new event 832 * notification 833 */ 834 if (xive_source_irq_is_lsi(xsrc, srcno) && 835 xsrc->status[srcno] & XIVE_STATUS_ASSERTED) { 836 ret = xive_source_lsi_trigger(xsrc, srcno); 837 } 838 839 return ret; 840 } 841 842 /* 843 * Forward the source event notification to the Router 844 */ 845 static void xive_source_notify(XiveSource *xsrc, int srcno) 846 { 847 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 848 849 if (xnc->notify) { 850 xnc->notify(xsrc->xive, srcno); 851 } 852 } 853 854 /* 855 * In a two pages ESB MMIO setting, even page is the trigger page, odd 856 * page is for management 857 */ 858 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 859 { 860 return !((addr >> shift) & 1); 861 } 862 863 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 864 { 865 return xive_source_esb_has_2page(xsrc) && 866 addr_is_even(addr, xsrc->esb_shift - 1); 867 } 868 869 /* 870 * ESB MMIO loads 871 * Trigger page Management/EOI page 872 * 873 * ESB MMIO setting 2 pages 1 or 2 pages 874 * 875 * 0x000 .. 0x3FF -1 EOI and return 0|1 876 * 0x400 .. 0x7FF -1 EOI and return 0|1 877 * 0x800 .. 0xBFF -1 return PQ 878 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 879 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 880 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 881 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 882 */ 883 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 884 { 885 XiveSource *xsrc = XIVE_SOURCE(opaque); 886 uint32_t offset = addr & 0xFFF; 887 uint32_t srcno = addr >> xsrc->esb_shift; 888 uint64_t ret = -1; 889 890 /* In a two pages ESB MMIO setting, trigger page should not be read */ 891 if (xive_source_is_trigger_page(xsrc, addr)) { 892 qemu_log_mask(LOG_GUEST_ERROR, 893 "XIVE: invalid load on IRQ %d trigger page at " 894 "0x%"HWADDR_PRIx"\n", srcno, addr); 895 return -1; 896 } 897 898 switch (offset) { 899 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 900 ret = xive_source_esb_eoi(xsrc, srcno); 901 902 /* Forward the source event notification for routing */ 903 if (ret) { 904 xive_source_notify(xsrc, srcno); 905 } 906 break; 907 908 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 909 ret = xive_source_esb_get(xsrc, srcno); 910 break; 911 912 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 913 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 914 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 915 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 916 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 917 break; 918 default: 919 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 920 offset); 921 } 922 923 return ret; 924 } 925 926 /* 927 * ESB MMIO stores 928 * Trigger page Management/EOI page 929 * 930 * ESB MMIO setting 2 pages 1 or 2 pages 931 * 932 * 0x000 .. 0x3FF Trigger Trigger 933 * 0x400 .. 0x7FF Trigger EOI 934 * 0x800 .. 0xBFF Trigger undefined 935 * 0xC00 .. 0xCFF Trigger PQ=00 936 * 0xD00 .. 0xDFF Trigger PQ=01 937 * 0xE00 .. 0xDFF Trigger PQ=10 938 * 0xF00 .. 0xDFF Trigger PQ=11 939 */ 940 static void xive_source_esb_write(void *opaque, hwaddr addr, 941 uint64_t value, unsigned size) 942 { 943 XiveSource *xsrc = XIVE_SOURCE(opaque); 944 uint32_t offset = addr & 0xFFF; 945 uint32_t srcno = addr >> xsrc->esb_shift; 946 bool notify = false; 947 948 /* In a two pages ESB MMIO setting, trigger page only triggers */ 949 if (xive_source_is_trigger_page(xsrc, addr)) { 950 notify = xive_source_esb_trigger(xsrc, srcno); 951 goto out; 952 } 953 954 switch (offset) { 955 case 0 ... 0x3FF: 956 notify = xive_source_esb_trigger(xsrc, srcno); 957 break; 958 959 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 960 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 961 qemu_log_mask(LOG_GUEST_ERROR, 962 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 963 return; 964 } 965 966 notify = xive_source_esb_eoi(xsrc, srcno); 967 break; 968 969 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 970 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 971 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 972 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 973 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 974 break; 975 976 default: 977 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 978 offset); 979 return; 980 } 981 982 out: 983 /* Forward the source event notification for routing */ 984 if (notify) { 985 xive_source_notify(xsrc, srcno); 986 } 987 } 988 989 static const MemoryRegionOps xive_source_esb_ops = { 990 .read = xive_source_esb_read, 991 .write = xive_source_esb_write, 992 .endianness = DEVICE_BIG_ENDIAN, 993 .valid = { 994 .min_access_size = 8, 995 .max_access_size = 8, 996 }, 997 .impl = { 998 .min_access_size = 8, 999 .max_access_size = 8, 1000 }, 1001 }; 1002 1003 void xive_source_set_irq(void *opaque, int srcno, int val) 1004 { 1005 XiveSource *xsrc = XIVE_SOURCE(opaque); 1006 bool notify = false; 1007 1008 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1009 if (val) { 1010 notify = xive_source_lsi_trigger(xsrc, srcno); 1011 } else { 1012 xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; 1013 } 1014 } else { 1015 if (val) { 1016 notify = xive_source_esb_trigger(xsrc, srcno); 1017 } 1018 } 1019 1020 /* Forward the source event notification for routing */ 1021 if (notify) { 1022 xive_source_notify(xsrc, srcno); 1023 } 1024 } 1025 1026 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 1027 { 1028 int i; 1029 1030 for (i = 0; i < xsrc->nr_irqs; i++) { 1031 uint8_t pq = xive_source_esb_get(xsrc, i); 1032 1033 if (pq == XIVE_ESB_OFF) { 1034 continue; 1035 } 1036 1037 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 1038 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1039 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1040 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1041 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' '); 1042 } 1043 } 1044 1045 static void xive_source_reset(void *dev) 1046 { 1047 XiveSource *xsrc = XIVE_SOURCE(dev); 1048 1049 /* Do not clear the LSI bitmap */ 1050 1051 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 1052 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 1053 } 1054 1055 static void xive_source_realize(DeviceState *dev, Error **errp) 1056 { 1057 XiveSource *xsrc = XIVE_SOURCE(dev); 1058 Object *obj; 1059 Error *local_err = NULL; 1060 1061 obj = object_property_get_link(OBJECT(dev), "xive", &local_err); 1062 if (!obj) { 1063 error_propagate(errp, local_err); 1064 error_prepend(errp, "required link 'xive' not found: "); 1065 return; 1066 } 1067 1068 xsrc->xive = XIVE_NOTIFIER(obj); 1069 1070 if (!xsrc->nr_irqs) { 1071 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1072 return; 1073 } 1074 1075 if (xsrc->esb_shift != XIVE_ESB_4K && 1076 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1077 xsrc->esb_shift != XIVE_ESB_64K && 1078 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1079 error_setg(errp, "Invalid ESB shift setting"); 1080 return; 1081 } 1082 1083 xsrc->status = g_malloc0(xsrc->nr_irqs); 1084 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1085 1086 if (!kvm_irqchip_in_kernel()) { 1087 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1088 &xive_source_esb_ops, xsrc, "xive.esb", 1089 (1ull << xsrc->esb_shift) * xsrc->nr_irqs); 1090 } 1091 1092 qemu_register_reset(xive_source_reset, dev); 1093 } 1094 1095 static const VMStateDescription vmstate_xive_source = { 1096 .name = TYPE_XIVE_SOURCE, 1097 .version_id = 1, 1098 .minimum_version_id = 1, 1099 .fields = (VMStateField[]) { 1100 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1101 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1102 VMSTATE_END_OF_LIST() 1103 }, 1104 }; 1105 1106 /* 1107 * The default XIVE interrupt source setting for the ESB MMIOs is two 1108 * 64k pages without Store EOI, to be in sync with KVM. 1109 */ 1110 static Property xive_source_properties[] = { 1111 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1112 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1113 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1114 DEFINE_PROP_END_OF_LIST(), 1115 }; 1116 1117 static void xive_source_class_init(ObjectClass *klass, void *data) 1118 { 1119 DeviceClass *dc = DEVICE_CLASS(klass); 1120 1121 dc->desc = "XIVE Interrupt Source"; 1122 dc->props = xive_source_properties; 1123 dc->realize = xive_source_realize; 1124 dc->vmsd = &vmstate_xive_source; 1125 /* 1126 * Reason: part of XIVE interrupt controller, needs to be wired up, 1127 * e.g. by spapr_xive_instance_init(). 1128 */ 1129 dc->user_creatable = false; 1130 } 1131 1132 static const TypeInfo xive_source_info = { 1133 .name = TYPE_XIVE_SOURCE, 1134 .parent = TYPE_DEVICE, 1135 .instance_size = sizeof(XiveSource), 1136 .class_init = xive_source_class_init, 1137 }; 1138 1139 /* 1140 * XiveEND helpers 1141 */ 1142 1143 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1144 { 1145 uint64_t qaddr_base = xive_end_qaddr(end); 1146 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1147 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1148 uint32_t qentries = 1 << (qsize + 10); 1149 int i; 1150 1151 /* 1152 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1153 */ 1154 monitor_printf(mon, " [ "); 1155 qindex = (qindex - (width - 1)) & (qentries - 1); 1156 for (i = 0; i < width; i++) { 1157 uint64_t qaddr = qaddr_base + (qindex << 2); 1158 uint32_t qdata = -1; 1159 1160 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 1161 sizeof(qdata))) { 1162 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1163 HWADDR_PRIx "\n", qaddr); 1164 return; 1165 } 1166 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1167 be32_to_cpu(qdata)); 1168 qindex = (qindex + 1) & (qentries - 1); 1169 } 1170 monitor_printf(mon, "]"); 1171 } 1172 1173 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1174 { 1175 uint64_t qaddr_base = xive_end_qaddr(end); 1176 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1177 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1178 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1179 uint32_t qentries = 1 << (qsize + 10); 1180 1181 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1182 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1183 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1184 uint8_t pq; 1185 1186 if (!xive_end_is_valid(end)) { 1187 return; 1188 } 1189 1190 pq = xive_get_field32(END_W1_ESn, end->w1); 1191 1192 monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1193 end_idx, 1194 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1195 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1196 xive_end_is_valid(end) ? 'v' : '-', 1197 xive_end_is_enqueue(end) ? 'q' : '-', 1198 xive_end_is_notify(end) ? 'n' : '-', 1199 xive_end_is_backlog(end) ? 'b' : '-', 1200 xive_end_is_escalate(end) ? 'e' : '-', 1201 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1202 xive_end_is_silent_escalation(end) ? 's' : '-', 1203 priority, nvt_blk, nvt_idx); 1204 1205 if (qaddr_base) { 1206 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1207 qaddr_base, qindex, qentries, qgen); 1208 xive_end_queue_pic_print_info(end, 6, mon); 1209 } 1210 monitor_printf(mon, "\n"); 1211 } 1212 1213 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1214 { 1215 uint64_t qaddr_base = xive_end_qaddr(end); 1216 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1217 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1218 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1219 1220 uint64_t qaddr = qaddr_base + (qindex << 2); 1221 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1222 uint32_t qentries = 1 << (qsize + 10); 1223 1224 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) { 1225 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1226 HWADDR_PRIx "\n", qaddr); 1227 return; 1228 } 1229 1230 qindex = (qindex + 1) & (qentries - 1); 1231 if (qindex == 0) { 1232 qgen ^= 1; 1233 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1234 } 1235 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1236 } 1237 1238 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, 1239 Monitor *mon) 1240 { 1241 XiveEAS *eas = (XiveEAS *) &end->w4; 1242 uint8_t pq; 1243 1244 if (!xive_end_is_escalate(end)) { 1245 return; 1246 } 1247 1248 pq = xive_get_field32(END_W1_ESe, end->w1); 1249 1250 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1251 end_idx, 1252 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1253 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1254 xive_eas_is_valid(eas) ? 'V' : ' ', 1255 xive_eas_is_masked(eas) ? 'M' : ' ', 1256 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1257 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1258 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1259 } 1260 1261 /* 1262 * XIVE Router (aka. Virtualization Controller or IVRE) 1263 */ 1264 1265 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1266 XiveEAS *eas) 1267 { 1268 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1269 1270 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1271 } 1272 1273 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1274 XiveEND *end) 1275 { 1276 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1277 1278 return xrc->get_end(xrtr, end_blk, end_idx, end); 1279 } 1280 1281 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1282 XiveEND *end, uint8_t word_number) 1283 { 1284 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1285 1286 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1287 } 1288 1289 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1290 XiveNVT *nvt) 1291 { 1292 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1293 1294 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1295 } 1296 1297 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1298 XiveNVT *nvt, uint8_t word_number) 1299 { 1300 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1301 1302 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1303 } 1304 1305 XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) 1306 { 1307 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1308 1309 return xrc->get_tctx(xrtr, cs); 1310 } 1311 1312 /* 1313 * Encode the HW CAM line in the block group mode format : 1314 * 1315 * chip << 19 | 0000000 0 0001 thread (7Bit) 1316 */ 1317 static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) 1318 { 1319 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1320 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1321 1322 return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f)); 1323 } 1324 1325 /* 1326 * The thread context register words are in big-endian format. 1327 */ 1328 static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format, 1329 uint8_t nvt_blk, uint32_t nvt_idx, 1330 bool cam_ignore, uint32_t logic_serv) 1331 { 1332 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1333 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1334 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1335 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1336 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1337 1338 /* 1339 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1340 * identifier are ignored in the "CAM" match. 1341 */ 1342 1343 if (format == 0) { 1344 if (cam_ignore == true) { 1345 /* 1346 * F=0 & i=1: Logical server notification (bits ignored at 1347 * the end of the NVT identifier) 1348 */ 1349 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1350 nvt_blk, nvt_idx); 1351 return -1; 1352 } 1353 1354 /* F=0 & i=0: Specific NVT notification */ 1355 1356 /* PHYS ring */ 1357 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1358 cam == xive_tctx_hw_cam_line(tctx)) { 1359 return TM_QW3_HV_PHYS; 1360 } 1361 1362 /* HV POOL ring */ 1363 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1364 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1365 return TM_QW2_HV_POOL; 1366 } 1367 1368 /* OS ring */ 1369 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1370 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1371 return TM_QW1_OS; 1372 } 1373 } else { 1374 /* F=1 : User level Event-Based Branch (EBB) notification */ 1375 1376 /* USER ring */ 1377 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1378 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1379 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1380 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1381 return TM_QW0_USER; 1382 } 1383 } 1384 return -1; 1385 } 1386 1387 typedef struct XiveTCTXMatch { 1388 XiveTCTX *tctx; 1389 uint8_t ring; 1390 } XiveTCTXMatch; 1391 1392 static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, 1393 uint8_t nvt_blk, uint32_t nvt_idx, 1394 bool cam_ignore, uint8_t priority, 1395 uint32_t logic_serv, XiveTCTXMatch *match) 1396 { 1397 CPUState *cs; 1398 1399 /* 1400 * TODO (PowerNV): handle chip_id overwrite of block field for 1401 * hardwired CAM compares 1402 */ 1403 1404 CPU_FOREACH(cs) { 1405 XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs); 1406 int ring; 1407 1408 /* 1409 * Skip partially initialized vCPUs. This can happen when 1410 * vCPUs are hotplugged. 1411 */ 1412 if (!tctx) { 1413 continue; 1414 } 1415 1416 /* 1417 * HW checks that the CPU is enabled in the Physical Thread 1418 * Enable Register (PTER). 1419 */ 1420 1421 /* 1422 * Check the thread context CAM lines and record matches. We 1423 * will handle CPU exception delivery later 1424 */ 1425 ring = xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx, 1426 cam_ignore, logic_serv); 1427 /* 1428 * Save the context and follow on to catch duplicates, that we 1429 * don't support yet. 1430 */ 1431 if (ring != -1) { 1432 if (match->tctx) { 1433 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread " 1434 "context NVT %x/%x\n", nvt_blk, nvt_idx); 1435 return false; 1436 } 1437 1438 match->ring = ring; 1439 match->tctx = tctx; 1440 } 1441 } 1442 1443 if (!match->tctx) { 1444 qemu_log_mask(LOG_UNIMP, "XIVE: NVT %x/%x is not dispatched\n", 1445 nvt_blk, nvt_idx); 1446 return false; 1447 } 1448 1449 return true; 1450 } 1451 1452 /* 1453 * This is our simple Xive Presenter Engine model. It is merged in the 1454 * Router as it does not require an extra object. 1455 * 1456 * It receives notification requests sent by the IVRE to find one 1457 * matching NVT (or more) dispatched on the processor threads. In case 1458 * of a single NVT notification, the process is abreviated and the 1459 * thread is signaled if a match is found. In case of a logical server 1460 * notification (bits ignored at the end of the NVT identifier), the 1461 * IVPE and IVRE select a winning thread using different filters. This 1462 * involves 2 or 3 exchanges on the PowerBus that the model does not 1463 * support. 1464 * 1465 * The parameters represent what is sent on the PowerBus 1466 */ 1467 static bool xive_presenter_notify(XiveRouter *xrtr, uint8_t format, 1468 uint8_t nvt_blk, uint32_t nvt_idx, 1469 bool cam_ignore, uint8_t priority, 1470 uint32_t logic_serv) 1471 { 1472 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1473 bool found; 1474 1475 found = xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ignore, 1476 priority, logic_serv, &match); 1477 if (found) { 1478 ipb_update(&match.tctx->regs[match.ring], priority); 1479 xive_tctx_notify(match.tctx, match.ring); 1480 } 1481 1482 return found; 1483 } 1484 1485 /* 1486 * Notification using the END ESe/ESn bit (Event State Buffer for 1487 * escalation and notification). Profide futher coalescing in the 1488 * Router. 1489 */ 1490 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1491 uint32_t end_idx, XiveEND *end, 1492 uint32_t end_esmask) 1493 { 1494 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1495 bool notify = xive_esb_trigger(&pq); 1496 1497 if (pq != xive_get_field32(end_esmask, end->w1)) { 1498 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1499 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1500 } 1501 1502 /* ESe/n[Q]=1 : end of notification */ 1503 return notify; 1504 } 1505 1506 /* 1507 * An END trigger can come from an event trigger (IPI or HW) or from 1508 * another chip. We don't model the PowerBus but the END trigger 1509 * message has the same parameters than in the function below. 1510 */ 1511 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1512 uint32_t end_idx, uint32_t end_data) 1513 { 1514 XiveEND end; 1515 uint8_t priority; 1516 uint8_t format; 1517 uint8_t nvt_blk; 1518 uint32_t nvt_idx; 1519 XiveNVT nvt; 1520 bool found; 1521 1522 /* END cache lookup */ 1523 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1524 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1525 end_idx); 1526 return; 1527 } 1528 1529 if (!xive_end_is_valid(&end)) { 1530 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1531 end_blk, end_idx); 1532 return; 1533 } 1534 1535 if (xive_end_is_enqueue(&end)) { 1536 xive_end_enqueue(&end, end_data); 1537 /* Enqueuing event data modifies the EQ toggle and index */ 1538 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1539 } 1540 1541 /* 1542 * When the END is silent, we skip the notification part. 1543 */ 1544 if (xive_end_is_silent_escalation(&end)) { 1545 goto do_escalation; 1546 } 1547 1548 /* 1549 * The W7 format depends on the F bit in W6. It defines the type 1550 * of the notification : 1551 * 1552 * F=0 : single or multiple NVT notification 1553 * F=1 : User level Event-Based Branch (EBB) notification, no 1554 * priority 1555 */ 1556 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1557 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1558 1559 /* The END is masked */ 1560 if (format == 0 && priority == 0xff) { 1561 return; 1562 } 1563 1564 /* 1565 * Check the END ESn (Event State Buffer for notification) for 1566 * even futher coalescing in the Router 1567 */ 1568 if (!xive_end_is_notify(&end)) { 1569 /* ESn[Q]=1 : end of notification */ 1570 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1571 &end, END_W1_ESn)) { 1572 return; 1573 } 1574 } 1575 1576 /* 1577 * Follows IVPE notification 1578 */ 1579 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1580 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1581 1582 /* NVT cache lookup */ 1583 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1584 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1585 nvt_blk, nvt_idx); 1586 return; 1587 } 1588 1589 if (!xive_nvt_is_valid(&nvt)) { 1590 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1591 nvt_blk, nvt_idx); 1592 return; 1593 } 1594 1595 found = xive_presenter_notify(xrtr, format, nvt_blk, nvt_idx, 1596 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1597 priority, 1598 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1599 1600 /* TODO: Auto EOI. */ 1601 1602 if (found) { 1603 return; 1604 } 1605 1606 /* 1607 * If no matching NVT is dispatched on a HW thread : 1608 * - specific VP: update the NVT structure if backlog is activated 1609 * - logical server : forward request to IVPE (not supported) 1610 */ 1611 if (xive_end_is_backlog(&end)) { 1612 if (format == 1) { 1613 qemu_log_mask(LOG_GUEST_ERROR, 1614 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1615 end_blk, end_idx); 1616 return; 1617 } 1618 /* Record the IPB in the associated NVT structure */ 1619 ipb_update((uint8_t *) &nvt.w4, priority); 1620 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1621 1622 /* 1623 * On HW, follows a "Broadcast Backlog" to IVPEs 1624 */ 1625 } 1626 1627 do_escalation: 1628 /* 1629 * If activated, escalate notification using the ESe PQ bits and 1630 * the EAS in w4-5 1631 */ 1632 if (!xive_end_is_escalate(&end)) { 1633 return; 1634 } 1635 1636 /* 1637 * Check the END ESe (Event State Buffer for escalation) for even 1638 * futher coalescing in the Router 1639 */ 1640 if (!xive_end_is_uncond_escalation(&end)) { 1641 /* ESe[Q]=1 : end of notification */ 1642 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1643 &end, END_W1_ESe)) { 1644 return; 1645 } 1646 } 1647 1648 /* 1649 * The END trigger becomes an Escalation trigger 1650 */ 1651 xive_router_end_notify(xrtr, 1652 xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1653 xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1654 xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1655 } 1656 1657 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 1658 { 1659 XiveRouter *xrtr = XIVE_ROUTER(xn); 1660 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1661 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1662 XiveEAS eas; 1663 1664 /* EAS cache lookup */ 1665 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1666 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1667 return; 1668 } 1669 1670 /* 1671 * The IVRE checks the State Bit Cache at this point. We skip the 1672 * SBC lookup because the state bits of the sources are modeled 1673 * internally in QEMU. 1674 */ 1675 1676 if (!xive_eas_is_valid(&eas)) { 1677 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1678 return; 1679 } 1680 1681 if (xive_eas_is_masked(&eas)) { 1682 /* Notification completed */ 1683 return; 1684 } 1685 1686 /* 1687 * The event trigger becomes an END trigger 1688 */ 1689 xive_router_end_notify(xrtr, 1690 xive_get_field64(EAS_END_BLOCK, eas.w), 1691 xive_get_field64(EAS_END_INDEX, eas.w), 1692 xive_get_field64(EAS_END_DATA, eas.w)); 1693 } 1694 1695 static void xive_router_class_init(ObjectClass *klass, void *data) 1696 { 1697 DeviceClass *dc = DEVICE_CLASS(klass); 1698 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1699 1700 dc->desc = "XIVE Router Engine"; 1701 xnc->notify = xive_router_notify; 1702 } 1703 1704 static const TypeInfo xive_router_info = { 1705 .name = TYPE_XIVE_ROUTER, 1706 .parent = TYPE_SYS_BUS_DEVICE, 1707 .abstract = true, 1708 .class_size = sizeof(XiveRouterClass), 1709 .class_init = xive_router_class_init, 1710 .interfaces = (InterfaceInfo[]) { 1711 { TYPE_XIVE_NOTIFIER }, 1712 { } 1713 } 1714 }; 1715 1716 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1717 { 1718 if (!xive_eas_is_valid(eas)) { 1719 return; 1720 } 1721 1722 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1723 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1724 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1725 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1726 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1727 } 1728 1729 /* 1730 * END ESB MMIO loads 1731 */ 1732 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1733 { 1734 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1735 uint32_t offset = addr & 0xFFF; 1736 uint8_t end_blk; 1737 uint32_t end_idx; 1738 XiveEND end; 1739 uint32_t end_esmask; 1740 uint8_t pq; 1741 uint64_t ret = -1; 1742 1743 end_blk = xsrc->block_id; 1744 end_idx = addr >> (xsrc->esb_shift + 1); 1745 1746 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1747 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1748 end_idx); 1749 return -1; 1750 } 1751 1752 if (!xive_end_is_valid(&end)) { 1753 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1754 end_blk, end_idx); 1755 return -1; 1756 } 1757 1758 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1759 pq = xive_get_field32(end_esmask, end.w1); 1760 1761 switch (offset) { 1762 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1763 ret = xive_esb_eoi(&pq); 1764 1765 /* Forward the source event notification for routing ?? */ 1766 break; 1767 1768 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1769 ret = pq; 1770 break; 1771 1772 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1773 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1774 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1775 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1776 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1777 break; 1778 default: 1779 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1780 offset); 1781 return -1; 1782 } 1783 1784 if (pq != xive_get_field32(end_esmask, end.w1)) { 1785 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1786 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1787 } 1788 1789 return ret; 1790 } 1791 1792 /* 1793 * END ESB MMIO stores are invalid 1794 */ 1795 static void xive_end_source_write(void *opaque, hwaddr addr, 1796 uint64_t value, unsigned size) 1797 { 1798 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1799 HWADDR_PRIx"\n", addr); 1800 } 1801 1802 static const MemoryRegionOps xive_end_source_ops = { 1803 .read = xive_end_source_read, 1804 .write = xive_end_source_write, 1805 .endianness = DEVICE_BIG_ENDIAN, 1806 .valid = { 1807 .min_access_size = 8, 1808 .max_access_size = 8, 1809 }, 1810 .impl = { 1811 .min_access_size = 8, 1812 .max_access_size = 8, 1813 }, 1814 }; 1815 1816 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1817 { 1818 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1819 Object *obj; 1820 Error *local_err = NULL; 1821 1822 obj = object_property_get_link(OBJECT(dev), "xive", &local_err); 1823 if (!obj) { 1824 error_propagate(errp, local_err); 1825 error_prepend(errp, "required link 'xive' not found: "); 1826 return; 1827 } 1828 1829 xsrc->xrtr = XIVE_ROUTER(obj); 1830 1831 if (!xsrc->nr_ends) { 1832 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1833 return; 1834 } 1835 1836 if (xsrc->esb_shift != XIVE_ESB_4K && 1837 xsrc->esb_shift != XIVE_ESB_64K) { 1838 error_setg(errp, "Invalid ESB shift setting"); 1839 return; 1840 } 1841 1842 /* 1843 * Each END is assigned an even/odd pair of MMIO pages, the even page 1844 * manages the ESn field while the odd page manages the ESe field. 1845 */ 1846 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1847 &xive_end_source_ops, xsrc, "xive.end", 1848 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1849 } 1850 1851 static Property xive_end_source_properties[] = { 1852 DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0), 1853 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1854 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1855 DEFINE_PROP_END_OF_LIST(), 1856 }; 1857 1858 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1859 { 1860 DeviceClass *dc = DEVICE_CLASS(klass); 1861 1862 dc->desc = "XIVE END Source"; 1863 dc->props = xive_end_source_properties; 1864 dc->realize = xive_end_source_realize; 1865 /* 1866 * Reason: part of XIVE interrupt controller, needs to be wired up, 1867 * e.g. by spapr_xive_instance_init(). 1868 */ 1869 dc->user_creatable = false; 1870 } 1871 1872 static const TypeInfo xive_end_source_info = { 1873 .name = TYPE_XIVE_END_SOURCE, 1874 .parent = TYPE_DEVICE, 1875 .instance_size = sizeof(XiveENDSource), 1876 .class_init = xive_end_source_class_init, 1877 }; 1878 1879 /* 1880 * XIVE Notifier 1881 */ 1882 static const TypeInfo xive_notifier_info = { 1883 .name = TYPE_XIVE_NOTIFIER, 1884 .parent = TYPE_INTERFACE, 1885 .class_size = sizeof(XiveNotifierClass), 1886 }; 1887 1888 static void xive_register_types(void) 1889 { 1890 type_register_static(&xive_source_info); 1891 type_register_static(&xive_notifier_info); 1892 type_register_static(&xive_router_info); 1893 type_register_static(&xive_end_source_info); 1894 type_register_static(&xive_tctx_info); 1895 } 1896 1897 type_init(xive_register_types) 1898