1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "monitor/monitor.h" 21 #include "hw/irq.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive_regs.h" 24 25 /* 26 * XIVE Thread Interrupt Management context 27 */ 28 29 /* 30 * Convert a priority number to an Interrupt Pending Buffer (IPB) 31 * register, which indicates a pending interrupt at the priority 32 * corresponding to the bit number 33 */ 34 static uint8_t priority_to_ipb(uint8_t priority) 35 { 36 return priority > XIVE_PRIORITY_MAX ? 37 0 : 1 << (XIVE_PRIORITY_MAX - priority); 38 } 39 40 /* 41 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 42 * Interrupt Priority Register (PIPR), which contains the priority of 43 * the most favored pending notification. 44 */ 45 static uint8_t ipb_to_pipr(uint8_t ibp) 46 { 47 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 48 } 49 50 static uint8_t exception_mask(uint8_t ring) 51 { 52 switch (ring) { 53 case TM_QW1_OS: 54 return TM_QW1_NSR_EO; 55 case TM_QW3_HV_PHYS: 56 return TM_QW3_NSR_HE; 57 default: 58 g_assert_not_reached(); 59 } 60 } 61 62 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 63 { 64 switch (ring) { 65 case TM_QW0_USER: 66 return 0; /* Not supported */ 67 case TM_QW1_OS: 68 return tctx->os_output; 69 case TM_QW2_HV_POOL: 70 case TM_QW3_HV_PHYS: 71 return tctx->hv_output; 72 default: 73 return 0; 74 } 75 } 76 77 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 78 { 79 uint8_t *regs = &tctx->regs[ring]; 80 uint8_t nsr = regs[TM_NSR]; 81 uint8_t mask = exception_mask(ring); 82 83 qemu_irq_lower(xive_tctx_output(tctx, ring)); 84 85 if (regs[TM_NSR] & mask) { 86 uint8_t cppr = regs[TM_PIPR]; 87 88 regs[TM_CPPR] = cppr; 89 90 /* Reset the pending buffer bit */ 91 regs[TM_IPB] &= ~priority_to_ipb(cppr); 92 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 93 94 /* Drop Exception bit */ 95 regs[TM_NSR] &= ~mask; 96 } 97 98 return (nsr << 8) | regs[TM_CPPR]; 99 } 100 101 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 102 { 103 uint8_t *regs = &tctx->regs[ring]; 104 105 if (regs[TM_PIPR] < regs[TM_CPPR]) { 106 switch (ring) { 107 case TM_QW1_OS: 108 regs[TM_NSR] |= TM_QW1_NSR_EO; 109 break; 110 case TM_QW3_HV_PHYS: 111 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 112 break; 113 default: 114 g_assert_not_reached(); 115 } 116 qemu_irq_raise(xive_tctx_output(tctx, ring)); 117 } 118 } 119 120 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 121 { 122 if (cppr > XIVE_PRIORITY_MAX) { 123 cppr = 0xff; 124 } 125 126 tctx->regs[ring + TM_CPPR] = cppr; 127 128 /* CPPR has changed, check if we need to raise a pending exception */ 129 xive_tctx_notify(tctx, ring); 130 } 131 132 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) 133 { 134 uint8_t *regs = &tctx->regs[ring]; 135 136 regs[TM_IPB] |= ipb; 137 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 138 xive_tctx_notify(tctx, ring); 139 } 140 141 static inline uint32_t xive_tctx_word2(uint8_t *ring) 142 { 143 return *((uint32_t *) &ring[TM_WORD2]); 144 } 145 146 /* 147 * XIVE Thread Interrupt Management Area (TIMA) 148 */ 149 150 static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 151 hwaddr offset, uint64_t value, unsigned size) 152 { 153 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 154 } 155 156 static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx, 157 hwaddr offset, unsigned size) 158 { 159 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 160 } 161 162 static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 163 hwaddr offset, unsigned size) 164 { 165 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 166 uint32_t qw2w2; 167 168 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 169 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 170 return qw2w2; 171 } 172 173 static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 174 uint64_t value, unsigned size) 175 { 176 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 177 } 178 179 static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, 180 hwaddr offset, unsigned size) 181 { 182 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 183 } 184 185 /* 186 * Define an access map for each page of the TIMA that we will use in 187 * the memory region ops to filter values when doing loads and stores 188 * of raw registers values 189 * 190 * Registers accessibility bits : 191 * 192 * 0x0 - no access 193 * 0x1 - write only 194 * 0x2 - read only 195 * 0x3 - read/write 196 */ 197 198 static const uint8_t xive_tm_hw_view[] = { 199 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 200 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 201 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 202 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 203 }; 204 205 static const uint8_t xive_tm_hv_view[] = { 206 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 207 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 208 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 209 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 210 }; 211 212 static const uint8_t xive_tm_os_view[] = { 213 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 214 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 215 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 217 }; 218 219 static const uint8_t xive_tm_user_view[] = { 220 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 223 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 224 }; 225 226 /* 227 * Overall TIMA access map for the thread interrupt management context 228 * registers 229 */ 230 static const uint8_t *xive_tm_views[] = { 231 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 232 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 233 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 234 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 235 }; 236 237 /* 238 * Computes a register access mask for a given offset in the TIMA 239 */ 240 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 241 { 242 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 243 uint8_t reg_offset = offset & 0x3F; 244 uint8_t reg_mask = write ? 0x1 : 0x2; 245 uint64_t mask = 0x0; 246 int i; 247 248 for (i = 0; i < size; i++) { 249 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 250 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 251 } 252 } 253 254 return mask; 255 } 256 257 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 258 unsigned size) 259 { 260 uint8_t ring_offset = offset & 0x30; 261 uint8_t reg_offset = offset & 0x3F; 262 uint64_t mask = xive_tm_mask(offset, size, true); 263 int i; 264 265 /* 266 * Only 4 or 8 bytes stores are allowed and the User ring is 267 * excluded 268 */ 269 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 270 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 271 HWADDR_PRIx"\n", offset); 272 return; 273 } 274 275 /* 276 * Use the register offset for the raw values and filter out 277 * reserved values 278 */ 279 for (i = 0; i < size; i++) { 280 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 281 if (byte_mask) { 282 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 283 byte_mask; 284 } 285 } 286 } 287 288 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 289 { 290 uint8_t ring_offset = offset & 0x30; 291 uint8_t reg_offset = offset & 0x3F; 292 uint64_t mask = xive_tm_mask(offset, size, false); 293 uint64_t ret; 294 int i; 295 296 /* 297 * Only 4 or 8 bytes loads are allowed and the User ring is 298 * excluded 299 */ 300 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 301 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 302 HWADDR_PRIx"\n", offset); 303 return -1; 304 } 305 306 /* Use the register offset for the raw values */ 307 ret = 0; 308 for (i = 0; i < size; i++) { 309 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 310 } 311 312 /* filter out reserved values */ 313 return ret & mask; 314 } 315 316 /* 317 * The TM context is mapped twice within each page. Stores and loads 318 * to the first mapping below 2K write and read the specified values 319 * without modification. The second mapping above 2K performs specific 320 * state changes (side effects) in addition to setting/returning the 321 * interrupt management area context of the processor thread. 322 */ 323 static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx, 324 hwaddr offset, unsigned size) 325 { 326 return xive_tctx_accept(tctx, TM_QW1_OS); 327 } 328 329 static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 330 hwaddr offset, uint64_t value, unsigned size) 331 { 332 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 333 } 334 335 /* 336 * Adjust the IPB to allow a CPU to process event queues of other 337 * priorities during one physical interrupt cycle. 338 */ 339 static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, 340 hwaddr offset, uint64_t value, unsigned size) 341 { 342 xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff)); 343 } 344 345 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, 346 uint32_t *nvt_idx, bool *vo) 347 { 348 if (nvt_blk) { 349 *nvt_blk = xive_nvt_blk(cam); 350 } 351 if (nvt_idx) { 352 *nvt_idx = xive_nvt_idx(cam); 353 } 354 if (vo) { 355 *vo = !!(cam & TM_QW1W2_VO); 356 } 357 } 358 359 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk, 360 uint32_t *nvt_idx, bool *vo) 361 { 362 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 363 uint32_t cam = be32_to_cpu(qw1w2); 364 365 xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo); 366 return qw1w2; 367 } 368 369 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) 370 { 371 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 372 } 373 374 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 375 hwaddr offset, unsigned size) 376 { 377 uint32_t qw1w2; 378 uint32_t qw1w2_new; 379 uint8_t nvt_blk; 380 uint32_t nvt_idx; 381 bool vo; 382 383 qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); 384 385 if (!vo) { 386 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n", 387 nvt_blk, nvt_idx); 388 } 389 390 /* Invalidate CAM line */ 391 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); 392 xive_tctx_set_os_cam(tctx, qw1w2_new); 393 return qw1w2; 394 } 395 396 static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx, 397 uint8_t nvt_blk, uint32_t nvt_idx) 398 { 399 XiveNVT nvt; 400 uint8_t ipb; 401 402 /* 403 * Grab the associated NVT to pull the pending bits, and merge 404 * them with the IPB of the thread interrupt context registers 405 */ 406 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 407 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n", 408 nvt_blk, nvt_idx); 409 return; 410 } 411 412 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4); 413 414 if (ipb) { 415 /* Reset the NVT value */ 416 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0); 417 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 418 419 /* Merge in current context */ 420 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); 421 } 422 } 423 424 /* 425 * Updating the OS CAM line can trigger a resend of interrupt 426 */ 427 static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 428 hwaddr offset, uint64_t value, unsigned size) 429 { 430 uint32_t cam = value; 431 uint32_t qw1w2 = cpu_to_be32(cam); 432 uint8_t nvt_blk; 433 uint32_t nvt_idx; 434 bool vo; 435 436 xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); 437 438 /* First update the registers */ 439 xive_tctx_set_os_cam(tctx, qw1w2); 440 441 /* Check the interrupt pending bits */ 442 if (vo) { 443 xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); 444 } 445 } 446 447 /* 448 * Define a mapping of "special" operations depending on the TIMA page 449 * offset and the size of the operation. 450 */ 451 typedef struct XiveTmOp { 452 uint8_t page_offset; 453 uint32_t op_offset; 454 unsigned size; 455 void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, 456 hwaddr offset, 457 uint64_t value, unsigned size); 458 uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 459 unsigned size); 460 } XiveTmOp; 461 462 static const XiveTmOp xive_tm_operations[] = { 463 /* 464 * MMIOs below 2K : raw values and special operations without side 465 * effects 466 */ 467 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 468 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, NULL }, 469 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 470 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 471 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 472 473 /* MMIOs above 2K : special operations with side effects */ 474 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 475 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 476 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, 477 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, 478 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 479 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 480 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 481 }; 482 483 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 484 { 485 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 486 uint32_t op_offset = offset & 0xFFF; 487 int i; 488 489 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 490 const XiveTmOp *xto = &xive_tm_operations[i]; 491 492 /* Accesses done from a more privileged TIMA page is allowed */ 493 if (xto->page_offset >= page_offset && 494 xto->op_offset == op_offset && 495 xto->size == size && 496 ((write && xto->write_handler) || (!write && xto->read_handler))) { 497 return xto; 498 } 499 } 500 return NULL; 501 } 502 503 /* 504 * TIMA MMIO handlers 505 */ 506 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 507 uint64_t value, unsigned size) 508 { 509 const XiveTmOp *xto; 510 511 /* 512 * TODO: check V bit in Q[0-3]W2 513 */ 514 515 /* 516 * First, check for special operations in the 2K region 517 */ 518 if (offset & 0x800) { 519 xto = xive_tm_find_op(offset, size, true); 520 if (!xto) { 521 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 522 "@%"HWADDR_PRIx"\n", offset); 523 } else { 524 xto->write_handler(xptr, tctx, offset, value, size); 525 } 526 return; 527 } 528 529 /* 530 * Then, for special operations in the region below 2K. 531 */ 532 xto = xive_tm_find_op(offset, size, true); 533 if (xto) { 534 xto->write_handler(xptr, tctx, offset, value, size); 535 return; 536 } 537 538 /* 539 * Finish with raw access to the register values 540 */ 541 xive_tm_raw_write(tctx, offset, value, size); 542 } 543 544 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 545 unsigned size) 546 { 547 const XiveTmOp *xto; 548 549 /* 550 * TODO: check V bit in Q[0-3]W2 551 */ 552 553 /* 554 * First, check for special operations in the 2K region 555 */ 556 if (offset & 0x800) { 557 xto = xive_tm_find_op(offset, size, false); 558 if (!xto) { 559 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 560 "@%"HWADDR_PRIx"\n", offset); 561 return -1; 562 } 563 return xto->read_handler(xptr, tctx, offset, size); 564 } 565 566 /* 567 * Then, for special operations in the region below 2K. 568 */ 569 xto = xive_tm_find_op(offset, size, false); 570 if (xto) { 571 return xto->read_handler(xptr, tctx, offset, size); 572 } 573 574 /* 575 * Finish with raw access to the register values 576 */ 577 return xive_tm_raw_read(tctx, offset, size); 578 } 579 580 static char *xive_tctx_ring_print(uint8_t *ring) 581 { 582 uint32_t w2 = xive_tctx_word2(ring); 583 584 return g_strdup_printf("%02x %02x %02x %02x %02x " 585 "%02x %02x %02x %08x", 586 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 587 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 588 be32_to_cpu(w2)); 589 } 590 591 static const char * const xive_tctx_ring_names[] = { 592 "USER", "OS", "POOL", "PHYS", 593 }; 594 595 /* 596 * kvm_irqchip_in_kernel() will cause the compiler to turn this 597 * info a nop if CONFIG_KVM isn't defined. 598 */ 599 #define xive_in_kernel(xptr) \ 600 (kvm_irqchip_in_kernel() && \ 601 ({ \ 602 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); \ 603 xpc->in_kernel ? xpc->in_kernel(xptr) : false; \ 604 })) 605 606 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 607 { 608 int cpu_index; 609 int i; 610 611 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs 612 * are hot plugged or unplugged. 613 */ 614 if (!tctx) { 615 return; 616 } 617 618 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 619 620 if (xive_in_kernel(tctx->xptr)) { 621 Error *local_err = NULL; 622 623 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 624 if (local_err) { 625 error_report_err(local_err); 626 return; 627 } 628 } 629 630 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 631 " W2\n", cpu_index); 632 633 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 634 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 635 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 636 xive_tctx_ring_names[i], s); 637 g_free(s); 638 } 639 } 640 641 void xive_tctx_reset(XiveTCTX *tctx) 642 { 643 memset(tctx->regs, 0, sizeof(tctx->regs)); 644 645 /* Set some defaults */ 646 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 647 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 648 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 649 650 /* 651 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 652 * CPPR is first set. 653 */ 654 tctx->regs[TM_QW1_OS + TM_PIPR] = 655 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 656 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 657 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 658 } 659 660 static void xive_tctx_realize(DeviceState *dev, Error **errp) 661 { 662 XiveTCTX *tctx = XIVE_TCTX(dev); 663 PowerPCCPU *cpu; 664 CPUPPCState *env; 665 Error *local_err = NULL; 666 667 assert(tctx->cs); 668 assert(tctx->xptr); 669 670 cpu = POWERPC_CPU(tctx->cs); 671 env = &cpu->env; 672 switch (PPC_INPUT(env)) { 673 case PPC_FLAGS_INPUT_POWER9: 674 tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT]; 675 tctx->os_output = env->irq_inputs[POWER9_INPUT_INT]; 676 break; 677 678 default: 679 error_setg(errp, "XIVE interrupt controller does not support " 680 "this CPU bus model"); 681 return; 682 } 683 684 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 685 if (xive_in_kernel(tctx->xptr)) { 686 kvmppc_xive_cpu_connect(tctx, &local_err); 687 if (local_err) { 688 error_propagate(errp, local_err); 689 return; 690 } 691 } 692 } 693 694 static int vmstate_xive_tctx_pre_save(void *opaque) 695 { 696 XiveTCTX *tctx = XIVE_TCTX(opaque); 697 Error *local_err = NULL; 698 int ret; 699 700 if (xive_in_kernel(tctx->xptr)) { 701 ret = kvmppc_xive_cpu_get_state(tctx, &local_err); 702 if (ret < 0) { 703 error_report_err(local_err); 704 return ret; 705 } 706 } 707 708 return 0; 709 } 710 711 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 712 { 713 XiveTCTX *tctx = XIVE_TCTX(opaque); 714 Error *local_err = NULL; 715 int ret; 716 717 if (xive_in_kernel(tctx->xptr)) { 718 /* 719 * Required for hotplugged CPU, for which the state comes 720 * after all states of the machine. 721 */ 722 ret = kvmppc_xive_cpu_set_state(tctx, &local_err); 723 if (ret < 0) { 724 error_report_err(local_err); 725 return ret; 726 } 727 } 728 729 return 0; 730 } 731 732 static const VMStateDescription vmstate_xive_tctx = { 733 .name = TYPE_XIVE_TCTX, 734 .version_id = 1, 735 .minimum_version_id = 1, 736 .pre_save = vmstate_xive_tctx_pre_save, 737 .post_load = vmstate_xive_tctx_post_load, 738 .fields = (VMStateField[]) { 739 VMSTATE_BUFFER(regs, XiveTCTX), 740 VMSTATE_END_OF_LIST() 741 }, 742 }; 743 744 static Property xive_tctx_properties[] = { 745 DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), 746 DEFINE_PROP_LINK("presenter", XiveTCTX, xptr, TYPE_XIVE_PRESENTER, 747 XivePresenter *), 748 DEFINE_PROP_END_OF_LIST(), 749 }; 750 751 static void xive_tctx_class_init(ObjectClass *klass, void *data) 752 { 753 DeviceClass *dc = DEVICE_CLASS(klass); 754 755 dc->desc = "XIVE Interrupt Thread Context"; 756 dc->realize = xive_tctx_realize; 757 dc->vmsd = &vmstate_xive_tctx; 758 device_class_set_props(dc, xive_tctx_properties); 759 /* 760 * Reason: part of XIVE interrupt controller, needs to be wired up 761 * by xive_tctx_create(). 762 */ 763 dc->user_creatable = false; 764 } 765 766 static const TypeInfo xive_tctx_info = { 767 .name = TYPE_XIVE_TCTX, 768 .parent = TYPE_DEVICE, 769 .instance_size = sizeof(XiveTCTX), 770 .class_init = xive_tctx_class_init, 771 }; 772 773 Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp) 774 { 775 Object *obj; 776 777 obj = object_new(TYPE_XIVE_TCTX); 778 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj); 779 object_unref(obj); 780 object_property_set_link(obj, "cpu", cpu, &error_abort); 781 object_property_set_link(obj, "presenter", OBJECT(xptr), &error_abort); 782 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 783 object_unparent(obj); 784 return NULL; 785 } 786 return obj; 787 } 788 789 void xive_tctx_destroy(XiveTCTX *tctx) 790 { 791 Object *obj = OBJECT(tctx); 792 793 object_unparent(obj); 794 } 795 796 /* 797 * XIVE ESB helpers 798 */ 799 800 static uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 801 { 802 uint8_t old_pq = *pq & 0x3; 803 804 *pq &= ~0x3; 805 *pq |= value & 0x3; 806 807 return old_pq; 808 } 809 810 static bool xive_esb_trigger(uint8_t *pq) 811 { 812 uint8_t old_pq = *pq & 0x3; 813 814 switch (old_pq) { 815 case XIVE_ESB_RESET: 816 xive_esb_set(pq, XIVE_ESB_PENDING); 817 return true; 818 case XIVE_ESB_PENDING: 819 case XIVE_ESB_QUEUED: 820 xive_esb_set(pq, XIVE_ESB_QUEUED); 821 return false; 822 case XIVE_ESB_OFF: 823 xive_esb_set(pq, XIVE_ESB_OFF); 824 return false; 825 default: 826 g_assert_not_reached(); 827 } 828 } 829 830 static bool xive_esb_eoi(uint8_t *pq) 831 { 832 uint8_t old_pq = *pq & 0x3; 833 834 switch (old_pq) { 835 case XIVE_ESB_RESET: 836 case XIVE_ESB_PENDING: 837 xive_esb_set(pq, XIVE_ESB_RESET); 838 return false; 839 case XIVE_ESB_QUEUED: 840 xive_esb_set(pq, XIVE_ESB_PENDING); 841 return true; 842 case XIVE_ESB_OFF: 843 xive_esb_set(pq, XIVE_ESB_OFF); 844 return false; 845 default: 846 g_assert_not_reached(); 847 } 848 } 849 850 /* 851 * XIVE Interrupt Source (or IVSE) 852 */ 853 854 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 855 { 856 assert(srcno < xsrc->nr_irqs); 857 858 return xsrc->status[srcno] & 0x3; 859 } 860 861 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 862 { 863 assert(srcno < xsrc->nr_irqs); 864 865 return xive_esb_set(&xsrc->status[srcno], pq); 866 } 867 868 /* 869 * Returns whether the event notification should be forwarded. 870 */ 871 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 872 { 873 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 874 875 xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; 876 877 switch (old_pq) { 878 case XIVE_ESB_RESET: 879 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 880 return true; 881 default: 882 return false; 883 } 884 } 885 886 /* 887 * Returns whether the event notification should be forwarded. 888 */ 889 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 890 { 891 bool ret; 892 893 assert(srcno < xsrc->nr_irqs); 894 895 ret = xive_esb_trigger(&xsrc->status[srcno]); 896 897 if (xive_source_irq_is_lsi(xsrc, srcno) && 898 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 899 qemu_log_mask(LOG_GUEST_ERROR, 900 "XIVE: queued an event on LSI IRQ %d\n", srcno); 901 } 902 903 return ret; 904 } 905 906 /* 907 * Returns whether the event notification should be forwarded. 908 */ 909 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 910 { 911 bool ret; 912 913 assert(srcno < xsrc->nr_irqs); 914 915 ret = xive_esb_eoi(&xsrc->status[srcno]); 916 917 /* 918 * LSI sources do not set the Q bit but they can still be 919 * asserted, in which case we should forward a new event 920 * notification 921 */ 922 if (xive_source_irq_is_lsi(xsrc, srcno) && 923 xsrc->status[srcno] & XIVE_STATUS_ASSERTED) { 924 ret = xive_source_lsi_trigger(xsrc, srcno); 925 } 926 927 return ret; 928 } 929 930 /* 931 * Forward the source event notification to the Router 932 */ 933 static void xive_source_notify(XiveSource *xsrc, int srcno) 934 { 935 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 936 937 if (xnc->notify) { 938 xnc->notify(xsrc->xive, srcno); 939 } 940 } 941 942 /* 943 * In a two pages ESB MMIO setting, even page is the trigger page, odd 944 * page is for management 945 */ 946 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 947 { 948 return !((addr >> shift) & 1); 949 } 950 951 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 952 { 953 return xive_source_esb_has_2page(xsrc) && 954 addr_is_even(addr, xsrc->esb_shift - 1); 955 } 956 957 /* 958 * ESB MMIO loads 959 * Trigger page Management/EOI page 960 * 961 * ESB MMIO setting 2 pages 1 or 2 pages 962 * 963 * 0x000 .. 0x3FF -1 EOI and return 0|1 964 * 0x400 .. 0x7FF -1 EOI and return 0|1 965 * 0x800 .. 0xBFF -1 return PQ 966 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 967 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 968 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 969 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 970 */ 971 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 972 { 973 XiveSource *xsrc = XIVE_SOURCE(opaque); 974 uint32_t offset = addr & 0xFFF; 975 uint32_t srcno = addr >> xsrc->esb_shift; 976 uint64_t ret = -1; 977 978 /* In a two pages ESB MMIO setting, trigger page should not be read */ 979 if (xive_source_is_trigger_page(xsrc, addr)) { 980 qemu_log_mask(LOG_GUEST_ERROR, 981 "XIVE: invalid load on IRQ %d trigger page at " 982 "0x%"HWADDR_PRIx"\n", srcno, addr); 983 return -1; 984 } 985 986 switch (offset) { 987 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 988 ret = xive_source_esb_eoi(xsrc, srcno); 989 990 /* Forward the source event notification for routing */ 991 if (ret) { 992 xive_source_notify(xsrc, srcno); 993 } 994 break; 995 996 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 997 ret = xive_source_esb_get(xsrc, srcno); 998 break; 999 1000 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1001 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1002 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1003 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1004 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1005 break; 1006 default: 1007 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 1008 offset); 1009 } 1010 1011 return ret; 1012 } 1013 1014 /* 1015 * ESB MMIO stores 1016 * Trigger page Management/EOI page 1017 * 1018 * ESB MMIO setting 2 pages 1 or 2 pages 1019 * 1020 * 0x000 .. 0x3FF Trigger Trigger 1021 * 0x400 .. 0x7FF Trigger EOI 1022 * 0x800 .. 0xBFF Trigger undefined 1023 * 0xC00 .. 0xCFF Trigger PQ=00 1024 * 0xD00 .. 0xDFF Trigger PQ=01 1025 * 0xE00 .. 0xDFF Trigger PQ=10 1026 * 0xF00 .. 0xDFF Trigger PQ=11 1027 */ 1028 static void xive_source_esb_write(void *opaque, hwaddr addr, 1029 uint64_t value, unsigned size) 1030 { 1031 XiveSource *xsrc = XIVE_SOURCE(opaque); 1032 uint32_t offset = addr & 0xFFF; 1033 uint32_t srcno = addr >> xsrc->esb_shift; 1034 bool notify = false; 1035 1036 /* In a two pages ESB MMIO setting, trigger page only triggers */ 1037 if (xive_source_is_trigger_page(xsrc, addr)) { 1038 notify = xive_source_esb_trigger(xsrc, srcno); 1039 goto out; 1040 } 1041 1042 switch (offset) { 1043 case 0 ... 0x3FF: 1044 notify = xive_source_esb_trigger(xsrc, srcno); 1045 break; 1046 1047 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 1048 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 1049 qemu_log_mask(LOG_GUEST_ERROR, 1050 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 1051 return; 1052 } 1053 1054 notify = xive_source_esb_eoi(xsrc, srcno); 1055 break; 1056 1057 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1058 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1059 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1060 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1061 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1062 break; 1063 1064 default: 1065 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 1066 offset); 1067 return; 1068 } 1069 1070 out: 1071 /* Forward the source event notification for routing */ 1072 if (notify) { 1073 xive_source_notify(xsrc, srcno); 1074 } 1075 } 1076 1077 static const MemoryRegionOps xive_source_esb_ops = { 1078 .read = xive_source_esb_read, 1079 .write = xive_source_esb_write, 1080 .endianness = DEVICE_BIG_ENDIAN, 1081 .valid = { 1082 .min_access_size = 8, 1083 .max_access_size = 8, 1084 }, 1085 .impl = { 1086 .min_access_size = 8, 1087 .max_access_size = 8, 1088 }, 1089 }; 1090 1091 void xive_source_set_irq(void *opaque, int srcno, int val) 1092 { 1093 XiveSource *xsrc = XIVE_SOURCE(opaque); 1094 bool notify = false; 1095 1096 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1097 if (val) { 1098 notify = xive_source_lsi_trigger(xsrc, srcno); 1099 } else { 1100 xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; 1101 } 1102 } else { 1103 if (val) { 1104 notify = xive_source_esb_trigger(xsrc, srcno); 1105 } 1106 } 1107 1108 /* Forward the source event notification for routing */ 1109 if (notify) { 1110 xive_source_notify(xsrc, srcno); 1111 } 1112 } 1113 1114 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 1115 { 1116 int i; 1117 1118 for (i = 0; i < xsrc->nr_irqs; i++) { 1119 uint8_t pq = xive_source_esb_get(xsrc, i); 1120 1121 if (pq == XIVE_ESB_OFF) { 1122 continue; 1123 } 1124 1125 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 1126 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1127 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1128 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1129 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' '); 1130 } 1131 } 1132 1133 static void xive_source_reset(void *dev) 1134 { 1135 XiveSource *xsrc = XIVE_SOURCE(dev); 1136 1137 /* Do not clear the LSI bitmap */ 1138 1139 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 1140 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 1141 } 1142 1143 static void xive_source_realize(DeviceState *dev, Error **errp) 1144 { 1145 XiveSource *xsrc = XIVE_SOURCE(dev); 1146 size_t esb_len = xive_source_esb_len(xsrc); 1147 1148 assert(xsrc->xive); 1149 1150 if (!xsrc->nr_irqs) { 1151 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1152 return; 1153 } 1154 1155 if (xsrc->esb_shift != XIVE_ESB_4K && 1156 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1157 xsrc->esb_shift != XIVE_ESB_64K && 1158 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1159 error_setg(errp, "Invalid ESB shift setting"); 1160 return; 1161 } 1162 1163 xsrc->status = g_malloc0(xsrc->nr_irqs); 1164 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1165 1166 memory_region_init(&xsrc->esb_mmio, OBJECT(xsrc), "xive.esb", esb_len); 1167 memory_region_init_io(&xsrc->esb_mmio_emulated, OBJECT(xsrc), 1168 &xive_source_esb_ops, xsrc, "xive.esb-emulated", 1169 esb_len); 1170 memory_region_add_subregion(&xsrc->esb_mmio, 0, &xsrc->esb_mmio_emulated); 1171 1172 qemu_register_reset(xive_source_reset, dev); 1173 } 1174 1175 static const VMStateDescription vmstate_xive_source = { 1176 .name = TYPE_XIVE_SOURCE, 1177 .version_id = 1, 1178 .minimum_version_id = 1, 1179 .fields = (VMStateField[]) { 1180 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1181 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1182 VMSTATE_END_OF_LIST() 1183 }, 1184 }; 1185 1186 /* 1187 * The default XIVE interrupt source setting for the ESB MMIOs is two 1188 * 64k pages without Store EOI, to be in sync with KVM. 1189 */ 1190 static Property xive_source_properties[] = { 1191 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1192 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1193 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1194 DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, 1195 XiveNotifier *), 1196 DEFINE_PROP_END_OF_LIST(), 1197 }; 1198 1199 static void xive_source_class_init(ObjectClass *klass, void *data) 1200 { 1201 DeviceClass *dc = DEVICE_CLASS(klass); 1202 1203 dc->desc = "XIVE Interrupt Source"; 1204 device_class_set_props(dc, xive_source_properties); 1205 dc->realize = xive_source_realize; 1206 dc->vmsd = &vmstate_xive_source; 1207 /* 1208 * Reason: part of XIVE interrupt controller, needs to be wired up, 1209 * e.g. by spapr_xive_instance_init(). 1210 */ 1211 dc->user_creatable = false; 1212 } 1213 1214 static const TypeInfo xive_source_info = { 1215 .name = TYPE_XIVE_SOURCE, 1216 .parent = TYPE_DEVICE, 1217 .instance_size = sizeof(XiveSource), 1218 .class_init = xive_source_class_init, 1219 }; 1220 1221 /* 1222 * XiveEND helpers 1223 */ 1224 1225 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1226 { 1227 uint64_t qaddr_base = xive_end_qaddr(end); 1228 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1229 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1230 uint32_t qentries = 1 << (qsize + 10); 1231 int i; 1232 1233 /* 1234 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1235 */ 1236 monitor_printf(mon, " [ "); 1237 qindex = (qindex - (width - 1)) & (qentries - 1); 1238 for (i = 0; i < width; i++) { 1239 uint64_t qaddr = qaddr_base + (qindex << 2); 1240 uint32_t qdata = -1; 1241 1242 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 1243 sizeof(qdata))) { 1244 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1245 HWADDR_PRIx "\n", qaddr); 1246 return; 1247 } 1248 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1249 be32_to_cpu(qdata)); 1250 qindex = (qindex + 1) & (qentries - 1); 1251 } 1252 monitor_printf(mon, "]"); 1253 } 1254 1255 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1256 { 1257 uint64_t qaddr_base = xive_end_qaddr(end); 1258 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1259 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1260 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1261 uint32_t qentries = 1 << (qsize + 10); 1262 1263 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1264 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1265 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1266 uint8_t pq; 1267 1268 if (!xive_end_is_valid(end)) { 1269 return; 1270 } 1271 1272 pq = xive_get_field32(END_W1_ESn, end->w1); 1273 1274 monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1275 end_idx, 1276 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1277 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1278 xive_end_is_valid(end) ? 'v' : '-', 1279 xive_end_is_enqueue(end) ? 'q' : '-', 1280 xive_end_is_notify(end) ? 'n' : '-', 1281 xive_end_is_backlog(end) ? 'b' : '-', 1282 xive_end_is_escalate(end) ? 'e' : '-', 1283 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1284 xive_end_is_silent_escalation(end) ? 's' : '-', 1285 priority, nvt_blk, nvt_idx); 1286 1287 if (qaddr_base) { 1288 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1289 qaddr_base, qindex, qentries, qgen); 1290 xive_end_queue_pic_print_info(end, 6, mon); 1291 } 1292 monitor_printf(mon, "\n"); 1293 } 1294 1295 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1296 { 1297 uint64_t qaddr_base = xive_end_qaddr(end); 1298 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1299 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1300 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1301 1302 uint64_t qaddr = qaddr_base + (qindex << 2); 1303 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1304 uint32_t qentries = 1 << (qsize + 10); 1305 1306 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) { 1307 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1308 HWADDR_PRIx "\n", qaddr); 1309 return; 1310 } 1311 1312 qindex = (qindex + 1) & (qentries - 1); 1313 if (qindex == 0) { 1314 qgen ^= 1; 1315 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1316 } 1317 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1318 } 1319 1320 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, 1321 Monitor *mon) 1322 { 1323 XiveEAS *eas = (XiveEAS *) &end->w4; 1324 uint8_t pq; 1325 1326 if (!xive_end_is_escalate(end)) { 1327 return; 1328 } 1329 1330 pq = xive_get_field32(END_W1_ESe, end->w1); 1331 1332 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1333 end_idx, 1334 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1335 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1336 xive_eas_is_valid(eas) ? 'V' : ' ', 1337 xive_eas_is_masked(eas) ? 'M' : ' ', 1338 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1339 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1340 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1341 } 1342 1343 /* 1344 * XIVE Router (aka. Virtualization Controller or IVRE) 1345 */ 1346 1347 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1348 XiveEAS *eas) 1349 { 1350 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1351 1352 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1353 } 1354 1355 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1356 XiveEND *end) 1357 { 1358 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1359 1360 return xrc->get_end(xrtr, end_blk, end_idx, end); 1361 } 1362 1363 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1364 XiveEND *end, uint8_t word_number) 1365 { 1366 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1367 1368 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1369 } 1370 1371 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1372 XiveNVT *nvt) 1373 { 1374 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1375 1376 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1377 } 1378 1379 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1380 XiveNVT *nvt, uint8_t word_number) 1381 { 1382 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1383 1384 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1385 } 1386 1387 static int xive_router_get_block_id(XiveRouter *xrtr) 1388 { 1389 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1390 1391 return xrc->get_block_id(xrtr); 1392 } 1393 1394 static void xive_router_realize(DeviceState *dev, Error **errp) 1395 { 1396 XiveRouter *xrtr = XIVE_ROUTER(dev); 1397 1398 assert(xrtr->xfb); 1399 } 1400 1401 /* 1402 * Encode the HW CAM line in the block group mode format : 1403 * 1404 * chip << 19 | 0000000 0 0001 thread (7Bit) 1405 */ 1406 static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 1407 { 1408 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1409 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1410 uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr)); 1411 1412 return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); 1413 } 1414 1415 /* 1416 * The thread context register words are in big-endian format. 1417 */ 1418 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1419 uint8_t format, 1420 uint8_t nvt_blk, uint32_t nvt_idx, 1421 bool cam_ignore, uint32_t logic_serv) 1422 { 1423 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1424 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1425 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1426 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1427 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1428 1429 /* 1430 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1431 * identifier are ignored in the "CAM" match. 1432 */ 1433 1434 if (format == 0) { 1435 if (cam_ignore == true) { 1436 /* 1437 * F=0 & i=1: Logical server notification (bits ignored at 1438 * the end of the NVT identifier) 1439 */ 1440 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1441 nvt_blk, nvt_idx); 1442 return -1; 1443 } 1444 1445 /* F=0 & i=0: Specific NVT notification */ 1446 1447 /* PHYS ring */ 1448 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1449 cam == xive_tctx_hw_cam_line(xptr, tctx)) { 1450 return TM_QW3_HV_PHYS; 1451 } 1452 1453 /* HV POOL ring */ 1454 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1455 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1456 return TM_QW2_HV_POOL; 1457 } 1458 1459 /* OS ring */ 1460 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1461 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1462 return TM_QW1_OS; 1463 } 1464 } else { 1465 /* F=1 : User level Event-Based Branch (EBB) notification */ 1466 1467 /* USER ring */ 1468 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1469 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1470 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1471 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1472 return TM_QW0_USER; 1473 } 1474 } 1475 return -1; 1476 } 1477 1478 /* 1479 * This is our simple Xive Presenter Engine model. It is merged in the 1480 * Router as it does not require an extra object. 1481 * 1482 * It receives notification requests sent by the IVRE to find one 1483 * matching NVT (or more) dispatched on the processor threads. In case 1484 * of a single NVT notification, the process is abreviated and the 1485 * thread is signaled if a match is found. In case of a logical server 1486 * notification (bits ignored at the end of the NVT identifier), the 1487 * IVPE and IVRE select a winning thread using different filters. This 1488 * involves 2 or 3 exchanges on the PowerBus that the model does not 1489 * support. 1490 * 1491 * The parameters represent what is sent on the PowerBus 1492 */ 1493 static bool xive_presenter_notify(XiveFabric *xfb, uint8_t format, 1494 uint8_t nvt_blk, uint32_t nvt_idx, 1495 bool cam_ignore, uint8_t priority, 1496 uint32_t logic_serv) 1497 { 1498 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb); 1499 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1500 int count; 1501 1502 /* 1503 * Ask the machine to scan the interrupt controllers for a match 1504 */ 1505 count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore, 1506 priority, logic_serv, &match); 1507 if (count < 0) { 1508 return false; 1509 } 1510 1511 /* handle CPU exception delivery */ 1512 if (count) { 1513 xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(priority)); 1514 } 1515 1516 return !!count; 1517 } 1518 1519 /* 1520 * Notification using the END ESe/ESn bit (Event State Buffer for 1521 * escalation and notification). Provide further coalescing in the 1522 * Router. 1523 */ 1524 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1525 uint32_t end_idx, XiveEND *end, 1526 uint32_t end_esmask) 1527 { 1528 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1529 bool notify = xive_esb_trigger(&pq); 1530 1531 if (pq != xive_get_field32(end_esmask, end->w1)) { 1532 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1533 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1534 } 1535 1536 /* ESe/n[Q]=1 : end of notification */ 1537 return notify; 1538 } 1539 1540 /* 1541 * An END trigger can come from an event trigger (IPI or HW) or from 1542 * another chip. We don't model the PowerBus but the END trigger 1543 * message has the same parameters than in the function below. 1544 */ 1545 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1546 uint32_t end_idx, uint32_t end_data) 1547 { 1548 XiveEND end; 1549 uint8_t priority; 1550 uint8_t format; 1551 uint8_t nvt_blk; 1552 uint32_t nvt_idx; 1553 XiveNVT nvt; 1554 bool found; 1555 1556 /* END cache lookup */ 1557 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1558 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1559 end_idx); 1560 return; 1561 } 1562 1563 if (!xive_end_is_valid(&end)) { 1564 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1565 end_blk, end_idx); 1566 return; 1567 } 1568 1569 if (xive_end_is_enqueue(&end)) { 1570 xive_end_enqueue(&end, end_data); 1571 /* Enqueuing event data modifies the EQ toggle and index */ 1572 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1573 } 1574 1575 /* 1576 * When the END is silent, we skip the notification part. 1577 */ 1578 if (xive_end_is_silent_escalation(&end)) { 1579 goto do_escalation; 1580 } 1581 1582 /* 1583 * The W7 format depends on the F bit in W6. It defines the type 1584 * of the notification : 1585 * 1586 * F=0 : single or multiple NVT notification 1587 * F=1 : User level Event-Based Branch (EBB) notification, no 1588 * priority 1589 */ 1590 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1591 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1592 1593 /* The END is masked */ 1594 if (format == 0 && priority == 0xff) { 1595 return; 1596 } 1597 1598 /* 1599 * Check the END ESn (Event State Buffer for notification) for 1600 * even further coalescing in the Router 1601 */ 1602 if (!xive_end_is_notify(&end)) { 1603 /* ESn[Q]=1 : end of notification */ 1604 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1605 &end, END_W1_ESn)) { 1606 return; 1607 } 1608 } 1609 1610 /* 1611 * Follows IVPE notification 1612 */ 1613 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1614 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1615 1616 /* NVT cache lookup */ 1617 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1618 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1619 nvt_blk, nvt_idx); 1620 return; 1621 } 1622 1623 if (!xive_nvt_is_valid(&nvt)) { 1624 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1625 nvt_blk, nvt_idx); 1626 return; 1627 } 1628 1629 found = xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx, 1630 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1631 priority, 1632 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1633 1634 /* TODO: Auto EOI. */ 1635 1636 if (found) { 1637 return; 1638 } 1639 1640 /* 1641 * If no matching NVT is dispatched on a HW thread : 1642 * - specific VP: update the NVT structure if backlog is activated 1643 * - logical server : forward request to IVPE (not supported) 1644 */ 1645 if (xive_end_is_backlog(&end)) { 1646 uint8_t ipb; 1647 1648 if (format == 1) { 1649 qemu_log_mask(LOG_GUEST_ERROR, 1650 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1651 end_blk, end_idx); 1652 return; 1653 } 1654 /* 1655 * Record the IPB in the associated NVT structure for later 1656 * use. The presenter will resend the interrupt when the vCPU 1657 * is dispatched again on a HW thread. 1658 */ 1659 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priority); 1660 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); 1661 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1662 1663 /* 1664 * On HW, follows a "Broadcast Backlog" to IVPEs 1665 */ 1666 } 1667 1668 do_escalation: 1669 /* 1670 * If activated, escalate notification using the ESe PQ bits and 1671 * the EAS in w4-5 1672 */ 1673 if (!xive_end_is_escalate(&end)) { 1674 return; 1675 } 1676 1677 /* 1678 * Check the END ESe (Event State Buffer for escalation) for even 1679 * further coalescing in the Router 1680 */ 1681 if (!xive_end_is_uncond_escalation(&end)) { 1682 /* ESe[Q]=1 : end of notification */ 1683 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1684 &end, END_W1_ESe)) { 1685 return; 1686 } 1687 } 1688 1689 /* 1690 * The END trigger becomes an Escalation trigger 1691 */ 1692 xive_router_end_notify(xrtr, 1693 xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1694 xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1695 xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1696 } 1697 1698 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 1699 { 1700 XiveRouter *xrtr = XIVE_ROUTER(xn); 1701 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1702 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1703 XiveEAS eas; 1704 1705 /* EAS cache lookup */ 1706 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1707 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1708 return; 1709 } 1710 1711 /* 1712 * The IVRE checks the State Bit Cache at this point. We skip the 1713 * SBC lookup because the state bits of the sources are modeled 1714 * internally in QEMU. 1715 */ 1716 1717 if (!xive_eas_is_valid(&eas)) { 1718 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1719 return; 1720 } 1721 1722 if (xive_eas_is_masked(&eas)) { 1723 /* Notification completed */ 1724 return; 1725 } 1726 1727 /* 1728 * The event trigger becomes an END trigger 1729 */ 1730 xive_router_end_notify(xrtr, 1731 xive_get_field64(EAS_END_BLOCK, eas.w), 1732 xive_get_field64(EAS_END_INDEX, eas.w), 1733 xive_get_field64(EAS_END_DATA, eas.w)); 1734 } 1735 1736 static Property xive_router_properties[] = { 1737 DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb, 1738 TYPE_XIVE_FABRIC, XiveFabric *), 1739 DEFINE_PROP_END_OF_LIST(), 1740 }; 1741 1742 static void xive_router_class_init(ObjectClass *klass, void *data) 1743 { 1744 DeviceClass *dc = DEVICE_CLASS(klass); 1745 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1746 1747 dc->desc = "XIVE Router Engine"; 1748 device_class_set_props(dc, xive_router_properties); 1749 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 1750 dc->realize = xive_router_realize; 1751 xnc->notify = xive_router_notify; 1752 } 1753 1754 static const TypeInfo xive_router_info = { 1755 .name = TYPE_XIVE_ROUTER, 1756 .parent = TYPE_SYS_BUS_DEVICE, 1757 .abstract = true, 1758 .instance_size = sizeof(XiveRouter), 1759 .class_size = sizeof(XiveRouterClass), 1760 .class_init = xive_router_class_init, 1761 .interfaces = (InterfaceInfo[]) { 1762 { TYPE_XIVE_NOTIFIER }, 1763 { TYPE_XIVE_PRESENTER }, 1764 { } 1765 } 1766 }; 1767 1768 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1769 { 1770 if (!xive_eas_is_valid(eas)) { 1771 return; 1772 } 1773 1774 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1775 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1776 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1777 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1778 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1779 } 1780 1781 /* 1782 * END ESB MMIO loads 1783 */ 1784 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1785 { 1786 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1787 uint32_t offset = addr & 0xFFF; 1788 uint8_t end_blk; 1789 uint32_t end_idx; 1790 XiveEND end; 1791 uint32_t end_esmask; 1792 uint8_t pq; 1793 uint64_t ret = -1; 1794 1795 /* 1796 * The block id should be deduced from the load address on the END 1797 * ESB MMIO but our model only supports a single block per XIVE chip. 1798 */ 1799 end_blk = xive_router_get_block_id(xsrc->xrtr); 1800 end_idx = addr >> (xsrc->esb_shift + 1); 1801 1802 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1803 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1804 end_idx); 1805 return -1; 1806 } 1807 1808 if (!xive_end_is_valid(&end)) { 1809 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1810 end_blk, end_idx); 1811 return -1; 1812 } 1813 1814 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1815 pq = xive_get_field32(end_esmask, end.w1); 1816 1817 switch (offset) { 1818 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1819 ret = xive_esb_eoi(&pq); 1820 1821 /* Forward the source event notification for routing ?? */ 1822 break; 1823 1824 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1825 ret = pq; 1826 break; 1827 1828 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1829 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1830 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1831 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1832 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1833 break; 1834 default: 1835 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1836 offset); 1837 return -1; 1838 } 1839 1840 if (pq != xive_get_field32(end_esmask, end.w1)) { 1841 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1842 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1843 } 1844 1845 return ret; 1846 } 1847 1848 /* 1849 * END ESB MMIO stores are invalid 1850 */ 1851 static void xive_end_source_write(void *opaque, hwaddr addr, 1852 uint64_t value, unsigned size) 1853 { 1854 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1855 HWADDR_PRIx"\n", addr); 1856 } 1857 1858 static const MemoryRegionOps xive_end_source_ops = { 1859 .read = xive_end_source_read, 1860 .write = xive_end_source_write, 1861 .endianness = DEVICE_BIG_ENDIAN, 1862 .valid = { 1863 .min_access_size = 8, 1864 .max_access_size = 8, 1865 }, 1866 .impl = { 1867 .min_access_size = 8, 1868 .max_access_size = 8, 1869 }, 1870 }; 1871 1872 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1873 { 1874 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1875 1876 assert(xsrc->xrtr); 1877 1878 if (!xsrc->nr_ends) { 1879 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1880 return; 1881 } 1882 1883 if (xsrc->esb_shift != XIVE_ESB_4K && 1884 xsrc->esb_shift != XIVE_ESB_64K) { 1885 error_setg(errp, "Invalid ESB shift setting"); 1886 return; 1887 } 1888 1889 /* 1890 * Each END is assigned an even/odd pair of MMIO pages, the even page 1891 * manages the ESn field while the odd page manages the ESe field. 1892 */ 1893 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1894 &xive_end_source_ops, xsrc, "xive.end", 1895 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1896 } 1897 1898 static Property xive_end_source_properties[] = { 1899 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1900 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1901 DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, 1902 XiveRouter *), 1903 DEFINE_PROP_END_OF_LIST(), 1904 }; 1905 1906 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1907 { 1908 DeviceClass *dc = DEVICE_CLASS(klass); 1909 1910 dc->desc = "XIVE END Source"; 1911 device_class_set_props(dc, xive_end_source_properties); 1912 dc->realize = xive_end_source_realize; 1913 /* 1914 * Reason: part of XIVE interrupt controller, needs to be wired up, 1915 * e.g. by spapr_xive_instance_init(). 1916 */ 1917 dc->user_creatable = false; 1918 } 1919 1920 static const TypeInfo xive_end_source_info = { 1921 .name = TYPE_XIVE_END_SOURCE, 1922 .parent = TYPE_DEVICE, 1923 .instance_size = sizeof(XiveENDSource), 1924 .class_init = xive_end_source_class_init, 1925 }; 1926 1927 /* 1928 * XIVE Notifier 1929 */ 1930 static const TypeInfo xive_notifier_info = { 1931 .name = TYPE_XIVE_NOTIFIER, 1932 .parent = TYPE_INTERFACE, 1933 .class_size = sizeof(XiveNotifierClass), 1934 }; 1935 1936 /* 1937 * XIVE Presenter 1938 */ 1939 static const TypeInfo xive_presenter_info = { 1940 .name = TYPE_XIVE_PRESENTER, 1941 .parent = TYPE_INTERFACE, 1942 .class_size = sizeof(XivePresenterClass), 1943 }; 1944 1945 /* 1946 * XIVE Fabric 1947 */ 1948 static const TypeInfo xive_fabric_info = { 1949 .name = TYPE_XIVE_FABRIC, 1950 .parent = TYPE_INTERFACE, 1951 .class_size = sizeof(XiveFabricClass), 1952 }; 1953 1954 static void xive_register_types(void) 1955 { 1956 type_register_static(&xive_fabric_info); 1957 type_register_static(&xive_source_info); 1958 type_register_static(&xive_notifier_info); 1959 type_register_static(&xive_presenter_info); 1960 type_register_static(&xive_router_info); 1961 type_register_static(&xive_end_source_info); 1962 type_register_static(&xive_tctx_info); 1963 } 1964 1965 type_init(xive_register_types) 1966