1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/log.h" 11 #include "qemu/module.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "system/cpus.h" 15 #include "system/dma.h" 16 #include "system/reset.h" 17 #include "hw/qdev-properties.h" 18 #include "migration/vmstate.h" 19 #include "hw/irq.h" 20 #include "hw/ppc/xive.h" 21 #include "hw/ppc/xive2.h" 22 #include "hw/ppc/xive_regs.h" 23 #include "trace.h" 24 25 /* 26 * XIVE Thread Interrupt Management context 27 */ 28 bool xive_nsr_indicates_exception(uint8_t ring, uint8_t nsr) 29 { 30 switch (ring) { 31 case TM_QW1_OS: 32 return !!(nsr & TM_QW1_NSR_EO); 33 case TM_QW2_HV_POOL: 34 case TM_QW3_HV_PHYS: 35 return !!(nsr & TM_QW3_NSR_HE); 36 default: 37 g_assert_not_reached(); 38 } 39 } 40 41 bool xive_nsr_indicates_group_exception(uint8_t ring, uint8_t nsr) 42 { 43 if ((nsr & TM_NSR_GRP_LVL) > 0) { 44 g_assert(xive_nsr_indicates_exception(ring, nsr)); 45 return true; 46 } 47 return false; 48 } 49 50 uint8_t xive_nsr_exception_ring(uint8_t ring, uint8_t nsr) 51 { 52 /* NSR determines if pool/phys ring is for phys or pool interrupt */ 53 if ((ring == TM_QW3_HV_PHYS) || (ring == TM_QW2_HV_POOL)) { 54 uint8_t he = (nsr & TM_QW3_NSR_HE) >> 6; 55 56 if (he == TM_QW3_NSR_HE_PHYS) { 57 return TM_QW3_HV_PHYS; 58 } else if (he == TM_QW3_NSR_HE_POOL) { 59 return TM_QW2_HV_POOL; 60 } else { 61 /* Don't support LSI mode */ 62 g_assert_not_reached(); 63 } 64 } 65 return ring; 66 } 67 68 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 69 { 70 switch (ring) { 71 case TM_QW0_USER: 72 return 0; /* Not supported */ 73 case TM_QW1_OS: 74 return tctx->os_output; 75 case TM_QW2_HV_POOL: 76 case TM_QW3_HV_PHYS: 77 return tctx->hv_output; 78 default: 79 return 0; 80 } 81 } 82 83 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 84 { 85 uint8_t *regs = &tctx->regs[ring]; 86 uint8_t nsr = regs[TM_NSR]; 87 88 qemu_irq_lower(xive_tctx_output(tctx, ring)); 89 90 if (xive_nsr_indicates_exception(ring, nsr)) { 91 uint8_t cppr = regs[TM_PIPR]; 92 uint8_t alt_ring; 93 uint8_t *alt_regs; 94 95 alt_ring = xive_nsr_exception_ring(ring, nsr); 96 alt_regs = &tctx->regs[alt_ring]; 97 98 regs[TM_CPPR] = cppr; 99 100 /* 101 * If the interrupt was for a specific VP, reset the pending 102 * buffer bit, otherwise clear the logical server indicator 103 */ 104 if (!xive_nsr_indicates_group_exception(ring, nsr)) { 105 alt_regs[TM_IPB] &= ~xive_priority_to_ipb(cppr); 106 } 107 108 /* Clear the exception from NSR */ 109 regs[TM_NSR] = 0; 110 111 trace_xive_tctx_accept(tctx->cs->cpu_index, alt_ring, 112 alt_regs[TM_IPB], regs[TM_PIPR], 113 regs[TM_CPPR], regs[TM_NSR]); 114 } 115 116 return ((uint64_t)nsr << 8) | regs[TM_CPPR]; 117 } 118 119 void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level) 120 { 121 /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ 122 uint8_t alt_ring = (ring == TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : ring; 123 uint8_t *alt_regs = &tctx->regs[alt_ring]; 124 uint8_t *regs = &tctx->regs[ring]; 125 126 if (alt_regs[TM_PIPR] < alt_regs[TM_CPPR]) { 127 switch (ring) { 128 case TM_QW1_OS: 129 regs[TM_NSR] = TM_QW1_NSR_EO | (group_level & 0x3F); 130 break; 131 case TM_QW2_HV_POOL: 132 alt_regs[TM_NSR] = (TM_QW3_NSR_HE_POOL << 6) | (group_level & 0x3F); 133 break; 134 case TM_QW3_HV_PHYS: 135 regs[TM_NSR] = (TM_QW3_NSR_HE_PHYS << 6) | (group_level & 0x3F); 136 break; 137 default: 138 g_assert_not_reached(); 139 } 140 trace_xive_tctx_notify(tctx->cs->cpu_index, ring, 141 regs[TM_IPB], alt_regs[TM_PIPR], 142 alt_regs[TM_CPPR], alt_regs[TM_NSR]); 143 qemu_irq_raise(xive_tctx_output(tctx, ring)); 144 } else { 145 alt_regs[TM_NSR] = 0; 146 qemu_irq_lower(xive_tctx_output(tctx, ring)); 147 } 148 } 149 150 void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring) 151 { 152 /* 153 * Lower the External interrupt. Used when pulling a context. It is 154 * necessary to avoid catching it in the higher privilege context. It 155 * should be raised again when re-pushing the lower privilege context. 156 */ 157 qemu_irq_lower(xive_tctx_output(tctx, ring)); 158 } 159 160 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 161 { 162 uint8_t *regs = &tctx->regs[ring]; 163 uint8_t pipr_min; 164 uint8_t ring_min; 165 166 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, 167 regs[TM_IPB], regs[TM_PIPR], 168 cppr, regs[TM_NSR]); 169 170 if (cppr > XIVE_PRIORITY_MAX) { 171 cppr = 0xff; 172 } 173 174 tctx->regs[ring + TM_CPPR] = cppr; 175 176 /* 177 * Recompute the PIPR based on local pending interrupts. The PHYS 178 * ring must take the minimum of both the PHYS and POOL PIPR values. 179 */ 180 pipr_min = xive_ipb_to_pipr(regs[TM_IPB]); 181 ring_min = ring; 182 183 /* PHYS updates also depend on POOL values */ 184 if (ring == TM_QW3_HV_PHYS) { 185 uint8_t *pool_regs = &tctx->regs[TM_QW2_HV_POOL]; 186 187 /* POOL values only matter if POOL ctx is valid */ 188 if (pool_regs[TM_WORD2] & 0x80) { 189 190 uint8_t pool_pipr = xive_ipb_to_pipr(pool_regs[TM_IPB]); 191 192 /* 193 * Determine highest priority interrupt and 194 * remember which ring has it. 195 */ 196 if (pool_pipr < pipr_min) { 197 pipr_min = pool_pipr; 198 ring_min = TM_QW2_HV_POOL; 199 } 200 } 201 } 202 203 regs[TM_PIPR] = pipr_min; 204 205 /* CPPR has changed, check if we need to raise a pending exception */ 206 xive_tctx_notify(tctx, ring_min, 0); 207 } 208 209 void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority, 210 uint8_t group_level) 211 { 212 /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ 213 uint8_t alt_ring = (ring == TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : ring; 214 uint8_t *alt_regs = &tctx->regs[alt_ring]; 215 uint8_t *regs = &tctx->regs[ring]; 216 217 if (group_level == 0) { 218 /* VP-specific */ 219 regs[TM_IPB] |= xive_priority_to_ipb(priority); 220 alt_regs[TM_PIPR] = xive_ipb_to_pipr(regs[TM_IPB]); 221 } else { 222 /* VP-group */ 223 alt_regs[TM_PIPR] = xive_priority_to_pipr(priority); 224 } 225 xive_tctx_notify(tctx, ring, group_level); 226 } 227 228 /* 229 * XIVE Thread Interrupt Management Area (TIMA) 230 */ 231 232 static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 233 hwaddr offset, uint64_t value, unsigned size) 234 { 235 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 236 } 237 238 static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx, 239 hwaddr offset, unsigned size) 240 { 241 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 242 } 243 244 static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, 245 hwaddr offset, unsigned size) 246 { 247 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 248 uint32_t qw2w2; 249 250 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 251 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 252 return qw2w2; 253 } 254 255 static uint64_t xive_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, 256 hwaddr offset, unsigned size) 257 { 258 uint8_t qw3b8_prev = tctx->regs[TM_QW3_HV_PHYS + TM_WORD2]; 259 uint8_t qw3b8; 260 261 qw3b8 = qw3b8_prev & ~TM_QW3B8_VT; 262 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = qw3b8; 263 return qw3b8; 264 } 265 266 static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 267 uint64_t value, unsigned size) 268 { 269 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 270 } 271 272 static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, 273 hwaddr offset, unsigned size) 274 { 275 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 276 } 277 278 /* 279 * Define an access map for each page of the TIMA that we will use in 280 * the memory region ops to filter values when doing loads and stores 281 * of raw registers values 282 * 283 * Registers accessibility bits : 284 * 285 * 0x0 - no access 286 * 0x1 - write only 287 * 0x2 - read only 288 * 0x3 - read/write 289 */ 290 291 static const uint8_t xive_tm_hw_view[] = { 292 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 293 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 294 0, 0, 3, 3, 0, 3, 3, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 295 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 296 }; 297 298 static const uint8_t xive_tm_hv_view[] = { 299 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 300 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 301 0, 0, 3, 3, 0, 3, 3, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 302 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 303 }; 304 305 static const uint8_t xive_tm_os_view[] = { 306 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 307 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 308 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 309 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 310 }; 311 312 static const uint8_t xive_tm_user_view[] = { 313 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 314 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 315 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 316 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 317 }; 318 319 /* 320 * Overall TIMA access map for the thread interrupt management context 321 * registers 322 */ 323 static const uint8_t *xive_tm_views[] = { 324 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 325 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 326 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 327 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 328 }; 329 330 /* 331 * Computes a register access mask for a given offset in the TIMA 332 */ 333 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 334 { 335 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 336 uint8_t reg_offset = offset & TM_REG_OFFSET; 337 uint8_t reg_mask = write ? 0x1 : 0x2; 338 uint64_t mask = 0x0; 339 int i; 340 341 for (i = 0; i < size; i++) { 342 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 343 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 344 } 345 } 346 347 return mask; 348 } 349 350 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 351 unsigned size) 352 { 353 uint8_t ring_offset = offset & TM_RING_OFFSET; 354 uint8_t reg_offset = offset & TM_REG_OFFSET; 355 uint64_t mask = xive_tm_mask(offset, size, true); 356 int i; 357 358 /* 359 * Only 4 or 8 bytes stores are allowed and the User ring is 360 * excluded 361 */ 362 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 363 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 364 HWADDR_PRIx" size %d\n", offset, size); 365 return; 366 } 367 368 /* 369 * Use the register offset for the raw values and filter out 370 * reserved values 371 */ 372 for (i = 0; i < size; i++) { 373 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 374 if (byte_mask) { 375 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 376 byte_mask; 377 } 378 } 379 } 380 381 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 382 { 383 uint8_t ring_offset = offset & TM_RING_OFFSET; 384 uint8_t reg_offset = offset & TM_REG_OFFSET; 385 uint64_t mask = xive_tm_mask(offset, size, false); 386 uint64_t ret; 387 int i; 388 389 /* 390 * Only 4 or 8 bytes loads are allowed and the User ring is 391 * excluded 392 */ 393 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 394 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 395 HWADDR_PRIx" size %d\n", offset, size); 396 return -1; 397 } 398 399 /* Use the register offset for the raw values */ 400 ret = 0; 401 for (i = 0; i < size; i++) { 402 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 403 } 404 405 /* filter out reserved values */ 406 return ret & mask; 407 } 408 409 /* 410 * The TM context is mapped twice within each page. Stores and loads 411 * to the first mapping below 2K write and read the specified values 412 * without modification. The second mapping above 2K performs specific 413 * state changes (side effects) in addition to setting/returning the 414 * interrupt management area context of the processor thread. 415 */ 416 static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx, 417 hwaddr offset, unsigned size) 418 { 419 return xive_tctx_accept(tctx, TM_QW1_OS); 420 } 421 422 static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 423 hwaddr offset, uint64_t value, unsigned size) 424 { 425 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 426 } 427 428 static void xive_tctx_set_lgs(XiveTCTX *tctx, uint8_t ring, uint8_t lgs) 429 { 430 uint8_t *regs = &tctx->regs[ring]; 431 432 regs[TM_LGS] = lgs; 433 } 434 435 static void xive_tm_set_os_lgs(XivePresenter *xptr, XiveTCTX *tctx, 436 hwaddr offset, uint64_t value, unsigned size) 437 { 438 xive_tctx_set_lgs(tctx, TM_QW1_OS, value & 0xff); 439 } 440 441 /* 442 * Adjust the PIPR to allow a CPU to process event queues of other 443 * priorities during one physical interrupt cycle. 444 */ 445 static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, 446 hwaddr offset, uint64_t value, unsigned size) 447 { 448 xive_tctx_pipr_update(tctx, TM_QW1_OS, value & 0xff, 0); 449 } 450 451 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, 452 uint32_t *nvt_idx, bool *vo) 453 { 454 if (nvt_blk) { 455 *nvt_blk = xive_nvt_blk(cam); 456 } 457 if (nvt_idx) { 458 *nvt_idx = xive_nvt_idx(cam); 459 } 460 if (vo) { 461 *vo = !!(cam & TM_QW1W2_VO); 462 } 463 } 464 465 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk, 466 uint32_t *nvt_idx, bool *vo) 467 { 468 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 469 uint32_t cam = be32_to_cpu(qw1w2); 470 471 xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo); 472 return qw1w2; 473 } 474 475 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) 476 { 477 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 478 } 479 480 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 481 hwaddr offset, unsigned size) 482 { 483 uint32_t qw1w2; 484 uint32_t qw1w2_new; 485 uint8_t nvt_blk; 486 uint32_t nvt_idx; 487 bool vo; 488 489 qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); 490 491 if (!vo) { 492 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n", 493 nvt_blk, nvt_idx); 494 } 495 496 /* Invalidate CAM line */ 497 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); 498 xive_tctx_set_os_cam(tctx, qw1w2_new); 499 500 xive_tctx_reset_signal(tctx, TM_QW1_OS); 501 return qw1w2; 502 } 503 504 static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx, 505 uint8_t nvt_blk, uint32_t nvt_idx) 506 { 507 XiveNVT nvt; 508 uint8_t ipb; 509 510 /* 511 * Grab the associated NVT to pull the pending bits, and merge 512 * them with the IPB of the thread interrupt context registers 513 */ 514 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 515 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n", 516 nvt_blk, nvt_idx); 517 return; 518 } 519 520 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4); 521 522 if (ipb) { 523 /* Reset the NVT value */ 524 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0); 525 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 526 527 uint8_t *regs = &tctx->regs[TM_QW1_OS]; 528 regs[TM_IPB] |= ipb; 529 } 530 531 /* 532 * Always call xive_tctx_pipr_update(). Even if there were no 533 * escalation triggered, there could be a pending interrupt which 534 * was saved when the context was pulled and that we need to take 535 * into account by recalculating the PIPR (which is not 536 * saved/restored). 537 * It will also raise the External interrupt signal if needed. 538 */ 539 xive_tctx_pipr_update(tctx, TM_QW1_OS, 0xFF, 0); /* fxb */ 540 } 541 542 /* 543 * Updating the OS CAM line can trigger a resend of interrupt 544 */ 545 static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 546 hwaddr offset, uint64_t value, unsigned size) 547 { 548 uint32_t cam = value; 549 uint32_t qw1w2 = cpu_to_be32(cam); 550 uint8_t nvt_blk; 551 uint32_t nvt_idx; 552 bool vo; 553 554 xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); 555 556 /* First update the registers */ 557 xive_tctx_set_os_cam(tctx, qw1w2); 558 559 /* Check the interrupt pending bits */ 560 if (vo) { 561 xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); 562 } 563 } 564 565 static uint32_t xive_presenter_get_config(XivePresenter *xptr) 566 { 567 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 568 569 return xpc->get_config(xptr); 570 } 571 572 /* 573 * Define a mapping of "special" operations depending on the TIMA page 574 * offset and the size of the operation. 575 */ 576 typedef struct XiveTmOp { 577 uint8_t page_offset; 578 uint32_t op_offset; 579 unsigned size; 580 void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, 581 hwaddr offset, 582 uint64_t value, unsigned size); 583 uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 584 unsigned size); 585 } XiveTmOp; 586 587 static const XiveTmOp xive_tm_operations[] = { 588 /* 589 * MMIOs below 2K : raw values and special operations without side 590 * effects 591 */ 592 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, 593 NULL }, 594 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, 595 NULL }, 596 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, 597 NULL }, 598 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, 599 NULL }, 600 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, 601 xive_tm_vt_poll }, 602 603 /* MMIOs above 2K : special operations with side effects */ 604 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, 605 xive_tm_ack_os_reg }, 606 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, 607 NULL }, 608 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, 609 xive_tm_pull_os_ctx }, 610 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, 611 xive_tm_pull_os_ctx }, 612 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, 613 xive_tm_ack_hv_reg }, 614 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, 615 xive_tm_pull_pool_ctx }, 616 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, 617 xive_tm_pull_pool_ctx }, 618 { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL, 619 xive_tm_pull_phys_ctx }, 620 }; 621 622 static const XiveTmOp xive2_tm_operations[] = { 623 /* 624 * MMIOs below 2K : raw values and special operations without side 625 * effects 626 */ 627 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive2_tm_set_os_cppr, 628 NULL }, 629 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx, 630 NULL }, 631 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 8, xive2_tm_push_os_ctx, 632 NULL }, 633 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, xive_tm_set_os_lgs, 634 NULL }, 635 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive2_tm_set_hv_cppr, 636 NULL }, 637 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, 638 NULL }, 639 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, 640 xive_tm_vt_poll }, 641 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_T, 1, xive2_tm_set_hv_target, 642 NULL }, 643 644 /* MMIOs above 2K : special operations with side effects */ 645 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, 646 xive_tm_ack_os_reg }, 647 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, 648 NULL }, 649 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_G2, 4, NULL, 650 xive2_tm_pull_os_ctx }, 651 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, 652 xive2_tm_pull_os_ctx }, 653 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, 654 xive2_tm_pull_os_ctx }, 655 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, 656 xive_tm_ack_hv_reg }, 657 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX_G2, 4, NULL, 658 xive_tm_pull_pool_ctx }, 659 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, 660 xive_tm_pull_pool_ctx }, 661 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, 662 xive_tm_pull_pool_ctx }, 663 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_OL, 1, xive2_tm_pull_os_ctx_ol, 664 NULL }, 665 { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_G2, 4, NULL, 666 xive_tm_pull_phys_ctx }, 667 { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL, 668 xive_tm_pull_phys_ctx }, 669 { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_OL, 1, xive2_tm_pull_phys_ctx_ol, 670 NULL }, 671 }; 672 673 static const XiveTmOp *xive_tm_find_op(XivePresenter *xptr, hwaddr offset, 674 unsigned size, bool write) 675 { 676 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 677 uint32_t op_offset = offset & TM_ADDRESS_MASK; 678 const XiveTmOp *tm_ops; 679 int i, tm_ops_count; 680 uint32_t cfg; 681 682 cfg = xive_presenter_get_config(xptr); 683 if (cfg & XIVE_PRESENTER_GEN1_TIMA_OS) { 684 tm_ops = xive_tm_operations; 685 tm_ops_count = ARRAY_SIZE(xive_tm_operations); 686 } else { 687 tm_ops = xive2_tm_operations; 688 tm_ops_count = ARRAY_SIZE(xive2_tm_operations); 689 } 690 691 for (i = 0; i < tm_ops_count; i++) { 692 const XiveTmOp *xto = &tm_ops[i]; 693 694 /* Accesses done from a more privileged TIMA page is allowed */ 695 if (xto->page_offset >= page_offset && 696 xto->op_offset == op_offset && 697 xto->size == size && 698 ((write && xto->write_handler) || (!write && xto->read_handler))) { 699 return xto; 700 } 701 } 702 return NULL; 703 } 704 705 /* 706 * TIMA MMIO handlers 707 */ 708 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 709 uint64_t value, unsigned size) 710 { 711 const XiveTmOp *xto; 712 713 trace_xive_tctx_tm_write(tctx->cs->cpu_index, offset, size, value); 714 715 /* 716 * TODO: check V bit in Q[0-3]W2 717 */ 718 719 /* 720 * First, check for special operations in the 2K region 721 */ 722 if (offset & TM_SPECIAL_OP) { 723 xto = xive_tm_find_op(tctx->xptr, offset, size, true); 724 if (!xto) { 725 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 726 "@%"HWADDR_PRIx" size %d\n", offset, size); 727 } else { 728 xto->write_handler(xptr, tctx, offset, value, size); 729 } 730 return; 731 } 732 733 /* 734 * Then, for special operations in the region below 2K. 735 */ 736 xto = xive_tm_find_op(tctx->xptr, offset, size, true); 737 if (xto) { 738 xto->write_handler(xptr, tctx, offset, value, size); 739 return; 740 } 741 742 /* 743 * Finish with raw access to the register values 744 */ 745 xive_tm_raw_write(tctx, offset, value, size); 746 } 747 748 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 749 unsigned size) 750 { 751 const XiveTmOp *xto; 752 uint64_t ret; 753 754 /* 755 * TODO: check V bit in Q[0-3]W2 756 */ 757 758 /* 759 * First, check for special operations in the 2K region 760 */ 761 if (offset & TM_SPECIAL_OP) { 762 xto = xive_tm_find_op(tctx->xptr, offset, size, false); 763 if (!xto) { 764 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 765 "@%"HWADDR_PRIx" size %d\n", offset, size); 766 return -1; 767 } 768 ret = xto->read_handler(xptr, tctx, offset, size); 769 goto out; 770 } 771 772 /* 773 * Then, for special operations in the region below 2K. 774 */ 775 xto = xive_tm_find_op(tctx->xptr, offset, size, false); 776 if (xto) { 777 ret = xto->read_handler(xptr, tctx, offset, size); 778 goto out; 779 } 780 781 /* 782 * Finish with raw access to the register values 783 */ 784 ret = xive_tm_raw_read(tctx, offset, size); 785 out: 786 trace_xive_tctx_tm_read(tctx->cs->cpu_index, offset, size, ret); 787 return ret; 788 } 789 790 static char *xive_tctx_ring_print(uint8_t *ring) 791 { 792 uint32_t w2 = xive_tctx_word2(ring); 793 794 return g_strdup_printf("%02x %02x %02x %02x %02x " 795 "%02x %02x %02x %08x", 796 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 797 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 798 be32_to_cpu(w2)); 799 } 800 801 static const char * const xive_tctx_ring_names[] = { 802 "USER", "OS", "POOL", "PHYS", 803 }; 804 805 /* 806 * kvm_irqchip_in_kernel() will cause the compiler to turn this 807 * info a nop if CONFIG_KVM isn't defined. 808 */ 809 #define xive_in_kernel(xptr) \ 810 (kvm_irqchip_in_kernel() && \ 811 ({ \ 812 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); \ 813 xpc->in_kernel ? xpc->in_kernel(xptr) : false; \ 814 })) 815 816 void xive_tctx_pic_print_info(XiveTCTX *tctx, GString *buf) 817 { 818 int cpu_index; 819 int i; 820 821 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs 822 * are hot plugged or unplugged. 823 */ 824 if (!tctx) { 825 return; 826 } 827 828 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 829 830 if (xive_in_kernel(tctx->xptr)) { 831 Error *local_err = NULL; 832 833 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 834 if (local_err) { 835 error_report_err(local_err); 836 return; 837 } 838 } 839 840 if (xive_presenter_get_config(tctx->xptr) & XIVE_PRESENTER_GEN1_TIMA_OS) { 841 g_string_append_printf(buf, "CPU[%04x]: " 842 "QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 843 " W2\n", cpu_index); 844 } else { 845 g_string_append_printf(buf, "CPU[%04x]: " 846 "QW NSR CPPR IPB LSMFB - LGS T PIPR" 847 " W2\n", cpu_index); 848 } 849 850 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 851 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 852 g_string_append_printf(buf, "CPU[%04x]: %4s %s\n", 853 cpu_index, xive_tctx_ring_names[i], s); 854 g_free(s); 855 } 856 } 857 858 void xive_tctx_reset(XiveTCTX *tctx) 859 { 860 memset(tctx->regs, 0, sizeof(tctx->regs)); 861 862 /* Set some defaults */ 863 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 864 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 865 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 866 if (!(xive_presenter_get_config(tctx->xptr) & 867 XIVE_PRESENTER_GEN1_TIMA_OS)) { 868 tctx->regs[TM_QW1_OS + TM_OGEN] = 2; 869 } 870 871 /* 872 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 873 * CPPR is first set. 874 */ 875 tctx->regs[TM_QW1_OS + TM_PIPR] = 876 xive_ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 877 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 878 xive_ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 879 } 880 881 static void xive_tctx_realize(DeviceState *dev, Error **errp) 882 { 883 XiveTCTX *tctx = XIVE_TCTX(dev); 884 PowerPCCPU *cpu; 885 CPUPPCState *env; 886 887 assert(tctx->cs); 888 assert(tctx->xptr); 889 890 cpu = POWERPC_CPU(tctx->cs); 891 env = &cpu->env; 892 switch (PPC_INPUT(env)) { 893 case PPC_FLAGS_INPUT_POWER9: 894 tctx->hv_output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_HINT); 895 tctx->os_output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_INT); 896 break; 897 898 default: 899 error_setg(errp, "XIVE interrupt controller does not support " 900 "this CPU bus model"); 901 return; 902 } 903 904 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 905 if (xive_in_kernel(tctx->xptr)) { 906 if (kvmppc_xive_cpu_connect(tctx, errp) < 0) { 907 return; 908 } 909 } 910 } 911 912 static int vmstate_xive_tctx_pre_save(void *opaque) 913 { 914 XiveTCTX *tctx = XIVE_TCTX(opaque); 915 Error *local_err = NULL; 916 int ret; 917 918 if (xive_in_kernel(tctx->xptr)) { 919 ret = kvmppc_xive_cpu_get_state(tctx, &local_err); 920 if (ret < 0) { 921 error_report_err(local_err); 922 return ret; 923 } 924 } 925 926 return 0; 927 } 928 929 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 930 { 931 XiveTCTX *tctx = XIVE_TCTX(opaque); 932 Error *local_err = NULL; 933 int ret; 934 935 if (xive_in_kernel(tctx->xptr)) { 936 /* 937 * Required for hotplugged CPU, for which the state comes 938 * after all states of the machine. 939 */ 940 ret = kvmppc_xive_cpu_set_state(tctx, &local_err); 941 if (ret < 0) { 942 error_report_err(local_err); 943 return ret; 944 } 945 } 946 947 return 0; 948 } 949 950 static const VMStateDescription vmstate_xive_tctx = { 951 .name = TYPE_XIVE_TCTX, 952 .version_id = 1, 953 .minimum_version_id = 1, 954 .pre_save = vmstate_xive_tctx_pre_save, 955 .post_load = vmstate_xive_tctx_post_load, 956 .fields = (const VMStateField[]) { 957 VMSTATE_BUFFER(regs, XiveTCTX), 958 VMSTATE_END_OF_LIST() 959 }, 960 }; 961 962 static const Property xive_tctx_properties[] = { 963 DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), 964 DEFINE_PROP_LINK("presenter", XiveTCTX, xptr, TYPE_XIVE_PRESENTER, 965 XivePresenter *), 966 }; 967 968 static void xive_tctx_class_init(ObjectClass *klass, const void *data) 969 { 970 DeviceClass *dc = DEVICE_CLASS(klass); 971 972 dc->desc = "XIVE Interrupt Thread Context"; 973 dc->realize = xive_tctx_realize; 974 dc->vmsd = &vmstate_xive_tctx; 975 device_class_set_props(dc, xive_tctx_properties); 976 /* 977 * Reason: part of XIVE interrupt controller, needs to be wired up 978 * by xive_tctx_create(). 979 */ 980 dc->user_creatable = false; 981 } 982 983 static const TypeInfo xive_tctx_info = { 984 .name = TYPE_XIVE_TCTX, 985 .parent = TYPE_DEVICE, 986 .instance_size = sizeof(XiveTCTX), 987 .class_init = xive_tctx_class_init, 988 }; 989 990 Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp) 991 { 992 Object *obj; 993 994 obj = object_new(TYPE_XIVE_TCTX); 995 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj); 996 object_unref(obj); 997 object_property_set_link(obj, "cpu", cpu, &error_abort); 998 object_property_set_link(obj, "presenter", OBJECT(xptr), &error_abort); 999 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1000 object_unparent(obj); 1001 return NULL; 1002 } 1003 return obj; 1004 } 1005 1006 void xive_tctx_destroy(XiveTCTX *tctx) 1007 { 1008 Object *obj = OBJECT(tctx); 1009 1010 object_unparent(obj); 1011 } 1012 1013 /* 1014 * XIVE ESB helpers 1015 */ 1016 1017 uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 1018 { 1019 uint8_t old_pq = *pq & 0x3; 1020 1021 *pq &= ~0x3; 1022 *pq |= value & 0x3; 1023 1024 return old_pq; 1025 } 1026 1027 bool xive_esb_trigger(uint8_t *pq) 1028 { 1029 uint8_t old_pq = *pq & 0x3; 1030 1031 switch (old_pq) { 1032 case XIVE_ESB_RESET: 1033 xive_esb_set(pq, XIVE_ESB_PENDING); 1034 return true; 1035 case XIVE_ESB_PENDING: 1036 case XIVE_ESB_QUEUED: 1037 xive_esb_set(pq, XIVE_ESB_QUEUED); 1038 return false; 1039 case XIVE_ESB_OFF: 1040 xive_esb_set(pq, XIVE_ESB_OFF); 1041 return false; 1042 default: 1043 g_assert_not_reached(); 1044 } 1045 } 1046 1047 bool xive_esb_eoi(uint8_t *pq) 1048 { 1049 uint8_t old_pq = *pq & 0x3; 1050 1051 switch (old_pq) { 1052 case XIVE_ESB_RESET: 1053 case XIVE_ESB_PENDING: 1054 xive_esb_set(pq, XIVE_ESB_RESET); 1055 return false; 1056 case XIVE_ESB_QUEUED: 1057 xive_esb_set(pq, XIVE_ESB_PENDING); 1058 return true; 1059 case XIVE_ESB_OFF: 1060 xive_esb_set(pq, XIVE_ESB_OFF); 1061 return false; 1062 default: 1063 g_assert_not_reached(); 1064 } 1065 } 1066 1067 /* 1068 * XIVE Interrupt Source (or IVSE) 1069 */ 1070 1071 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 1072 { 1073 assert(srcno < xsrc->nr_irqs); 1074 1075 return xsrc->status[srcno] & 0x3; 1076 } 1077 1078 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 1079 { 1080 assert(srcno < xsrc->nr_irqs); 1081 1082 return xive_esb_set(&xsrc->status[srcno], pq); 1083 } 1084 1085 /* 1086 * Returns whether the event notification should be forwarded. 1087 */ 1088 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 1089 { 1090 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 1091 1092 xive_source_set_asserted(xsrc, srcno, true); 1093 1094 switch (old_pq) { 1095 case XIVE_ESB_RESET: 1096 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 1097 return true; 1098 default: 1099 return false; 1100 } 1101 } 1102 1103 /* 1104 * Sources can be configured with PQ offloading in which case the check 1105 * on the PQ state bits of MSIs is disabled 1106 */ 1107 static bool xive_source_esb_disabled(XiveSource *xsrc, uint32_t srcno) 1108 { 1109 return (xsrc->esb_flags & XIVE_SRC_PQ_DISABLE) && 1110 !xive_source_irq_is_lsi(xsrc, srcno); 1111 } 1112 1113 /* 1114 * Returns whether the event notification should be forwarded. 1115 */ 1116 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 1117 { 1118 bool ret; 1119 1120 assert(srcno < xsrc->nr_irqs); 1121 1122 if (xive_source_esb_disabled(xsrc, srcno)) { 1123 return true; 1124 } 1125 1126 ret = xive_esb_trigger(&xsrc->status[srcno]); 1127 1128 if (xive_source_irq_is_lsi(xsrc, srcno) && 1129 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 1130 qemu_log_mask(LOG_GUEST_ERROR, 1131 "XIVE: queued an event on LSI IRQ %d\n", srcno); 1132 } 1133 1134 return ret; 1135 } 1136 1137 /* 1138 * Returns whether the event notification should be forwarded. 1139 */ 1140 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 1141 { 1142 bool ret; 1143 1144 assert(srcno < xsrc->nr_irqs); 1145 1146 if (xive_source_esb_disabled(xsrc, srcno)) { 1147 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EOI for IRQ %d\n", srcno); 1148 return false; 1149 } 1150 1151 ret = xive_esb_eoi(&xsrc->status[srcno]); 1152 1153 /* 1154 * LSI sources do not set the Q bit but they can still be 1155 * asserted, in which case we should forward a new event 1156 * notification 1157 */ 1158 if (xive_source_irq_is_lsi(xsrc, srcno) && 1159 xive_source_is_asserted(xsrc, srcno)) { 1160 ret = xive_source_lsi_trigger(xsrc, srcno); 1161 } 1162 1163 return ret; 1164 } 1165 1166 /* 1167 * Forward the source event notification to the Router 1168 */ 1169 static void xive_source_notify(XiveSource *xsrc, int srcno) 1170 { 1171 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 1172 bool pq_checked = !xive_source_esb_disabled(xsrc, srcno); 1173 1174 if (xnc->notify) { 1175 xnc->notify(xsrc->xive, srcno, pq_checked); 1176 } 1177 } 1178 1179 /* 1180 * In a two pages ESB MMIO setting, even page is the trigger page, odd 1181 * page is for management 1182 */ 1183 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 1184 { 1185 return !((addr >> shift) & 1); 1186 } 1187 1188 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 1189 { 1190 return xive_source_esb_has_2page(xsrc) && 1191 addr_is_even(addr, xsrc->esb_shift - 1); 1192 } 1193 1194 /* 1195 * ESB MMIO loads 1196 * Trigger page Management/EOI page 1197 * 1198 * ESB MMIO setting 2 pages 1 or 2 pages 1199 * 1200 * 0x000 .. 0x3FF -1 EOI and return 0|1 1201 * 0x400 .. 0x7FF -1 EOI and return 0|1 1202 * 0x800 .. 0xBFF -1 return PQ 1203 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 1204 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 1205 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 1206 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 1207 */ 1208 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 1209 { 1210 XiveSource *xsrc = XIVE_SOURCE(opaque); 1211 uint32_t offset = addr & 0xFFF; 1212 uint32_t srcno = addr >> xsrc->esb_shift; 1213 uint64_t ret = -1; 1214 1215 /* In a two pages ESB MMIO setting, trigger page should not be read */ 1216 if (xive_source_is_trigger_page(xsrc, addr)) { 1217 qemu_log_mask(LOG_GUEST_ERROR, 1218 "XIVE: invalid load on IRQ %d trigger page at " 1219 "0x%"HWADDR_PRIx"\n", srcno, addr); 1220 return -1; 1221 } 1222 1223 switch (offset) { 1224 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1225 ret = xive_source_esb_eoi(xsrc, srcno); 1226 1227 /* Forward the source event notification for routing */ 1228 if (ret) { 1229 xive_source_notify(xsrc, srcno); 1230 } 1231 break; 1232 1233 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1234 ret = xive_source_esb_get(xsrc, srcno); 1235 break; 1236 1237 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1238 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1239 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1240 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1241 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1242 break; 1243 default: 1244 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 1245 offset); 1246 } 1247 1248 trace_xive_source_esb_read(addr, srcno, ret); 1249 1250 return ret; 1251 } 1252 1253 /* 1254 * ESB MMIO stores 1255 * Trigger page Management/EOI page 1256 * 1257 * ESB MMIO setting 2 pages 1 or 2 pages 1258 * 1259 * 0x000 .. 0x3FF Trigger Trigger 1260 * 0x400 .. 0x7FF Trigger EOI 1261 * 0x800 .. 0xBFF Trigger undefined 1262 * 0xC00 .. 0xCFF Trigger PQ=00 1263 * 0xD00 .. 0xDFF Trigger PQ=01 1264 * 0xE00 .. 0xDFF Trigger PQ=10 1265 * 0xF00 .. 0xDFF Trigger PQ=11 1266 */ 1267 static void xive_source_esb_write(void *opaque, hwaddr addr, 1268 uint64_t value, unsigned size) 1269 { 1270 XiveSource *xsrc = XIVE_SOURCE(opaque); 1271 uint32_t offset = addr & 0xFFF; 1272 uint32_t srcno = addr >> xsrc->esb_shift; 1273 bool notify = false; 1274 1275 trace_xive_source_esb_write(addr, srcno, value); 1276 1277 /* In a two pages ESB MMIO setting, trigger page only triggers */ 1278 if (xive_source_is_trigger_page(xsrc, addr)) { 1279 notify = xive_source_esb_trigger(xsrc, srcno); 1280 goto out; 1281 } 1282 1283 switch (offset) { 1284 case 0 ... 0x3FF: 1285 notify = xive_source_esb_trigger(xsrc, srcno); 1286 break; 1287 1288 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 1289 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 1290 qemu_log_mask(LOG_GUEST_ERROR, 1291 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 1292 return; 1293 } 1294 1295 notify = xive_source_esb_eoi(xsrc, srcno); 1296 break; 1297 1298 /* 1299 * This is an internal offset used to inject triggers when the PQ 1300 * state bits are not controlled locally. Such as for LSIs when 1301 * under ABT mode. 1302 */ 1303 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: 1304 notify = true; 1305 break; 1306 1307 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1308 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1309 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1310 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1311 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1312 break; 1313 1314 default: 1315 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 1316 offset); 1317 return; 1318 } 1319 1320 out: 1321 /* Forward the source event notification for routing */ 1322 if (notify) { 1323 xive_source_notify(xsrc, srcno); 1324 } 1325 } 1326 1327 static const MemoryRegionOps xive_source_esb_ops = { 1328 .read = xive_source_esb_read, 1329 .write = xive_source_esb_write, 1330 .endianness = DEVICE_BIG_ENDIAN, 1331 .valid = { 1332 .min_access_size = 1, 1333 .max_access_size = 8, 1334 }, 1335 .impl = { 1336 .min_access_size = 1, 1337 .max_access_size = 8, 1338 }, 1339 }; 1340 1341 void xive_source_set_irq(void *opaque, int srcno, int val) 1342 { 1343 XiveSource *xsrc = XIVE_SOURCE(opaque); 1344 bool notify = false; 1345 1346 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1347 if (val) { 1348 notify = xive_source_lsi_trigger(xsrc, srcno); 1349 } else { 1350 xive_source_set_asserted(xsrc, srcno, false); 1351 } 1352 } else { 1353 if (val) { 1354 notify = xive_source_esb_trigger(xsrc, srcno); 1355 } 1356 } 1357 1358 /* Forward the source event notification for routing */ 1359 if (notify) { 1360 xive_source_notify(xsrc, srcno); 1361 } 1362 } 1363 1364 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, GString *buf) 1365 { 1366 for (unsigned i = 0; i < xsrc->nr_irqs; i++) { 1367 uint8_t pq = xive_source_esb_get(xsrc, i); 1368 1369 if (pq == XIVE_ESB_OFF) { 1370 continue; 1371 } 1372 1373 g_string_append_printf(buf, " %08x %s %c%c%c\n", i + offset, 1374 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1375 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1376 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1377 xive_source_is_asserted(xsrc, i) ? 'A' : ' '); 1378 } 1379 } 1380 1381 static void xive_source_reset(void *dev) 1382 { 1383 XiveSource *xsrc = XIVE_SOURCE(dev); 1384 1385 /* Do not clear the LSI bitmap */ 1386 1387 memset(xsrc->status, xsrc->reset_pq, xsrc->nr_irqs); 1388 } 1389 1390 static void xive_source_realize(DeviceState *dev, Error **errp) 1391 { 1392 XiveSource *xsrc = XIVE_SOURCE(dev); 1393 uint64_t esb_len = xive_source_esb_len(xsrc); 1394 1395 assert(xsrc->xive); 1396 1397 if (!xsrc->nr_irqs) { 1398 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1399 return; 1400 } 1401 1402 if (xsrc->esb_shift != XIVE_ESB_4K && 1403 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1404 xsrc->esb_shift != XIVE_ESB_64K && 1405 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1406 error_setg(errp, "Invalid ESB shift setting"); 1407 return; 1408 } 1409 1410 xsrc->status = g_malloc0(xsrc->nr_irqs); 1411 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1412 1413 memory_region_init(&xsrc->esb_mmio, OBJECT(xsrc), "xive.esb", esb_len); 1414 memory_region_init_io(&xsrc->esb_mmio_emulated, OBJECT(xsrc), 1415 &xive_source_esb_ops, xsrc, "xive.esb-emulated", 1416 esb_len); 1417 memory_region_add_subregion(&xsrc->esb_mmio, 0, &xsrc->esb_mmio_emulated); 1418 1419 qemu_register_reset(xive_source_reset, dev); 1420 } 1421 1422 static const VMStateDescription vmstate_xive_source = { 1423 .name = TYPE_XIVE_SOURCE, 1424 .version_id = 1, 1425 .minimum_version_id = 1, 1426 .fields = (const VMStateField[]) { 1427 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1428 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1429 VMSTATE_END_OF_LIST() 1430 }, 1431 }; 1432 1433 /* 1434 * The default XIVE interrupt source setting for the ESB MMIOs is two 1435 * 64k pages without Store EOI, to be in sync with KVM. 1436 */ 1437 static const Property xive_source_properties[] = { 1438 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1439 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1440 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1441 /* 1442 * By default, PQs are initialized to 0b01 (Q=1) which corresponds 1443 * to "ints off" 1444 */ 1445 DEFINE_PROP_UINT8("reset-pq", XiveSource, reset_pq, XIVE_ESB_OFF), 1446 DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, 1447 XiveNotifier *), 1448 }; 1449 1450 static void xive_source_class_init(ObjectClass *klass, const void *data) 1451 { 1452 DeviceClass *dc = DEVICE_CLASS(klass); 1453 1454 dc->desc = "XIVE Interrupt Source"; 1455 device_class_set_props(dc, xive_source_properties); 1456 dc->realize = xive_source_realize; 1457 dc->vmsd = &vmstate_xive_source; 1458 /* 1459 * Reason: part of XIVE interrupt controller, needs to be wired up, 1460 * e.g. by spapr_xive_instance_init(). 1461 */ 1462 dc->user_creatable = false; 1463 } 1464 1465 static const TypeInfo xive_source_info = { 1466 .name = TYPE_XIVE_SOURCE, 1467 .parent = TYPE_DEVICE, 1468 .instance_size = sizeof(XiveSource), 1469 .class_init = xive_source_class_init, 1470 }; 1471 1472 /* 1473 * XiveEND helpers 1474 */ 1475 1476 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, GString *buf) 1477 { 1478 uint64_t qaddr_base = xive_end_qaddr(end); 1479 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1480 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1481 uint32_t qentries = 1 << (qsize + 10); 1482 int i; 1483 1484 /* 1485 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1486 */ 1487 g_string_append_printf(buf, " [ "); 1488 qindex = (qindex - (width - 1)) & (qentries - 1); 1489 for (i = 0; i < width; i++) { 1490 uint64_t qaddr = qaddr_base + (qindex << 2); 1491 uint32_t qdata = -1; 1492 1493 if (dma_memory_read(&address_space_memory, qaddr, 1494 &qdata, sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 1495 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1496 HWADDR_PRIx "\n", qaddr); 1497 return; 1498 } 1499 g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "", 1500 be32_to_cpu(qdata)); 1501 qindex = (qindex + 1) & (qentries - 1); 1502 } 1503 g_string_append_c(buf, ']'); 1504 } 1505 1506 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf) 1507 { 1508 uint64_t qaddr_base = xive_end_qaddr(end); 1509 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1510 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1511 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1512 uint32_t qentries = 1 << (qsize + 10); 1513 1514 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1515 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1516 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1517 uint8_t pq; 1518 1519 if (!xive_end_is_valid(end)) { 1520 return; 1521 } 1522 1523 pq = xive_get_field32(END_W1_ESn, end->w1); 1524 1525 g_string_append_printf(buf, 1526 " %08x %c%c %c%c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1527 end_idx, 1528 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1529 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1530 xive_end_is_valid(end) ? 'v' : '-', 1531 xive_end_is_enqueue(end) ? 'q' : '-', 1532 xive_end_is_notify(end) ? 'n' : '-', 1533 xive_end_is_backlog(end) ? 'b' : '-', 1534 xive_end_is_escalate(end) ? 'e' : '-', 1535 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1536 xive_end_is_silent_escalation(end) ? 's' : '-', 1537 xive_end_is_firmware(end) ? 'f' : '-', 1538 priority, nvt_blk, nvt_idx); 1539 1540 if (qaddr_base) { 1541 g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1542 qaddr_base, qindex, qentries, qgen); 1543 xive_end_queue_pic_print_info(end, 6, buf); 1544 } 1545 g_string_append_c(buf, '\n'); 1546 } 1547 1548 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1549 { 1550 uint64_t qaddr_base = xive_end_qaddr(end); 1551 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1552 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1553 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1554 1555 uint64_t qaddr = qaddr_base + (qindex << 2); 1556 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1557 uint32_t qentries = 1 << (qsize + 10); 1558 1559 if (dma_memory_write(&address_space_memory, qaddr, 1560 &qdata, sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 1561 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1562 HWADDR_PRIx "\n", qaddr); 1563 return; 1564 } 1565 1566 qindex = (qindex + 1) & (qentries - 1); 1567 if (qindex == 0) { 1568 qgen ^= 1; 1569 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1570 } 1571 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1572 } 1573 1574 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf) 1575 { 1576 XiveEAS *eas = (XiveEAS *) &end->w4; 1577 uint8_t pq; 1578 1579 if (!xive_end_is_escalate(end)) { 1580 return; 1581 } 1582 1583 pq = xive_get_field32(END_W1_ESe, end->w1); 1584 1585 g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1586 end_idx, 1587 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1588 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1589 xive_eas_is_valid(eas) ? 'V' : ' ', 1590 xive_eas_is_masked(eas) ? 'M' : ' ', 1591 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1592 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1593 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1594 } 1595 1596 /* 1597 * XIVE Router (aka. Virtualization Controller or IVRE) 1598 */ 1599 1600 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1601 XiveEAS *eas) 1602 { 1603 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1604 1605 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1606 } 1607 1608 static 1609 int xive_router_get_pq(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1610 uint8_t *pq) 1611 { 1612 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1613 1614 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); 1615 } 1616 1617 static 1618 int xive_router_set_pq(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1619 uint8_t *pq) 1620 { 1621 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1622 1623 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); 1624 } 1625 1626 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1627 XiveEND *end) 1628 { 1629 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1630 1631 return xrc->get_end(xrtr, end_blk, end_idx, end); 1632 } 1633 1634 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1635 XiveEND *end, uint8_t word_number) 1636 { 1637 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1638 1639 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1640 } 1641 1642 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1643 XiveNVT *nvt) 1644 { 1645 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1646 1647 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1648 } 1649 1650 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1651 XiveNVT *nvt, uint8_t word_number) 1652 { 1653 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1654 1655 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1656 } 1657 1658 static int xive_router_get_block_id(XiveRouter *xrtr) 1659 { 1660 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1661 1662 return xrc->get_block_id(xrtr); 1663 } 1664 1665 static void xive_router_realize(DeviceState *dev, Error **errp) 1666 { 1667 XiveRouter *xrtr = XIVE_ROUTER(dev); 1668 1669 assert(xrtr->xfb); 1670 } 1671 1672 static void xive_router_end_notify_handler(XiveRouter *xrtr, XiveEAS *eas) 1673 { 1674 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1675 1676 return xrc->end_notify(xrtr, eas); 1677 } 1678 1679 /* 1680 * Encode the HW CAM line in the block group mode format : 1681 * 1682 * chip << 19 | 0000000 0 0001 thread (7Bit) 1683 */ 1684 static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 1685 { 1686 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1687 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1688 uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr)); 1689 1690 return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); 1691 } 1692 1693 uint32_t xive_get_vpgroup_size(uint32_t nvp_index) 1694 { 1695 /* 1696 * Group size is a power of 2. The position of the first 0 1697 * (starting with the least significant bits) in the NVP index 1698 * gives the size of the group. 1699 */ 1700 int first_zero = cto32(nvp_index); 1701 if (first_zero >= 31) { 1702 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid group index 0x%08x", 1703 nvp_index); 1704 return 0; 1705 } 1706 1707 return 1U << (first_zero + 1); 1708 } 1709 1710 static uint8_t xive_get_group_level(bool crowd, bool ignore, 1711 uint32_t nvp_blk, uint32_t nvp_index) 1712 { 1713 int first_zero; 1714 uint8_t level; 1715 1716 if (!ignore) { 1717 g_assert(!crowd); 1718 return 0; 1719 } 1720 1721 first_zero = cto32(nvp_index); 1722 if (first_zero >= 31) { 1723 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid group index 0x%08x", 1724 nvp_index); 1725 return 0; 1726 } 1727 1728 level = (first_zero + 1) & 0b1111; 1729 if (crowd) { 1730 uint32_t blk; 1731 1732 /* crowd level is bit position of first 0 from the right in nvp_blk */ 1733 first_zero = cto32(nvp_blk); 1734 if (first_zero >= 31) { 1735 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid crowd block 0x%08x", 1736 nvp_blk); 1737 return 0; 1738 } 1739 blk = first_zero + 1; 1740 1741 /* 1742 * Supported crowd sizes are 2^1, 2^2, and 2^4. 2^3 is not supported. 1743 * HW will encode level 4 as the value 3. See xive2_pgofnext(). 1744 */ 1745 switch (blk) { 1746 case 1: 1747 case 2: 1748 break; 1749 case 4: 1750 blk = 3; 1751 break; 1752 default: 1753 g_assert_not_reached(); 1754 } 1755 1756 /* Crowd level bits reside in upper 2 bits of the 6 bit group level */ 1757 level |= blk << 4; 1758 } 1759 return level; 1760 } 1761 1762 /* 1763 * The thread context register words are in big-endian format. 1764 */ 1765 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1766 uint8_t format, 1767 uint8_t nvt_blk, uint32_t nvt_idx, 1768 bool cam_ignore, uint32_t logic_serv) 1769 { 1770 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1771 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1772 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1773 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1774 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1775 1776 /* 1777 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1778 * identifier are ignored in the "CAM" match. 1779 */ 1780 1781 if (format == 0) { 1782 if (cam_ignore == true) { 1783 /* 1784 * F=0 & i=1: Logical server notification (bits ignored at 1785 * the end of the NVT identifier) 1786 */ 1787 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1788 nvt_blk, nvt_idx); 1789 return -1; 1790 } 1791 1792 /* F=0 & i=0: Specific NVT notification */ 1793 1794 /* PHYS ring */ 1795 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1796 cam == xive_tctx_hw_cam_line(xptr, tctx)) { 1797 return TM_QW3_HV_PHYS; 1798 } 1799 1800 /* HV POOL ring */ 1801 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1802 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1803 return TM_QW2_HV_POOL; 1804 } 1805 1806 /* OS ring */ 1807 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1808 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1809 return TM_QW1_OS; 1810 } 1811 } else { 1812 /* F=1 : User level Event-Based Branch (EBB) notification */ 1813 1814 /* USER ring */ 1815 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1816 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1817 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1818 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1819 return TM_QW0_USER; 1820 } 1821 } 1822 return -1; 1823 } 1824 1825 /* 1826 * This is our simple Xive Presenter Engine model. It is merged in the 1827 * Router as it does not require an extra object. 1828 */ 1829 bool xive_presenter_notify(XiveFabric *xfb, uint8_t format, 1830 uint8_t nvt_blk, uint32_t nvt_idx, 1831 bool crowd, bool cam_ignore, uint8_t priority, 1832 uint32_t logic_serv, bool *precluded) 1833 { 1834 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb); 1835 XiveTCTXMatch match = { .tctx = NULL, .ring = 0, .precluded = false }; 1836 uint8_t group_level; 1837 int count; 1838 1839 /* 1840 * Ask the machine to scan the interrupt controllers for a match. 1841 * 1842 * For VP-specific notification, we expect at most one match and 1843 * one call to the presenters is all we need (abbreviated notify 1844 * sequence documented by the architecture). 1845 * 1846 * For VP-group notification, match_nvt() is the equivalent of the 1847 * "histogram" and "poll" commands sent to the power bus to the 1848 * presenters. 'count' could be more than one, but we always 1849 * select the first match for now. 'precluded' tells if (at least) 1850 * one thread matches but can't take the interrupt now because 1851 * it's running at a more favored priority. We return the 1852 * information to the router so that it can take appropriate 1853 * actions (backlog, escalation, broadcast, etc...) 1854 * 1855 * If we were to implement a better way of dispatching the 1856 * interrupt in case of multiple matches (instead of the first 1857 * match), we would need a heuristic to elect a thread (for 1858 * example, the hardware keeps track of an 'age' in the TIMA) and 1859 * a new command to the presenters (the equivalent of the "assign" 1860 * power bus command in the documented full notify sequence. 1861 */ 1862 count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, crowd, cam_ignore, 1863 priority, logic_serv, &match); 1864 if (count < 0) { 1865 return false; 1866 } 1867 1868 /* handle CPU exception delivery */ 1869 if (count) { 1870 group_level = xive_get_group_level(crowd, cam_ignore, nvt_blk, nvt_idx); 1871 trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring, group_level); 1872 xive_tctx_pipr_update(match.tctx, match.ring, priority, group_level); 1873 } else { 1874 *precluded = match.precluded; 1875 } 1876 1877 return !!count; 1878 } 1879 1880 /* 1881 * Notification using the END ESe/ESn bit (Event State Buffer for 1882 * escalation and notification). Provide further coalescing in the 1883 * Router. 1884 */ 1885 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1886 uint32_t end_idx, XiveEND *end, 1887 uint32_t end_esmask) 1888 { 1889 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1890 bool notify = xive_esb_trigger(&pq); 1891 1892 if (pq != xive_get_field32(end_esmask, end->w1)) { 1893 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1894 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1895 } 1896 1897 /* ESe/n[Q]=1 : end of notification */ 1898 return notify; 1899 } 1900 1901 /* 1902 * An END trigger can come from an event trigger (IPI or HW) or from 1903 * another chip. We don't model the PowerBus but the END trigger 1904 * message has the same parameters than in the function below. 1905 */ 1906 void xive_router_end_notify(XiveRouter *xrtr, XiveEAS *eas) 1907 { 1908 XiveEND end; 1909 uint8_t priority; 1910 uint8_t format; 1911 uint8_t nvt_blk; 1912 uint32_t nvt_idx; 1913 XiveNVT nvt; 1914 bool found, precluded; 1915 1916 uint8_t end_blk = xive_get_field64(EAS_END_BLOCK, eas->w); 1917 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 1918 uint32_t end_data = xive_get_field64(EAS_END_DATA, eas->w); 1919 1920 /* END cache lookup */ 1921 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1922 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1923 end_idx); 1924 return; 1925 } 1926 1927 if (!xive_end_is_valid(&end)) { 1928 trace_xive_router_end_notify(end_blk, end_idx, end_data); 1929 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1930 end_blk, end_idx); 1931 return; 1932 } 1933 1934 if (xive_end_is_enqueue(&end)) { 1935 xive_end_enqueue(&end, end_data); 1936 /* Enqueuing event data modifies the EQ toggle and index */ 1937 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1938 } 1939 1940 /* 1941 * When the END is silent, we skip the notification part. 1942 */ 1943 if (xive_end_is_silent_escalation(&end)) { 1944 goto do_escalation; 1945 } 1946 1947 /* 1948 * The W7 format depends on the F bit in W6. It defines the type 1949 * of the notification : 1950 * 1951 * F=0 : single or multiple NVT notification 1952 * F=1 : User level Event-Based Branch (EBB) notification, no 1953 * priority 1954 */ 1955 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1956 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1957 1958 /* The END is masked */ 1959 if (format == 0 && priority == 0xff) { 1960 return; 1961 } 1962 1963 /* 1964 * Check the END ESn (Event State Buffer for notification) for 1965 * even further coalescing in the Router 1966 */ 1967 if (!xive_end_is_notify(&end)) { 1968 /* ESn[Q]=1 : end of notification */ 1969 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1970 &end, END_W1_ESn)) { 1971 return; 1972 } 1973 } 1974 1975 /* 1976 * Follows IVPE notification 1977 */ 1978 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1979 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1980 1981 /* NVT cache lookup */ 1982 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1983 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1984 nvt_blk, nvt_idx); 1985 return; 1986 } 1987 1988 if (!xive_nvt_is_valid(&nvt)) { 1989 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1990 nvt_blk, nvt_idx); 1991 return; 1992 } 1993 1994 found = xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx, 1995 false /* crowd */, 1996 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1997 priority, 1998 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7), 1999 &precluded); 2000 /* we don't support VP-group notification on P9, so precluded is not used */ 2001 /* TODO: Auto EOI. */ 2002 2003 if (found) { 2004 return; 2005 } 2006 2007 /* 2008 * If no matching NVT is dispatched on a HW thread : 2009 * - specific VP: update the NVT structure if backlog is activated 2010 * - logical server : forward request to IVPE (not supported) 2011 */ 2012 if (xive_end_is_backlog(&end)) { 2013 uint8_t ipb; 2014 2015 if (format == 1) { 2016 qemu_log_mask(LOG_GUEST_ERROR, 2017 "XIVE: END %x/%x invalid config: F1 & backlog\n", 2018 end_blk, end_idx); 2019 return; 2020 } 2021 /* 2022 * Record the IPB in the associated NVT structure for later 2023 * use. The presenter will resend the interrupt when the vCPU 2024 * is dispatched again on a HW thread. 2025 */ 2026 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | 2027 xive_priority_to_ipb(priority); 2028 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); 2029 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 2030 2031 /* 2032 * On HW, follows a "Broadcast Backlog" to IVPEs 2033 */ 2034 } 2035 2036 do_escalation: 2037 /* 2038 * If activated, escalate notification using the ESe PQ bits and 2039 * the EAS in w4-5 2040 */ 2041 if (!xive_end_is_escalate(&end)) { 2042 return; 2043 } 2044 2045 /* 2046 * Check the END ESe (Event State Buffer for escalation) for even 2047 * further coalescing in the Router 2048 */ 2049 if (!xive_end_is_uncond_escalation(&end)) { 2050 /* ESe[Q]=1 : end of notification */ 2051 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 2052 &end, END_W1_ESe)) { 2053 return; 2054 } 2055 } 2056 2057 trace_xive_router_end_escalate(end_blk, end_idx, 2058 (uint8_t) xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 2059 (uint32_t) xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 2060 (uint32_t) xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 2061 /* 2062 * The END trigger becomes an Escalation trigger 2063 */ 2064 xive_router_end_notify_handler(xrtr, (XiveEAS *) &end.w4); 2065 } 2066 2067 void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) 2068 { 2069 XiveRouter *xrtr = XIVE_ROUTER(xn); 2070 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 2071 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 2072 XiveEAS eas; 2073 2074 /* EAS cache lookup */ 2075 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 2076 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 2077 return; 2078 } 2079 2080 if (!pq_checked) { 2081 bool notify; 2082 uint8_t pq; 2083 2084 /* PQ cache lookup */ 2085 if (xive_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) { 2086 /* Set FIR */ 2087 g_assert_not_reached(); 2088 } 2089 2090 notify = xive_esb_trigger(&pq); 2091 2092 if (xive_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) { 2093 /* Set FIR */ 2094 g_assert_not_reached(); 2095 } 2096 2097 if (!notify) { 2098 return; 2099 } 2100 } 2101 2102 if (!xive_eas_is_valid(&eas)) { 2103 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 2104 return; 2105 } 2106 2107 if (xive_eas_is_masked(&eas)) { 2108 /* Notification completed */ 2109 return; 2110 } 2111 2112 /* 2113 * The event trigger becomes an END trigger 2114 */ 2115 xive_router_end_notify_handler(xrtr, &eas); 2116 } 2117 2118 static const Property xive_router_properties[] = { 2119 DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb, 2120 TYPE_XIVE_FABRIC, XiveFabric *), 2121 }; 2122 2123 static void xive_router_class_init(ObjectClass *klass, const void *data) 2124 { 2125 DeviceClass *dc = DEVICE_CLASS(klass); 2126 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 2127 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 2128 2129 dc->desc = "XIVE Router Engine"; 2130 device_class_set_props(dc, xive_router_properties); 2131 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 2132 dc->realize = xive_router_realize; 2133 xnc->notify = xive_router_notify; 2134 2135 /* By default, the router handles END triggers locally */ 2136 xrc->end_notify = xive_router_end_notify; 2137 } 2138 2139 static const TypeInfo xive_router_info = { 2140 .name = TYPE_XIVE_ROUTER, 2141 .parent = TYPE_SYS_BUS_DEVICE, 2142 .abstract = true, 2143 .instance_size = sizeof(XiveRouter), 2144 .class_size = sizeof(XiveRouterClass), 2145 .class_init = xive_router_class_init, 2146 .interfaces = (const InterfaceInfo[]) { 2147 { TYPE_XIVE_NOTIFIER }, 2148 { TYPE_XIVE_PRESENTER }, 2149 { } 2150 } 2151 }; 2152 2153 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, GString *buf) 2154 { 2155 if (!xive_eas_is_valid(eas)) { 2156 return; 2157 } 2158 2159 g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n", 2160 lisn, xive_eas_is_masked(eas) ? "M" : " ", 2161 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 2162 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 2163 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 2164 } 2165 2166 /* 2167 * END ESB MMIO loads 2168 */ 2169 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 2170 { 2171 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 2172 uint32_t offset = addr & 0xFFF; 2173 uint8_t end_blk; 2174 uint32_t end_idx; 2175 XiveEND end; 2176 uint32_t end_esmask; 2177 uint8_t pq; 2178 uint64_t ret = -1; 2179 2180 /* 2181 * The block id should be deduced from the load address on the END 2182 * ESB MMIO but our model only supports a single block per XIVE chip. 2183 */ 2184 end_blk = xive_router_get_block_id(xsrc->xrtr); 2185 end_idx = addr >> (xsrc->esb_shift + 1); 2186 2187 trace_xive_end_source_read(end_blk, end_idx, addr); 2188 2189 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 2190 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 2191 end_idx); 2192 return -1; 2193 } 2194 2195 if (!xive_end_is_valid(&end)) { 2196 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 2197 end_blk, end_idx); 2198 return -1; 2199 } 2200 2201 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 2202 pq = xive_get_field32(end_esmask, end.w1); 2203 2204 switch (offset) { 2205 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 2206 ret = xive_esb_eoi(&pq); 2207 2208 /* Forward the source event notification for routing ?? */ 2209 break; 2210 2211 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 2212 ret = pq; 2213 break; 2214 2215 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 2216 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 2217 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 2218 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 2219 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 2220 break; 2221 default: 2222 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 2223 offset); 2224 return -1; 2225 } 2226 2227 if (pq != xive_get_field32(end_esmask, end.w1)) { 2228 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 2229 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 2230 } 2231 2232 return ret; 2233 } 2234 2235 /* 2236 * END ESB MMIO stores are invalid 2237 */ 2238 static void xive_end_source_write(void *opaque, hwaddr addr, 2239 uint64_t value, unsigned size) 2240 { 2241 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 2242 HWADDR_PRIx"\n", addr); 2243 } 2244 2245 static const MemoryRegionOps xive_end_source_ops = { 2246 .read = xive_end_source_read, 2247 .write = xive_end_source_write, 2248 .endianness = DEVICE_BIG_ENDIAN, 2249 .valid = { 2250 .min_access_size = 1, 2251 .max_access_size = 8, 2252 }, 2253 .impl = { 2254 .min_access_size = 1, 2255 .max_access_size = 8, 2256 }, 2257 }; 2258 2259 static void xive_end_source_realize(DeviceState *dev, Error **errp) 2260 { 2261 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 2262 2263 assert(xsrc->xrtr); 2264 2265 if (!xsrc->nr_ends) { 2266 error_setg(errp, "Number of interrupt needs to be greater than 0"); 2267 return; 2268 } 2269 2270 if (xsrc->esb_shift != XIVE_ESB_4K && 2271 xsrc->esb_shift != XIVE_ESB_64K) { 2272 error_setg(errp, "Invalid ESB shift setting"); 2273 return; 2274 } 2275 2276 /* 2277 * Each END is assigned an even/odd pair of MMIO pages, the even page 2278 * manages the ESn field while the odd page manages the ESe field. 2279 */ 2280 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 2281 &xive_end_source_ops, xsrc, "xive.end", 2282 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 2283 } 2284 2285 static const Property xive_end_source_properties[] = { 2286 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 2287 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 2288 DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, 2289 XiveRouter *), 2290 }; 2291 2292 static void xive_end_source_class_init(ObjectClass *klass, const void *data) 2293 { 2294 DeviceClass *dc = DEVICE_CLASS(klass); 2295 2296 dc->desc = "XIVE END Source"; 2297 device_class_set_props(dc, xive_end_source_properties); 2298 dc->realize = xive_end_source_realize; 2299 /* 2300 * Reason: part of XIVE interrupt controller, needs to be wired up, 2301 * e.g. by spapr_xive_instance_init(). 2302 */ 2303 dc->user_creatable = false; 2304 } 2305 2306 static const TypeInfo xive_end_source_info = { 2307 .name = TYPE_XIVE_END_SOURCE, 2308 .parent = TYPE_DEVICE, 2309 .instance_size = sizeof(XiveENDSource), 2310 .class_init = xive_end_source_class_init, 2311 }; 2312 2313 /* 2314 * XIVE Notifier 2315 */ 2316 static const TypeInfo xive_notifier_info = { 2317 .name = TYPE_XIVE_NOTIFIER, 2318 .parent = TYPE_INTERFACE, 2319 .class_size = sizeof(XiveNotifierClass), 2320 }; 2321 2322 /* 2323 * XIVE Presenter 2324 */ 2325 static const TypeInfo xive_presenter_info = { 2326 .name = TYPE_XIVE_PRESENTER, 2327 .parent = TYPE_INTERFACE, 2328 .class_size = sizeof(XivePresenterClass), 2329 }; 2330 2331 /* 2332 * XIVE Fabric 2333 */ 2334 static const TypeInfo xive_fabric_info = { 2335 .name = TYPE_XIVE_FABRIC, 2336 .parent = TYPE_INTERFACE, 2337 .class_size = sizeof(XiveFabricClass), 2338 }; 2339 2340 static void xive_register_types(void) 2341 { 2342 type_register_static(&xive_fabric_info); 2343 type_register_static(&xive_source_info); 2344 type_register_static(&xive_notifier_info); 2345 type_register_static(&xive_presenter_info); 2346 type_register_static(&xive_router_info); 2347 type_register_static(&xive_end_source_info); 2348 type_register_static(&xive_tctx_info); 2349 } 2350 2351 type_init(xive_register_types) 2352