1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "monitor/monitor.h" 21 #include "hw/irq.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive_regs.h" 24 25 /* 26 * XIVE Thread Interrupt Management context 27 */ 28 29 /* 30 * Convert a priority number to an Interrupt Pending Buffer (IPB) 31 * register, which indicates a pending interrupt at the priority 32 * corresponding to the bit number 33 */ 34 static uint8_t priority_to_ipb(uint8_t priority) 35 { 36 return priority > XIVE_PRIORITY_MAX ? 37 0 : 1 << (XIVE_PRIORITY_MAX - priority); 38 } 39 40 /* 41 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 42 * Interrupt Priority Register (PIPR), which contains the priority of 43 * the most favored pending notification. 44 */ 45 static uint8_t ipb_to_pipr(uint8_t ibp) 46 { 47 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 48 } 49 50 static void ipb_update(uint8_t *regs, uint8_t priority) 51 { 52 regs[TM_IPB] |= priority_to_ipb(priority); 53 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 54 } 55 56 static uint8_t exception_mask(uint8_t ring) 57 { 58 switch (ring) { 59 case TM_QW1_OS: 60 return TM_QW1_NSR_EO; 61 case TM_QW3_HV_PHYS: 62 return TM_QW3_NSR_HE; 63 default: 64 g_assert_not_reached(); 65 } 66 } 67 68 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 69 { 70 switch (ring) { 71 case TM_QW0_USER: 72 return 0; /* Not supported */ 73 case TM_QW1_OS: 74 return tctx->os_output; 75 case TM_QW2_HV_POOL: 76 case TM_QW3_HV_PHYS: 77 return tctx->hv_output; 78 default: 79 return 0; 80 } 81 } 82 83 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 84 { 85 uint8_t *regs = &tctx->regs[ring]; 86 uint8_t nsr = regs[TM_NSR]; 87 uint8_t mask = exception_mask(ring); 88 89 qemu_irq_lower(xive_tctx_output(tctx, ring)); 90 91 if (regs[TM_NSR] & mask) { 92 uint8_t cppr = regs[TM_PIPR]; 93 94 regs[TM_CPPR] = cppr; 95 96 /* Reset the pending buffer bit */ 97 regs[TM_IPB] &= ~priority_to_ipb(cppr); 98 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 99 100 /* Drop Exception bit */ 101 regs[TM_NSR] &= ~mask; 102 } 103 104 return (nsr << 8) | regs[TM_CPPR]; 105 } 106 107 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 108 { 109 uint8_t *regs = &tctx->regs[ring]; 110 111 if (regs[TM_PIPR] < regs[TM_CPPR]) { 112 switch (ring) { 113 case TM_QW1_OS: 114 regs[TM_NSR] |= TM_QW1_NSR_EO; 115 break; 116 case TM_QW3_HV_PHYS: 117 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 118 break; 119 default: 120 g_assert_not_reached(); 121 } 122 qemu_irq_raise(xive_tctx_output(tctx, ring)); 123 } 124 } 125 126 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 127 { 128 if (cppr > XIVE_PRIORITY_MAX) { 129 cppr = 0xff; 130 } 131 132 tctx->regs[ring + TM_CPPR] = cppr; 133 134 /* CPPR has changed, check if we need to raise a pending exception */ 135 xive_tctx_notify(tctx, ring); 136 } 137 138 static inline uint32_t xive_tctx_word2(uint8_t *ring) 139 { 140 return *((uint32_t *) &ring[TM_WORD2]); 141 } 142 143 /* 144 * XIVE Thread Interrupt Management Area (TIMA) 145 */ 146 147 static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset, 148 uint64_t value, unsigned size) 149 { 150 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 151 } 152 153 static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) 154 { 155 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 156 } 157 158 static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, 159 unsigned size) 160 { 161 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 162 uint32_t qw2w2; 163 164 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 165 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 166 return qw2w2; 167 } 168 169 static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset, 170 uint64_t value, unsigned size) 171 { 172 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 173 } 174 175 static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned size) 176 { 177 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 178 } 179 180 /* 181 * Define an access map for each page of the TIMA that we will use in 182 * the memory region ops to filter values when doing loads and stores 183 * of raw registers values 184 * 185 * Registers accessibility bits : 186 * 187 * 0x0 - no access 188 * 0x1 - write only 189 * 0x2 - read only 190 * 0x3 - read/write 191 */ 192 193 static const uint8_t xive_tm_hw_view[] = { 194 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 195 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 196 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 197 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 198 }; 199 200 static const uint8_t xive_tm_hv_view[] = { 201 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 202 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 203 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 204 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 205 }; 206 207 static const uint8_t xive_tm_os_view[] = { 208 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 209 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 210 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 211 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 212 }; 213 214 static const uint8_t xive_tm_user_view[] = { 215 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 219 }; 220 221 /* 222 * Overall TIMA access map for the thread interrupt management context 223 * registers 224 */ 225 static const uint8_t *xive_tm_views[] = { 226 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 227 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 228 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 229 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 230 }; 231 232 /* 233 * Computes a register access mask for a given offset in the TIMA 234 */ 235 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 236 { 237 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 238 uint8_t reg_offset = offset & 0x3F; 239 uint8_t reg_mask = write ? 0x1 : 0x2; 240 uint64_t mask = 0x0; 241 int i; 242 243 for (i = 0; i < size; i++) { 244 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 245 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 246 } 247 } 248 249 return mask; 250 } 251 252 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 253 unsigned size) 254 { 255 uint8_t ring_offset = offset & 0x30; 256 uint8_t reg_offset = offset & 0x3F; 257 uint64_t mask = xive_tm_mask(offset, size, true); 258 int i; 259 260 /* 261 * Only 4 or 8 bytes stores are allowed and the User ring is 262 * excluded 263 */ 264 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 265 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 266 HWADDR_PRIx"\n", offset); 267 return; 268 } 269 270 /* 271 * Use the register offset for the raw values and filter out 272 * reserved values 273 */ 274 for (i = 0; i < size; i++) { 275 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 276 if (byte_mask) { 277 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 278 byte_mask; 279 } 280 } 281 } 282 283 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 284 { 285 uint8_t ring_offset = offset & 0x30; 286 uint8_t reg_offset = offset & 0x3F; 287 uint64_t mask = xive_tm_mask(offset, size, false); 288 uint64_t ret; 289 int i; 290 291 /* 292 * Only 4 or 8 bytes loads are allowed and the User ring is 293 * excluded 294 */ 295 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 296 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 297 HWADDR_PRIx"\n", offset); 298 return -1; 299 } 300 301 /* Use the register offset for the raw values */ 302 ret = 0; 303 for (i = 0; i < size; i++) { 304 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 305 } 306 307 /* filter out reserved values */ 308 return ret & mask; 309 } 310 311 /* 312 * The TM context is mapped twice within each page. Stores and loads 313 * to the first mapping below 2K write and read the specified values 314 * without modification. The second mapping above 2K performs specific 315 * state changes (side effects) in addition to setting/returning the 316 * interrupt management area context of the processor thread. 317 */ 318 static uint64_t xive_tm_ack_os_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) 319 { 320 return xive_tctx_accept(tctx, TM_QW1_OS); 321 } 322 323 static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset, 324 uint64_t value, unsigned size) 325 { 326 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 327 } 328 329 /* 330 * Adjust the IPB to allow a CPU to process event queues of other 331 * priorities during one physical interrupt cycle. 332 */ 333 static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset, 334 uint64_t value, unsigned size) 335 { 336 ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff); 337 xive_tctx_notify(tctx, TM_QW1_OS); 338 } 339 340 static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, 341 uint32_t *nvt_idx, bool *vo) 342 { 343 if (nvt_blk) { 344 *nvt_blk = xive_nvt_blk(cam); 345 } 346 if (nvt_idx) { 347 *nvt_idx = xive_nvt_idx(cam); 348 } 349 if (vo) { 350 *vo = !!(cam & TM_QW1W2_VO); 351 } 352 } 353 354 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk, 355 uint32_t *nvt_idx, bool *vo) 356 { 357 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 358 uint32_t cam = be32_to_cpu(qw1w2); 359 360 xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo); 361 return qw1w2; 362 } 363 364 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) 365 { 366 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 367 } 368 369 static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset, 370 unsigned size) 371 { 372 uint32_t qw1w2; 373 uint32_t qw1w2_new; 374 uint8_t nvt_blk; 375 uint32_t nvt_idx; 376 bool vo; 377 378 qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); 379 380 if (!vo) { 381 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n", 382 nvt_blk, nvt_idx); 383 } 384 385 /* Invalidate CAM line */ 386 qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); 387 xive_tctx_set_os_cam(tctx, qw1w2_new); 388 return qw1w2; 389 } 390 391 /* 392 * Define a mapping of "special" operations depending on the TIMA page 393 * offset and the size of the operation. 394 */ 395 typedef struct XiveTmOp { 396 uint8_t page_offset; 397 uint32_t op_offset; 398 unsigned size; 399 void (*write_handler)(XiveTCTX *tctx, hwaddr offset, uint64_t value, 400 unsigned size); 401 uint64_t (*read_handler)(XiveTCTX *tctx, hwaddr offset, unsigned size); 402 } XiveTmOp; 403 404 static const XiveTmOp xive_tm_operations[] = { 405 /* 406 * MMIOs below 2K : raw values and special operations without side 407 * effects 408 */ 409 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 410 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 411 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 412 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 413 414 /* MMIOs above 2K : special operations with side effects */ 415 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 416 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 417 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, 418 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, 419 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 420 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 421 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 422 }; 423 424 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 425 { 426 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 427 uint32_t op_offset = offset & 0xFFF; 428 int i; 429 430 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 431 const XiveTmOp *xto = &xive_tm_operations[i]; 432 433 /* Accesses done from a more privileged TIMA page is allowed */ 434 if (xto->page_offset >= page_offset && 435 xto->op_offset == op_offset && 436 xto->size == size && 437 ((write && xto->write_handler) || (!write && xto->read_handler))) { 438 return xto; 439 } 440 } 441 return NULL; 442 } 443 444 /* 445 * TIMA MMIO handlers 446 */ 447 void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 448 unsigned size) 449 { 450 const XiveTmOp *xto; 451 452 /* 453 * TODO: check V bit in Q[0-3]W2 454 */ 455 456 /* 457 * First, check for special operations in the 2K region 458 */ 459 if (offset & 0x800) { 460 xto = xive_tm_find_op(offset, size, true); 461 if (!xto) { 462 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 463 "@%"HWADDR_PRIx"\n", offset); 464 } else { 465 xto->write_handler(tctx, offset, value, size); 466 } 467 return; 468 } 469 470 /* 471 * Then, for special operations in the region below 2K. 472 */ 473 xto = xive_tm_find_op(offset, size, true); 474 if (xto) { 475 xto->write_handler(tctx, offset, value, size); 476 return; 477 } 478 479 /* 480 * Finish with raw access to the register values 481 */ 482 xive_tm_raw_write(tctx, offset, value, size); 483 } 484 485 uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 486 { 487 const XiveTmOp *xto; 488 489 /* 490 * TODO: check V bit in Q[0-3]W2 491 */ 492 493 /* 494 * First, check for special operations in the 2K region 495 */ 496 if (offset & 0x800) { 497 xto = xive_tm_find_op(offset, size, false); 498 if (!xto) { 499 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 500 "@%"HWADDR_PRIx"\n", offset); 501 return -1; 502 } 503 return xto->read_handler(tctx, offset, size); 504 } 505 506 /* 507 * Then, for special operations in the region below 2K. 508 */ 509 xto = xive_tm_find_op(offset, size, false); 510 if (xto) { 511 return xto->read_handler(tctx, offset, size); 512 } 513 514 /* 515 * Finish with raw access to the register values 516 */ 517 return xive_tm_raw_read(tctx, offset, size); 518 } 519 520 static void xive_tm_write(void *opaque, hwaddr offset, 521 uint64_t value, unsigned size) 522 { 523 XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); 524 525 xive_tctx_tm_write(tctx, offset, value, size); 526 } 527 528 static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) 529 { 530 XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); 531 532 return xive_tctx_tm_read(tctx, offset, size); 533 } 534 535 const MemoryRegionOps xive_tm_ops = { 536 .read = xive_tm_read, 537 .write = xive_tm_write, 538 .endianness = DEVICE_BIG_ENDIAN, 539 .valid = { 540 .min_access_size = 1, 541 .max_access_size = 8, 542 }, 543 .impl = { 544 .min_access_size = 1, 545 .max_access_size = 8, 546 }, 547 }; 548 549 static char *xive_tctx_ring_print(uint8_t *ring) 550 { 551 uint32_t w2 = xive_tctx_word2(ring); 552 553 return g_strdup_printf("%02x %02x %02x %02x %02x " 554 "%02x %02x %02x %08x", 555 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 556 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 557 be32_to_cpu(w2)); 558 } 559 560 static const char * const xive_tctx_ring_names[] = { 561 "USER", "OS", "POOL", "PHYS", 562 }; 563 564 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 565 { 566 int cpu_index; 567 int i; 568 569 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs 570 * are hot plugged or unplugged. 571 */ 572 if (!tctx) { 573 return; 574 } 575 576 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 577 578 if (kvm_irqchip_in_kernel()) { 579 Error *local_err = NULL; 580 581 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 582 if (local_err) { 583 error_report_err(local_err); 584 return; 585 } 586 } 587 588 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 589 " W2\n", cpu_index); 590 591 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 592 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 593 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 594 xive_tctx_ring_names[i], s); 595 g_free(s); 596 } 597 } 598 599 void xive_tctx_reset(XiveTCTX *tctx) 600 { 601 memset(tctx->regs, 0, sizeof(tctx->regs)); 602 603 /* Set some defaults */ 604 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 605 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 606 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 607 608 /* 609 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 610 * CPPR is first set. 611 */ 612 tctx->regs[TM_QW1_OS + TM_PIPR] = 613 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 614 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 615 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 616 } 617 618 static void xive_tctx_realize(DeviceState *dev, Error **errp) 619 { 620 XiveTCTX *tctx = XIVE_TCTX(dev); 621 PowerPCCPU *cpu; 622 CPUPPCState *env; 623 Error *local_err = NULL; 624 625 assert(tctx->cs); 626 627 cpu = POWERPC_CPU(tctx->cs); 628 env = &cpu->env; 629 switch (PPC_INPUT(env)) { 630 case PPC_FLAGS_INPUT_POWER9: 631 tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT]; 632 tctx->os_output = env->irq_inputs[POWER9_INPUT_INT]; 633 break; 634 635 default: 636 error_setg(errp, "XIVE interrupt controller does not support " 637 "this CPU bus model"); 638 return; 639 } 640 641 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 642 if (kvm_irqchip_in_kernel()) { 643 kvmppc_xive_cpu_connect(tctx, &local_err); 644 if (local_err) { 645 error_propagate(errp, local_err); 646 return; 647 } 648 } 649 } 650 651 static int vmstate_xive_tctx_pre_save(void *opaque) 652 { 653 Error *local_err = NULL; 654 655 if (kvm_irqchip_in_kernel()) { 656 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque), &local_err); 657 if (local_err) { 658 error_report_err(local_err); 659 return -1; 660 } 661 } 662 663 return 0; 664 } 665 666 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 667 { 668 Error *local_err = NULL; 669 670 if (kvm_irqchip_in_kernel()) { 671 /* 672 * Required for hotplugged CPU, for which the state comes 673 * after all states of the machine. 674 */ 675 kvmppc_xive_cpu_set_state(XIVE_TCTX(opaque), &local_err); 676 if (local_err) { 677 error_report_err(local_err); 678 return -1; 679 } 680 } 681 682 return 0; 683 } 684 685 static const VMStateDescription vmstate_xive_tctx = { 686 .name = TYPE_XIVE_TCTX, 687 .version_id = 1, 688 .minimum_version_id = 1, 689 .pre_save = vmstate_xive_tctx_pre_save, 690 .post_load = vmstate_xive_tctx_post_load, 691 .fields = (VMStateField[]) { 692 VMSTATE_BUFFER(regs, XiveTCTX), 693 VMSTATE_END_OF_LIST() 694 }, 695 }; 696 697 static Property xive_tctx_properties[] = { 698 DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), 699 DEFINE_PROP_END_OF_LIST(), 700 }; 701 702 static void xive_tctx_class_init(ObjectClass *klass, void *data) 703 { 704 DeviceClass *dc = DEVICE_CLASS(klass); 705 706 dc->desc = "XIVE Interrupt Thread Context"; 707 dc->realize = xive_tctx_realize; 708 dc->vmsd = &vmstate_xive_tctx; 709 dc->props = xive_tctx_properties; 710 /* 711 * Reason: part of XIVE interrupt controller, needs to be wired up 712 * by xive_tctx_create(). 713 */ 714 dc->user_creatable = false; 715 } 716 717 static const TypeInfo xive_tctx_info = { 718 .name = TYPE_XIVE_TCTX, 719 .parent = TYPE_DEVICE, 720 .instance_size = sizeof(XiveTCTX), 721 .class_init = xive_tctx_class_init, 722 }; 723 724 Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) 725 { 726 Error *local_err = NULL; 727 Object *obj; 728 729 obj = object_new(TYPE_XIVE_TCTX); 730 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); 731 object_unref(obj); 732 object_property_set_link(obj, cpu, "cpu", &error_abort); 733 object_property_set_bool(obj, true, "realized", &local_err); 734 if (local_err) { 735 goto error; 736 } 737 738 return obj; 739 740 error: 741 object_unparent(obj); 742 error_propagate(errp, local_err); 743 return NULL; 744 } 745 746 void xive_tctx_destroy(XiveTCTX *tctx) 747 { 748 Object *obj = OBJECT(tctx); 749 750 object_unparent(obj); 751 } 752 753 /* 754 * XIVE ESB helpers 755 */ 756 757 static uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 758 { 759 uint8_t old_pq = *pq & 0x3; 760 761 *pq &= ~0x3; 762 *pq |= value & 0x3; 763 764 return old_pq; 765 } 766 767 static bool xive_esb_trigger(uint8_t *pq) 768 { 769 uint8_t old_pq = *pq & 0x3; 770 771 switch (old_pq) { 772 case XIVE_ESB_RESET: 773 xive_esb_set(pq, XIVE_ESB_PENDING); 774 return true; 775 case XIVE_ESB_PENDING: 776 case XIVE_ESB_QUEUED: 777 xive_esb_set(pq, XIVE_ESB_QUEUED); 778 return false; 779 case XIVE_ESB_OFF: 780 xive_esb_set(pq, XIVE_ESB_OFF); 781 return false; 782 default: 783 g_assert_not_reached(); 784 } 785 } 786 787 static bool xive_esb_eoi(uint8_t *pq) 788 { 789 uint8_t old_pq = *pq & 0x3; 790 791 switch (old_pq) { 792 case XIVE_ESB_RESET: 793 case XIVE_ESB_PENDING: 794 xive_esb_set(pq, XIVE_ESB_RESET); 795 return false; 796 case XIVE_ESB_QUEUED: 797 xive_esb_set(pq, XIVE_ESB_PENDING); 798 return true; 799 case XIVE_ESB_OFF: 800 xive_esb_set(pq, XIVE_ESB_OFF); 801 return false; 802 default: 803 g_assert_not_reached(); 804 } 805 } 806 807 /* 808 * XIVE Interrupt Source (or IVSE) 809 */ 810 811 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 812 { 813 assert(srcno < xsrc->nr_irqs); 814 815 return xsrc->status[srcno] & 0x3; 816 } 817 818 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 819 { 820 assert(srcno < xsrc->nr_irqs); 821 822 return xive_esb_set(&xsrc->status[srcno], pq); 823 } 824 825 /* 826 * Returns whether the event notification should be forwarded. 827 */ 828 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 829 { 830 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 831 832 xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; 833 834 switch (old_pq) { 835 case XIVE_ESB_RESET: 836 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 837 return true; 838 default: 839 return false; 840 } 841 } 842 843 /* 844 * Returns whether the event notification should be forwarded. 845 */ 846 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 847 { 848 bool ret; 849 850 assert(srcno < xsrc->nr_irqs); 851 852 ret = xive_esb_trigger(&xsrc->status[srcno]); 853 854 if (xive_source_irq_is_lsi(xsrc, srcno) && 855 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 856 qemu_log_mask(LOG_GUEST_ERROR, 857 "XIVE: queued an event on LSI IRQ %d\n", srcno); 858 } 859 860 return ret; 861 } 862 863 /* 864 * Returns whether the event notification should be forwarded. 865 */ 866 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 867 { 868 bool ret; 869 870 assert(srcno < xsrc->nr_irqs); 871 872 ret = xive_esb_eoi(&xsrc->status[srcno]); 873 874 /* 875 * LSI sources do not set the Q bit but they can still be 876 * asserted, in which case we should forward a new event 877 * notification 878 */ 879 if (xive_source_irq_is_lsi(xsrc, srcno) && 880 xsrc->status[srcno] & XIVE_STATUS_ASSERTED) { 881 ret = xive_source_lsi_trigger(xsrc, srcno); 882 } 883 884 return ret; 885 } 886 887 /* 888 * Forward the source event notification to the Router 889 */ 890 static void xive_source_notify(XiveSource *xsrc, int srcno) 891 { 892 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 893 894 if (xnc->notify) { 895 xnc->notify(xsrc->xive, srcno); 896 } 897 } 898 899 /* 900 * In a two pages ESB MMIO setting, even page is the trigger page, odd 901 * page is for management 902 */ 903 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 904 { 905 return !((addr >> shift) & 1); 906 } 907 908 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 909 { 910 return xive_source_esb_has_2page(xsrc) && 911 addr_is_even(addr, xsrc->esb_shift - 1); 912 } 913 914 /* 915 * ESB MMIO loads 916 * Trigger page Management/EOI page 917 * 918 * ESB MMIO setting 2 pages 1 or 2 pages 919 * 920 * 0x000 .. 0x3FF -1 EOI and return 0|1 921 * 0x400 .. 0x7FF -1 EOI and return 0|1 922 * 0x800 .. 0xBFF -1 return PQ 923 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 924 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 925 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 926 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 927 */ 928 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 929 { 930 XiveSource *xsrc = XIVE_SOURCE(opaque); 931 uint32_t offset = addr & 0xFFF; 932 uint32_t srcno = addr >> xsrc->esb_shift; 933 uint64_t ret = -1; 934 935 /* In a two pages ESB MMIO setting, trigger page should not be read */ 936 if (xive_source_is_trigger_page(xsrc, addr)) { 937 qemu_log_mask(LOG_GUEST_ERROR, 938 "XIVE: invalid load on IRQ %d trigger page at " 939 "0x%"HWADDR_PRIx"\n", srcno, addr); 940 return -1; 941 } 942 943 switch (offset) { 944 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 945 ret = xive_source_esb_eoi(xsrc, srcno); 946 947 /* Forward the source event notification for routing */ 948 if (ret) { 949 xive_source_notify(xsrc, srcno); 950 } 951 break; 952 953 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 954 ret = xive_source_esb_get(xsrc, srcno); 955 break; 956 957 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 958 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 959 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 960 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 961 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 962 break; 963 default: 964 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 965 offset); 966 } 967 968 return ret; 969 } 970 971 /* 972 * ESB MMIO stores 973 * Trigger page Management/EOI page 974 * 975 * ESB MMIO setting 2 pages 1 or 2 pages 976 * 977 * 0x000 .. 0x3FF Trigger Trigger 978 * 0x400 .. 0x7FF Trigger EOI 979 * 0x800 .. 0xBFF Trigger undefined 980 * 0xC00 .. 0xCFF Trigger PQ=00 981 * 0xD00 .. 0xDFF Trigger PQ=01 982 * 0xE00 .. 0xDFF Trigger PQ=10 983 * 0xF00 .. 0xDFF Trigger PQ=11 984 */ 985 static void xive_source_esb_write(void *opaque, hwaddr addr, 986 uint64_t value, unsigned size) 987 { 988 XiveSource *xsrc = XIVE_SOURCE(opaque); 989 uint32_t offset = addr & 0xFFF; 990 uint32_t srcno = addr >> xsrc->esb_shift; 991 bool notify = false; 992 993 /* In a two pages ESB MMIO setting, trigger page only triggers */ 994 if (xive_source_is_trigger_page(xsrc, addr)) { 995 notify = xive_source_esb_trigger(xsrc, srcno); 996 goto out; 997 } 998 999 switch (offset) { 1000 case 0 ... 0x3FF: 1001 notify = xive_source_esb_trigger(xsrc, srcno); 1002 break; 1003 1004 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 1005 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 1006 qemu_log_mask(LOG_GUEST_ERROR, 1007 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 1008 return; 1009 } 1010 1011 notify = xive_source_esb_eoi(xsrc, srcno); 1012 break; 1013 1014 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1015 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1016 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1017 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1018 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 1019 break; 1020 1021 default: 1022 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 1023 offset); 1024 return; 1025 } 1026 1027 out: 1028 /* Forward the source event notification for routing */ 1029 if (notify) { 1030 xive_source_notify(xsrc, srcno); 1031 } 1032 } 1033 1034 static const MemoryRegionOps xive_source_esb_ops = { 1035 .read = xive_source_esb_read, 1036 .write = xive_source_esb_write, 1037 .endianness = DEVICE_BIG_ENDIAN, 1038 .valid = { 1039 .min_access_size = 8, 1040 .max_access_size = 8, 1041 }, 1042 .impl = { 1043 .min_access_size = 8, 1044 .max_access_size = 8, 1045 }, 1046 }; 1047 1048 void xive_source_set_irq(void *opaque, int srcno, int val) 1049 { 1050 XiveSource *xsrc = XIVE_SOURCE(opaque); 1051 bool notify = false; 1052 1053 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1054 if (val) { 1055 notify = xive_source_lsi_trigger(xsrc, srcno); 1056 } else { 1057 xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; 1058 } 1059 } else { 1060 if (val) { 1061 notify = xive_source_esb_trigger(xsrc, srcno); 1062 } 1063 } 1064 1065 /* Forward the source event notification for routing */ 1066 if (notify) { 1067 xive_source_notify(xsrc, srcno); 1068 } 1069 } 1070 1071 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 1072 { 1073 int i; 1074 1075 for (i = 0; i < xsrc->nr_irqs; i++) { 1076 uint8_t pq = xive_source_esb_get(xsrc, i); 1077 1078 if (pq == XIVE_ESB_OFF) { 1079 continue; 1080 } 1081 1082 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 1083 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1084 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1085 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1086 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' '); 1087 } 1088 } 1089 1090 static void xive_source_reset(void *dev) 1091 { 1092 XiveSource *xsrc = XIVE_SOURCE(dev); 1093 1094 /* Do not clear the LSI bitmap */ 1095 1096 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 1097 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 1098 } 1099 1100 static void xive_source_realize(DeviceState *dev, Error **errp) 1101 { 1102 XiveSource *xsrc = XIVE_SOURCE(dev); 1103 1104 assert(xsrc->xive); 1105 1106 if (!xsrc->nr_irqs) { 1107 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1108 return; 1109 } 1110 1111 if (xsrc->esb_shift != XIVE_ESB_4K && 1112 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1113 xsrc->esb_shift != XIVE_ESB_64K && 1114 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1115 error_setg(errp, "Invalid ESB shift setting"); 1116 return; 1117 } 1118 1119 xsrc->status = g_malloc0(xsrc->nr_irqs); 1120 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1121 1122 if (!kvm_irqchip_in_kernel()) { 1123 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1124 &xive_source_esb_ops, xsrc, "xive.esb", 1125 (1ull << xsrc->esb_shift) * xsrc->nr_irqs); 1126 } 1127 1128 qemu_register_reset(xive_source_reset, dev); 1129 } 1130 1131 static const VMStateDescription vmstate_xive_source = { 1132 .name = TYPE_XIVE_SOURCE, 1133 .version_id = 1, 1134 .minimum_version_id = 1, 1135 .fields = (VMStateField[]) { 1136 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1137 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1138 VMSTATE_END_OF_LIST() 1139 }, 1140 }; 1141 1142 /* 1143 * The default XIVE interrupt source setting for the ESB MMIOs is two 1144 * 64k pages without Store EOI, to be in sync with KVM. 1145 */ 1146 static Property xive_source_properties[] = { 1147 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1148 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1149 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1150 DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, 1151 XiveNotifier *), 1152 DEFINE_PROP_END_OF_LIST(), 1153 }; 1154 1155 static void xive_source_class_init(ObjectClass *klass, void *data) 1156 { 1157 DeviceClass *dc = DEVICE_CLASS(klass); 1158 1159 dc->desc = "XIVE Interrupt Source"; 1160 dc->props = xive_source_properties; 1161 dc->realize = xive_source_realize; 1162 dc->vmsd = &vmstate_xive_source; 1163 /* 1164 * Reason: part of XIVE interrupt controller, needs to be wired up, 1165 * e.g. by spapr_xive_instance_init(). 1166 */ 1167 dc->user_creatable = false; 1168 } 1169 1170 static const TypeInfo xive_source_info = { 1171 .name = TYPE_XIVE_SOURCE, 1172 .parent = TYPE_DEVICE, 1173 .instance_size = sizeof(XiveSource), 1174 .class_init = xive_source_class_init, 1175 }; 1176 1177 /* 1178 * XiveEND helpers 1179 */ 1180 1181 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1182 { 1183 uint64_t qaddr_base = xive_end_qaddr(end); 1184 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1185 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1186 uint32_t qentries = 1 << (qsize + 10); 1187 int i; 1188 1189 /* 1190 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1191 */ 1192 monitor_printf(mon, " [ "); 1193 qindex = (qindex - (width - 1)) & (qentries - 1); 1194 for (i = 0; i < width; i++) { 1195 uint64_t qaddr = qaddr_base + (qindex << 2); 1196 uint32_t qdata = -1; 1197 1198 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 1199 sizeof(qdata))) { 1200 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1201 HWADDR_PRIx "\n", qaddr); 1202 return; 1203 } 1204 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1205 be32_to_cpu(qdata)); 1206 qindex = (qindex + 1) & (qentries - 1); 1207 } 1208 monitor_printf(mon, "]"); 1209 } 1210 1211 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1212 { 1213 uint64_t qaddr_base = xive_end_qaddr(end); 1214 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1215 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1216 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1217 uint32_t qentries = 1 << (qsize + 10); 1218 1219 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1220 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1221 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1222 uint8_t pq; 1223 1224 if (!xive_end_is_valid(end)) { 1225 return; 1226 } 1227 1228 pq = xive_get_field32(END_W1_ESn, end->w1); 1229 1230 monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1231 end_idx, 1232 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1233 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1234 xive_end_is_valid(end) ? 'v' : '-', 1235 xive_end_is_enqueue(end) ? 'q' : '-', 1236 xive_end_is_notify(end) ? 'n' : '-', 1237 xive_end_is_backlog(end) ? 'b' : '-', 1238 xive_end_is_escalate(end) ? 'e' : '-', 1239 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1240 xive_end_is_silent_escalation(end) ? 's' : '-', 1241 priority, nvt_blk, nvt_idx); 1242 1243 if (qaddr_base) { 1244 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1245 qaddr_base, qindex, qentries, qgen); 1246 xive_end_queue_pic_print_info(end, 6, mon); 1247 } 1248 monitor_printf(mon, "\n"); 1249 } 1250 1251 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1252 { 1253 uint64_t qaddr_base = xive_end_qaddr(end); 1254 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1255 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1256 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1257 1258 uint64_t qaddr = qaddr_base + (qindex << 2); 1259 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1260 uint32_t qentries = 1 << (qsize + 10); 1261 1262 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) { 1263 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1264 HWADDR_PRIx "\n", qaddr); 1265 return; 1266 } 1267 1268 qindex = (qindex + 1) & (qentries - 1); 1269 if (qindex == 0) { 1270 qgen ^= 1; 1271 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1272 } 1273 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1274 } 1275 1276 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, 1277 Monitor *mon) 1278 { 1279 XiveEAS *eas = (XiveEAS *) &end->w4; 1280 uint8_t pq; 1281 1282 if (!xive_end_is_escalate(end)) { 1283 return; 1284 } 1285 1286 pq = xive_get_field32(END_W1_ESe, end->w1); 1287 1288 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1289 end_idx, 1290 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1291 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1292 xive_eas_is_valid(eas) ? 'V' : ' ', 1293 xive_eas_is_masked(eas) ? 'M' : ' ', 1294 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1295 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1296 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1297 } 1298 1299 /* 1300 * XIVE Router (aka. Virtualization Controller or IVRE) 1301 */ 1302 1303 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1304 XiveEAS *eas) 1305 { 1306 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1307 1308 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1309 } 1310 1311 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1312 XiveEND *end) 1313 { 1314 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1315 1316 return xrc->get_end(xrtr, end_blk, end_idx, end); 1317 } 1318 1319 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1320 XiveEND *end, uint8_t word_number) 1321 { 1322 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1323 1324 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1325 } 1326 1327 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1328 XiveNVT *nvt) 1329 { 1330 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1331 1332 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1333 } 1334 1335 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1336 XiveNVT *nvt, uint8_t word_number) 1337 { 1338 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1339 1340 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1341 } 1342 1343 XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) 1344 { 1345 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1346 1347 return xrc->get_tctx(xrtr, cs); 1348 } 1349 1350 /* 1351 * Encode the HW CAM line in the block group mode format : 1352 * 1353 * chip << 19 | 0000000 0 0001 thread (7Bit) 1354 */ 1355 static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) 1356 { 1357 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1358 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1359 1360 return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f)); 1361 } 1362 1363 /* 1364 * The thread context register words are in big-endian format. 1365 */ 1366 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1367 uint8_t format, 1368 uint8_t nvt_blk, uint32_t nvt_idx, 1369 bool cam_ignore, uint32_t logic_serv) 1370 { 1371 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1372 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1373 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1374 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1375 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1376 1377 /* 1378 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1379 * identifier are ignored in the "CAM" match. 1380 */ 1381 1382 if (format == 0) { 1383 if (cam_ignore == true) { 1384 /* 1385 * F=0 & i=1: Logical server notification (bits ignored at 1386 * the end of the NVT identifier) 1387 */ 1388 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1389 nvt_blk, nvt_idx); 1390 return -1; 1391 } 1392 1393 /* F=0 & i=0: Specific NVT notification */ 1394 1395 /* PHYS ring */ 1396 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1397 cam == xive_tctx_hw_cam_line(tctx)) { 1398 return TM_QW3_HV_PHYS; 1399 } 1400 1401 /* HV POOL ring */ 1402 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1403 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1404 return TM_QW2_HV_POOL; 1405 } 1406 1407 /* OS ring */ 1408 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1409 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1410 return TM_QW1_OS; 1411 } 1412 } else { 1413 /* F=1 : User level Event-Based Branch (EBB) notification */ 1414 1415 /* USER ring */ 1416 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1417 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1418 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1419 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1420 return TM_QW0_USER; 1421 } 1422 } 1423 return -1; 1424 } 1425 1426 static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, 1427 uint8_t nvt_blk, uint32_t nvt_idx, 1428 bool cam_ignore, uint8_t priority, 1429 uint32_t logic_serv, XiveTCTXMatch *match) 1430 { 1431 CPUState *cs; 1432 1433 /* 1434 * TODO (PowerNV): handle chip_id overwrite of block field for 1435 * hardwired CAM compares 1436 */ 1437 1438 CPU_FOREACH(cs) { 1439 XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs); 1440 int ring; 1441 1442 /* 1443 * Skip partially initialized vCPUs. This can happen when 1444 * vCPUs are hotplugged. 1445 */ 1446 if (!tctx) { 1447 continue; 1448 } 1449 1450 /* 1451 * HW checks that the CPU is enabled in the Physical Thread 1452 * Enable Register (PTER). 1453 */ 1454 1455 /* 1456 * Check the thread context CAM lines and record matches. We 1457 * will handle CPU exception delivery later 1458 */ 1459 ring = xive_presenter_tctx_match(XIVE_PRESENTER(xrtr), tctx, format, 1460 nvt_blk, nvt_idx, 1461 cam_ignore, logic_serv); 1462 /* 1463 * Save the context and follow on to catch duplicates, that we 1464 * don't support yet. 1465 */ 1466 if (ring != -1) { 1467 if (match->tctx) { 1468 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread " 1469 "context NVT %x/%x\n", nvt_blk, nvt_idx); 1470 return false; 1471 } 1472 1473 match->ring = ring; 1474 match->tctx = tctx; 1475 } 1476 } 1477 1478 if (!match->tctx) { 1479 qemu_log_mask(LOG_UNIMP, "XIVE: NVT %x/%x is not dispatched\n", 1480 nvt_blk, nvt_idx); 1481 return false; 1482 } 1483 1484 return true; 1485 } 1486 1487 /* 1488 * This is our simple Xive Presenter Engine model. It is merged in the 1489 * Router as it does not require an extra object. 1490 * 1491 * It receives notification requests sent by the IVRE to find one 1492 * matching NVT (or more) dispatched on the processor threads. In case 1493 * of a single NVT notification, the process is abreviated and the 1494 * thread is signaled if a match is found. In case of a logical server 1495 * notification (bits ignored at the end of the NVT identifier), the 1496 * IVPE and IVRE select a winning thread using different filters. This 1497 * involves 2 or 3 exchanges on the PowerBus that the model does not 1498 * support. 1499 * 1500 * The parameters represent what is sent on the PowerBus 1501 */ 1502 static bool xive_presenter_notify(XiveRouter *xrtr, uint8_t format, 1503 uint8_t nvt_blk, uint32_t nvt_idx, 1504 bool cam_ignore, uint8_t priority, 1505 uint32_t logic_serv) 1506 { 1507 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1508 bool found; 1509 1510 found = xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ignore, 1511 priority, logic_serv, &match); 1512 if (found) { 1513 ipb_update(&match.tctx->regs[match.ring], priority); 1514 xive_tctx_notify(match.tctx, match.ring); 1515 } 1516 1517 return found; 1518 } 1519 1520 /* 1521 * Notification using the END ESe/ESn bit (Event State Buffer for 1522 * escalation and notification). Profide futher coalescing in the 1523 * Router. 1524 */ 1525 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1526 uint32_t end_idx, XiveEND *end, 1527 uint32_t end_esmask) 1528 { 1529 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1530 bool notify = xive_esb_trigger(&pq); 1531 1532 if (pq != xive_get_field32(end_esmask, end->w1)) { 1533 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1534 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1535 } 1536 1537 /* ESe/n[Q]=1 : end of notification */ 1538 return notify; 1539 } 1540 1541 /* 1542 * An END trigger can come from an event trigger (IPI or HW) or from 1543 * another chip. We don't model the PowerBus but the END trigger 1544 * message has the same parameters than in the function below. 1545 */ 1546 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1547 uint32_t end_idx, uint32_t end_data) 1548 { 1549 XiveEND end; 1550 uint8_t priority; 1551 uint8_t format; 1552 uint8_t nvt_blk; 1553 uint32_t nvt_idx; 1554 XiveNVT nvt; 1555 bool found; 1556 1557 /* END cache lookup */ 1558 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1559 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1560 end_idx); 1561 return; 1562 } 1563 1564 if (!xive_end_is_valid(&end)) { 1565 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1566 end_blk, end_idx); 1567 return; 1568 } 1569 1570 if (xive_end_is_enqueue(&end)) { 1571 xive_end_enqueue(&end, end_data); 1572 /* Enqueuing event data modifies the EQ toggle and index */ 1573 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1574 } 1575 1576 /* 1577 * When the END is silent, we skip the notification part. 1578 */ 1579 if (xive_end_is_silent_escalation(&end)) { 1580 goto do_escalation; 1581 } 1582 1583 /* 1584 * The W7 format depends on the F bit in W6. It defines the type 1585 * of the notification : 1586 * 1587 * F=0 : single or multiple NVT notification 1588 * F=1 : User level Event-Based Branch (EBB) notification, no 1589 * priority 1590 */ 1591 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1592 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1593 1594 /* The END is masked */ 1595 if (format == 0 && priority == 0xff) { 1596 return; 1597 } 1598 1599 /* 1600 * Check the END ESn (Event State Buffer for notification) for 1601 * even futher coalescing in the Router 1602 */ 1603 if (!xive_end_is_notify(&end)) { 1604 /* ESn[Q]=1 : end of notification */ 1605 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1606 &end, END_W1_ESn)) { 1607 return; 1608 } 1609 } 1610 1611 /* 1612 * Follows IVPE notification 1613 */ 1614 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1615 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1616 1617 /* NVT cache lookup */ 1618 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1619 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1620 nvt_blk, nvt_idx); 1621 return; 1622 } 1623 1624 if (!xive_nvt_is_valid(&nvt)) { 1625 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1626 nvt_blk, nvt_idx); 1627 return; 1628 } 1629 1630 found = xive_presenter_notify(xrtr, format, nvt_blk, nvt_idx, 1631 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1632 priority, 1633 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1634 1635 /* TODO: Auto EOI. */ 1636 1637 if (found) { 1638 return; 1639 } 1640 1641 /* 1642 * If no matching NVT is dispatched on a HW thread : 1643 * - specific VP: update the NVT structure if backlog is activated 1644 * - logical server : forward request to IVPE (not supported) 1645 */ 1646 if (xive_end_is_backlog(&end)) { 1647 uint8_t ipb; 1648 1649 if (format == 1) { 1650 qemu_log_mask(LOG_GUEST_ERROR, 1651 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1652 end_blk, end_idx); 1653 return; 1654 } 1655 /* 1656 * Record the IPB in the associated NVT structure for later 1657 * use. The presenter will resend the interrupt when the vCPU 1658 * is dispatched again on a HW thread. 1659 */ 1660 ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priority); 1661 nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); 1662 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1663 1664 /* 1665 * On HW, follows a "Broadcast Backlog" to IVPEs 1666 */ 1667 } 1668 1669 do_escalation: 1670 /* 1671 * If activated, escalate notification using the ESe PQ bits and 1672 * the EAS in w4-5 1673 */ 1674 if (!xive_end_is_escalate(&end)) { 1675 return; 1676 } 1677 1678 /* 1679 * Check the END ESe (Event State Buffer for escalation) for even 1680 * futher coalescing in the Router 1681 */ 1682 if (!xive_end_is_uncond_escalation(&end)) { 1683 /* ESe[Q]=1 : end of notification */ 1684 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1685 &end, END_W1_ESe)) { 1686 return; 1687 } 1688 } 1689 1690 /* 1691 * The END trigger becomes an Escalation trigger 1692 */ 1693 xive_router_end_notify(xrtr, 1694 xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1695 xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1696 xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1697 } 1698 1699 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 1700 { 1701 XiveRouter *xrtr = XIVE_ROUTER(xn); 1702 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1703 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1704 XiveEAS eas; 1705 1706 /* EAS cache lookup */ 1707 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1708 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1709 return; 1710 } 1711 1712 /* 1713 * The IVRE checks the State Bit Cache at this point. We skip the 1714 * SBC lookup because the state bits of the sources are modeled 1715 * internally in QEMU. 1716 */ 1717 1718 if (!xive_eas_is_valid(&eas)) { 1719 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1720 return; 1721 } 1722 1723 if (xive_eas_is_masked(&eas)) { 1724 /* Notification completed */ 1725 return; 1726 } 1727 1728 /* 1729 * The event trigger becomes an END trigger 1730 */ 1731 xive_router_end_notify(xrtr, 1732 xive_get_field64(EAS_END_BLOCK, eas.w), 1733 xive_get_field64(EAS_END_INDEX, eas.w), 1734 xive_get_field64(EAS_END_DATA, eas.w)); 1735 } 1736 1737 static void xive_router_class_init(ObjectClass *klass, void *data) 1738 { 1739 DeviceClass *dc = DEVICE_CLASS(klass); 1740 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1741 1742 dc->desc = "XIVE Router Engine"; 1743 xnc->notify = xive_router_notify; 1744 } 1745 1746 static const TypeInfo xive_router_info = { 1747 .name = TYPE_XIVE_ROUTER, 1748 .parent = TYPE_SYS_BUS_DEVICE, 1749 .abstract = true, 1750 .class_size = sizeof(XiveRouterClass), 1751 .class_init = xive_router_class_init, 1752 .interfaces = (InterfaceInfo[]) { 1753 { TYPE_XIVE_NOTIFIER }, 1754 { TYPE_XIVE_PRESENTER }, 1755 { } 1756 } 1757 }; 1758 1759 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1760 { 1761 if (!xive_eas_is_valid(eas)) { 1762 return; 1763 } 1764 1765 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1766 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1767 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1768 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1769 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1770 } 1771 1772 /* 1773 * END ESB MMIO loads 1774 */ 1775 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1776 { 1777 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1778 uint32_t offset = addr & 0xFFF; 1779 uint8_t end_blk; 1780 uint32_t end_idx; 1781 XiveEND end; 1782 uint32_t end_esmask; 1783 uint8_t pq; 1784 uint64_t ret = -1; 1785 1786 end_blk = xsrc->block_id; 1787 end_idx = addr >> (xsrc->esb_shift + 1); 1788 1789 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1790 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1791 end_idx); 1792 return -1; 1793 } 1794 1795 if (!xive_end_is_valid(&end)) { 1796 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1797 end_blk, end_idx); 1798 return -1; 1799 } 1800 1801 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1802 pq = xive_get_field32(end_esmask, end.w1); 1803 1804 switch (offset) { 1805 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1806 ret = xive_esb_eoi(&pq); 1807 1808 /* Forward the source event notification for routing ?? */ 1809 break; 1810 1811 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1812 ret = pq; 1813 break; 1814 1815 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1816 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1817 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1818 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1819 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1820 break; 1821 default: 1822 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1823 offset); 1824 return -1; 1825 } 1826 1827 if (pq != xive_get_field32(end_esmask, end.w1)) { 1828 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1829 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1830 } 1831 1832 return ret; 1833 } 1834 1835 /* 1836 * END ESB MMIO stores are invalid 1837 */ 1838 static void xive_end_source_write(void *opaque, hwaddr addr, 1839 uint64_t value, unsigned size) 1840 { 1841 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1842 HWADDR_PRIx"\n", addr); 1843 } 1844 1845 static const MemoryRegionOps xive_end_source_ops = { 1846 .read = xive_end_source_read, 1847 .write = xive_end_source_write, 1848 .endianness = DEVICE_BIG_ENDIAN, 1849 .valid = { 1850 .min_access_size = 8, 1851 .max_access_size = 8, 1852 }, 1853 .impl = { 1854 .min_access_size = 8, 1855 .max_access_size = 8, 1856 }, 1857 }; 1858 1859 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1860 { 1861 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1862 1863 assert(xsrc->xrtr); 1864 1865 if (!xsrc->nr_ends) { 1866 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1867 return; 1868 } 1869 1870 if (xsrc->esb_shift != XIVE_ESB_4K && 1871 xsrc->esb_shift != XIVE_ESB_64K) { 1872 error_setg(errp, "Invalid ESB shift setting"); 1873 return; 1874 } 1875 1876 /* 1877 * Each END is assigned an even/odd pair of MMIO pages, the even page 1878 * manages the ESn field while the odd page manages the ESe field. 1879 */ 1880 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1881 &xive_end_source_ops, xsrc, "xive.end", 1882 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1883 } 1884 1885 static Property xive_end_source_properties[] = { 1886 DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0), 1887 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1888 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1889 DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, 1890 XiveRouter *), 1891 DEFINE_PROP_END_OF_LIST(), 1892 }; 1893 1894 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1895 { 1896 DeviceClass *dc = DEVICE_CLASS(klass); 1897 1898 dc->desc = "XIVE END Source"; 1899 dc->props = xive_end_source_properties; 1900 dc->realize = xive_end_source_realize; 1901 /* 1902 * Reason: part of XIVE interrupt controller, needs to be wired up, 1903 * e.g. by spapr_xive_instance_init(). 1904 */ 1905 dc->user_creatable = false; 1906 } 1907 1908 static const TypeInfo xive_end_source_info = { 1909 .name = TYPE_XIVE_END_SOURCE, 1910 .parent = TYPE_DEVICE, 1911 .instance_size = sizeof(XiveENDSource), 1912 .class_init = xive_end_source_class_init, 1913 }; 1914 1915 /* 1916 * XIVE Notifier 1917 */ 1918 static const TypeInfo xive_notifier_info = { 1919 .name = TYPE_XIVE_NOTIFIER, 1920 .parent = TYPE_INTERFACE, 1921 .class_size = sizeof(XiveNotifierClass), 1922 }; 1923 1924 /* 1925 * XIVE Presenter 1926 */ 1927 static const TypeInfo xive_presenter_info = { 1928 .name = TYPE_XIVE_PRESENTER, 1929 .parent = TYPE_INTERFACE, 1930 .class_size = sizeof(XivePresenterClass), 1931 }; 1932 1933 static void xive_register_types(void) 1934 { 1935 type_register_static(&xive_source_info); 1936 type_register_static(&xive_notifier_info); 1937 type_register_static(&xive_presenter_info); 1938 type_register_static(&xive_router_info); 1939 type_register_static(&xive_end_source_info); 1940 type_register_static(&xive_tctx_info); 1941 } 1942 1943 type_init(xive_register_types) 1944