1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "hw/qdev-properties.h" 19 #include "migration/vmstate.h" 20 #include "monitor/monitor.h" 21 #include "hw/irq.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive_regs.h" 24 25 /* 26 * XIVE Thread Interrupt Management context 27 */ 28 29 /* 30 * Convert a priority number to an Interrupt Pending Buffer (IPB) 31 * register, which indicates a pending interrupt at the priority 32 * corresponding to the bit number 33 */ 34 static uint8_t priority_to_ipb(uint8_t priority) 35 { 36 return priority > XIVE_PRIORITY_MAX ? 37 0 : 1 << (XIVE_PRIORITY_MAX - priority); 38 } 39 40 /* 41 * Convert an Interrupt Pending Buffer (IPB) register to a Pending 42 * Interrupt Priority Register (PIPR), which contains the priority of 43 * the most favored pending notification. 44 */ 45 static uint8_t ipb_to_pipr(uint8_t ibp) 46 { 47 return ibp ? clz32((uint32_t)ibp << 24) : 0xff; 48 } 49 50 static void ipb_update(uint8_t *regs, uint8_t priority) 51 { 52 regs[TM_IPB] |= priority_to_ipb(priority); 53 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 54 } 55 56 static uint8_t exception_mask(uint8_t ring) 57 { 58 switch (ring) { 59 case TM_QW1_OS: 60 return TM_QW1_NSR_EO; 61 case TM_QW3_HV_PHYS: 62 return TM_QW3_NSR_HE; 63 default: 64 g_assert_not_reached(); 65 } 66 } 67 68 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) 69 { 70 switch (ring) { 71 case TM_QW0_USER: 72 return 0; /* Not supported */ 73 case TM_QW1_OS: 74 return tctx->os_output; 75 case TM_QW2_HV_POOL: 76 case TM_QW3_HV_PHYS: 77 return tctx->hv_output; 78 default: 79 return 0; 80 } 81 } 82 83 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) 84 { 85 uint8_t *regs = &tctx->regs[ring]; 86 uint8_t nsr = regs[TM_NSR]; 87 uint8_t mask = exception_mask(ring); 88 89 qemu_irq_lower(xive_tctx_output(tctx, ring)); 90 91 if (regs[TM_NSR] & mask) { 92 uint8_t cppr = regs[TM_PIPR]; 93 94 regs[TM_CPPR] = cppr; 95 96 /* Reset the pending buffer bit */ 97 regs[TM_IPB] &= ~priority_to_ipb(cppr); 98 regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); 99 100 /* Drop Exception bit */ 101 regs[TM_NSR] &= ~mask; 102 } 103 104 return (nsr << 8) | regs[TM_CPPR]; 105 } 106 107 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) 108 { 109 uint8_t *regs = &tctx->regs[ring]; 110 111 if (regs[TM_PIPR] < regs[TM_CPPR]) { 112 switch (ring) { 113 case TM_QW1_OS: 114 regs[TM_NSR] |= TM_QW1_NSR_EO; 115 break; 116 case TM_QW3_HV_PHYS: 117 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); 118 break; 119 default: 120 g_assert_not_reached(); 121 } 122 qemu_irq_raise(xive_tctx_output(tctx, ring)); 123 } 124 } 125 126 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 127 { 128 if (cppr > XIVE_PRIORITY_MAX) { 129 cppr = 0xff; 130 } 131 132 tctx->regs[ring + TM_CPPR] = cppr; 133 134 /* CPPR has changed, check if we need to raise a pending exception */ 135 xive_tctx_notify(tctx, ring); 136 } 137 138 static inline uint32_t xive_tctx_word2(uint8_t *ring) 139 { 140 return *((uint32_t *) &ring[TM_WORD2]); 141 } 142 143 /* 144 * XIVE Thread Interrupt Management Area (TIMA) 145 */ 146 147 static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset, 148 uint64_t value, unsigned size) 149 { 150 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 151 } 152 153 static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) 154 { 155 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); 156 } 157 158 static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, 159 unsigned size) 160 { 161 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 162 uint32_t qw2w2; 163 164 qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0); 165 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); 166 return qw2w2; 167 } 168 169 static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset, 170 uint64_t value, unsigned size) 171 { 172 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; 173 } 174 175 static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned size) 176 { 177 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; 178 } 179 180 /* 181 * Define an access map for each page of the TIMA that we will use in 182 * the memory region ops to filter values when doing loads and stores 183 * of raw registers values 184 * 185 * Registers accessibility bits : 186 * 187 * 0x0 - no access 188 * 0x1 - write only 189 * 0x2 - read only 190 * 0x3 - read/write 191 */ 192 193 static const uint8_t xive_tm_hw_view[] = { 194 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 195 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 196 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 197 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ 198 }; 199 200 static const uint8_t xive_tm_hv_view[] = { 201 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 202 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ 203 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 204 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ 205 }; 206 207 static const uint8_t xive_tm_os_view[] = { 208 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 209 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 210 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 211 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 212 }; 213 214 static const uint8_t xive_tm_user_view[] = { 215 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */ 216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */ 217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */ 218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */ 219 }; 220 221 /* 222 * Overall TIMA access map for the thread interrupt management context 223 * registers 224 */ 225 static const uint8_t *xive_tm_views[] = { 226 [XIVE_TM_HW_PAGE] = xive_tm_hw_view, 227 [XIVE_TM_HV_PAGE] = xive_tm_hv_view, 228 [XIVE_TM_OS_PAGE] = xive_tm_os_view, 229 [XIVE_TM_USER_PAGE] = xive_tm_user_view, 230 }; 231 232 /* 233 * Computes a register access mask for a given offset in the TIMA 234 */ 235 static uint64_t xive_tm_mask(hwaddr offset, unsigned size, bool write) 236 { 237 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 238 uint8_t reg_offset = offset & 0x3F; 239 uint8_t reg_mask = write ? 0x1 : 0x2; 240 uint64_t mask = 0x0; 241 int i; 242 243 for (i = 0; i < size; i++) { 244 if (xive_tm_views[page_offset][reg_offset + i] & reg_mask) { 245 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); 246 } 247 } 248 249 return mask; 250 } 251 252 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 253 unsigned size) 254 { 255 uint8_t ring_offset = offset & 0x30; 256 uint8_t reg_offset = offset & 0x3F; 257 uint64_t mask = xive_tm_mask(offset, size, true); 258 int i; 259 260 /* 261 * Only 4 or 8 bytes stores are allowed and the User ring is 262 * excluded 263 */ 264 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 265 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA @%" 266 HWADDR_PRIx"\n", offset); 267 return; 268 } 269 270 /* 271 * Use the register offset for the raw values and filter out 272 * reserved values 273 */ 274 for (i = 0; i < size; i++) { 275 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); 276 if (byte_mask) { 277 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & 278 byte_mask; 279 } 280 } 281 } 282 283 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 284 { 285 uint8_t ring_offset = offset & 0x30; 286 uint8_t reg_offset = offset & 0x3F; 287 uint64_t mask = xive_tm_mask(offset, size, false); 288 uint64_t ret; 289 int i; 290 291 /* 292 * Only 4 or 8 bytes loads are allowed and the User ring is 293 * excluded 294 */ 295 if (size < 4 || !mask || ring_offset == TM_QW0_USER) { 296 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access at TIMA @%" 297 HWADDR_PRIx"\n", offset); 298 return -1; 299 } 300 301 /* Use the register offset for the raw values */ 302 ret = 0; 303 for (i = 0; i < size; i++) { 304 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); 305 } 306 307 /* filter out reserved values */ 308 return ret & mask; 309 } 310 311 /* 312 * The TM context is mapped twice within each page. Stores and loads 313 * to the first mapping below 2K write and read the specified values 314 * without modification. The second mapping above 2K performs specific 315 * state changes (side effects) in addition to setting/returning the 316 * interrupt management area context of the processor thread. 317 */ 318 static uint64_t xive_tm_ack_os_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) 319 { 320 return xive_tctx_accept(tctx, TM_QW1_OS); 321 } 322 323 static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset, 324 uint64_t value, unsigned size) 325 { 326 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 327 } 328 329 /* 330 * Adjust the IPB to allow a CPU to process event queues of other 331 * priorities during one physical interrupt cycle. 332 */ 333 static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset, 334 uint64_t value, unsigned size) 335 { 336 ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff); 337 xive_tctx_notify(tctx, TM_QW1_OS); 338 } 339 340 static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset, 341 unsigned size) 342 { 343 uint32_t qw1w2_prev = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 344 uint32_t qw1w2; 345 346 qw1w2 = xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0); 347 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 348 return qw1w2; 349 } 350 351 /* 352 * Define a mapping of "special" operations depending on the TIMA page 353 * offset and the size of the operation. 354 */ 355 typedef struct XiveTmOp { 356 uint8_t page_offset; 357 uint32_t op_offset; 358 unsigned size; 359 void (*write_handler)(XiveTCTX *tctx, hwaddr offset, uint64_t value, 360 unsigned size); 361 uint64_t (*read_handler)(XiveTCTX *tctx, hwaddr offset, unsigned size); 362 } XiveTmOp; 363 364 static const XiveTmOp xive_tm_operations[] = { 365 /* 366 * MMIOs below 2K : raw values and special operations without side 367 * effects 368 */ 369 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 370 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 371 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, 372 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, 373 374 /* MMIOs above 2K : special operations with side effects */ 375 { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, 376 { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, 377 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, 378 { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, 379 { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, 380 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, 381 { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, 382 }; 383 384 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 385 { 386 uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; 387 uint32_t op_offset = offset & 0xFFF; 388 int i; 389 390 for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) { 391 const XiveTmOp *xto = &xive_tm_operations[i]; 392 393 /* Accesses done from a more privileged TIMA page is allowed */ 394 if (xto->page_offset >= page_offset && 395 xto->op_offset == op_offset && 396 xto->size == size && 397 ((write && xto->write_handler) || (!write && xto->read_handler))) { 398 return xto; 399 } 400 } 401 return NULL; 402 } 403 404 /* 405 * TIMA MMIO handlers 406 */ 407 void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 408 unsigned size) 409 { 410 const XiveTmOp *xto; 411 412 /* 413 * TODO: check V bit in Q[0-3]W2 414 */ 415 416 /* 417 * First, check for special operations in the 2K region 418 */ 419 if (offset & 0x800) { 420 xto = xive_tm_find_op(offset, size, true); 421 if (!xto) { 422 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " 423 "@%"HWADDR_PRIx"\n", offset); 424 } else { 425 xto->write_handler(tctx, offset, value, size); 426 } 427 return; 428 } 429 430 /* 431 * Then, for special operations in the region below 2K. 432 */ 433 xto = xive_tm_find_op(offset, size, true); 434 if (xto) { 435 xto->write_handler(tctx, offset, value, size); 436 return; 437 } 438 439 /* 440 * Finish with raw access to the register values 441 */ 442 xive_tm_raw_write(tctx, offset, value, size); 443 } 444 445 uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size) 446 { 447 const XiveTmOp *xto; 448 449 /* 450 * TODO: check V bit in Q[0-3]W2 451 */ 452 453 /* 454 * First, check for special operations in the 2K region 455 */ 456 if (offset & 0x800) { 457 xto = xive_tm_find_op(offset, size, false); 458 if (!xto) { 459 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA" 460 "@%"HWADDR_PRIx"\n", offset); 461 return -1; 462 } 463 return xto->read_handler(tctx, offset, size); 464 } 465 466 /* 467 * Then, for special operations in the region below 2K. 468 */ 469 xto = xive_tm_find_op(offset, size, false); 470 if (xto) { 471 return xto->read_handler(tctx, offset, size); 472 } 473 474 /* 475 * Finish with raw access to the register values 476 */ 477 return xive_tm_raw_read(tctx, offset, size); 478 } 479 480 static void xive_tm_write(void *opaque, hwaddr offset, 481 uint64_t value, unsigned size) 482 { 483 XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); 484 485 xive_tctx_tm_write(tctx, offset, value, size); 486 } 487 488 static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) 489 { 490 XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); 491 492 return xive_tctx_tm_read(tctx, offset, size); 493 } 494 495 const MemoryRegionOps xive_tm_ops = { 496 .read = xive_tm_read, 497 .write = xive_tm_write, 498 .endianness = DEVICE_BIG_ENDIAN, 499 .valid = { 500 .min_access_size = 1, 501 .max_access_size = 8, 502 }, 503 .impl = { 504 .min_access_size = 1, 505 .max_access_size = 8, 506 }, 507 }; 508 509 static char *xive_tctx_ring_print(uint8_t *ring) 510 { 511 uint32_t w2 = xive_tctx_word2(ring); 512 513 return g_strdup_printf("%02x %02x %02x %02x %02x " 514 "%02x %02x %02x %08x", 515 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], 516 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], 517 be32_to_cpu(w2)); 518 } 519 520 static const char * const xive_tctx_ring_names[] = { 521 "USER", "OS", "POOL", "PHYS", 522 }; 523 524 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 525 { 526 int cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; 527 int i; 528 529 if (kvm_irqchip_in_kernel()) { 530 Error *local_err = NULL; 531 532 kvmppc_xive_cpu_synchronize_state(tctx, &local_err); 533 if (local_err) { 534 error_report_err(local_err); 535 return; 536 } 537 } 538 539 monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR" 540 " W2\n", cpu_index); 541 542 for (i = 0; i < XIVE_TM_RING_COUNT; i++) { 543 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); 544 monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index, 545 xive_tctx_ring_names[i], s); 546 g_free(s); 547 } 548 } 549 550 void xive_tctx_reset(XiveTCTX *tctx) 551 { 552 memset(tctx->regs, 0, sizeof(tctx->regs)); 553 554 /* Set some defaults */ 555 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; 556 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; 557 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; 558 559 /* 560 * Initialize PIPR to 0xFF to avoid phantom interrupts when the 561 * CPPR is first set. 562 */ 563 tctx->regs[TM_QW1_OS + TM_PIPR] = 564 ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); 565 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = 566 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); 567 } 568 569 static void xive_tctx_realize(DeviceState *dev, Error **errp) 570 { 571 XiveTCTX *tctx = XIVE_TCTX(dev); 572 PowerPCCPU *cpu; 573 CPUPPCState *env; 574 Object *obj; 575 Error *local_err = NULL; 576 577 obj = object_property_get_link(OBJECT(dev), "cpu", &local_err); 578 if (!obj) { 579 error_propagate(errp, local_err); 580 error_prepend(errp, "required link 'cpu' not found: "); 581 return; 582 } 583 584 cpu = POWERPC_CPU(obj); 585 tctx->cs = CPU(obj); 586 587 env = &cpu->env; 588 switch (PPC_INPUT(env)) { 589 case PPC_FLAGS_INPUT_POWER9: 590 tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT]; 591 tctx->os_output = env->irq_inputs[POWER9_INPUT_INT]; 592 break; 593 594 default: 595 error_setg(errp, "XIVE interrupt controller does not support " 596 "this CPU bus model"); 597 return; 598 } 599 600 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 601 if (kvm_irqchip_in_kernel()) { 602 kvmppc_xive_cpu_connect(tctx, &local_err); 603 if (local_err) { 604 error_propagate(errp, local_err); 605 return; 606 } 607 } 608 } 609 610 static int vmstate_xive_tctx_pre_save(void *opaque) 611 { 612 Error *local_err = NULL; 613 614 if (kvm_irqchip_in_kernel()) { 615 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque), &local_err); 616 if (local_err) { 617 error_report_err(local_err); 618 return -1; 619 } 620 } 621 622 return 0; 623 } 624 625 static int vmstate_xive_tctx_post_load(void *opaque, int version_id) 626 { 627 Error *local_err = NULL; 628 629 if (kvm_irqchip_in_kernel()) { 630 /* 631 * Required for hotplugged CPU, for which the state comes 632 * after all states of the machine. 633 */ 634 kvmppc_xive_cpu_set_state(XIVE_TCTX(opaque), &local_err); 635 if (local_err) { 636 error_report_err(local_err); 637 return -1; 638 } 639 } 640 641 return 0; 642 } 643 644 static const VMStateDescription vmstate_xive_tctx = { 645 .name = TYPE_XIVE_TCTX, 646 .version_id = 1, 647 .minimum_version_id = 1, 648 .pre_save = vmstate_xive_tctx_pre_save, 649 .post_load = vmstate_xive_tctx_post_load, 650 .fields = (VMStateField[]) { 651 VMSTATE_BUFFER(regs, XiveTCTX), 652 VMSTATE_END_OF_LIST() 653 }, 654 }; 655 656 static void xive_tctx_class_init(ObjectClass *klass, void *data) 657 { 658 DeviceClass *dc = DEVICE_CLASS(klass); 659 660 dc->desc = "XIVE Interrupt Thread Context"; 661 dc->realize = xive_tctx_realize; 662 dc->vmsd = &vmstate_xive_tctx; 663 /* 664 * Reason: part of XIVE interrupt controller, needs to be wired up 665 * by xive_tctx_create(). 666 */ 667 dc->user_creatable = false; 668 } 669 670 static const TypeInfo xive_tctx_info = { 671 .name = TYPE_XIVE_TCTX, 672 .parent = TYPE_DEVICE, 673 .instance_size = sizeof(XiveTCTX), 674 .class_init = xive_tctx_class_init, 675 }; 676 677 Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) 678 { 679 Error *local_err = NULL; 680 Object *obj; 681 682 obj = object_new(TYPE_XIVE_TCTX); 683 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); 684 object_unref(obj); 685 object_property_add_const_link(obj, "cpu", cpu, &error_abort); 686 object_property_set_bool(obj, true, "realized", &local_err); 687 if (local_err) { 688 goto error; 689 } 690 691 return obj; 692 693 error: 694 object_unparent(obj); 695 error_propagate(errp, local_err); 696 return NULL; 697 } 698 699 /* 700 * XIVE ESB helpers 701 */ 702 703 static uint8_t xive_esb_set(uint8_t *pq, uint8_t value) 704 { 705 uint8_t old_pq = *pq & 0x3; 706 707 *pq &= ~0x3; 708 *pq |= value & 0x3; 709 710 return old_pq; 711 } 712 713 static bool xive_esb_trigger(uint8_t *pq) 714 { 715 uint8_t old_pq = *pq & 0x3; 716 717 switch (old_pq) { 718 case XIVE_ESB_RESET: 719 xive_esb_set(pq, XIVE_ESB_PENDING); 720 return true; 721 case XIVE_ESB_PENDING: 722 case XIVE_ESB_QUEUED: 723 xive_esb_set(pq, XIVE_ESB_QUEUED); 724 return false; 725 case XIVE_ESB_OFF: 726 xive_esb_set(pq, XIVE_ESB_OFF); 727 return false; 728 default: 729 g_assert_not_reached(); 730 } 731 } 732 733 static bool xive_esb_eoi(uint8_t *pq) 734 { 735 uint8_t old_pq = *pq & 0x3; 736 737 switch (old_pq) { 738 case XIVE_ESB_RESET: 739 case XIVE_ESB_PENDING: 740 xive_esb_set(pq, XIVE_ESB_RESET); 741 return false; 742 case XIVE_ESB_QUEUED: 743 xive_esb_set(pq, XIVE_ESB_PENDING); 744 return true; 745 case XIVE_ESB_OFF: 746 xive_esb_set(pq, XIVE_ESB_OFF); 747 return false; 748 default: 749 g_assert_not_reached(); 750 } 751 } 752 753 /* 754 * XIVE Interrupt Source (or IVSE) 755 */ 756 757 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno) 758 { 759 assert(srcno < xsrc->nr_irqs); 760 761 return xsrc->status[srcno] & 0x3; 762 } 763 764 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq) 765 { 766 assert(srcno < xsrc->nr_irqs); 767 768 return xive_esb_set(&xsrc->status[srcno], pq); 769 } 770 771 /* 772 * Returns whether the event notification should be forwarded. 773 */ 774 static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) 775 { 776 uint8_t old_pq = xive_source_esb_get(xsrc, srcno); 777 778 xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; 779 780 switch (old_pq) { 781 case XIVE_ESB_RESET: 782 xive_source_esb_set(xsrc, srcno, XIVE_ESB_PENDING); 783 return true; 784 default: 785 return false; 786 } 787 } 788 789 /* 790 * Returns whether the event notification should be forwarded. 791 */ 792 static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) 793 { 794 bool ret; 795 796 assert(srcno < xsrc->nr_irqs); 797 798 ret = xive_esb_trigger(&xsrc->status[srcno]); 799 800 if (xive_source_irq_is_lsi(xsrc, srcno) && 801 xive_source_esb_get(xsrc, srcno) == XIVE_ESB_QUEUED) { 802 qemu_log_mask(LOG_GUEST_ERROR, 803 "XIVE: queued an event on LSI IRQ %d\n", srcno); 804 } 805 806 return ret; 807 } 808 809 /* 810 * Returns whether the event notification should be forwarded. 811 */ 812 static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) 813 { 814 bool ret; 815 816 assert(srcno < xsrc->nr_irqs); 817 818 ret = xive_esb_eoi(&xsrc->status[srcno]); 819 820 /* 821 * LSI sources do not set the Q bit but they can still be 822 * asserted, in which case we should forward a new event 823 * notification 824 */ 825 if (xive_source_irq_is_lsi(xsrc, srcno) && 826 xsrc->status[srcno] & XIVE_STATUS_ASSERTED) { 827 ret = xive_source_lsi_trigger(xsrc, srcno); 828 } 829 830 return ret; 831 } 832 833 /* 834 * Forward the source event notification to the Router 835 */ 836 static void xive_source_notify(XiveSource *xsrc, int srcno) 837 { 838 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); 839 840 if (xnc->notify) { 841 xnc->notify(xsrc->xive, srcno); 842 } 843 } 844 845 /* 846 * In a two pages ESB MMIO setting, even page is the trigger page, odd 847 * page is for management 848 */ 849 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 850 { 851 return !((addr >> shift) & 1); 852 } 853 854 static inline bool xive_source_is_trigger_page(XiveSource *xsrc, hwaddr addr) 855 { 856 return xive_source_esb_has_2page(xsrc) && 857 addr_is_even(addr, xsrc->esb_shift - 1); 858 } 859 860 /* 861 * ESB MMIO loads 862 * Trigger page Management/EOI page 863 * 864 * ESB MMIO setting 2 pages 1 or 2 pages 865 * 866 * 0x000 .. 0x3FF -1 EOI and return 0|1 867 * 0x400 .. 0x7FF -1 EOI and return 0|1 868 * 0x800 .. 0xBFF -1 return PQ 869 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00 870 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01 871 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10 872 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11 873 */ 874 static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size) 875 { 876 XiveSource *xsrc = XIVE_SOURCE(opaque); 877 uint32_t offset = addr & 0xFFF; 878 uint32_t srcno = addr >> xsrc->esb_shift; 879 uint64_t ret = -1; 880 881 /* In a two pages ESB MMIO setting, trigger page should not be read */ 882 if (xive_source_is_trigger_page(xsrc, addr)) { 883 qemu_log_mask(LOG_GUEST_ERROR, 884 "XIVE: invalid load on IRQ %d trigger page at " 885 "0x%"HWADDR_PRIx"\n", srcno, addr); 886 return -1; 887 } 888 889 switch (offset) { 890 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 891 ret = xive_source_esb_eoi(xsrc, srcno); 892 893 /* Forward the source event notification for routing */ 894 if (ret) { 895 xive_source_notify(xsrc, srcno); 896 } 897 break; 898 899 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 900 ret = xive_source_esb_get(xsrc, srcno); 901 break; 902 903 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 904 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 905 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 906 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 907 ret = xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 908 break; 909 default: 910 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB load addr %x\n", 911 offset); 912 } 913 914 return ret; 915 } 916 917 /* 918 * ESB MMIO stores 919 * Trigger page Management/EOI page 920 * 921 * ESB MMIO setting 2 pages 1 or 2 pages 922 * 923 * 0x000 .. 0x3FF Trigger Trigger 924 * 0x400 .. 0x7FF Trigger EOI 925 * 0x800 .. 0xBFF Trigger undefined 926 * 0xC00 .. 0xCFF Trigger PQ=00 927 * 0xD00 .. 0xDFF Trigger PQ=01 928 * 0xE00 .. 0xDFF Trigger PQ=10 929 * 0xF00 .. 0xDFF Trigger PQ=11 930 */ 931 static void xive_source_esb_write(void *opaque, hwaddr addr, 932 uint64_t value, unsigned size) 933 { 934 XiveSource *xsrc = XIVE_SOURCE(opaque); 935 uint32_t offset = addr & 0xFFF; 936 uint32_t srcno = addr >> xsrc->esb_shift; 937 bool notify = false; 938 939 /* In a two pages ESB MMIO setting, trigger page only triggers */ 940 if (xive_source_is_trigger_page(xsrc, addr)) { 941 notify = xive_source_esb_trigger(xsrc, srcno); 942 goto out; 943 } 944 945 switch (offset) { 946 case 0 ... 0x3FF: 947 notify = xive_source_esb_trigger(xsrc, srcno); 948 break; 949 950 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 951 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { 952 qemu_log_mask(LOG_GUEST_ERROR, 953 "XIVE: invalid Store EOI for IRQ %d\n", srcno); 954 return; 955 } 956 957 notify = xive_source_esb_eoi(xsrc, srcno); 958 break; 959 960 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 961 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 962 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 963 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 964 xive_source_esb_set(xsrc, srcno, (offset >> 8) & 0x3); 965 break; 966 967 default: 968 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %x\n", 969 offset); 970 return; 971 } 972 973 out: 974 /* Forward the source event notification for routing */ 975 if (notify) { 976 xive_source_notify(xsrc, srcno); 977 } 978 } 979 980 static const MemoryRegionOps xive_source_esb_ops = { 981 .read = xive_source_esb_read, 982 .write = xive_source_esb_write, 983 .endianness = DEVICE_BIG_ENDIAN, 984 .valid = { 985 .min_access_size = 8, 986 .max_access_size = 8, 987 }, 988 .impl = { 989 .min_access_size = 8, 990 .max_access_size = 8, 991 }, 992 }; 993 994 void xive_source_set_irq(void *opaque, int srcno, int val) 995 { 996 XiveSource *xsrc = XIVE_SOURCE(opaque); 997 bool notify = false; 998 999 if (xive_source_irq_is_lsi(xsrc, srcno)) { 1000 if (val) { 1001 notify = xive_source_lsi_trigger(xsrc, srcno); 1002 } else { 1003 xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; 1004 } 1005 } else { 1006 if (val) { 1007 notify = xive_source_esb_trigger(xsrc, srcno); 1008 } 1009 } 1010 1011 /* Forward the source event notification for routing */ 1012 if (notify) { 1013 xive_source_notify(xsrc, srcno); 1014 } 1015 } 1016 1017 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon) 1018 { 1019 int i; 1020 1021 for (i = 0; i < xsrc->nr_irqs; i++) { 1022 uint8_t pq = xive_source_esb_get(xsrc, i); 1023 1024 if (pq == XIVE_ESB_OFF) { 1025 continue; 1026 } 1027 1028 monitor_printf(mon, " %08x %s %c%c%c\n", i + offset, 1029 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 1030 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1031 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1032 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' '); 1033 } 1034 } 1035 1036 static void xive_source_reset(void *dev) 1037 { 1038 XiveSource *xsrc = XIVE_SOURCE(dev); 1039 1040 /* Do not clear the LSI bitmap */ 1041 1042 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ 1043 memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); 1044 } 1045 1046 static void xive_source_realize(DeviceState *dev, Error **errp) 1047 { 1048 XiveSource *xsrc = XIVE_SOURCE(dev); 1049 Object *obj; 1050 Error *local_err = NULL; 1051 1052 obj = object_property_get_link(OBJECT(dev), "xive", &local_err); 1053 if (!obj) { 1054 error_propagate(errp, local_err); 1055 error_prepend(errp, "required link 'xive' not found: "); 1056 return; 1057 } 1058 1059 xsrc->xive = XIVE_NOTIFIER(obj); 1060 1061 if (!xsrc->nr_irqs) { 1062 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1063 return; 1064 } 1065 1066 if (xsrc->esb_shift != XIVE_ESB_4K && 1067 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && 1068 xsrc->esb_shift != XIVE_ESB_64K && 1069 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { 1070 error_setg(errp, "Invalid ESB shift setting"); 1071 return; 1072 } 1073 1074 xsrc->status = g_malloc0(xsrc->nr_irqs); 1075 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); 1076 1077 if (!kvm_irqchip_in_kernel()) { 1078 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1079 &xive_source_esb_ops, xsrc, "xive.esb", 1080 (1ull << xsrc->esb_shift) * xsrc->nr_irqs); 1081 } 1082 1083 qemu_register_reset(xive_source_reset, dev); 1084 } 1085 1086 static const VMStateDescription vmstate_xive_source = { 1087 .name = TYPE_XIVE_SOURCE, 1088 .version_id = 1, 1089 .minimum_version_id = 1, 1090 .fields = (VMStateField[]) { 1091 VMSTATE_UINT32_EQUAL(nr_irqs, XiveSource, NULL), 1092 VMSTATE_VBUFFER_UINT32(status, XiveSource, 1, NULL, nr_irqs), 1093 VMSTATE_END_OF_LIST() 1094 }, 1095 }; 1096 1097 /* 1098 * The default XIVE interrupt source setting for the ESB MMIOs is two 1099 * 64k pages without Store EOI, to be in sync with KVM. 1100 */ 1101 static Property xive_source_properties[] = { 1102 DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), 1103 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), 1104 DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), 1105 DEFINE_PROP_END_OF_LIST(), 1106 }; 1107 1108 static void xive_source_class_init(ObjectClass *klass, void *data) 1109 { 1110 DeviceClass *dc = DEVICE_CLASS(klass); 1111 1112 dc->desc = "XIVE Interrupt Source"; 1113 dc->props = xive_source_properties; 1114 dc->realize = xive_source_realize; 1115 dc->vmsd = &vmstate_xive_source; 1116 /* 1117 * Reason: part of XIVE interrupt controller, needs to be wired up, 1118 * e.g. by spapr_xive_instance_init(). 1119 */ 1120 dc->user_creatable = false; 1121 } 1122 1123 static const TypeInfo xive_source_info = { 1124 .name = TYPE_XIVE_SOURCE, 1125 .parent = TYPE_DEVICE, 1126 .instance_size = sizeof(XiveSource), 1127 .class_init = xive_source_class_init, 1128 }; 1129 1130 /* 1131 * XiveEND helpers 1132 */ 1133 1134 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon) 1135 { 1136 uint64_t qaddr_base = xive_end_qaddr(end); 1137 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1138 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1139 uint32_t qentries = 1 << (qsize + 10); 1140 int i; 1141 1142 /* 1143 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 1144 */ 1145 monitor_printf(mon, " [ "); 1146 qindex = (qindex - (width - 1)) & (qentries - 1); 1147 for (i = 0; i < width; i++) { 1148 uint64_t qaddr = qaddr_base + (qindex << 2); 1149 uint32_t qdata = -1; 1150 1151 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 1152 sizeof(qdata))) { 1153 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 1154 HWADDR_PRIx "\n", qaddr); 1155 return; 1156 } 1157 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 1158 be32_to_cpu(qdata)); 1159 qindex = (qindex + 1) & (qentries - 1); 1160 } 1161 monitor_printf(mon, "]"); 1162 } 1163 1164 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon) 1165 { 1166 uint64_t qaddr_base = xive_end_qaddr(end); 1167 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1168 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1169 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1170 uint32_t qentries = 1 << (qsize + 10); 1171 1172 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1173 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1174 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1175 uint8_t pq; 1176 1177 if (!xive_end_is_valid(end)) { 1178 return; 1179 } 1180 1181 pq = xive_get_field32(END_W1_ESn, end->w1); 1182 1183 monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x", 1184 end_idx, 1185 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1186 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1187 xive_end_is_valid(end) ? 'v' : '-', 1188 xive_end_is_enqueue(end) ? 'q' : '-', 1189 xive_end_is_notify(end) ? 'n' : '-', 1190 xive_end_is_backlog(end) ? 'b' : '-', 1191 xive_end_is_escalate(end) ? 'e' : '-', 1192 xive_end_is_uncond_escalation(end) ? 'u' : '-', 1193 xive_end_is_silent_escalation(end) ? 's' : '-', 1194 priority, nvt_blk, nvt_idx); 1195 1196 if (qaddr_base) { 1197 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 1198 qaddr_base, qindex, qentries, qgen); 1199 xive_end_queue_pic_print_info(end, 6, mon); 1200 } 1201 monitor_printf(mon, "\n"); 1202 } 1203 1204 static void xive_end_enqueue(XiveEND *end, uint32_t data) 1205 { 1206 uint64_t qaddr_base = xive_end_qaddr(end); 1207 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 1208 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1209 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 1210 1211 uint64_t qaddr = qaddr_base + (qindex << 2); 1212 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 1213 uint32_t qentries = 1 << (qsize + 10); 1214 1215 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) { 1216 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 1217 HWADDR_PRIx "\n", qaddr); 1218 return; 1219 } 1220 1221 qindex = (qindex + 1) & (qentries - 1); 1222 if (qindex == 0) { 1223 qgen ^= 1; 1224 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); 1225 } 1226 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); 1227 } 1228 1229 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, 1230 Monitor *mon) 1231 { 1232 XiveEAS *eas = (XiveEAS *) &end->w4; 1233 uint8_t pq; 1234 1235 if (!xive_end_is_escalate(end)) { 1236 return; 1237 } 1238 1239 pq = xive_get_field32(END_W1_ESe, end->w1); 1240 1241 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 1242 end_idx, 1243 pq & XIVE_ESB_VAL_P ? 'P' : '-', 1244 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 1245 xive_eas_is_valid(eas) ? 'V' : ' ', 1246 xive_eas_is_masked(eas) ? 'M' : ' ', 1247 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1248 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1249 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1250 } 1251 1252 /* 1253 * XIVE Router (aka. Virtualization Controller or IVRE) 1254 */ 1255 1256 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1257 XiveEAS *eas) 1258 { 1259 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1260 1261 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1262 } 1263 1264 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1265 XiveEND *end) 1266 { 1267 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1268 1269 return xrc->get_end(xrtr, end_blk, end_idx, end); 1270 } 1271 1272 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 1273 XiveEND *end, uint8_t word_number) 1274 { 1275 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1276 1277 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1278 } 1279 1280 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1281 XiveNVT *nvt) 1282 { 1283 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1284 1285 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); 1286 } 1287 1288 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 1289 XiveNVT *nvt, uint8_t word_number) 1290 { 1291 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1292 1293 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); 1294 } 1295 1296 XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) 1297 { 1298 XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); 1299 1300 return xrc->get_tctx(xrtr, cs); 1301 } 1302 1303 /* 1304 * Encode the HW CAM line in the block group mode format : 1305 * 1306 * chip << 19 | 0000000 0 0001 thread (7Bit) 1307 */ 1308 static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) 1309 { 1310 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 1311 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 1312 1313 return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f)); 1314 } 1315 1316 /* 1317 * The thread context register words are in big-endian format. 1318 */ 1319 static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format, 1320 uint8_t nvt_blk, uint32_t nvt_idx, 1321 bool cam_ignore, uint32_t logic_serv) 1322 { 1323 uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); 1324 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1325 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1326 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1327 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1328 1329 /* 1330 * TODO (PowerNV): ignore mode. The low order bits of the NVT 1331 * identifier are ignored in the "CAM" match. 1332 */ 1333 1334 if (format == 0) { 1335 if (cam_ignore == true) { 1336 /* 1337 * F=0 & i=1: Logical server notification (bits ignored at 1338 * the end of the NVT identifier) 1339 */ 1340 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 1341 nvt_blk, nvt_idx); 1342 return -1; 1343 } 1344 1345 /* F=0 & i=0: Specific NVT notification */ 1346 1347 /* PHYS ring */ 1348 if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && 1349 cam == xive_tctx_hw_cam_line(tctx)) { 1350 return TM_QW3_HV_PHYS; 1351 } 1352 1353 /* HV POOL ring */ 1354 if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && 1355 cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) { 1356 return TM_QW2_HV_POOL; 1357 } 1358 1359 /* OS ring */ 1360 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1361 cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) { 1362 return TM_QW1_OS; 1363 } 1364 } else { 1365 /* F=1 : User level Event-Based Branch (EBB) notification */ 1366 1367 /* USER ring */ 1368 if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) && 1369 (cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) && 1370 (be32_to_cpu(qw0w2) & TM_QW0W2_VU) && 1371 (logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) { 1372 return TM_QW0_USER; 1373 } 1374 } 1375 return -1; 1376 } 1377 1378 typedef struct XiveTCTXMatch { 1379 XiveTCTX *tctx; 1380 uint8_t ring; 1381 } XiveTCTXMatch; 1382 1383 static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, 1384 uint8_t nvt_blk, uint32_t nvt_idx, 1385 bool cam_ignore, uint8_t priority, 1386 uint32_t logic_serv, XiveTCTXMatch *match) 1387 { 1388 CPUState *cs; 1389 1390 /* 1391 * TODO (PowerNV): handle chip_id overwrite of block field for 1392 * hardwired CAM compares 1393 */ 1394 1395 CPU_FOREACH(cs) { 1396 XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs); 1397 int ring; 1398 1399 /* 1400 * Skip partially initialized vCPUs. This can happen when 1401 * vCPUs are hotplugged. 1402 */ 1403 if (!tctx) { 1404 continue; 1405 } 1406 1407 /* 1408 * HW checks that the CPU is enabled in the Physical Thread 1409 * Enable Register (PTER). 1410 */ 1411 1412 /* 1413 * Check the thread context CAM lines and record matches. We 1414 * will handle CPU exception delivery later 1415 */ 1416 ring = xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx, 1417 cam_ignore, logic_serv); 1418 /* 1419 * Save the context and follow on to catch duplicates, that we 1420 * don't support yet. 1421 */ 1422 if (ring != -1) { 1423 if (match->tctx) { 1424 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread " 1425 "context NVT %x/%x\n", nvt_blk, nvt_idx); 1426 return false; 1427 } 1428 1429 match->ring = ring; 1430 match->tctx = tctx; 1431 } 1432 } 1433 1434 if (!match->tctx) { 1435 qemu_log_mask(LOG_UNIMP, "XIVE: NVT %x/%x is not dispatched\n", 1436 nvt_blk, nvt_idx); 1437 return false; 1438 } 1439 1440 return true; 1441 } 1442 1443 /* 1444 * This is our simple Xive Presenter Engine model. It is merged in the 1445 * Router as it does not require an extra object. 1446 * 1447 * It receives notification requests sent by the IVRE to find one 1448 * matching NVT (or more) dispatched on the processor threads. In case 1449 * of a single NVT notification, the process is abreviated and the 1450 * thread is signaled if a match is found. In case of a logical server 1451 * notification (bits ignored at the end of the NVT identifier), the 1452 * IVPE and IVRE select a winning thread using different filters. This 1453 * involves 2 or 3 exchanges on the PowerBus that the model does not 1454 * support. 1455 * 1456 * The parameters represent what is sent on the PowerBus 1457 */ 1458 static bool xive_presenter_notify(XiveRouter *xrtr, uint8_t format, 1459 uint8_t nvt_blk, uint32_t nvt_idx, 1460 bool cam_ignore, uint8_t priority, 1461 uint32_t logic_serv) 1462 { 1463 XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; 1464 bool found; 1465 1466 found = xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ignore, 1467 priority, logic_serv, &match); 1468 if (found) { 1469 ipb_update(&match.tctx->regs[match.ring], priority); 1470 xive_tctx_notify(match.tctx, match.ring); 1471 } 1472 1473 return found; 1474 } 1475 1476 /* 1477 * Notification using the END ESe/ESn bit (Event State Buffer for 1478 * escalation and notification). Profide futher coalescing in the 1479 * Router. 1480 */ 1481 static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, 1482 uint32_t end_idx, XiveEND *end, 1483 uint32_t end_esmask) 1484 { 1485 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1486 bool notify = xive_esb_trigger(&pq); 1487 1488 if (pq != xive_get_field32(end_esmask, end->w1)) { 1489 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1490 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); 1491 } 1492 1493 /* ESe/n[Q]=1 : end of notification */ 1494 return notify; 1495 } 1496 1497 /* 1498 * An END trigger can come from an event trigger (IPI or HW) or from 1499 * another chip. We don't model the PowerBus but the END trigger 1500 * message has the same parameters than in the function below. 1501 */ 1502 static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 1503 uint32_t end_idx, uint32_t end_data) 1504 { 1505 XiveEND end; 1506 uint8_t priority; 1507 uint8_t format; 1508 uint8_t nvt_blk; 1509 uint32_t nvt_idx; 1510 XiveNVT nvt; 1511 bool found; 1512 1513 /* END cache lookup */ 1514 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { 1515 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1516 end_idx); 1517 return; 1518 } 1519 1520 if (!xive_end_is_valid(&end)) { 1521 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1522 end_blk, end_idx); 1523 return; 1524 } 1525 1526 if (xive_end_is_enqueue(&end)) { 1527 xive_end_enqueue(&end, end_data); 1528 /* Enqueuing event data modifies the EQ toggle and index */ 1529 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1530 } 1531 1532 /* 1533 * When the END is silent, we skip the notification part. 1534 */ 1535 if (xive_end_is_silent_escalation(&end)) { 1536 goto do_escalation; 1537 } 1538 1539 /* 1540 * The W7 format depends on the F bit in W6. It defines the type 1541 * of the notification : 1542 * 1543 * F=0 : single or multiple NVT notification 1544 * F=1 : User level Event-Based Branch (EBB) notification, no 1545 * priority 1546 */ 1547 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); 1548 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); 1549 1550 /* The END is masked */ 1551 if (format == 0 && priority == 0xff) { 1552 return; 1553 } 1554 1555 /* 1556 * Check the END ESn (Event State Buffer for notification) for 1557 * even futher coalescing in the Router 1558 */ 1559 if (!xive_end_is_notify(&end)) { 1560 /* ESn[Q]=1 : end of notification */ 1561 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1562 &end, END_W1_ESn)) { 1563 return; 1564 } 1565 } 1566 1567 /* 1568 * Follows IVPE notification 1569 */ 1570 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); 1571 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); 1572 1573 /* NVT cache lookup */ 1574 if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { 1575 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n", 1576 nvt_blk, nvt_idx); 1577 return; 1578 } 1579 1580 if (!xive_nvt_is_valid(&nvt)) { 1581 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n", 1582 nvt_blk, nvt_idx); 1583 return; 1584 } 1585 1586 found = xive_presenter_notify(xrtr, format, nvt_blk, nvt_idx, 1587 xive_get_field32(END_W7_F0_IGNORE, end.w7), 1588 priority, 1589 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); 1590 1591 /* TODO: Auto EOI. */ 1592 1593 if (found) { 1594 return; 1595 } 1596 1597 /* 1598 * If no matching NVT is dispatched on a HW thread : 1599 * - specific VP: update the NVT structure if backlog is activated 1600 * - logical server : forward request to IVPE (not supported) 1601 */ 1602 if (xive_end_is_backlog(&end)) { 1603 if (format == 1) { 1604 qemu_log_mask(LOG_GUEST_ERROR, 1605 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1606 end_blk, end_idx); 1607 return; 1608 } 1609 /* Record the IPB in the associated NVT structure */ 1610 ipb_update((uint8_t *) &nvt.w4, priority); 1611 xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); 1612 1613 /* 1614 * On HW, follows a "Broadcast Backlog" to IVPEs 1615 */ 1616 } 1617 1618 do_escalation: 1619 /* 1620 * If activated, escalate notification using the ESe PQ bits and 1621 * the EAS in w4-5 1622 */ 1623 if (!xive_end_is_escalate(&end)) { 1624 return; 1625 } 1626 1627 /* 1628 * Check the END ESe (Event State Buffer for escalation) for even 1629 * futher coalescing in the Router 1630 */ 1631 if (!xive_end_is_uncond_escalation(&end)) { 1632 /* ESe[Q]=1 : end of notification */ 1633 if (!xive_router_end_es_notify(xrtr, end_blk, end_idx, 1634 &end, END_W1_ESe)) { 1635 return; 1636 } 1637 } 1638 1639 /* 1640 * The END trigger becomes an Escalation trigger 1641 */ 1642 xive_router_end_notify(xrtr, 1643 xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), 1644 xive_get_field32(END_W4_ESC_END_INDEX, end.w4), 1645 xive_get_field32(END_W5_ESC_END_DATA, end.w5)); 1646 } 1647 1648 void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 1649 { 1650 XiveRouter *xrtr = XIVE_ROUTER(xn); 1651 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1652 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1653 XiveEAS eas; 1654 1655 /* EAS cache lookup */ 1656 if (xive_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1657 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1658 return; 1659 } 1660 1661 /* 1662 * The IVRE checks the State Bit Cache at this point. We skip the 1663 * SBC lookup because the state bits of the sources are modeled 1664 * internally in QEMU. 1665 */ 1666 1667 if (!xive_eas_is_valid(&eas)) { 1668 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); 1669 return; 1670 } 1671 1672 if (xive_eas_is_masked(&eas)) { 1673 /* Notification completed */ 1674 return; 1675 } 1676 1677 /* 1678 * The event trigger becomes an END trigger 1679 */ 1680 xive_router_end_notify(xrtr, 1681 xive_get_field64(EAS_END_BLOCK, eas.w), 1682 xive_get_field64(EAS_END_INDEX, eas.w), 1683 xive_get_field64(EAS_END_DATA, eas.w)); 1684 } 1685 1686 static void xive_router_class_init(ObjectClass *klass, void *data) 1687 { 1688 DeviceClass *dc = DEVICE_CLASS(klass); 1689 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1690 1691 dc->desc = "XIVE Router Engine"; 1692 xnc->notify = xive_router_notify; 1693 } 1694 1695 static const TypeInfo xive_router_info = { 1696 .name = TYPE_XIVE_ROUTER, 1697 .parent = TYPE_SYS_BUS_DEVICE, 1698 .abstract = true, 1699 .class_size = sizeof(XiveRouterClass), 1700 .class_init = xive_router_class_init, 1701 .interfaces = (InterfaceInfo[]) { 1702 { TYPE_XIVE_NOTIFIER }, 1703 { } 1704 } 1705 }; 1706 1707 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon) 1708 { 1709 if (!xive_eas_is_valid(eas)) { 1710 return; 1711 } 1712 1713 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 1714 lisn, xive_eas_is_masked(eas) ? "M" : " ", 1715 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), 1716 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), 1717 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); 1718 } 1719 1720 /* 1721 * END ESB MMIO loads 1722 */ 1723 static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) 1724 { 1725 XiveENDSource *xsrc = XIVE_END_SOURCE(opaque); 1726 uint32_t offset = addr & 0xFFF; 1727 uint8_t end_blk; 1728 uint32_t end_idx; 1729 XiveEND end; 1730 uint32_t end_esmask; 1731 uint8_t pq; 1732 uint64_t ret = -1; 1733 1734 end_blk = xsrc->block_id; 1735 end_idx = addr >> (xsrc->esb_shift + 1); 1736 1737 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1738 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1739 end_idx); 1740 return -1; 1741 } 1742 1743 if (!xive_end_is_valid(&end)) { 1744 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1745 end_blk, end_idx); 1746 return -1; 1747 } 1748 1749 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; 1750 pq = xive_get_field32(end_esmask, end.w1); 1751 1752 switch (offset) { 1753 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1754 ret = xive_esb_eoi(&pq); 1755 1756 /* Forward the source event notification for routing ?? */ 1757 break; 1758 1759 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1760 ret = pq; 1761 break; 1762 1763 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1764 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1765 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1766 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1767 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1768 break; 1769 default: 1770 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1771 offset); 1772 return -1; 1773 } 1774 1775 if (pq != xive_get_field32(end_esmask, end.w1)) { 1776 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1777 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1778 } 1779 1780 return ret; 1781 } 1782 1783 /* 1784 * END ESB MMIO stores are invalid 1785 */ 1786 static void xive_end_source_write(void *opaque, hwaddr addr, 1787 uint64_t value, unsigned size) 1788 { 1789 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr 0x%" 1790 HWADDR_PRIx"\n", addr); 1791 } 1792 1793 static const MemoryRegionOps xive_end_source_ops = { 1794 .read = xive_end_source_read, 1795 .write = xive_end_source_write, 1796 .endianness = DEVICE_BIG_ENDIAN, 1797 .valid = { 1798 .min_access_size = 8, 1799 .max_access_size = 8, 1800 }, 1801 .impl = { 1802 .min_access_size = 8, 1803 .max_access_size = 8, 1804 }, 1805 }; 1806 1807 static void xive_end_source_realize(DeviceState *dev, Error **errp) 1808 { 1809 XiveENDSource *xsrc = XIVE_END_SOURCE(dev); 1810 Object *obj; 1811 Error *local_err = NULL; 1812 1813 obj = object_property_get_link(OBJECT(dev), "xive", &local_err); 1814 if (!obj) { 1815 error_propagate(errp, local_err); 1816 error_prepend(errp, "required link 'xive' not found: "); 1817 return; 1818 } 1819 1820 xsrc->xrtr = XIVE_ROUTER(obj); 1821 1822 if (!xsrc->nr_ends) { 1823 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1824 return; 1825 } 1826 1827 if (xsrc->esb_shift != XIVE_ESB_4K && 1828 xsrc->esb_shift != XIVE_ESB_64K) { 1829 error_setg(errp, "Invalid ESB shift setting"); 1830 return; 1831 } 1832 1833 /* 1834 * Each END is assigned an even/odd pair of MMIO pages, the even page 1835 * manages the ESn field while the odd page manages the ESe field. 1836 */ 1837 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1838 &xive_end_source_ops, xsrc, "xive.end", 1839 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1840 } 1841 1842 static Property xive_end_source_properties[] = { 1843 DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0), 1844 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), 1845 DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), 1846 DEFINE_PROP_END_OF_LIST(), 1847 }; 1848 1849 static void xive_end_source_class_init(ObjectClass *klass, void *data) 1850 { 1851 DeviceClass *dc = DEVICE_CLASS(klass); 1852 1853 dc->desc = "XIVE END Source"; 1854 dc->props = xive_end_source_properties; 1855 dc->realize = xive_end_source_realize; 1856 /* 1857 * Reason: part of XIVE interrupt controller, needs to be wired up, 1858 * e.g. by spapr_xive_instance_init(). 1859 */ 1860 dc->user_creatable = false; 1861 } 1862 1863 static const TypeInfo xive_end_source_info = { 1864 .name = TYPE_XIVE_END_SOURCE, 1865 .parent = TYPE_DEVICE, 1866 .instance_size = sizeof(XiveENDSource), 1867 .class_init = xive_end_source_class_init, 1868 }; 1869 1870 /* 1871 * XIVE Notifier 1872 */ 1873 static const TypeInfo xive_notifier_info = { 1874 .name = TYPE_XIVE_NOTIFIER, 1875 .parent = TYPE_INTERFACE, 1876 .class_size = sizeof(XiveNotifierClass), 1877 }; 1878 1879 static void xive_register_types(void) 1880 { 1881 type_register_static(&xive_source_info); 1882 type_register_static(&xive_notifier_info); 1883 type_register_static(&xive_router_info); 1884 type_register_static(&xive_end_source_info); 1885 type_register_static(&xive_tctx_info); 1886 } 1887 1888 type_init(xive_register_types) 1889