1 /* 2 * QEMU Xilinx OPB Interrupt Controller. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "qemu/module.h" 28 #include "hw/irq.h" 29 #include "hw/qdev-properties.h" 30 #include "qom/object.h" 31 32 #define D(x) 33 34 #define R_ISR 0 35 #define R_IPR 1 36 #define R_IER 2 37 #define R_IAR 3 38 #define R_SIE 4 39 #define R_CIE 5 40 #define R_IVR 6 41 #define R_MER 7 42 #define R_MAX 8 43 44 #define TYPE_XILINX_INTC "xlnx.xps-intc" 45 DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC, 46 TYPE_XILINX_INTC) 47 48 struct xlx_pic 49 { 50 SysBusDevice parent_obj; 51 52 MemoryRegion mmio; 53 qemu_irq parent_irq; 54 55 /* Configuration reg chosen at synthesis-time. QEMU populates 56 the bits at board-setup. */ 57 uint32_t c_kind_of_intr; 58 59 /* Runtime control registers. */ 60 uint32_t regs[R_MAX]; 61 /* state of the interrupt input pins */ 62 uint32_t irq_pin_state; 63 }; 64 65 static void update_irq(struct xlx_pic *p) 66 { 67 uint32_t i; 68 69 /* level triggered interrupt */ 70 if (p->regs[R_MER] & 2) { 71 p->regs[R_ISR] |= p->irq_pin_state & ~p->c_kind_of_intr; 72 } 73 74 /* Update the pending register. */ 75 p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER]; 76 77 /* Update the vector register. */ 78 for (i = 0; i < 32; i++) { 79 if (p->regs[R_IPR] & (1U << i)) { 80 break; 81 } 82 } 83 if (i == 32) 84 i = ~0; 85 86 p->regs[R_IVR] = i; 87 qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]); 88 } 89 90 static uint64_t 91 pic_read(void *opaque, hwaddr addr, unsigned int size) 92 { 93 struct xlx_pic *p = opaque; 94 uint32_t r = 0; 95 96 addr >>= 2; 97 switch (addr) 98 { 99 default: 100 if (addr < ARRAY_SIZE(p->regs)) 101 r = p->regs[addr]; 102 break; 103 104 } 105 D(printf("%s %x=%x\n", __func__, addr * 4, r)); 106 return r; 107 } 108 109 static void 110 pic_write(void *opaque, hwaddr addr, 111 uint64_t val64, unsigned int size) 112 { 113 struct xlx_pic *p = opaque; 114 uint32_t value = val64; 115 116 addr >>= 2; 117 D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value)); 118 switch (addr) 119 { 120 case R_IAR: 121 p->regs[R_ISR] &= ~value; /* ACK. */ 122 break; 123 case R_SIE: 124 p->regs[R_IER] |= value; /* Atomic set ie. */ 125 break; 126 case R_CIE: 127 p->regs[R_IER] &= ~value; /* Atomic clear ie. */ 128 break; 129 case R_MER: 130 p->regs[R_MER] = value & 0x3; 131 break; 132 case R_ISR: 133 if ((p->regs[R_MER] & 2)) { 134 break; 135 } 136 /* fallthrough */ 137 default: 138 if (addr < ARRAY_SIZE(p->regs)) 139 p->regs[addr] = value; 140 break; 141 } 142 update_irq(p); 143 } 144 145 static const MemoryRegionOps pic_ops = { 146 .read = pic_read, 147 .write = pic_write, 148 .endianness = DEVICE_NATIVE_ENDIAN, 149 .valid = { 150 .min_access_size = 4, 151 .max_access_size = 4 152 } 153 }; 154 155 static void irq_handler(void *opaque, int irq, int level) 156 { 157 struct xlx_pic *p = opaque; 158 159 /* edge triggered interrupt */ 160 if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) { 161 p->regs[R_ISR] |= (level << irq); 162 } 163 164 p->irq_pin_state &= ~(1 << irq); 165 p->irq_pin_state |= level << irq; 166 update_irq(p); 167 } 168 169 static void xilinx_intc_init(Object *obj) 170 { 171 struct xlx_pic *p = XILINX_INTC(obj); 172 173 qdev_init_gpio_in(DEVICE(obj), irq_handler, 32); 174 sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq); 175 176 memory_region_init_io(&p->mmio, obj, &pic_ops, p, "xlnx.xps-intc", 177 R_MAX * 4); 178 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio); 179 } 180 181 static Property xilinx_intc_properties[] = { 182 DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0), 183 DEFINE_PROP_END_OF_LIST(), 184 }; 185 186 static void xilinx_intc_class_init(ObjectClass *klass, void *data) 187 { 188 DeviceClass *dc = DEVICE_CLASS(klass); 189 190 device_class_set_props(dc, xilinx_intc_properties); 191 } 192 193 static const TypeInfo xilinx_intc_info = { 194 .name = TYPE_XILINX_INTC, 195 .parent = TYPE_SYS_BUS_DEVICE, 196 .instance_size = sizeof(struct xlx_pic), 197 .instance_init = xilinx_intc_init, 198 .class_init = xilinx_intc_class_init, 199 }; 200 201 static void xilinx_intc_register_types(void) 202 { 203 type_register_static(&xilinx_intc_info); 204 } 205 206 type_init(xilinx_intc_register_types) 207