1 /* 2 * QEMU Xilinx OPB Interrupt Controller. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "hw/sysbus.h" 26 #include "hw/hw.h" 27 28 #define D(x) 29 30 #define R_ISR 0 31 #define R_IPR 1 32 #define R_IER 2 33 #define R_IAR 3 34 #define R_SIE 4 35 #define R_CIE 5 36 #define R_IVR 6 37 #define R_MER 7 38 #define R_MAX 8 39 40 #define TYPE_XILINX_INTC "xlnx.xps-intc" 41 #define XILINX_INTC(obj) OBJECT_CHECK(struct xlx_pic, (obj), TYPE_XILINX_INTC) 42 43 struct xlx_pic 44 { 45 SysBusDevice parent_obj; 46 47 MemoryRegion mmio; 48 qemu_irq parent_irq; 49 50 /* Configuration reg chosen at synthesis-time. QEMU populates 51 the bits at board-setup. */ 52 uint32_t c_kind_of_intr; 53 54 /* Runtime control registers. */ 55 uint32_t regs[R_MAX]; 56 /* state of the interrupt input pins */ 57 uint32_t irq_pin_state; 58 }; 59 60 static void update_irq(struct xlx_pic *p) 61 { 62 uint32_t i; 63 64 /* level triggered interrupt */ 65 if (p->regs[R_MER] & 2) { 66 p->regs[R_ISR] |= p->irq_pin_state & ~p->c_kind_of_intr; 67 } 68 69 /* Update the pending register. */ 70 p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER]; 71 72 /* Update the vector register. */ 73 for (i = 0; i < 32; i++) { 74 if (p->regs[R_IPR] & (1U << i)) { 75 break; 76 } 77 } 78 if (i == 32) 79 i = ~0; 80 81 p->regs[R_IVR] = i; 82 qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]); 83 } 84 85 static uint64_t 86 pic_read(void *opaque, hwaddr addr, unsigned int size) 87 { 88 struct xlx_pic *p = opaque; 89 uint32_t r = 0; 90 91 addr >>= 2; 92 switch (addr) 93 { 94 default: 95 if (addr < ARRAY_SIZE(p->regs)) 96 r = p->regs[addr]; 97 break; 98 99 } 100 D(printf("%s %x=%x\n", __func__, addr * 4, r)); 101 return r; 102 } 103 104 static void 105 pic_write(void *opaque, hwaddr addr, 106 uint64_t val64, unsigned int size) 107 { 108 struct xlx_pic *p = opaque; 109 uint32_t value = val64; 110 111 addr >>= 2; 112 D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value)); 113 switch (addr) 114 { 115 case R_IAR: 116 p->regs[R_ISR] &= ~value; /* ACK. */ 117 break; 118 case R_SIE: 119 p->regs[R_IER] |= value; /* Atomic set ie. */ 120 break; 121 case R_CIE: 122 p->regs[R_IER] &= ~value; /* Atomic clear ie. */ 123 break; 124 case R_MER: 125 p->regs[R_MER] = value & 0x3; 126 break; 127 case R_ISR: 128 if ((p->regs[R_MER] & 2)) { 129 break; 130 } 131 /* fallthrough */ 132 default: 133 if (addr < ARRAY_SIZE(p->regs)) 134 p->regs[addr] = value; 135 break; 136 } 137 update_irq(p); 138 } 139 140 static const MemoryRegionOps pic_ops = { 141 .read = pic_read, 142 .write = pic_write, 143 .endianness = DEVICE_NATIVE_ENDIAN, 144 .valid = { 145 .min_access_size = 4, 146 .max_access_size = 4 147 } 148 }; 149 150 static void irq_handler(void *opaque, int irq, int level) 151 { 152 struct xlx_pic *p = opaque; 153 154 /* edge triggered interrupt */ 155 if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) { 156 p->regs[R_ISR] |= (level << irq); 157 } 158 159 p->irq_pin_state &= ~(1 << irq); 160 p->irq_pin_state |= level << irq; 161 update_irq(p); 162 } 163 164 static int xilinx_intc_init(SysBusDevice *sbd) 165 { 166 DeviceState *dev = DEVICE(sbd); 167 struct xlx_pic *p = XILINX_INTC(dev); 168 169 qdev_init_gpio_in(dev, irq_handler, 32); 170 sysbus_init_irq(sbd, &p->parent_irq); 171 172 memory_region_init_io(&p->mmio, OBJECT(p), &pic_ops, p, "xlnx.xps-intc", 173 R_MAX * 4); 174 sysbus_init_mmio(sbd, &p->mmio); 175 return 0; 176 } 177 178 static Property xilinx_intc_properties[] = { 179 DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0), 180 DEFINE_PROP_END_OF_LIST(), 181 }; 182 183 static void xilinx_intc_class_init(ObjectClass *klass, void *data) 184 { 185 DeviceClass *dc = DEVICE_CLASS(klass); 186 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 187 188 k->init = xilinx_intc_init; 189 dc->props = xilinx_intc_properties; 190 } 191 192 static const TypeInfo xilinx_intc_info = { 193 .name = TYPE_XILINX_INTC, 194 .parent = TYPE_SYS_BUS_DEVICE, 195 .instance_size = sizeof(struct xlx_pic), 196 .class_init = xilinx_intc_class_init, 197 }; 198 199 static void xilinx_intc_register_types(void) 200 { 201 type_register_static(&xilinx_intc_info); 202 } 203 204 type_init(xilinx_intc_register_types) 205