1 /* 2 * QEMU Xilinx OPB Interrupt Controller. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "hw/sysbus.h" 26 #include "hw/hw.h" 27 28 #define D(x) 29 30 #define R_ISR 0 31 #define R_IPR 1 32 #define R_IER 2 33 #define R_IAR 3 34 #define R_SIE 4 35 #define R_CIE 5 36 #define R_IVR 6 37 #define R_MER 7 38 #define R_MAX 8 39 40 #define TYPE_XILINX_INTC "xlnx.xps-intc" 41 #define XILINX_INTC(obj) OBJECT_CHECK(struct xlx_pic, (obj), TYPE_XILINX_INTC) 42 43 struct xlx_pic 44 { 45 SysBusDevice parent_obj; 46 47 MemoryRegion mmio; 48 qemu_irq parent_irq; 49 50 /* Configuration reg chosen at synthesis-time. QEMU populates 51 the bits at board-setup. */ 52 uint32_t c_kind_of_intr; 53 54 /* Runtime control registers. */ 55 uint32_t regs[R_MAX]; 56 /* state of the interrupt input pins */ 57 uint32_t irq_pin_state; 58 }; 59 60 static void update_irq(struct xlx_pic *p) 61 { 62 uint32_t i; 63 64 /* level triggered interrupt */ 65 if (p->regs[R_MER] & 2) { 66 p->regs[R_ISR] |= p->irq_pin_state & ~p->c_kind_of_intr; 67 } 68 69 /* Update the pending register. */ 70 p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER]; 71 72 /* Update the vector register. */ 73 for (i = 0; i < 32; i++) { 74 if (p->regs[R_IPR] & (1 << i)) 75 break; 76 } 77 if (i == 32) 78 i = ~0; 79 80 p->regs[R_IVR] = i; 81 qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]); 82 } 83 84 static uint64_t 85 pic_read(void *opaque, hwaddr addr, unsigned int size) 86 { 87 struct xlx_pic *p = opaque; 88 uint32_t r = 0; 89 90 addr >>= 2; 91 switch (addr) 92 { 93 default: 94 if (addr < ARRAY_SIZE(p->regs)) 95 r = p->regs[addr]; 96 break; 97 98 } 99 D(printf("%s %x=%x\n", __func__, addr * 4, r)); 100 return r; 101 } 102 103 static void 104 pic_write(void *opaque, hwaddr addr, 105 uint64_t val64, unsigned int size) 106 { 107 struct xlx_pic *p = opaque; 108 uint32_t value = val64; 109 110 addr >>= 2; 111 D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value)); 112 switch (addr) 113 { 114 case R_IAR: 115 p->regs[R_ISR] &= ~value; /* ACK. */ 116 break; 117 case R_SIE: 118 p->regs[R_IER] |= value; /* Atomic set ie. */ 119 break; 120 case R_CIE: 121 p->regs[R_IER] &= ~value; /* Atomic clear ie. */ 122 break; 123 case R_ISR: 124 if ((p->regs[R_MER] & 2)) { 125 break; 126 } 127 /* fallthrough */ 128 default: 129 if (addr < ARRAY_SIZE(p->regs)) 130 p->regs[addr] = value; 131 break; 132 } 133 update_irq(p); 134 } 135 136 static const MemoryRegionOps pic_ops = { 137 .read = pic_read, 138 .write = pic_write, 139 .endianness = DEVICE_NATIVE_ENDIAN, 140 .valid = { 141 .min_access_size = 4, 142 .max_access_size = 4 143 } 144 }; 145 146 static void irq_handler(void *opaque, int irq, int level) 147 { 148 struct xlx_pic *p = opaque; 149 150 /* edge triggered interrupt */ 151 if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) { 152 p->regs[R_ISR] |= (level << irq); 153 } 154 155 p->irq_pin_state &= ~(1 << irq); 156 p->irq_pin_state |= level << irq; 157 update_irq(p); 158 } 159 160 static int xilinx_intc_init(SysBusDevice *sbd) 161 { 162 DeviceState *dev = DEVICE(sbd); 163 struct xlx_pic *p = XILINX_INTC(dev); 164 165 qdev_init_gpio_in(dev, irq_handler, 32); 166 sysbus_init_irq(sbd, &p->parent_irq); 167 168 memory_region_init_io(&p->mmio, OBJECT(p), &pic_ops, p, "xlnx.xps-intc", 169 R_MAX * 4); 170 sysbus_init_mmio(sbd, &p->mmio); 171 return 0; 172 } 173 174 static Property xilinx_intc_properties[] = { 175 DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0), 176 DEFINE_PROP_END_OF_LIST(), 177 }; 178 179 static void xilinx_intc_class_init(ObjectClass *klass, void *data) 180 { 181 DeviceClass *dc = DEVICE_CLASS(klass); 182 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 183 184 k->init = xilinx_intc_init; 185 dc->props = xilinx_intc_properties; 186 } 187 188 static const TypeInfo xilinx_intc_info = { 189 .name = TYPE_XILINX_INTC, 190 .parent = TYPE_SYS_BUS_DEVICE, 191 .instance_size = sizeof(struct xlx_pic), 192 .class_init = xilinx_intc_class_init, 193 }; 194 195 static void xilinx_intc_register_types(void) 196 { 197 type_register_static(&xilinx_intc_info); 198 } 199 200 type_init(xilinx_intc_register_types) 201