xref: /openbmc/qemu/hw/intc/xilinx_intc.c (revision 4a66d3bf) 
1 /*
2  * QEMU Xilinx OPB Interrupt Controller.
3  *
4  * Copyright (c) 2009 Edgar E. Iglesias.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "hw/sysbus.h"
26 #include "hw/hw.h"
27 
28 #define D(x)
29 
30 #define R_ISR       0
31 #define R_IPR       1
32 #define R_IER       2
33 #define R_IAR       3
34 #define R_SIE       4
35 #define R_CIE       5
36 #define R_IVR       6
37 #define R_MER       7
38 #define R_MAX       8
39 
40 #define TYPE_XILINX_INTC "xlnx.xps-intc"
41 #define XILINX_INTC(obj) OBJECT_CHECK(struct xlx_pic, (obj), TYPE_XILINX_INTC)
42 
43 struct xlx_pic
44 {
45     SysBusDevice parent_obj;
46 
47     MemoryRegion mmio;
48     qemu_irq parent_irq;
49 
50     /* Configuration reg chosen at synthesis-time. QEMU populates
51        the bits at board-setup.  */
52     uint32_t c_kind_of_intr;
53 
54     /* Runtime control registers.  */
55     uint32_t regs[R_MAX];
56     /* state of the interrupt input pins */
57     uint32_t irq_pin_state;
58 };
59 
60 static void update_irq(struct xlx_pic *p)
61 {
62     uint32_t i;
63 
64     /* level triggered interrupt */
65     if (p->regs[R_MER] & 2) {
66         p->regs[R_ISR] |= p->irq_pin_state & ~p->c_kind_of_intr;
67     }
68 
69     /* Update the pending register.  */
70     p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER];
71 
72     /* Update the vector register.  */
73     for (i = 0; i < 32; i++) {
74         if (p->regs[R_IPR] & (1U << i)) {
75             break;
76         }
77     }
78     if (i == 32)
79         i = ~0;
80 
81     p->regs[R_IVR] = i;
82     qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]);
83 }
84 
85 static uint64_t
86 pic_read(void *opaque, hwaddr addr, unsigned int size)
87 {
88     struct xlx_pic *p = opaque;
89     uint32_t r = 0;
90 
91     addr >>= 2;
92     switch (addr)
93     {
94         default:
95             if (addr < ARRAY_SIZE(p->regs))
96                 r = p->regs[addr];
97             break;
98 
99     }
100     D(printf("%s %x=%x\n", __func__, addr * 4, r));
101     return r;
102 }
103 
104 static void
105 pic_write(void *opaque, hwaddr addr,
106           uint64_t val64, unsigned int size)
107 {
108     struct xlx_pic *p = opaque;
109     uint32_t value = val64;
110 
111     addr >>= 2;
112     D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
113     switch (addr)
114     {
115         case R_IAR:
116             p->regs[R_ISR] &= ~value; /* ACK.  */
117             break;
118         case R_SIE:
119             p->regs[R_IER] |= value;  /* Atomic set ie.  */
120             break;
121         case R_CIE:
122             p->regs[R_IER] &= ~value; /* Atomic clear ie.  */
123             break;
124         case R_ISR:
125             if ((p->regs[R_MER] & 2)) {
126                 break;
127             }
128             /* fallthrough */
129         default:
130             if (addr < ARRAY_SIZE(p->regs))
131                 p->regs[addr] = value;
132             break;
133     }
134     update_irq(p);
135 }
136 
137 static const MemoryRegionOps pic_ops = {
138     .read = pic_read,
139     .write = pic_write,
140     .endianness = DEVICE_NATIVE_ENDIAN,
141     .valid = {
142         .min_access_size = 4,
143         .max_access_size = 4
144     }
145 };
146 
147 static void irq_handler(void *opaque, int irq, int level)
148 {
149     struct xlx_pic *p = opaque;
150 
151     /* edge triggered interrupt */
152     if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) {
153         p->regs[R_ISR] |= (level << irq);
154     }
155 
156     p->irq_pin_state &= ~(1 << irq);
157     p->irq_pin_state |= level << irq;
158     update_irq(p);
159 }
160 
161 static int xilinx_intc_init(SysBusDevice *sbd)
162 {
163     DeviceState *dev = DEVICE(sbd);
164     struct xlx_pic *p = XILINX_INTC(dev);
165 
166     qdev_init_gpio_in(dev, irq_handler, 32);
167     sysbus_init_irq(sbd, &p->parent_irq);
168 
169     memory_region_init_io(&p->mmio, OBJECT(p), &pic_ops, p, "xlnx.xps-intc",
170                           R_MAX * 4);
171     sysbus_init_mmio(sbd, &p->mmio);
172     return 0;
173 }
174 
175 static Property xilinx_intc_properties[] = {
176     DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0),
177     DEFINE_PROP_END_OF_LIST(),
178 };
179 
180 static void xilinx_intc_class_init(ObjectClass *klass, void *data)
181 {
182     DeviceClass *dc = DEVICE_CLASS(klass);
183     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
184 
185     k->init = xilinx_intc_init;
186     dc->props = xilinx_intc_properties;
187 }
188 
189 static const TypeInfo xilinx_intc_info = {
190     .name          = TYPE_XILINX_INTC,
191     .parent        = TYPE_SYS_BUS_DEVICE,
192     .instance_size = sizeof(struct xlx_pic),
193     .class_init    = xilinx_intc_class_init,
194 };
195 
196 static void xilinx_intc_register_types(void)
197 {
198     type_register_static(&xilinx_intc_info);
199 }
200 
201 type_init(xilinx_intc_register_types)
202