1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics 5 * 6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 28 #include "qemu/osdep.h" 29 #include "cpu.h" 30 #include "hw/hw.h" 31 #include "trace.h" 32 #include "qemu/timer.h" 33 #include "hw/ppc/spapr.h" 34 #include "hw/ppc/spapr_cpu_core.h" 35 #include "hw/ppc/xics.h" 36 #include "hw/ppc/xics_spapr.h" 37 #include "hw/ppc/fdt.h" 38 #include "qapi/visitor.h" 39 40 /* 41 * Guest interfaces 42 */ 43 44 static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 45 target_ulong opcode, target_ulong *args) 46 { 47 target_ulong cppr = args[0]; 48 49 icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr); 50 return H_SUCCESS; 51 } 52 53 static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 54 target_ulong opcode, target_ulong *args) 55 { 56 target_ulong mfrr = args[1]; 57 ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]); 58 59 if (!icp) { 60 return H_PARAMETER; 61 } 62 63 icp_set_mfrr(icp, mfrr); 64 return H_SUCCESS; 65 } 66 67 static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 68 target_ulong opcode, target_ulong *args) 69 { 70 uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp); 71 72 args[0] = xirr; 73 return H_SUCCESS; 74 } 75 76 static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr, 77 target_ulong opcode, target_ulong *args) 78 { 79 uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp); 80 81 args[0] = xirr; 82 args[1] = cpu_get_host_ticks(); 83 return H_SUCCESS; 84 } 85 86 static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 87 target_ulong opcode, target_ulong *args) 88 { 89 target_ulong xirr = args[0]; 90 91 icp_eoi(spapr_cpu_state(cpu)->icp, xirr); 92 return H_SUCCESS; 93 } 94 95 static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr, 96 target_ulong opcode, target_ulong *args) 97 { 98 uint32_t mfrr; 99 uint32_t xirr = icp_ipoll(spapr_cpu_state(cpu)->icp, &mfrr); 100 101 args[0] = xirr; 102 args[1] = mfrr; 103 104 return H_SUCCESS; 105 } 106 107 static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr, 108 uint32_t token, 109 uint32_t nargs, target_ulong args, 110 uint32_t nret, target_ulong rets) 111 { 112 ICSState *ics = spapr->ics; 113 uint32_t nr, srcno, server, priority; 114 115 if ((nargs != 3) || (nret != 1)) { 116 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 117 return; 118 } 119 if (!ics) { 120 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 121 return; 122 } 123 124 nr = rtas_ld(args, 0); 125 server = rtas_ld(args, 1); 126 priority = rtas_ld(args, 2); 127 128 if (!ics_valid_irq(ics, nr) || !xics_icp_get(XICS_FABRIC(spapr), server) 129 || (priority > 0xff)) { 130 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 131 return; 132 } 133 134 srcno = nr - ics->offset; 135 ics_simple_write_xive(ics, srcno, server, priority, priority); 136 137 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 138 } 139 140 static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr, 141 uint32_t token, 142 uint32_t nargs, target_ulong args, 143 uint32_t nret, target_ulong rets) 144 { 145 ICSState *ics = spapr->ics; 146 uint32_t nr, srcno; 147 148 if ((nargs != 1) || (nret != 3)) { 149 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 150 return; 151 } 152 if (!ics) { 153 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 154 return; 155 } 156 157 nr = rtas_ld(args, 0); 158 159 if (!ics_valid_irq(ics, nr)) { 160 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 161 return; 162 } 163 164 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 165 srcno = nr - ics->offset; 166 rtas_st(rets, 1, ics->irqs[srcno].server); 167 rtas_st(rets, 2, ics->irqs[srcno].priority); 168 } 169 170 static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr, 171 uint32_t token, 172 uint32_t nargs, target_ulong args, 173 uint32_t nret, target_ulong rets) 174 { 175 ICSState *ics = spapr->ics; 176 uint32_t nr, srcno; 177 178 if ((nargs != 1) || (nret != 1)) { 179 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 180 return; 181 } 182 if (!ics) { 183 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 184 return; 185 } 186 187 nr = rtas_ld(args, 0); 188 189 if (!ics_valid_irq(ics, nr)) { 190 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 191 return; 192 } 193 194 srcno = nr - ics->offset; 195 ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff, 196 ics->irqs[srcno].priority); 197 198 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 199 } 200 201 static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr, 202 uint32_t token, 203 uint32_t nargs, target_ulong args, 204 uint32_t nret, target_ulong rets) 205 { 206 ICSState *ics = spapr->ics; 207 uint32_t nr, srcno; 208 209 if ((nargs != 1) || (nret != 1)) { 210 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 211 return; 212 } 213 if (!ics) { 214 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 215 return; 216 } 217 218 nr = rtas_ld(args, 0); 219 220 if (!ics_valid_irq(ics, nr)) { 221 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 222 return; 223 } 224 225 srcno = nr - ics->offset; 226 ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server, 227 ics->irqs[srcno].saved_priority, 228 ics->irqs[srcno].saved_priority); 229 230 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 231 } 232 233 void xics_spapr_init(sPAPRMachineState *spapr) 234 { 235 /* Registration of global state belongs into realize */ 236 spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive); 237 spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive); 238 spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off); 239 spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on); 240 241 spapr_register_hypercall(H_CPPR, h_cppr); 242 spapr_register_hypercall(H_IPI, h_ipi); 243 spapr_register_hypercall(H_XIRR, h_xirr); 244 spapr_register_hypercall(H_XIRR_X, h_xirr_x); 245 spapr_register_hypercall(H_EOI, h_eoi); 246 spapr_register_hypercall(H_IPOLL, h_ipoll); 247 } 248 249 void spapr_dt_xics(sPAPRMachineState *spapr, uint32_t nr_servers, void *fdt, 250 uint32_t phandle) 251 { 252 uint32_t interrupt_server_ranges_prop[] = { 253 0, cpu_to_be32(nr_servers), 254 }; 255 int node; 256 257 _FDT(node = fdt_add_subnode(fdt, 0, XICS_NODENAME)); 258 259 _FDT(fdt_setprop_string(fdt, node, "device_type", 260 "PowerPC-External-Interrupt-Presentation")); 261 _FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp")); 262 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 263 _FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges", 264 interrupt_server_ranges_prop, 265 sizeof(interrupt_server_ranges_prop))); 266 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 267 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 268 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 269 } 270