1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics 5 * 6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qapi/error.h" 30 #include "cpu.h" 31 #include "trace.h" 32 #include "qemu/timer.h" 33 #include "hw/ppc/xics.h" 34 #include "hw/qdev-properties.h" 35 #include "qemu/error-report.h" 36 #include "qemu/module.h" 37 #include "qapi/visitor.h" 38 #include "migration/vmstate.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/irq.h" 42 #include "sysemu/kvm.h" 43 #include "sysemu/reset.h" 44 45 void icp_pic_print_info(ICPState *icp, Monitor *mon) 46 { 47 int cpu_index; 48 49 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs 50 * are hot plugged or unplugged. 51 */ 52 if (!icp) { 53 return; 54 } 55 56 cpu_index = icp->cs ? icp->cs->cpu_index : -1; 57 58 if (!icp->output) { 59 return; 60 } 61 62 if (kvm_irqchip_in_kernel()) { 63 icp_synchronize_state(icp); 64 } 65 66 monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n", 67 cpu_index, icp->xirr, icp->xirr_owner, 68 icp->pending_priority, icp->mfrr); 69 } 70 71 void ics_pic_print_info(ICSState *ics, Monitor *mon) 72 { 73 uint32_t i; 74 75 monitor_printf(mon, "ICS %4x..%4x %p\n", 76 ics->offset, ics->offset + ics->nr_irqs - 1, ics); 77 78 if (!ics->irqs) { 79 return; 80 } 81 82 if (kvm_irqchip_in_kernel()) { 83 ics_synchronize_state(ics); 84 } 85 86 for (i = 0; i < ics->nr_irqs; i++) { 87 ICSIRQState *irq = ics->irqs + i; 88 89 if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) { 90 continue; 91 } 92 monitor_printf(mon, " %4x %s %02x %02x\n", 93 ics->offset + i, 94 (irq->flags & XICS_FLAGS_IRQ_LSI) ? 95 "LSI" : "MSI", 96 irq->priority, irq->status); 97 } 98 } 99 100 /* 101 * ICP: Presentation layer 102 */ 103 104 #define XISR_MASK 0x00ffffff 105 #define CPPR_MASK 0xff000000 106 107 #define XISR(icp) (((icp)->xirr) & XISR_MASK) 108 #define CPPR(icp) (((icp)->xirr) >> 24) 109 110 static void ics_reject(ICSState *ics, uint32_t nr); 111 static void ics_eoi(ICSState *ics, uint32_t nr); 112 113 static void icp_check_ipi(ICPState *icp) 114 { 115 if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) { 116 return; 117 } 118 119 trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr); 120 121 if (XISR(icp) && icp->xirr_owner) { 122 ics_reject(icp->xirr_owner, XISR(icp)); 123 } 124 125 icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI; 126 icp->pending_priority = icp->mfrr; 127 icp->xirr_owner = NULL; 128 qemu_irq_raise(icp->output); 129 } 130 131 void icp_resend(ICPState *icp) 132 { 133 XICSFabric *xi = icp->xics; 134 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); 135 136 if (icp->mfrr < CPPR(icp)) { 137 icp_check_ipi(icp); 138 } 139 140 xic->ics_resend(xi); 141 } 142 143 void icp_set_cppr(ICPState *icp, uint8_t cppr) 144 { 145 uint8_t old_cppr; 146 uint32_t old_xisr; 147 148 old_cppr = CPPR(icp); 149 icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24); 150 151 if (cppr < old_cppr) { 152 if (XISR(icp) && (cppr <= icp->pending_priority)) { 153 old_xisr = XISR(icp); 154 icp->xirr &= ~XISR_MASK; /* Clear XISR */ 155 icp->pending_priority = 0xff; 156 qemu_irq_lower(icp->output); 157 if (icp->xirr_owner) { 158 ics_reject(icp->xirr_owner, old_xisr); 159 icp->xirr_owner = NULL; 160 } 161 } 162 } else { 163 if (!XISR(icp)) { 164 icp_resend(icp); 165 } 166 } 167 } 168 169 void icp_set_mfrr(ICPState *icp, uint8_t mfrr) 170 { 171 icp->mfrr = mfrr; 172 if (mfrr < CPPR(icp)) { 173 icp_check_ipi(icp); 174 } 175 } 176 177 uint32_t icp_accept(ICPState *icp) 178 { 179 uint32_t xirr = icp->xirr; 180 181 qemu_irq_lower(icp->output); 182 icp->xirr = icp->pending_priority << 24; 183 icp->pending_priority = 0xff; 184 icp->xirr_owner = NULL; 185 186 trace_xics_icp_accept(xirr, icp->xirr); 187 188 return xirr; 189 } 190 191 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr) 192 { 193 if (mfrr) { 194 *mfrr = icp->mfrr; 195 } 196 return icp->xirr; 197 } 198 199 void icp_eoi(ICPState *icp, uint32_t xirr) 200 { 201 XICSFabric *xi = icp->xics; 202 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); 203 ICSState *ics; 204 uint32_t irq; 205 206 /* Send EOI -> ICS */ 207 icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK); 208 trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr); 209 irq = xirr & XISR_MASK; 210 211 ics = xic->ics_get(xi, irq); 212 if (ics) { 213 ics_eoi(ics, irq); 214 } 215 if (!XISR(icp)) { 216 icp_resend(icp); 217 } 218 } 219 220 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority) 221 { 222 ICPState *icp = xics_icp_get(ics->xics, server); 223 224 trace_xics_icp_irq(server, nr, priority); 225 226 if ((priority >= CPPR(icp)) 227 || (XISR(icp) && (icp->pending_priority <= priority))) { 228 ics_reject(ics, nr); 229 } else { 230 if (XISR(icp) && icp->xirr_owner) { 231 ics_reject(icp->xirr_owner, XISR(icp)); 232 icp->xirr_owner = NULL; 233 } 234 icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK); 235 icp->xirr_owner = ics; 236 icp->pending_priority = priority; 237 trace_xics_icp_raise(icp->xirr, icp->pending_priority); 238 qemu_irq_raise(icp->output); 239 } 240 } 241 242 static int icp_pre_save(void *opaque) 243 { 244 ICPState *icp = opaque; 245 246 if (kvm_irqchip_in_kernel()) { 247 icp_get_kvm_state(icp); 248 } 249 250 return 0; 251 } 252 253 static int icp_post_load(void *opaque, int version_id) 254 { 255 ICPState *icp = opaque; 256 257 if (kvm_irqchip_in_kernel()) { 258 Error *local_err = NULL; 259 int ret; 260 261 ret = icp_set_kvm_state(icp, &local_err); 262 if (ret < 0) { 263 error_report_err(local_err); 264 return ret; 265 } 266 } 267 268 return 0; 269 } 270 271 static const VMStateDescription vmstate_icp_server = { 272 .name = "icp/server", 273 .version_id = 1, 274 .minimum_version_id = 1, 275 .pre_save = icp_pre_save, 276 .post_load = icp_post_load, 277 .fields = (VMStateField[]) { 278 /* Sanity check */ 279 VMSTATE_UINT32(xirr, ICPState), 280 VMSTATE_UINT8(pending_priority, ICPState), 281 VMSTATE_UINT8(mfrr, ICPState), 282 VMSTATE_END_OF_LIST() 283 }, 284 }; 285 286 void icp_reset(ICPState *icp) 287 { 288 icp->xirr = 0; 289 icp->pending_priority = 0xff; 290 icp->mfrr = 0xff; 291 292 /* Make all outputs are deasserted */ 293 qemu_set_irq(icp->output, 0); 294 295 if (kvm_irqchip_in_kernel()) { 296 Error *local_err = NULL; 297 298 icp_set_kvm_state(icp, &local_err); 299 if (local_err) { 300 error_report_err(local_err); 301 } 302 } 303 } 304 305 static void icp_realize(DeviceState *dev, Error **errp) 306 { 307 ICPState *icp = ICP(dev); 308 PowerPCCPU *cpu; 309 CPUPPCState *env; 310 Object *obj; 311 Error *err = NULL; 312 313 obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err); 314 if (!obj) { 315 error_propagate_prepend(errp, err, 316 "required link '" ICP_PROP_XICS 317 "' not found: "); 318 return; 319 } 320 321 icp->xics = XICS_FABRIC(obj); 322 323 obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err); 324 if (!obj) { 325 error_propagate_prepend(errp, err, 326 "required link '" ICP_PROP_CPU 327 "' not found: "); 328 return; 329 } 330 331 cpu = POWERPC_CPU(obj); 332 icp->cs = CPU(obj); 333 334 env = &cpu->env; 335 switch (PPC_INPUT(env)) { 336 case PPC_FLAGS_INPUT_POWER7: 337 icp->output = env->irq_inputs[POWER7_INPUT_INT]; 338 break; 339 case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */ 340 icp->output = env->irq_inputs[POWER9_INPUT_INT]; 341 break; 342 343 case PPC_FLAGS_INPUT_970: 344 icp->output = env->irq_inputs[PPC970_INPUT_INT]; 345 break; 346 347 default: 348 error_setg(errp, "XICS interrupt controller does not support this CPU bus model"); 349 return; 350 } 351 352 /* Connect the presenter to the VCPU (required for CPU hotplug) */ 353 if (kvm_irqchip_in_kernel()) { 354 icp_kvm_realize(dev, &err); 355 if (err) { 356 error_propagate(errp, err); 357 return; 358 } 359 } 360 361 vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp); 362 } 363 364 static void icp_unrealize(DeviceState *dev, Error **errp) 365 { 366 ICPState *icp = ICP(dev); 367 368 vmstate_unregister(NULL, &vmstate_icp_server, icp); 369 } 370 371 static void icp_class_init(ObjectClass *klass, void *data) 372 { 373 DeviceClass *dc = DEVICE_CLASS(klass); 374 375 dc->realize = icp_realize; 376 dc->unrealize = icp_unrealize; 377 /* 378 * Reason: part of XICS interrupt controller, needs to be wired up 379 * by icp_create(). 380 */ 381 dc->user_creatable = false; 382 } 383 384 static const TypeInfo icp_info = { 385 .name = TYPE_ICP, 386 .parent = TYPE_DEVICE, 387 .instance_size = sizeof(ICPState), 388 .class_init = icp_class_init, 389 .class_size = sizeof(ICPStateClass), 390 }; 391 392 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp) 393 { 394 Error *local_err = NULL; 395 Object *obj; 396 397 obj = object_new(type); 398 object_property_add_child(cpu, type, obj, &error_abort); 399 object_unref(obj); 400 object_ref(OBJECT(xi)); 401 object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi), 402 &error_abort); 403 object_ref(cpu); 404 object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort); 405 object_property_set_bool(obj, true, "realized", &local_err); 406 if (local_err) { 407 object_unparent(obj); 408 error_propagate(errp, local_err); 409 obj = NULL; 410 } 411 412 return obj; 413 } 414 415 void icp_destroy(ICPState *icp) 416 { 417 Object *obj = OBJECT(icp); 418 419 object_unref(object_property_get_link(obj, ICP_PROP_CPU, &error_abort)); 420 object_unref(object_property_get_link(obj, ICP_PROP_XICS, &error_abort)); 421 object_unparent(obj); 422 } 423 424 /* 425 * ICS: Source layer 426 */ 427 static void ics_resend_msi(ICSState *ics, int srcno) 428 { 429 ICSIRQState *irq = ics->irqs + srcno; 430 431 /* FIXME: filter by server#? */ 432 if (irq->status & XICS_STATUS_REJECTED) { 433 irq->status &= ~XICS_STATUS_REJECTED; 434 if (irq->priority != 0xff) { 435 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); 436 } 437 } 438 } 439 440 static void ics_resend_lsi(ICSState *ics, int srcno) 441 { 442 ICSIRQState *irq = ics->irqs + srcno; 443 444 if ((irq->priority != 0xff) 445 && (irq->status & XICS_STATUS_ASSERTED) 446 && !(irq->status & XICS_STATUS_SENT)) { 447 irq->status |= XICS_STATUS_SENT; 448 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); 449 } 450 } 451 452 static void ics_set_irq_msi(ICSState *ics, int srcno, int val) 453 { 454 ICSIRQState *irq = ics->irqs + srcno; 455 456 trace_xics_ics_set_irq_msi(srcno, srcno + ics->offset); 457 458 if (val) { 459 if (irq->priority == 0xff) { 460 irq->status |= XICS_STATUS_MASKED_PENDING; 461 trace_xics_masked_pending(); 462 } else { 463 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); 464 } 465 } 466 } 467 468 static void ics_set_irq_lsi(ICSState *ics, int srcno, int val) 469 { 470 ICSIRQState *irq = ics->irqs + srcno; 471 472 trace_xics_ics_set_irq_lsi(srcno, srcno + ics->offset); 473 if (val) { 474 irq->status |= XICS_STATUS_ASSERTED; 475 } else { 476 irq->status &= ~XICS_STATUS_ASSERTED; 477 } 478 ics_resend_lsi(ics, srcno); 479 } 480 481 void ics_set_irq(void *opaque, int srcno, int val) 482 { 483 ICSState *ics = (ICSState *)opaque; 484 485 if (kvm_irqchip_in_kernel()) { 486 ics_kvm_set_irq(ics, srcno, val); 487 return; 488 } 489 490 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { 491 ics_set_irq_lsi(ics, srcno, val); 492 } else { 493 ics_set_irq_msi(ics, srcno, val); 494 } 495 } 496 497 static void ics_write_xive_msi(ICSState *ics, int srcno) 498 { 499 ICSIRQState *irq = ics->irqs + srcno; 500 501 if (!(irq->status & XICS_STATUS_MASKED_PENDING) 502 || (irq->priority == 0xff)) { 503 return; 504 } 505 506 irq->status &= ~XICS_STATUS_MASKED_PENDING; 507 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); 508 } 509 510 static void ics_write_xive_lsi(ICSState *ics, int srcno) 511 { 512 ics_resend_lsi(ics, srcno); 513 } 514 515 void ics_write_xive(ICSState *ics, int srcno, int server, 516 uint8_t priority, uint8_t saved_priority) 517 { 518 ICSIRQState *irq = ics->irqs + srcno; 519 520 irq->server = server; 521 irq->priority = priority; 522 irq->saved_priority = saved_priority; 523 524 trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority); 525 526 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { 527 ics_write_xive_lsi(ics, srcno); 528 } else { 529 ics_write_xive_msi(ics, srcno); 530 } 531 } 532 533 static void ics_reject(ICSState *ics, uint32_t nr) 534 { 535 ICSIRQState *irq = ics->irqs + nr - ics->offset; 536 537 trace_xics_ics_reject(nr, nr - ics->offset); 538 if (irq->flags & XICS_FLAGS_IRQ_MSI) { 539 irq->status |= XICS_STATUS_REJECTED; 540 } else if (irq->flags & XICS_FLAGS_IRQ_LSI) { 541 irq->status &= ~XICS_STATUS_SENT; 542 } 543 } 544 545 void ics_resend(ICSState *ics) 546 { 547 int i; 548 549 for (i = 0; i < ics->nr_irqs; i++) { 550 /* FIXME: filter by server#? */ 551 if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) { 552 ics_resend_lsi(ics, i); 553 } else { 554 ics_resend_msi(ics, i); 555 } 556 } 557 } 558 559 static void ics_eoi(ICSState *ics, uint32_t nr) 560 { 561 int srcno = nr - ics->offset; 562 ICSIRQState *irq = ics->irqs + srcno; 563 564 trace_xics_ics_eoi(nr); 565 566 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { 567 irq->status &= ~XICS_STATUS_SENT; 568 } 569 } 570 571 static void ics_reset_irq(ICSIRQState *irq) 572 { 573 irq->priority = 0xff; 574 irq->saved_priority = 0xff; 575 } 576 577 static void ics_reset(DeviceState *dev) 578 { 579 ICSState *ics = ICS(dev); 580 int i; 581 uint8_t flags[ics->nr_irqs]; 582 583 for (i = 0; i < ics->nr_irqs; i++) { 584 flags[i] = ics->irqs[i].flags; 585 } 586 587 memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs); 588 589 for (i = 0; i < ics->nr_irqs; i++) { 590 ics_reset_irq(ics->irqs + i); 591 ics->irqs[i].flags = flags[i]; 592 } 593 594 if (kvm_irqchip_in_kernel()) { 595 Error *local_err = NULL; 596 597 ics_set_kvm_state(ICS(dev), &local_err); 598 if (local_err) { 599 error_report_err(local_err); 600 } 601 } 602 } 603 604 static void ics_reset_handler(void *dev) 605 { 606 ics_reset(dev); 607 } 608 609 static void ics_realize(DeviceState *dev, Error **errp) 610 { 611 ICSState *ics = ICS(dev); 612 Error *local_err = NULL; 613 Object *obj; 614 615 obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &local_err); 616 if (!obj) { 617 error_propagate_prepend(errp, local_err, 618 "required link '" ICS_PROP_XICS 619 "' not found: "); 620 return; 621 } 622 ics->xics = XICS_FABRIC(obj); 623 624 if (!ics->nr_irqs) { 625 error_setg(errp, "Number of interrupts needs to be greater 0"); 626 return; 627 } 628 ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); 629 630 qemu_register_reset(ics_reset_handler, ics); 631 } 632 633 static void ics_instance_init(Object *obj) 634 { 635 ICSState *ics = ICS(obj); 636 637 ics->offset = XICS_IRQ_BASE; 638 } 639 640 static int ics_pre_save(void *opaque) 641 { 642 ICSState *ics = opaque; 643 644 if (kvm_irqchip_in_kernel()) { 645 ics_get_kvm_state(ics); 646 } 647 648 return 0; 649 } 650 651 static int ics_post_load(void *opaque, int version_id) 652 { 653 ICSState *ics = opaque; 654 655 if (kvm_irqchip_in_kernel()) { 656 Error *local_err = NULL; 657 int ret; 658 659 ret = ics_set_kvm_state(ics, &local_err); 660 if (ret < 0) { 661 error_report_err(local_err); 662 return ret; 663 } 664 } 665 666 return 0; 667 } 668 669 static const VMStateDescription vmstate_ics_irq = { 670 .name = "ics/irq", 671 .version_id = 2, 672 .minimum_version_id = 1, 673 .fields = (VMStateField[]) { 674 VMSTATE_UINT32(server, ICSIRQState), 675 VMSTATE_UINT8(priority, ICSIRQState), 676 VMSTATE_UINT8(saved_priority, ICSIRQState), 677 VMSTATE_UINT8(status, ICSIRQState), 678 VMSTATE_UINT8(flags, ICSIRQState), 679 VMSTATE_END_OF_LIST() 680 }, 681 }; 682 683 static const VMStateDescription vmstate_ics = { 684 .name = "ics", 685 .version_id = 1, 686 .minimum_version_id = 1, 687 .pre_save = ics_pre_save, 688 .post_load = ics_post_load, 689 .fields = (VMStateField[]) { 690 /* Sanity check */ 691 VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL), 692 693 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs, 694 vmstate_ics_irq, 695 ICSIRQState), 696 VMSTATE_END_OF_LIST() 697 }, 698 }; 699 700 static Property ics_properties[] = { 701 DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0), 702 DEFINE_PROP_END_OF_LIST(), 703 }; 704 705 static void ics_class_init(ObjectClass *klass, void *data) 706 { 707 DeviceClass *dc = DEVICE_CLASS(klass); 708 709 dc->realize = ics_realize; 710 dc->props = ics_properties; 711 dc->reset = ics_reset; 712 dc->vmsd = &vmstate_ics; 713 /* 714 * Reason: part of XICS interrupt controller, needs to be wired up, 715 * e.g. by spapr_irq_init(). 716 */ 717 dc->user_creatable = false; 718 } 719 720 static const TypeInfo ics_info = { 721 .name = TYPE_ICS, 722 .parent = TYPE_DEVICE, 723 .instance_size = sizeof(ICSState), 724 .instance_init = ics_instance_init, 725 .class_init = ics_class_init, 726 .class_size = sizeof(ICSStateClass), 727 }; 728 729 static const TypeInfo xics_fabric_info = { 730 .name = TYPE_XICS_FABRIC, 731 .parent = TYPE_INTERFACE, 732 .class_size = sizeof(XICSFabricClass), 733 }; 734 735 /* 736 * Exported functions 737 */ 738 ICPState *xics_icp_get(XICSFabric *xi, int server) 739 { 740 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); 741 742 return xic->icp_get(xi, server); 743 } 744 745 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi) 746 { 747 assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK)); 748 749 ics->irqs[srcno].flags |= 750 lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI; 751 752 if (kvm_irqchip_in_kernel()) { 753 Error *local_err = NULL; 754 755 ics_reset_irq(ics->irqs + srcno); 756 ics_set_kvm_state_one(ics, srcno, &local_err); 757 if (local_err) { 758 error_report_err(local_err); 759 } 760 } 761 } 762 763 static void xics_register_types(void) 764 { 765 type_register_static(&ics_info); 766 type_register_static(&icp_info); 767 type_register_static(&xics_fabric_info); 768 } 769 770 type_init(xics_register_types) 771