xref: /openbmc/qemu/hw/intc/xics.c (revision c39f95dc)
1 /*
2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3  *
4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
5  *
6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a copy
9  * of this software and associated documentation files (the "Software"), to deal
10  * in the Software without restriction, including without limitation the rights
11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12  * copies of the Software, and to permit persons to whom the Software is
13  * furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be included in
16  * all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24  * THE SOFTWARE.
25  *
26  */
27 
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "qemu-common.h"
31 #include "cpu.h"
32 #include "hw/hw.h"
33 #include "trace.h"
34 #include "qemu/timer.h"
35 #include "hw/ppc/xics.h"
36 #include "qemu/error-report.h"
37 #include "qapi/visitor.h"
38 #include "monitor/monitor.h"
39 #include "hw/intc/intc.h"
40 
41 void icp_pic_print_info(ICPState *icp, Monitor *mon)
42 {
43     int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
44 
45     if (!icp->output) {
46         return;
47     }
48     monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
49                    cpu_index, icp->xirr, icp->xirr_owner,
50                    icp->pending_priority, icp->mfrr);
51 }
52 
53 void ics_pic_print_info(ICSState *ics, Monitor *mon)
54 {
55     uint32_t i;
56 
57     monitor_printf(mon, "ICS %4x..%4x %p\n",
58                    ics->offset, ics->offset + ics->nr_irqs - 1, ics);
59 
60     if (!ics->irqs) {
61         return;
62     }
63 
64     for (i = 0; i < ics->nr_irqs; i++) {
65         ICSIRQState *irq = ics->irqs + i;
66 
67         if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
68             continue;
69         }
70         monitor_printf(mon, "  %4x %s %02x %02x\n",
71                        ics->offset + i,
72                        (irq->flags & XICS_FLAGS_IRQ_LSI) ?
73                        "LSI" : "MSI",
74                        irq->priority, irq->status);
75     }
76 }
77 
78 /*
79  * ICP: Presentation layer
80  */
81 
82 #define XISR_MASK  0x00ffffff
83 #define CPPR_MASK  0xff000000
84 
85 #define XISR(icp)   (((icp)->xirr) & XISR_MASK)
86 #define CPPR(icp)   (((icp)->xirr) >> 24)
87 
88 static void ics_reject(ICSState *ics, uint32_t nr)
89 {
90     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
91 
92     if (k->reject) {
93         k->reject(ics, nr);
94     }
95 }
96 
97 void ics_resend(ICSState *ics)
98 {
99     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
100 
101     if (k->resend) {
102         k->resend(ics);
103     }
104 }
105 
106 static void ics_eoi(ICSState *ics, int nr)
107 {
108     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
109 
110     if (k->eoi) {
111         k->eoi(ics, nr);
112     }
113 }
114 
115 static void icp_check_ipi(ICPState *icp)
116 {
117     if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
118         return;
119     }
120 
121     trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
122 
123     if (XISR(icp) && icp->xirr_owner) {
124         ics_reject(icp->xirr_owner, XISR(icp));
125     }
126 
127     icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
128     icp->pending_priority = icp->mfrr;
129     icp->xirr_owner = NULL;
130     qemu_irq_raise(icp->output);
131 }
132 
133 void icp_resend(ICPState *icp)
134 {
135     XICSFabric *xi = icp->xics;
136     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
137 
138     if (icp->mfrr < CPPR(icp)) {
139         icp_check_ipi(icp);
140     }
141 
142     xic->ics_resend(xi);
143 }
144 
145 void icp_set_cppr(ICPState *icp, uint8_t cppr)
146 {
147     uint8_t old_cppr;
148     uint32_t old_xisr;
149 
150     old_cppr = CPPR(icp);
151     icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
152 
153     if (cppr < old_cppr) {
154         if (XISR(icp) && (cppr <= icp->pending_priority)) {
155             old_xisr = XISR(icp);
156             icp->xirr &= ~XISR_MASK; /* Clear XISR */
157             icp->pending_priority = 0xff;
158             qemu_irq_lower(icp->output);
159             if (icp->xirr_owner) {
160                 ics_reject(icp->xirr_owner, old_xisr);
161                 icp->xirr_owner = NULL;
162             }
163         }
164     } else {
165         if (!XISR(icp)) {
166             icp_resend(icp);
167         }
168     }
169 }
170 
171 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
172 {
173     icp->mfrr = mfrr;
174     if (mfrr < CPPR(icp)) {
175         icp_check_ipi(icp);
176     }
177 }
178 
179 uint32_t icp_accept(ICPState *icp)
180 {
181     uint32_t xirr = icp->xirr;
182 
183     qemu_irq_lower(icp->output);
184     icp->xirr = icp->pending_priority << 24;
185     icp->pending_priority = 0xff;
186     icp->xirr_owner = NULL;
187 
188     trace_xics_icp_accept(xirr, icp->xirr);
189 
190     return xirr;
191 }
192 
193 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
194 {
195     if (mfrr) {
196         *mfrr = icp->mfrr;
197     }
198     return icp->xirr;
199 }
200 
201 void icp_eoi(ICPState *icp, uint32_t xirr)
202 {
203     XICSFabric *xi = icp->xics;
204     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
205     ICSState *ics;
206     uint32_t irq;
207 
208     /* Send EOI -> ICS */
209     icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
210     trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
211     irq = xirr & XISR_MASK;
212 
213     ics = xic->ics_get(xi, irq);
214     if (ics) {
215         ics_eoi(ics, irq);
216     }
217     if (!XISR(icp)) {
218         icp_resend(icp);
219     }
220 }
221 
222 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
223 {
224     ICPState *icp = xics_icp_get(ics->xics, server);
225 
226     trace_xics_icp_irq(server, nr, priority);
227 
228     if ((priority >= CPPR(icp))
229         || (XISR(icp) && (icp->pending_priority <= priority))) {
230         ics_reject(ics, nr);
231     } else {
232         if (XISR(icp) && icp->xirr_owner) {
233             ics_reject(icp->xirr_owner, XISR(icp));
234             icp->xirr_owner = NULL;
235         }
236         icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
237         icp->xirr_owner = ics;
238         icp->pending_priority = priority;
239         trace_xics_icp_raise(icp->xirr, icp->pending_priority);
240         qemu_irq_raise(icp->output);
241     }
242 }
243 
244 static int icp_dispatch_pre_save(void *opaque)
245 {
246     ICPState *icp = opaque;
247     ICPStateClass *info = ICP_GET_CLASS(icp);
248 
249     if (info->pre_save) {
250         info->pre_save(icp);
251     }
252 
253     return 0;
254 }
255 
256 static int icp_dispatch_post_load(void *opaque, int version_id)
257 {
258     ICPState *icp = opaque;
259     ICPStateClass *info = ICP_GET_CLASS(icp);
260 
261     if (info->post_load) {
262         return info->post_load(icp, version_id);
263     }
264 
265     return 0;
266 }
267 
268 static const VMStateDescription vmstate_icp_server = {
269     .name = "icp/server",
270     .version_id = 1,
271     .minimum_version_id = 1,
272     .pre_save = icp_dispatch_pre_save,
273     .post_load = icp_dispatch_post_load,
274     .fields = (VMStateField[]) {
275         /* Sanity check */
276         VMSTATE_UINT32(xirr, ICPState),
277         VMSTATE_UINT8(pending_priority, ICPState),
278         VMSTATE_UINT8(mfrr, ICPState),
279         VMSTATE_END_OF_LIST()
280     },
281 };
282 
283 static void icp_reset(void *dev)
284 {
285     ICPState *icp = ICP(dev);
286     ICPStateClass *icpc = ICP_GET_CLASS(icp);
287 
288     icp->xirr = 0;
289     icp->pending_priority = 0xff;
290     icp->mfrr = 0xff;
291 
292     /* Make all outputs are deasserted */
293     qemu_set_irq(icp->output, 0);
294 
295     if (icpc->reset) {
296         icpc->reset(icp);
297     }
298 }
299 
300 static void icp_realize(DeviceState *dev, Error **errp)
301 {
302     ICPState *icp = ICP(dev);
303     ICPStateClass *icpc = ICP_GET_CLASS(dev);
304     PowerPCCPU *cpu;
305     CPUPPCState *env;
306     Object *obj;
307     Error *err = NULL;
308 
309     obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
310     if (!obj) {
311         error_propagate(errp, err);
312         error_prepend(errp, "required link '" ICP_PROP_XICS "' not found: ");
313         return;
314     }
315 
316     icp->xics = XICS_FABRIC(obj);
317 
318     obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
319     if (!obj) {
320         error_propagate(errp, err);
321         error_prepend(errp, "required link '" ICP_PROP_CPU "' not found: ");
322         return;
323     }
324 
325     cpu = POWERPC_CPU(obj);
326     cpu->intc = OBJECT(icp);
327     icp->cs = CPU(obj);
328 
329     env = &cpu->env;
330     switch (PPC_INPUT(env)) {
331     case PPC_FLAGS_INPUT_POWER7:
332         icp->output = env->irq_inputs[POWER7_INPUT_INT];
333         break;
334 
335     case PPC_FLAGS_INPUT_970:
336         icp->output = env->irq_inputs[PPC970_INPUT_INT];
337         break;
338 
339     default:
340         error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
341         return;
342     }
343 
344     if (icpc->realize) {
345         icpc->realize(icp, errp);
346     }
347 
348     qemu_register_reset(icp_reset, dev);
349     vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
350 }
351 
352 static void icp_unrealize(DeviceState *dev, Error **errp)
353 {
354     ICPState *icp = ICP(dev);
355 
356     vmstate_unregister(NULL, &vmstate_icp_server, icp);
357     qemu_unregister_reset(icp_reset, dev);
358 }
359 
360 static void icp_class_init(ObjectClass *klass, void *data)
361 {
362     DeviceClass *dc = DEVICE_CLASS(klass);
363 
364     dc->realize = icp_realize;
365     dc->unrealize = icp_unrealize;
366 }
367 
368 static const TypeInfo icp_info = {
369     .name = TYPE_ICP,
370     .parent = TYPE_DEVICE,
371     .instance_size = sizeof(ICPState),
372     .class_init = icp_class_init,
373     .class_size = sizeof(ICPStateClass),
374 };
375 
376 /*
377  * ICS: Source layer
378  */
379 static void ics_simple_resend_msi(ICSState *ics, int srcno)
380 {
381     ICSIRQState *irq = ics->irqs + srcno;
382 
383     /* FIXME: filter by server#? */
384     if (irq->status & XICS_STATUS_REJECTED) {
385         irq->status &= ~XICS_STATUS_REJECTED;
386         if (irq->priority != 0xff) {
387             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
388         }
389     }
390 }
391 
392 static void ics_simple_resend_lsi(ICSState *ics, int srcno)
393 {
394     ICSIRQState *irq = ics->irqs + srcno;
395 
396     if ((irq->priority != 0xff)
397         && (irq->status & XICS_STATUS_ASSERTED)
398         && !(irq->status & XICS_STATUS_SENT)) {
399         irq->status |= XICS_STATUS_SENT;
400         icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
401     }
402 }
403 
404 static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val)
405 {
406     ICSIRQState *irq = ics->irqs + srcno;
407 
408     trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset);
409 
410     if (val) {
411         if (irq->priority == 0xff) {
412             irq->status |= XICS_STATUS_MASKED_PENDING;
413             trace_xics_masked_pending();
414         } else  {
415             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
416         }
417     }
418 }
419 
420 static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val)
421 {
422     ICSIRQState *irq = ics->irqs + srcno;
423 
424     trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset);
425     if (val) {
426         irq->status |= XICS_STATUS_ASSERTED;
427     } else {
428         irq->status &= ~XICS_STATUS_ASSERTED;
429     }
430     ics_simple_resend_lsi(ics, srcno);
431 }
432 
433 static void ics_simple_set_irq(void *opaque, int srcno, int val)
434 {
435     ICSState *ics = (ICSState *)opaque;
436 
437     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
438         ics_simple_set_irq_lsi(ics, srcno, val);
439     } else {
440         ics_simple_set_irq_msi(ics, srcno, val);
441     }
442 }
443 
444 static void ics_simple_write_xive_msi(ICSState *ics, int srcno)
445 {
446     ICSIRQState *irq = ics->irqs + srcno;
447 
448     if (!(irq->status & XICS_STATUS_MASKED_PENDING)
449         || (irq->priority == 0xff)) {
450         return;
451     }
452 
453     irq->status &= ~XICS_STATUS_MASKED_PENDING;
454     icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
455 }
456 
457 static void ics_simple_write_xive_lsi(ICSState *ics, int srcno)
458 {
459     ics_simple_resend_lsi(ics, srcno);
460 }
461 
462 void ics_simple_write_xive(ICSState *ics, int srcno, int server,
463                            uint8_t priority, uint8_t saved_priority)
464 {
465     ICSIRQState *irq = ics->irqs + srcno;
466 
467     irq->server = server;
468     irq->priority = priority;
469     irq->saved_priority = saved_priority;
470 
471     trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server,
472                                      priority);
473 
474     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
475         ics_simple_write_xive_lsi(ics, srcno);
476     } else {
477         ics_simple_write_xive_msi(ics, srcno);
478     }
479 }
480 
481 static void ics_simple_reject(ICSState *ics, uint32_t nr)
482 {
483     ICSIRQState *irq = ics->irqs + nr - ics->offset;
484 
485     trace_xics_ics_simple_reject(nr, nr - ics->offset);
486     if (irq->flags & XICS_FLAGS_IRQ_MSI) {
487         irq->status |= XICS_STATUS_REJECTED;
488     } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
489         irq->status &= ~XICS_STATUS_SENT;
490     }
491 }
492 
493 static void ics_simple_resend(ICSState *ics)
494 {
495     int i;
496 
497     for (i = 0; i < ics->nr_irqs; i++) {
498         /* FIXME: filter by server#? */
499         if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
500             ics_simple_resend_lsi(ics, i);
501         } else {
502             ics_simple_resend_msi(ics, i);
503         }
504     }
505 }
506 
507 static void ics_simple_eoi(ICSState *ics, uint32_t nr)
508 {
509     int srcno = nr - ics->offset;
510     ICSIRQState *irq = ics->irqs + srcno;
511 
512     trace_xics_ics_simple_eoi(nr);
513 
514     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
515         irq->status &= ~XICS_STATUS_SENT;
516     }
517 }
518 
519 static void ics_simple_reset(void *dev)
520 {
521     ICSState *ics = ICS_SIMPLE(dev);
522     int i;
523     uint8_t flags[ics->nr_irqs];
524 
525     for (i = 0; i < ics->nr_irqs; i++) {
526         flags[i] = ics->irqs[i].flags;
527     }
528 
529     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
530 
531     for (i = 0; i < ics->nr_irqs; i++) {
532         ics->irqs[i].priority = 0xff;
533         ics->irqs[i].saved_priority = 0xff;
534         ics->irqs[i].flags = flags[i];
535     }
536 }
537 
538 static int ics_simple_dispatch_pre_save(void *opaque)
539 {
540     ICSState *ics = opaque;
541     ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
542 
543     if (info->pre_save) {
544         info->pre_save(ics);
545     }
546 
547     return 0;
548 }
549 
550 static int ics_simple_dispatch_post_load(void *opaque, int version_id)
551 {
552     ICSState *ics = opaque;
553     ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
554 
555     if (info->post_load) {
556         return info->post_load(ics, version_id);
557     }
558 
559     return 0;
560 }
561 
562 static const VMStateDescription vmstate_ics_simple_irq = {
563     .name = "ics/irq",
564     .version_id = 2,
565     .minimum_version_id = 1,
566     .fields = (VMStateField[]) {
567         VMSTATE_UINT32(server, ICSIRQState),
568         VMSTATE_UINT8(priority, ICSIRQState),
569         VMSTATE_UINT8(saved_priority, ICSIRQState),
570         VMSTATE_UINT8(status, ICSIRQState),
571         VMSTATE_UINT8(flags, ICSIRQState),
572         VMSTATE_END_OF_LIST()
573     },
574 };
575 
576 static const VMStateDescription vmstate_ics_simple = {
577     .name = "ics",
578     .version_id = 1,
579     .minimum_version_id = 1,
580     .pre_save = ics_simple_dispatch_pre_save,
581     .post_load = ics_simple_dispatch_post_load,
582     .fields = (VMStateField[]) {
583         /* Sanity check */
584         VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
585 
586         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
587                                              vmstate_ics_simple_irq,
588                                              ICSIRQState),
589         VMSTATE_END_OF_LIST()
590     },
591 };
592 
593 static void ics_simple_initfn(Object *obj)
594 {
595     ICSState *ics = ICS_SIMPLE(obj);
596 
597     ics->offset = XICS_IRQ_BASE;
598 }
599 
600 static void ics_simple_realize(ICSState *ics, Error **errp)
601 {
602     if (!ics->nr_irqs) {
603         error_setg(errp, "Number of interrupts needs to be greater 0");
604         return;
605     }
606     ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
607     ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
608 
609     qemu_register_reset(ics_simple_reset, ics);
610 }
611 
612 static Property ics_simple_properties[] = {
613     DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
614     DEFINE_PROP_END_OF_LIST(),
615 };
616 
617 static void ics_simple_class_init(ObjectClass *klass, void *data)
618 {
619     DeviceClass *dc = DEVICE_CLASS(klass);
620     ICSStateClass *isc = ICS_BASE_CLASS(klass);
621 
622     isc->realize = ics_simple_realize;
623     dc->props = ics_simple_properties;
624     dc->vmsd = &vmstate_ics_simple;
625     isc->reject = ics_simple_reject;
626     isc->resend = ics_simple_resend;
627     isc->eoi = ics_simple_eoi;
628 }
629 
630 static const TypeInfo ics_simple_info = {
631     .name = TYPE_ICS_SIMPLE,
632     .parent = TYPE_ICS_BASE,
633     .instance_size = sizeof(ICSState),
634     .class_init = ics_simple_class_init,
635     .class_size = sizeof(ICSStateClass),
636     .instance_init = ics_simple_initfn,
637 };
638 
639 static void ics_base_realize(DeviceState *dev, Error **errp)
640 {
641     ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev);
642     ICSState *ics = ICS_BASE(dev);
643     Object *obj;
644     Error *err = NULL;
645 
646     obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &err);
647     if (!obj) {
648         error_propagate(errp, err);
649         error_prepend(errp, "required link '" ICS_PROP_XICS "' not found: ");
650         return;
651     }
652     ics->xics = XICS_FABRIC(obj);
653 
654 
655     if (icsc->realize) {
656         icsc->realize(ics, errp);
657     }
658 }
659 
660 static void ics_base_class_init(ObjectClass *klass, void *data)
661 {
662     DeviceClass *dc = DEVICE_CLASS(klass);
663 
664     dc->realize = ics_base_realize;
665 }
666 
667 static const TypeInfo ics_base_info = {
668     .name = TYPE_ICS_BASE,
669     .parent = TYPE_DEVICE,
670     .abstract = true,
671     .instance_size = sizeof(ICSState),
672     .class_init = ics_base_class_init,
673     .class_size = sizeof(ICSStateClass),
674 };
675 
676 static const TypeInfo xics_fabric_info = {
677     .name = TYPE_XICS_FABRIC,
678     .parent = TYPE_INTERFACE,
679     .class_size = sizeof(XICSFabricClass),
680 };
681 
682 /*
683  * Exported functions
684  */
685 qemu_irq xics_get_qirq(XICSFabric *xi, int irq)
686 {
687     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
688     ICSState *ics = xic->ics_get(xi, irq);
689 
690     if (ics) {
691         return ics->qirqs[irq - ics->offset];
692     }
693 
694     return NULL;
695 }
696 
697 ICPState *xics_icp_get(XICSFabric *xi, int server)
698 {
699     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
700 
701     return xic->icp_get(xi, server);
702 }
703 
704 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
705 {
706     assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
707 
708     ics->irqs[srcno].flags |=
709         lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
710 }
711 
712 static void xics_register_types(void)
713 {
714     type_register_static(&ics_simple_info);
715     type_register_static(&ics_base_info);
716     type_register_static(&icp_info);
717     type_register_static(&xics_fabric_info);
718 }
719 
720 type_init(xics_register_types)
721