1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics 5 * 6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qapi/error.h" 30 #include "qemu-common.h" 31 #include "cpu.h" 32 #include "hw/hw.h" 33 #include "trace.h" 34 #include "qemu/timer.h" 35 #include "hw/ppc/xics.h" 36 #include "qemu/error-report.h" 37 #include "qapi/visitor.h" 38 #include "monitor/monitor.h" 39 #include "hw/intc/intc.h" 40 #include "sysemu/kvm.h" 41 42 void icp_pic_print_info(ICPState *icp, Monitor *mon) 43 { 44 int cpu_index = icp->cs ? icp->cs->cpu_index : -1; 45 46 if (!icp->output) { 47 return; 48 } 49 50 if (kvm_irqchip_in_kernel()) { 51 icp_synchronize_state(icp); 52 } 53 54 monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n", 55 cpu_index, icp->xirr, icp->xirr_owner, 56 icp->pending_priority, icp->mfrr); 57 } 58 59 void ics_pic_print_info(ICSState *ics, Monitor *mon) 60 { 61 uint32_t i; 62 63 monitor_printf(mon, "ICS %4x..%4x %p\n", 64 ics->offset, ics->offset + ics->nr_irqs - 1, ics); 65 66 if (!ics->irqs) { 67 return; 68 } 69 70 if (kvm_irqchip_in_kernel()) { 71 ics_synchronize_state(ics); 72 } 73 74 for (i = 0; i < ics->nr_irqs; i++) { 75 ICSIRQState *irq = ics->irqs + i; 76 77 if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) { 78 continue; 79 } 80 monitor_printf(mon, " %4x %s %02x %02x\n", 81 ics->offset + i, 82 (irq->flags & XICS_FLAGS_IRQ_LSI) ? 83 "LSI" : "MSI", 84 irq->priority, irq->status); 85 } 86 } 87 88 /* 89 * ICP: Presentation layer 90 */ 91 92 #define XISR_MASK 0x00ffffff 93 #define CPPR_MASK 0xff000000 94 95 #define XISR(icp) (((icp)->xirr) & XISR_MASK) 96 #define CPPR(icp) (((icp)->xirr) >> 24) 97 98 static void ics_reject(ICSState *ics, uint32_t nr) 99 { 100 ICSStateClass *k = ICS_BASE_GET_CLASS(ics); 101 102 if (k->reject) { 103 k->reject(ics, nr); 104 } 105 } 106 107 void ics_resend(ICSState *ics) 108 { 109 ICSStateClass *k = ICS_BASE_GET_CLASS(ics); 110 111 if (k->resend) { 112 k->resend(ics); 113 } 114 } 115 116 static void ics_eoi(ICSState *ics, int nr) 117 { 118 ICSStateClass *k = ICS_BASE_GET_CLASS(ics); 119 120 if (k->eoi) { 121 k->eoi(ics, nr); 122 } 123 } 124 125 static void icp_check_ipi(ICPState *icp) 126 { 127 if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) { 128 return; 129 } 130 131 trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr); 132 133 if (XISR(icp) && icp->xirr_owner) { 134 ics_reject(icp->xirr_owner, XISR(icp)); 135 } 136 137 icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI; 138 icp->pending_priority = icp->mfrr; 139 icp->xirr_owner = NULL; 140 qemu_irq_raise(icp->output); 141 } 142 143 void icp_resend(ICPState *icp) 144 { 145 XICSFabric *xi = icp->xics; 146 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); 147 148 if (icp->mfrr < CPPR(icp)) { 149 icp_check_ipi(icp); 150 } 151 152 xic->ics_resend(xi); 153 } 154 155 void icp_set_cppr(ICPState *icp, uint8_t cppr) 156 { 157 uint8_t old_cppr; 158 uint32_t old_xisr; 159 160 old_cppr = CPPR(icp); 161 icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24); 162 163 if (cppr < old_cppr) { 164 if (XISR(icp) && (cppr <= icp->pending_priority)) { 165 old_xisr = XISR(icp); 166 icp->xirr &= ~XISR_MASK; /* Clear XISR */ 167 icp->pending_priority = 0xff; 168 qemu_irq_lower(icp->output); 169 if (icp->xirr_owner) { 170 ics_reject(icp->xirr_owner, old_xisr); 171 icp->xirr_owner = NULL; 172 } 173 } 174 } else { 175 if (!XISR(icp)) { 176 icp_resend(icp); 177 } 178 } 179 } 180 181 void icp_set_mfrr(ICPState *icp, uint8_t mfrr) 182 { 183 icp->mfrr = mfrr; 184 if (mfrr < CPPR(icp)) { 185 icp_check_ipi(icp); 186 } 187 } 188 189 uint32_t icp_accept(ICPState *icp) 190 { 191 uint32_t xirr = icp->xirr; 192 193 qemu_irq_lower(icp->output); 194 icp->xirr = icp->pending_priority << 24; 195 icp->pending_priority = 0xff; 196 icp->xirr_owner = NULL; 197 198 trace_xics_icp_accept(xirr, icp->xirr); 199 200 return xirr; 201 } 202 203 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr) 204 { 205 if (mfrr) { 206 *mfrr = icp->mfrr; 207 } 208 return icp->xirr; 209 } 210 211 void icp_eoi(ICPState *icp, uint32_t xirr) 212 { 213 XICSFabric *xi = icp->xics; 214 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); 215 ICSState *ics; 216 uint32_t irq; 217 218 /* Send EOI -> ICS */ 219 icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK); 220 trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr); 221 irq = xirr & XISR_MASK; 222 223 ics = xic->ics_get(xi, irq); 224 if (ics) { 225 ics_eoi(ics, irq); 226 } 227 if (!XISR(icp)) { 228 icp_resend(icp); 229 } 230 } 231 232 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority) 233 { 234 ICPState *icp = xics_icp_get(ics->xics, server); 235 236 trace_xics_icp_irq(server, nr, priority); 237 238 if ((priority >= CPPR(icp)) 239 || (XISR(icp) && (icp->pending_priority <= priority))) { 240 ics_reject(ics, nr); 241 } else { 242 if (XISR(icp) && icp->xirr_owner) { 243 ics_reject(icp->xirr_owner, XISR(icp)); 244 icp->xirr_owner = NULL; 245 } 246 icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK); 247 icp->xirr_owner = ics; 248 icp->pending_priority = priority; 249 trace_xics_icp_raise(icp->xirr, icp->pending_priority); 250 qemu_irq_raise(icp->output); 251 } 252 } 253 254 static int icp_pre_save(void *opaque) 255 { 256 ICPState *icp = opaque; 257 258 if (kvm_irqchip_in_kernel()) { 259 icp_get_kvm_state(icp); 260 } 261 262 return 0; 263 } 264 265 static int icp_post_load(void *opaque, int version_id) 266 { 267 ICPState *icp = opaque; 268 269 if (kvm_irqchip_in_kernel()) { 270 return icp_set_kvm_state(icp); 271 } 272 273 return 0; 274 } 275 276 static const VMStateDescription vmstate_icp_server = { 277 .name = "icp/server", 278 .version_id = 1, 279 .minimum_version_id = 1, 280 .pre_save = icp_pre_save, 281 .post_load = icp_post_load, 282 .fields = (VMStateField[]) { 283 /* Sanity check */ 284 VMSTATE_UINT32(xirr, ICPState), 285 VMSTATE_UINT8(pending_priority, ICPState), 286 VMSTATE_UINT8(mfrr, ICPState), 287 VMSTATE_END_OF_LIST() 288 }, 289 }; 290 291 static void icp_reset_handler(void *dev) 292 { 293 ICPState *icp = ICP(dev); 294 295 icp->xirr = 0; 296 icp->pending_priority = 0xff; 297 icp->mfrr = 0xff; 298 299 /* Make all outputs are deasserted */ 300 qemu_set_irq(icp->output, 0); 301 302 if (kvm_irqchip_in_kernel()) { 303 icp_set_kvm_state(ICP(dev)); 304 } 305 } 306 307 static void icp_realize(DeviceState *dev, Error **errp) 308 { 309 ICPState *icp = ICP(dev); 310 PowerPCCPU *cpu; 311 CPUPPCState *env; 312 Object *obj; 313 Error *err = NULL; 314 315 obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err); 316 if (!obj) { 317 error_propagate_prepend(errp, err, 318 "required link '" ICP_PROP_XICS 319 "' not found: "); 320 return; 321 } 322 323 icp->xics = XICS_FABRIC(obj); 324 325 obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err); 326 if (!obj) { 327 error_propagate_prepend(errp, err, 328 "required link '" ICP_PROP_CPU 329 "' not found: "); 330 return; 331 } 332 333 cpu = POWERPC_CPU(obj); 334 icp->cs = CPU(obj); 335 336 env = &cpu->env; 337 switch (PPC_INPUT(env)) { 338 case PPC_FLAGS_INPUT_POWER7: 339 icp->output = env->irq_inputs[POWER7_INPUT_INT]; 340 break; 341 342 case PPC_FLAGS_INPUT_970: 343 icp->output = env->irq_inputs[PPC970_INPUT_INT]; 344 break; 345 346 default: 347 error_setg(errp, "XICS interrupt controller does not support this CPU bus model"); 348 return; 349 } 350 351 if (kvm_irqchip_in_kernel()) { 352 icp_kvm_realize(dev, &err); 353 if (err) { 354 error_propagate(errp, err); 355 return; 356 } 357 } 358 359 qemu_register_reset(icp_reset_handler, dev); 360 vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp); 361 } 362 363 static void icp_unrealize(DeviceState *dev, Error **errp) 364 { 365 ICPState *icp = ICP(dev); 366 367 vmstate_unregister(NULL, &vmstate_icp_server, icp); 368 qemu_unregister_reset(icp_reset_handler, dev); 369 } 370 371 static void icp_class_init(ObjectClass *klass, void *data) 372 { 373 DeviceClass *dc = DEVICE_CLASS(klass); 374 375 dc->realize = icp_realize; 376 dc->unrealize = icp_unrealize; 377 } 378 379 static const TypeInfo icp_info = { 380 .name = TYPE_ICP, 381 .parent = TYPE_DEVICE, 382 .instance_size = sizeof(ICPState), 383 .class_init = icp_class_init, 384 .class_size = sizeof(ICPStateClass), 385 }; 386 387 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp) 388 { 389 Error *local_err = NULL; 390 Object *obj; 391 392 obj = object_new(type); 393 object_property_add_child(cpu, type, obj, &error_abort); 394 object_unref(obj); 395 object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi), 396 &error_abort); 397 object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort); 398 object_property_set_bool(obj, true, "realized", &local_err); 399 if (local_err) { 400 object_unparent(obj); 401 error_propagate(errp, local_err); 402 obj = NULL; 403 } 404 405 return obj; 406 } 407 408 /* 409 * ICS: Source layer 410 */ 411 static void ics_simple_resend_msi(ICSState *ics, int srcno) 412 { 413 ICSIRQState *irq = ics->irqs + srcno; 414 415 /* FIXME: filter by server#? */ 416 if (irq->status & XICS_STATUS_REJECTED) { 417 irq->status &= ~XICS_STATUS_REJECTED; 418 if (irq->priority != 0xff) { 419 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); 420 } 421 } 422 } 423 424 static void ics_simple_resend_lsi(ICSState *ics, int srcno) 425 { 426 ICSIRQState *irq = ics->irqs + srcno; 427 428 if ((irq->priority != 0xff) 429 && (irq->status & XICS_STATUS_ASSERTED) 430 && !(irq->status & XICS_STATUS_SENT)) { 431 irq->status |= XICS_STATUS_SENT; 432 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); 433 } 434 } 435 436 static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val) 437 { 438 ICSIRQState *irq = ics->irqs + srcno; 439 440 trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset); 441 442 if (val) { 443 if (irq->priority == 0xff) { 444 irq->status |= XICS_STATUS_MASKED_PENDING; 445 trace_xics_masked_pending(); 446 } else { 447 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); 448 } 449 } 450 } 451 452 static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val) 453 { 454 ICSIRQState *irq = ics->irqs + srcno; 455 456 trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset); 457 if (val) { 458 irq->status |= XICS_STATUS_ASSERTED; 459 } else { 460 irq->status &= ~XICS_STATUS_ASSERTED; 461 } 462 ics_simple_resend_lsi(ics, srcno); 463 } 464 465 void ics_simple_set_irq(void *opaque, int srcno, int val) 466 { 467 ICSState *ics = (ICSState *)opaque; 468 469 if (kvm_irqchip_in_kernel()) { 470 ics_kvm_set_irq(ics, srcno, val); 471 return; 472 } 473 474 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { 475 ics_simple_set_irq_lsi(ics, srcno, val); 476 } else { 477 ics_simple_set_irq_msi(ics, srcno, val); 478 } 479 } 480 481 static void ics_simple_write_xive_msi(ICSState *ics, int srcno) 482 { 483 ICSIRQState *irq = ics->irqs + srcno; 484 485 if (!(irq->status & XICS_STATUS_MASKED_PENDING) 486 || (irq->priority == 0xff)) { 487 return; 488 } 489 490 irq->status &= ~XICS_STATUS_MASKED_PENDING; 491 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); 492 } 493 494 static void ics_simple_write_xive_lsi(ICSState *ics, int srcno) 495 { 496 ics_simple_resend_lsi(ics, srcno); 497 } 498 499 void ics_simple_write_xive(ICSState *ics, int srcno, int server, 500 uint8_t priority, uint8_t saved_priority) 501 { 502 ICSIRQState *irq = ics->irqs + srcno; 503 504 irq->server = server; 505 irq->priority = priority; 506 irq->saved_priority = saved_priority; 507 508 trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server, 509 priority); 510 511 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { 512 ics_simple_write_xive_lsi(ics, srcno); 513 } else { 514 ics_simple_write_xive_msi(ics, srcno); 515 } 516 } 517 518 static void ics_simple_reject(ICSState *ics, uint32_t nr) 519 { 520 ICSIRQState *irq = ics->irqs + nr - ics->offset; 521 522 trace_xics_ics_simple_reject(nr, nr - ics->offset); 523 if (irq->flags & XICS_FLAGS_IRQ_MSI) { 524 irq->status |= XICS_STATUS_REJECTED; 525 } else if (irq->flags & XICS_FLAGS_IRQ_LSI) { 526 irq->status &= ~XICS_STATUS_SENT; 527 } 528 } 529 530 static void ics_simple_resend(ICSState *ics) 531 { 532 int i; 533 534 for (i = 0; i < ics->nr_irqs; i++) { 535 /* FIXME: filter by server#? */ 536 if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) { 537 ics_simple_resend_lsi(ics, i); 538 } else { 539 ics_simple_resend_msi(ics, i); 540 } 541 } 542 } 543 544 static void ics_simple_eoi(ICSState *ics, uint32_t nr) 545 { 546 int srcno = nr - ics->offset; 547 ICSIRQState *irq = ics->irqs + srcno; 548 549 trace_xics_ics_simple_eoi(nr); 550 551 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { 552 irq->status &= ~XICS_STATUS_SENT; 553 } 554 } 555 556 static void ics_simple_reset(DeviceState *dev) 557 { 558 ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev); 559 560 icsc->parent_reset(dev); 561 562 if (kvm_irqchip_in_kernel()) { 563 ics_set_kvm_state(ICS_BASE(dev)); 564 } 565 } 566 567 static void ics_simple_reset_handler(void *dev) 568 { 569 ics_simple_reset(dev); 570 } 571 572 static void ics_simple_realize(DeviceState *dev, Error **errp) 573 { 574 ICSState *ics = ICS_SIMPLE(dev); 575 ICSStateClass *icsc = ICS_BASE_GET_CLASS(ics); 576 Error *local_err = NULL; 577 578 icsc->parent_realize(dev, &local_err); 579 if (local_err) { 580 error_propagate(errp, local_err); 581 return; 582 } 583 584 qemu_register_reset(ics_simple_reset_handler, ics); 585 } 586 587 static void ics_simple_class_init(ObjectClass *klass, void *data) 588 { 589 DeviceClass *dc = DEVICE_CLASS(klass); 590 ICSStateClass *isc = ICS_BASE_CLASS(klass); 591 592 device_class_set_parent_realize(dc, ics_simple_realize, 593 &isc->parent_realize); 594 device_class_set_parent_reset(dc, ics_simple_reset, 595 &isc->parent_reset); 596 597 isc->reject = ics_simple_reject; 598 isc->resend = ics_simple_resend; 599 isc->eoi = ics_simple_eoi; 600 } 601 602 static const TypeInfo ics_simple_info = { 603 .name = TYPE_ICS_SIMPLE, 604 .parent = TYPE_ICS_BASE, 605 .instance_size = sizeof(ICSState), 606 .class_init = ics_simple_class_init, 607 .class_size = sizeof(ICSStateClass), 608 }; 609 610 static void ics_base_reset(DeviceState *dev) 611 { 612 ICSState *ics = ICS_BASE(dev); 613 int i; 614 uint8_t flags[ics->nr_irqs]; 615 616 for (i = 0; i < ics->nr_irqs; i++) { 617 flags[i] = ics->irqs[i].flags; 618 } 619 620 memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs); 621 622 for (i = 0; i < ics->nr_irqs; i++) { 623 ics->irqs[i].priority = 0xff; 624 ics->irqs[i].saved_priority = 0xff; 625 ics->irqs[i].flags = flags[i]; 626 } 627 } 628 629 static void ics_base_realize(DeviceState *dev, Error **errp) 630 { 631 ICSState *ics = ICS_BASE(dev); 632 Object *obj; 633 Error *err = NULL; 634 635 obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &err); 636 if (!obj) { 637 error_propagate_prepend(errp, err, 638 "required link '" ICS_PROP_XICS 639 "' not found: "); 640 return; 641 } 642 ics->xics = XICS_FABRIC(obj); 643 644 if (!ics->nr_irqs) { 645 error_setg(errp, "Number of interrupts needs to be greater 0"); 646 return; 647 } 648 ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); 649 } 650 651 static void ics_base_instance_init(Object *obj) 652 { 653 ICSState *ics = ICS_BASE(obj); 654 655 ics->offset = XICS_IRQ_BASE; 656 } 657 658 static int ics_base_pre_save(void *opaque) 659 { 660 ICSState *ics = opaque; 661 662 if (kvm_irqchip_in_kernel()) { 663 ics_get_kvm_state(ics); 664 } 665 666 return 0; 667 } 668 669 static int ics_base_post_load(void *opaque, int version_id) 670 { 671 ICSState *ics = opaque; 672 673 if (kvm_irqchip_in_kernel()) { 674 return ics_set_kvm_state(ics); 675 } 676 677 return 0; 678 } 679 680 static const VMStateDescription vmstate_ics_base_irq = { 681 .name = "ics/irq", 682 .version_id = 2, 683 .minimum_version_id = 1, 684 .fields = (VMStateField[]) { 685 VMSTATE_UINT32(server, ICSIRQState), 686 VMSTATE_UINT8(priority, ICSIRQState), 687 VMSTATE_UINT8(saved_priority, ICSIRQState), 688 VMSTATE_UINT8(status, ICSIRQState), 689 VMSTATE_UINT8(flags, ICSIRQState), 690 VMSTATE_END_OF_LIST() 691 }, 692 }; 693 694 static const VMStateDescription vmstate_ics_base = { 695 .name = "ics", 696 .version_id = 1, 697 .minimum_version_id = 1, 698 .pre_save = ics_base_pre_save, 699 .post_load = ics_base_post_load, 700 .fields = (VMStateField[]) { 701 /* Sanity check */ 702 VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL), 703 704 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs, 705 vmstate_ics_base_irq, 706 ICSIRQState), 707 VMSTATE_END_OF_LIST() 708 }, 709 }; 710 711 static Property ics_base_properties[] = { 712 DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0), 713 DEFINE_PROP_END_OF_LIST(), 714 }; 715 716 static void ics_base_class_init(ObjectClass *klass, void *data) 717 { 718 DeviceClass *dc = DEVICE_CLASS(klass); 719 720 dc->realize = ics_base_realize; 721 dc->props = ics_base_properties; 722 dc->reset = ics_base_reset; 723 dc->vmsd = &vmstate_ics_base; 724 } 725 726 static const TypeInfo ics_base_info = { 727 .name = TYPE_ICS_BASE, 728 .parent = TYPE_DEVICE, 729 .abstract = true, 730 .instance_size = sizeof(ICSState), 731 .instance_init = ics_base_instance_init, 732 .class_init = ics_base_class_init, 733 .class_size = sizeof(ICSStateClass), 734 }; 735 736 static const TypeInfo xics_fabric_info = { 737 .name = TYPE_XICS_FABRIC, 738 .parent = TYPE_INTERFACE, 739 .class_size = sizeof(XICSFabricClass), 740 }; 741 742 /* 743 * Exported functions 744 */ 745 ICPState *xics_icp_get(XICSFabric *xi, int server) 746 { 747 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); 748 749 return xic->icp_get(xi, server); 750 } 751 752 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi) 753 { 754 assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK)); 755 756 ics->irqs[srcno].flags |= 757 lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI; 758 } 759 760 static void xics_register_types(void) 761 { 762 type_register_static(&ics_simple_info); 763 type_register_static(&ics_base_info); 764 type_register_static(&icp_info); 765 type_register_static(&xics_fabric_info); 766 } 767 768 type_init(xics_register_types) 769