1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "qemu/error-report.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "monitor/monitor.h" 17 #include "hw/ppc/fdt.h" 18 #include "hw/ppc/spapr.h" 19 #include "hw/ppc/spapr_cpu_core.h" 20 #include "hw/ppc/spapr_xive.h" 21 #include "hw/ppc/xive.h" 22 #include "hw/ppc/xive_regs.h" 23 24 /* 25 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 26 * use for the ESB pages and the TIMA pages 27 */ 28 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 29 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 30 31 /* 32 * The allocation of VP blocks is a complex operation in OPAL and the 33 * VP identifiers have a relation with the number of HW chips, the 34 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 35 * controller model does not have the same constraints and can use a 36 * simple mapping scheme of the CPU vcpu_id 37 * 38 * These identifiers are never returned to the OS. 39 */ 40 41 #define SPAPR_XIVE_NVT_BASE 0x400 42 43 /* 44 * The sPAPR machine has a unique XIVE IC device. Assign a fixed value 45 * to the controller block id value. It can nevertheless be changed 46 * for testing purpose. 47 */ 48 #define SPAPR_XIVE_BLOCK_ID 0x0 49 50 /* 51 * sPAPR NVT and END indexing helpers 52 */ 53 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 54 { 55 return nvt_idx - SPAPR_XIVE_NVT_BASE; 56 } 57 58 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 59 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 60 { 61 assert(cpu); 62 63 if (out_nvt_blk) { 64 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 65 } 66 67 if (out_nvt_blk) { 68 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 69 } 70 } 71 72 static int spapr_xive_target_to_nvt(uint32_t target, 73 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 74 { 75 PowerPCCPU *cpu = spapr_find_cpu(target); 76 77 if (!cpu) { 78 return -1; 79 } 80 81 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 82 return 0; 83 } 84 85 /* 86 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 87 * priorities per CPU 88 */ 89 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 90 uint8_t *out_end_blk, uint32_t *out_end_idx) 91 { 92 assert(cpu); 93 94 if (out_end_blk) { 95 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 96 } 97 98 if (out_end_idx) { 99 *out_end_idx = (cpu->vcpu_id << 3) + prio; 100 } 101 } 102 103 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 104 uint8_t *out_end_blk, uint32_t *out_end_idx) 105 { 106 PowerPCCPU *cpu = spapr_find_cpu(target); 107 108 if (!cpu) { 109 return -1; 110 } 111 112 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 113 return 0; 114 } 115 116 /* 117 * On sPAPR machines, use a simplified output for the XIVE END 118 * structure dumping only the information related to the OS EQ. 119 */ 120 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 121 Monitor *mon) 122 { 123 uint64_t qaddr_base = xive_end_qaddr(end); 124 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 125 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 126 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 127 uint32_t qentries = 1 << (qsize + 10); 128 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 129 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 130 131 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 132 spapr_xive_nvt_to_target(0, nvt), 133 priority, qindex, qentries, qaddr_base, qgen); 134 135 xive_end_queue_pic_print_info(end, 6, mon); 136 monitor_printf(mon, "]"); 137 } 138 139 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 140 { 141 XiveSource *xsrc = &xive->source; 142 int i; 143 144 monitor_printf(mon, " LSIN PQ EISN CPU/PRIO EQ\n"); 145 146 for (i = 0; i < xive->nr_irqs; i++) { 147 uint8_t pq = xive_source_esb_get(xsrc, i); 148 XiveEAS *eas = &xive->eat[i]; 149 150 if (!xive_eas_is_valid(eas)) { 151 continue; 152 } 153 154 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 155 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 156 pq & XIVE_ESB_VAL_P ? 'P' : '-', 157 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 158 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 159 xive_eas_is_masked(eas) ? "M" : " ", 160 (int) xive_get_field64(EAS_END_DATA, eas->w)); 161 162 if (!xive_eas_is_masked(eas)) { 163 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 164 XiveEND *end; 165 166 assert(end_idx < xive->nr_ends); 167 end = &xive->endt[end_idx]; 168 169 if (xive_end_is_valid(end)) { 170 spapr_xive_end_pic_print_info(xive, end, mon); 171 } 172 } 173 monitor_printf(mon, "\n"); 174 } 175 } 176 177 static void spapr_xive_map_mmio(SpaprXive *xive) 178 { 179 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 180 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 181 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 182 } 183 184 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 185 { 186 memory_region_set_enabled(&xive->source.esb_mmio, enable); 187 memory_region_set_enabled(&xive->tm_mmio, enable); 188 189 /* Disable the END ESBs until a guest OS makes use of them */ 190 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 191 } 192 193 /* 194 * When a Virtual Processor is scheduled to run on a HW thread, the 195 * hypervisor pushes its identifier in the OS CAM line. Emulate the 196 * same behavior under QEMU. 197 */ 198 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 199 { 200 uint8_t nvt_blk; 201 uint32_t nvt_idx; 202 uint32_t nvt_cam; 203 204 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 205 206 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 207 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 208 } 209 210 static void spapr_xive_end_reset(XiveEND *end) 211 { 212 memset(end, 0, sizeof(*end)); 213 214 /* switch off the escalation and notification ESBs */ 215 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 216 } 217 218 static void spapr_xive_reset(void *dev) 219 { 220 SpaprXive *xive = SPAPR_XIVE(dev); 221 int i; 222 223 /* 224 * The XiveSource has its own reset handler, which mask off all 225 * IRQs (!P|Q) 226 */ 227 228 /* Mask all valid EASs in the IRQ number space. */ 229 for (i = 0; i < xive->nr_irqs; i++) { 230 XiveEAS *eas = &xive->eat[i]; 231 if (xive_eas_is_valid(eas)) { 232 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 233 } else { 234 eas->w = 0; 235 } 236 } 237 238 /* Clear all ENDs */ 239 for (i = 0; i < xive->nr_ends; i++) { 240 spapr_xive_end_reset(&xive->endt[i]); 241 } 242 } 243 244 static void spapr_xive_instance_init(Object *obj) 245 { 246 SpaprXive *xive = SPAPR_XIVE(obj); 247 248 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 249 TYPE_XIVE_SOURCE, &error_abort, NULL); 250 251 object_initialize_child(obj, "end_source", &xive->end_source, 252 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 253 &error_abort, NULL); 254 } 255 256 static void spapr_xive_realize(DeviceState *dev, Error **errp) 257 { 258 SpaprXive *xive = SPAPR_XIVE(dev); 259 XiveSource *xsrc = &xive->source; 260 XiveENDSource *end_xsrc = &xive->end_source; 261 Error *local_err = NULL; 262 263 if (!xive->nr_irqs) { 264 error_setg(errp, "Number of interrupt needs to be greater 0"); 265 return; 266 } 267 268 if (!xive->nr_ends) { 269 error_setg(errp, "Number of interrupt needs to be greater 0"); 270 return; 271 } 272 273 /* 274 * Initialize the internal sources, for IPIs and virtual devices. 275 */ 276 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 277 &error_fatal); 278 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 279 &error_fatal); 280 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 281 if (local_err) { 282 error_propagate(errp, local_err); 283 return; 284 } 285 286 /* 287 * Initialize the END ESB source 288 */ 289 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 290 &error_fatal); 291 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 292 &error_fatal); 293 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 294 if (local_err) { 295 error_propagate(errp, local_err); 296 return; 297 } 298 299 /* Set the mapping address of the END ESB pages after the source ESBs */ 300 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 301 302 /* 303 * Allocate the routing tables 304 */ 305 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 306 xive->endt = g_new0(XiveEND, xive->nr_ends); 307 308 /* TIMA initialization */ 309 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 310 "xive.tima", 4ull << TM_SHIFT); 311 312 /* Define all XIVE MMIO regions on SysBus */ 313 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 314 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 315 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 316 317 /* Map all regions */ 318 spapr_xive_map_mmio(xive); 319 320 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 321 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 322 323 qemu_register_reset(spapr_xive_reset, dev); 324 } 325 326 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 327 uint32_t eas_idx, XiveEAS *eas) 328 { 329 SpaprXive *xive = SPAPR_XIVE(xrtr); 330 331 if (eas_idx >= xive->nr_irqs) { 332 return -1; 333 } 334 335 *eas = xive->eat[eas_idx]; 336 return 0; 337 } 338 339 static int spapr_xive_get_end(XiveRouter *xrtr, 340 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 341 { 342 SpaprXive *xive = SPAPR_XIVE(xrtr); 343 344 if (end_idx >= xive->nr_ends) { 345 return -1; 346 } 347 348 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 349 return 0; 350 } 351 352 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 353 uint32_t end_idx, XiveEND *end, 354 uint8_t word_number) 355 { 356 SpaprXive *xive = SPAPR_XIVE(xrtr); 357 358 if (end_idx >= xive->nr_ends) { 359 return -1; 360 } 361 362 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 363 return 0; 364 } 365 366 static int spapr_xive_get_nvt(XiveRouter *xrtr, 367 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 368 { 369 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 370 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 371 372 if (!cpu) { 373 /* TODO: should we assert() if we can find a NVT ? */ 374 return -1; 375 } 376 377 /* 378 * sPAPR does not maintain a NVT table. Return that the NVT is 379 * valid if we have found a matching CPU 380 */ 381 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 382 return 0; 383 } 384 385 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 386 uint32_t nvt_idx, XiveNVT *nvt, 387 uint8_t word_number) 388 { 389 /* 390 * We don't need to write back to the NVTs because the sPAPR 391 * machine should never hit a non-scheduled NVT. It should never 392 * get called. 393 */ 394 g_assert_not_reached(); 395 } 396 397 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 398 { 399 PowerPCCPU *cpu = POWERPC_CPU(cs); 400 401 return spapr_cpu_state(cpu)->tctx; 402 } 403 404 static const VMStateDescription vmstate_spapr_xive_end = { 405 .name = TYPE_SPAPR_XIVE "/end", 406 .version_id = 1, 407 .minimum_version_id = 1, 408 .fields = (VMStateField []) { 409 VMSTATE_UINT32(w0, XiveEND), 410 VMSTATE_UINT32(w1, XiveEND), 411 VMSTATE_UINT32(w2, XiveEND), 412 VMSTATE_UINT32(w3, XiveEND), 413 VMSTATE_UINT32(w4, XiveEND), 414 VMSTATE_UINT32(w5, XiveEND), 415 VMSTATE_UINT32(w6, XiveEND), 416 VMSTATE_UINT32(w7, XiveEND), 417 VMSTATE_END_OF_LIST() 418 }, 419 }; 420 421 static const VMStateDescription vmstate_spapr_xive_eas = { 422 .name = TYPE_SPAPR_XIVE "/eas", 423 .version_id = 1, 424 .minimum_version_id = 1, 425 .fields = (VMStateField []) { 426 VMSTATE_UINT64(w, XiveEAS), 427 VMSTATE_END_OF_LIST() 428 }, 429 }; 430 431 static const VMStateDescription vmstate_spapr_xive = { 432 .name = TYPE_SPAPR_XIVE, 433 .version_id = 1, 434 .minimum_version_id = 1, 435 .fields = (VMStateField[]) { 436 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 437 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 438 vmstate_spapr_xive_eas, XiveEAS), 439 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 440 vmstate_spapr_xive_end, XiveEND), 441 VMSTATE_END_OF_LIST() 442 }, 443 }; 444 445 static Property spapr_xive_properties[] = { 446 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 447 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 448 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 449 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 450 DEFINE_PROP_END_OF_LIST(), 451 }; 452 453 static void spapr_xive_class_init(ObjectClass *klass, void *data) 454 { 455 DeviceClass *dc = DEVICE_CLASS(klass); 456 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 457 458 dc->desc = "sPAPR XIVE Interrupt Controller"; 459 dc->props = spapr_xive_properties; 460 dc->realize = spapr_xive_realize; 461 dc->vmsd = &vmstate_spapr_xive; 462 463 xrc->get_eas = spapr_xive_get_eas; 464 xrc->get_end = spapr_xive_get_end; 465 xrc->write_end = spapr_xive_write_end; 466 xrc->get_nvt = spapr_xive_get_nvt; 467 xrc->write_nvt = spapr_xive_write_nvt; 468 xrc->get_tctx = spapr_xive_get_tctx; 469 } 470 471 static const TypeInfo spapr_xive_info = { 472 .name = TYPE_SPAPR_XIVE, 473 .parent = TYPE_XIVE_ROUTER, 474 .instance_init = spapr_xive_instance_init, 475 .instance_size = sizeof(SpaprXive), 476 .class_init = spapr_xive_class_init, 477 }; 478 479 static void spapr_xive_register_types(void) 480 { 481 type_register_static(&spapr_xive_info); 482 } 483 484 type_init(spapr_xive_register_types) 485 486 bool spapr_xive_irq_claim(SpaprXive *xive, uint32_t lisn, bool lsi) 487 { 488 XiveSource *xsrc = &xive->source; 489 490 if (lisn >= xive->nr_irqs) { 491 return false; 492 } 493 494 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID); 495 if (lsi) { 496 xive_source_irq_set_lsi(xsrc, lisn); 497 } 498 return true; 499 } 500 501 bool spapr_xive_irq_free(SpaprXive *xive, uint32_t lisn) 502 { 503 if (lisn >= xive->nr_irqs) { 504 return false; 505 } 506 507 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 508 return true; 509 } 510 511 /* 512 * XIVE hcalls 513 * 514 * The terminology used by the XIVE hcalls is the following : 515 * 516 * TARGET vCPU number 517 * EQ Event Queue assigned by OS to receive event data 518 * ESB page for source interrupt management 519 * LISN Logical Interrupt Source Number identifying a source in the 520 * machine 521 * EISN Effective Interrupt Source Number used by guest OS to 522 * identify source in the guest 523 * 524 * The EAS, END, NVT structures are not exposed. 525 */ 526 527 /* 528 * Linux hosts under OPAL reserve priority 7 for their own escalation 529 * interrupts (DD2.X POWER9). So we only allow the guest to use 530 * priorities [0..6]. 531 */ 532 static bool spapr_xive_priority_is_reserved(uint8_t priority) 533 { 534 switch (priority) { 535 case 0 ... 6: 536 return false; 537 case 7: /* OPAL escalation queue */ 538 default: 539 return true; 540 } 541 } 542 543 /* 544 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 545 * real address of the MMIO page through which the Event State Buffer 546 * entry associated with the value of the "lisn" parameter is managed. 547 * 548 * Parameters: 549 * Input 550 * - R4: "flags" 551 * Bits 0-63 reserved 552 * - R5: "lisn" is per "interrupts", "interrupt-map", or 553 * "ibm,xive-lisn-ranges" properties, or as returned by the 554 * ibm,query-interrupt-source-number RTAS call, or as returned 555 * by the H_ALLOCATE_VAS_WINDOW hcall 556 * 557 * Output 558 * - R4: "flags" 559 * Bits 0-59: Reserved 560 * Bit 60: H_INT_ESB must be used for Event State Buffer 561 * management 562 * Bit 61: 1 == LSI 0 == MSI 563 * Bit 62: the full function page supports trigger 564 * Bit 63: Store EOI Supported 565 * - R5: Logical Real address of full function Event State Buffer 566 * management page, -1 if H_INT_ESB hcall flag is set to 1. 567 * - R6: Logical Real Address of trigger only Event State Buffer 568 * management page or -1. 569 * - R7: Power of 2 page size for the ESB management pages returned in 570 * R5 and R6. 571 */ 572 573 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 574 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 575 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 576 on same page */ 577 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 578 579 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 580 SpaprMachineState *spapr, 581 target_ulong opcode, 582 target_ulong *args) 583 { 584 SpaprXive *xive = spapr->xive; 585 XiveSource *xsrc = &xive->source; 586 target_ulong flags = args[0]; 587 target_ulong lisn = args[1]; 588 589 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 590 return H_FUNCTION; 591 } 592 593 if (flags) { 594 return H_PARAMETER; 595 } 596 597 if (lisn >= xive->nr_irqs) { 598 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 599 lisn); 600 return H_P2; 601 } 602 603 if (!xive_eas_is_valid(&xive->eat[lisn])) { 604 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 605 lisn); 606 return H_P2; 607 } 608 609 /* 610 * All sources are emulated under the main XIVE object and share 611 * the same characteristics. 612 */ 613 args[0] = 0; 614 if (!xive_source_esb_has_2page(xsrc)) { 615 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 616 } 617 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 618 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 619 } 620 621 /* 622 * Force the use of the H_INT_ESB hcall in case of an LSI 623 * interrupt. This is necessary under KVM to re-trigger the 624 * interrupt if the level is still asserted 625 */ 626 if (xive_source_irq_is_lsi(xsrc, lisn)) { 627 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 628 } 629 630 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 631 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 632 } else { 633 args[1] = -1; 634 } 635 636 if (xive_source_esb_has_2page(xsrc) && 637 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 638 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 639 } else { 640 args[2] = -1; 641 } 642 643 if (xive_source_esb_has_2page(xsrc)) { 644 args[3] = xsrc->esb_shift - 1; 645 } else { 646 args[3] = xsrc->esb_shift; 647 } 648 649 return H_SUCCESS; 650 } 651 652 /* 653 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 654 * Interrupt Source to a target. The Logical Interrupt Source is 655 * designated with the "lisn" parameter and the target is designated 656 * with the "target" and "priority" parameters. Upon return from the 657 * hcall(), no additional interrupts will be directed to the old EQ. 658 * 659 * Parameters: 660 * Input: 661 * - R4: "flags" 662 * Bits 0-61: Reserved 663 * Bit 62: set the "eisn" in the EAS 664 * Bit 63: masks the interrupt source in the hardware interrupt 665 * control structure. An interrupt masked by this mechanism will 666 * be dropped, but it's source state bits will still be 667 * set. There is no race-free way of unmasking and restoring the 668 * source. Thus this should only be used in interrupts that are 669 * also masked at the source, and only in cases where the 670 * interrupt is not meant to be used for a large amount of time 671 * because no valid target exists for it for example 672 * - R5: "lisn" is per "interrupts", "interrupt-map", or 673 * "ibm,xive-lisn-ranges" properties, or as returned by the 674 * ibm,query-interrupt-source-number RTAS call, or as returned by 675 * the H_ALLOCATE_VAS_WINDOW hcall 676 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 677 * "ibm,ppc-interrupt-gserver#s" 678 * - R7: "priority" is a valid priority not in 679 * "ibm,plat-res-int-priorities" 680 * - R8: "eisn" is the guest EISN associated with the "lisn" 681 * 682 * Output: 683 * - None 684 */ 685 686 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 687 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 688 689 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 690 SpaprMachineState *spapr, 691 target_ulong opcode, 692 target_ulong *args) 693 { 694 SpaprXive *xive = spapr->xive; 695 XiveEAS eas, new_eas; 696 target_ulong flags = args[0]; 697 target_ulong lisn = args[1]; 698 target_ulong target = args[2]; 699 target_ulong priority = args[3]; 700 target_ulong eisn = args[4]; 701 uint8_t end_blk; 702 uint32_t end_idx; 703 704 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 705 return H_FUNCTION; 706 } 707 708 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 709 return H_PARAMETER; 710 } 711 712 if (lisn >= xive->nr_irqs) { 713 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 714 lisn); 715 return H_P2; 716 } 717 718 eas = xive->eat[lisn]; 719 if (!xive_eas_is_valid(&eas)) { 720 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 721 lisn); 722 return H_P2; 723 } 724 725 /* priority 0xff is used to reset the EAS */ 726 if (priority == 0xff) { 727 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 728 goto out; 729 } 730 731 if (flags & SPAPR_XIVE_SRC_MASK) { 732 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 733 } else { 734 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 735 } 736 737 if (spapr_xive_priority_is_reserved(priority)) { 738 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 739 " is reserved\n", priority); 740 return H_P4; 741 } 742 743 /* 744 * Validate that "target" is part of the list of threads allocated 745 * to the partition. For that, find the END corresponding to the 746 * target. 747 */ 748 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 749 return H_P3; 750 } 751 752 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 753 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 754 755 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 756 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 757 } 758 759 out: 760 xive->eat[lisn] = new_eas; 761 return H_SUCCESS; 762 } 763 764 /* 765 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 766 * target/priority pair is assigned to the specified Logical Interrupt 767 * Source. 768 * 769 * Parameters: 770 * Input: 771 * - R4: "flags" 772 * Bits 0-63 Reserved 773 * - R5: "lisn" is per "interrupts", "interrupt-map", or 774 * "ibm,xive-lisn-ranges" properties, or as returned by the 775 * ibm,query-interrupt-source-number RTAS call, or as 776 * returned by the H_ALLOCATE_VAS_WINDOW hcall 777 * 778 * Output: 779 * - R4: Target to which the specified Logical Interrupt Source is 780 * assigned 781 * - R5: Priority to which the specified Logical Interrupt Source is 782 * assigned 783 * - R6: EISN for the specified Logical Interrupt Source (this will be 784 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 785 */ 786 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 787 SpaprMachineState *spapr, 788 target_ulong opcode, 789 target_ulong *args) 790 { 791 SpaprXive *xive = spapr->xive; 792 target_ulong flags = args[0]; 793 target_ulong lisn = args[1]; 794 XiveEAS eas; 795 XiveEND *end; 796 uint8_t nvt_blk; 797 uint32_t end_idx, nvt_idx; 798 799 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 800 return H_FUNCTION; 801 } 802 803 if (flags) { 804 return H_PARAMETER; 805 } 806 807 if (lisn >= xive->nr_irqs) { 808 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 809 lisn); 810 return H_P2; 811 } 812 813 eas = xive->eat[lisn]; 814 if (!xive_eas_is_valid(&eas)) { 815 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 816 lisn); 817 return H_P2; 818 } 819 820 /* EAS_END_BLOCK is unused on sPAPR */ 821 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 822 823 assert(end_idx < xive->nr_ends); 824 end = &xive->endt[end_idx]; 825 826 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 827 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 828 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 829 830 if (xive_eas_is_masked(&eas)) { 831 args[1] = 0xff; 832 } else { 833 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 834 } 835 836 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 837 838 return H_SUCCESS; 839 } 840 841 /* 842 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 843 * address of the notification management page associated with the 844 * specified target and priority. 845 * 846 * Parameters: 847 * Input: 848 * - R4: "flags" 849 * Bits 0-63 Reserved 850 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 851 * "ibm,ppc-interrupt-gserver#s" 852 * - R6: "priority" is a valid priority not in 853 * "ibm,plat-res-int-priorities" 854 * 855 * Output: 856 * - R4: Logical real address of notification page 857 * - R5: Power of 2 page size of the notification page 858 */ 859 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 860 SpaprMachineState *spapr, 861 target_ulong opcode, 862 target_ulong *args) 863 { 864 SpaprXive *xive = spapr->xive; 865 XiveENDSource *end_xsrc = &xive->end_source; 866 target_ulong flags = args[0]; 867 target_ulong target = args[1]; 868 target_ulong priority = args[2]; 869 XiveEND *end; 870 uint8_t end_blk; 871 uint32_t end_idx; 872 873 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 874 return H_FUNCTION; 875 } 876 877 if (flags) { 878 return H_PARAMETER; 879 } 880 881 /* 882 * H_STATE should be returned if a H_INT_RESET is in progress. 883 * This is not needed when running the emulation under QEMU 884 */ 885 886 if (spapr_xive_priority_is_reserved(priority)) { 887 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 888 " is reserved\n", priority); 889 return H_P3; 890 } 891 892 /* 893 * Validate that "target" is part of the list of threads allocated 894 * to the partition. For that, find the END corresponding to the 895 * target. 896 */ 897 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 898 return H_P2; 899 } 900 901 assert(end_idx < xive->nr_ends); 902 end = &xive->endt[end_idx]; 903 904 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 905 if (xive_end_is_enqueue(end)) { 906 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 907 } else { 908 args[1] = 0; 909 } 910 911 return H_SUCCESS; 912 } 913 914 /* 915 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 916 * a given "target" and "priority". It is also used to set the 917 * notification config associated with the EQ. An EQ size of 0 is 918 * used to reset the EQ config for a given target and priority. If 919 * resetting the EQ config, the END associated with the given "target" 920 * and "priority" will be changed to disable queueing. 921 * 922 * Upon return from the hcall(), no additional interrupts will be 923 * directed to the old EQ (if one was set). The old EQ (if one was 924 * set) should be investigated for interrupts that occurred prior to 925 * or during the hcall(). 926 * 927 * Parameters: 928 * Input: 929 * - R4: "flags" 930 * Bits 0-62: Reserved 931 * Bit 63: Unconditional Notify (n) per the XIVE spec 932 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 933 * "ibm,ppc-interrupt-gserver#s" 934 * - R6: "priority" is a valid priority not in 935 * "ibm,plat-res-int-priorities" 936 * - R7: "eventQueue": The logical real address of the start of the EQ 937 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 938 * 939 * Output: 940 * - None 941 */ 942 943 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 944 945 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 946 SpaprMachineState *spapr, 947 target_ulong opcode, 948 target_ulong *args) 949 { 950 SpaprXive *xive = spapr->xive; 951 target_ulong flags = args[0]; 952 target_ulong target = args[1]; 953 target_ulong priority = args[2]; 954 target_ulong qpage = args[3]; 955 target_ulong qsize = args[4]; 956 XiveEND end; 957 uint8_t end_blk, nvt_blk; 958 uint32_t end_idx, nvt_idx; 959 960 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 961 return H_FUNCTION; 962 } 963 964 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 965 return H_PARAMETER; 966 } 967 968 /* 969 * H_STATE should be returned if a H_INT_RESET is in progress. 970 * This is not needed when running the emulation under QEMU 971 */ 972 973 if (spapr_xive_priority_is_reserved(priority)) { 974 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 975 " is reserved\n", priority); 976 return H_P3; 977 } 978 979 /* 980 * Validate that "target" is part of the list of threads allocated 981 * to the partition. For that, find the END corresponding to the 982 * target. 983 */ 984 985 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 986 return H_P2; 987 } 988 989 assert(end_idx < xive->nr_ends); 990 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 991 992 switch (qsize) { 993 case 12: 994 case 16: 995 case 21: 996 case 24: 997 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 998 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 999 " is not naturally aligned with %" HWADDR_PRIx "\n", 1000 qpage, (hwaddr)1 << qsize); 1001 return H_P4; 1002 } 1003 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1004 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1005 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1006 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1007 break; 1008 case 0: 1009 /* reset queue and disable queueing */ 1010 spapr_xive_end_reset(&end); 1011 goto out; 1012 1013 default: 1014 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1015 qsize); 1016 return H_P5; 1017 } 1018 1019 if (qsize) { 1020 hwaddr plen = 1 << qsize; 1021 void *eq; 1022 1023 /* 1024 * Validate the guest EQ. We should also check that the queue 1025 * has been zeroed by the OS. 1026 */ 1027 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1028 MEMTXATTRS_UNSPECIFIED); 1029 if (plen != 1 << qsize) { 1030 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1031 HWADDR_PRIx "\n", qpage); 1032 return H_P4; 1033 } 1034 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1035 } 1036 1037 /* "target" should have been validated above */ 1038 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1039 g_assert_not_reached(); 1040 } 1041 1042 /* 1043 * Ensure the priority and target are correctly set (they will not 1044 * be right after allocation) 1045 */ 1046 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1047 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1048 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1049 1050 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1051 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1052 } else { 1053 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1054 } 1055 1056 /* 1057 * The generation bit for the END starts at 1 and The END page 1058 * offset counter starts at 0. 1059 */ 1060 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1061 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1062 end.w0 |= cpu_to_be32(END_W0_VALID); 1063 1064 /* 1065 * TODO: issue syncs required to ensure all in-flight interrupts 1066 * are complete on the old END 1067 */ 1068 1069 out: 1070 /* Update END */ 1071 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1072 return H_SUCCESS; 1073 } 1074 1075 /* 1076 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1077 * target and priority. 1078 * 1079 * Parameters: 1080 * Input: 1081 * - R4: "flags" 1082 * Bits 0-62: Reserved 1083 * Bit 63: Debug: Return debug data 1084 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1085 * "ibm,ppc-interrupt-gserver#s" 1086 * - R6: "priority" is a valid priority not in 1087 * "ibm,plat-res-int-priorities" 1088 * 1089 * Output: 1090 * - R4: "flags": 1091 * Bits 0-61: Reserved 1092 * Bit 62: The value of Event Queue Generation Number (g) per 1093 * the XIVE spec if "Debug" = 1 1094 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1095 * - R5: The logical real address of the start of the EQ 1096 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1097 * - R7: The value of Event Queue Offset Counter per XIVE spec 1098 * if "Debug" = 1, else 0 1099 * 1100 */ 1101 1102 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1103 1104 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1105 SpaprMachineState *spapr, 1106 target_ulong opcode, 1107 target_ulong *args) 1108 { 1109 SpaprXive *xive = spapr->xive; 1110 target_ulong flags = args[0]; 1111 target_ulong target = args[1]; 1112 target_ulong priority = args[2]; 1113 XiveEND *end; 1114 uint8_t end_blk; 1115 uint32_t end_idx; 1116 1117 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1118 return H_FUNCTION; 1119 } 1120 1121 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1122 return H_PARAMETER; 1123 } 1124 1125 /* 1126 * H_STATE should be returned if a H_INT_RESET is in progress. 1127 * This is not needed when running the emulation under QEMU 1128 */ 1129 1130 if (spapr_xive_priority_is_reserved(priority)) { 1131 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1132 " is reserved\n", priority); 1133 return H_P3; 1134 } 1135 1136 /* 1137 * Validate that "target" is part of the list of threads allocated 1138 * to the partition. For that, find the END corresponding to the 1139 * target. 1140 */ 1141 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1142 return H_P2; 1143 } 1144 1145 assert(end_idx < xive->nr_ends); 1146 end = &xive->endt[end_idx]; 1147 1148 args[0] = 0; 1149 if (xive_end_is_notify(end)) { 1150 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1151 } 1152 1153 if (xive_end_is_enqueue(end)) { 1154 args[1] = xive_end_qaddr(end); 1155 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1156 } else { 1157 args[1] = 0; 1158 args[2] = 0; 1159 } 1160 1161 /* TODO: do we need any locking on the END ? */ 1162 if (flags & SPAPR_XIVE_END_DEBUG) { 1163 /* Load the event queue generation number into the return flags */ 1164 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1165 1166 /* Load R7 with the event queue offset counter */ 1167 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1168 } else { 1169 args[3] = 0; 1170 } 1171 1172 return H_SUCCESS; 1173 } 1174 1175 /* 1176 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1177 * reporting cache line pair for the calling thread. The reporting 1178 * cache lines will contain the OS interrupt context when the OS 1179 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1180 * interrupt. The reporting cache lines can be reset by inputting -1 1181 * in "reportingLine". Issuing the CI store byte without reporting 1182 * cache lines registered will result in the data not being accessible 1183 * to the OS. 1184 * 1185 * Parameters: 1186 * Input: 1187 * - R4: "flags" 1188 * Bits 0-63: Reserved 1189 * - R5: "reportingLine": The logical real address of the reporting cache 1190 * line pair 1191 * 1192 * Output: 1193 * - None 1194 */ 1195 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1196 SpaprMachineState *spapr, 1197 target_ulong opcode, 1198 target_ulong *args) 1199 { 1200 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1201 return H_FUNCTION; 1202 } 1203 1204 /* 1205 * H_STATE should be returned if a H_INT_RESET is in progress. 1206 * This is not needed when running the emulation under QEMU 1207 */ 1208 1209 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1210 return H_FUNCTION; 1211 } 1212 1213 /* 1214 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1215 * real address of the reporting cache line pair set for the input 1216 * "target". If no reporting cache line pair has been set, -1 is 1217 * returned. 1218 * 1219 * Parameters: 1220 * Input: 1221 * - R4: "flags" 1222 * Bits 0-63: Reserved 1223 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1224 * "ibm,ppc-interrupt-gserver#s" 1225 * - R6: "reportingLine": The logical real address of the reporting 1226 * cache line pair 1227 * 1228 * Output: 1229 * - R4: The logical real address of the reporting line if set, else -1 1230 */ 1231 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1232 SpaprMachineState *spapr, 1233 target_ulong opcode, 1234 target_ulong *args) 1235 { 1236 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1237 return H_FUNCTION; 1238 } 1239 1240 /* 1241 * H_STATE should be returned if a H_INT_RESET is in progress. 1242 * This is not needed when running the emulation under QEMU 1243 */ 1244 1245 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1246 return H_FUNCTION; 1247 } 1248 1249 /* 1250 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1251 * page for the input "lisn". This hcall is only supported for LISNs 1252 * that have the ESB hcall flag set to 1 when returned from hcall() 1253 * H_INT_GET_SOURCE_INFO. 1254 * 1255 * Parameters: 1256 * Input: 1257 * - R4: "flags" 1258 * Bits 0-62: Reserved 1259 * bit 63: Store: Store=1, store operation, else load operation 1260 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1261 * "ibm,xive-lisn-ranges" properties, or as returned by the 1262 * ibm,query-interrupt-source-number RTAS call, or as 1263 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1264 * - R6: "esbOffset" is the offset into the ESB page for the load or 1265 * store operation 1266 * - R7: "storeData" is the data to write for a store operation 1267 * 1268 * Output: 1269 * - R4: The value of the load if load operation, else -1 1270 */ 1271 1272 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1273 1274 static target_ulong h_int_esb(PowerPCCPU *cpu, 1275 SpaprMachineState *spapr, 1276 target_ulong opcode, 1277 target_ulong *args) 1278 { 1279 SpaprXive *xive = spapr->xive; 1280 XiveEAS eas; 1281 target_ulong flags = args[0]; 1282 target_ulong lisn = args[1]; 1283 target_ulong offset = args[2]; 1284 target_ulong data = args[3]; 1285 hwaddr mmio_addr; 1286 XiveSource *xsrc = &xive->source; 1287 1288 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1289 return H_FUNCTION; 1290 } 1291 1292 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1293 return H_PARAMETER; 1294 } 1295 1296 if (lisn >= xive->nr_irqs) { 1297 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1298 lisn); 1299 return H_P2; 1300 } 1301 1302 eas = xive->eat[lisn]; 1303 if (!xive_eas_is_valid(&eas)) { 1304 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1305 lisn); 1306 return H_P2; 1307 } 1308 1309 if (offset > (1ull << xsrc->esb_shift)) { 1310 return H_P3; 1311 } 1312 1313 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1314 1315 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1316 (flags & SPAPR_XIVE_ESB_STORE))) { 1317 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1318 HWADDR_PRIx "\n", mmio_addr); 1319 return H_HARDWARE; 1320 } 1321 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1322 return H_SUCCESS; 1323 } 1324 1325 /* 1326 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1327 * ensure any in flight events for the input lisn are in the event 1328 * queue. 1329 * 1330 * Parameters: 1331 * Input: 1332 * - R4: "flags" 1333 * Bits 0-63: Reserved 1334 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1335 * "ibm,xive-lisn-ranges" properties, or as returned by the 1336 * ibm,query-interrupt-source-number RTAS call, or as 1337 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1338 * 1339 * Output: 1340 * - None 1341 */ 1342 static target_ulong h_int_sync(PowerPCCPU *cpu, 1343 SpaprMachineState *spapr, 1344 target_ulong opcode, 1345 target_ulong *args) 1346 { 1347 SpaprXive *xive = spapr->xive; 1348 XiveEAS eas; 1349 target_ulong flags = args[0]; 1350 target_ulong lisn = args[1]; 1351 1352 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1353 return H_FUNCTION; 1354 } 1355 1356 if (flags) { 1357 return H_PARAMETER; 1358 } 1359 1360 if (lisn >= xive->nr_irqs) { 1361 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1362 lisn); 1363 return H_P2; 1364 } 1365 1366 eas = xive->eat[lisn]; 1367 if (!xive_eas_is_valid(&eas)) { 1368 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1369 lisn); 1370 return H_P2; 1371 } 1372 1373 /* 1374 * H_STATE should be returned if a H_INT_RESET is in progress. 1375 * This is not needed when running the emulation under QEMU 1376 */ 1377 1378 /* This is not real hardware. Nothing to be done */ 1379 return H_SUCCESS; 1380 } 1381 1382 /* 1383 * The H_INT_RESET hcall() is used to reset all of the partition's 1384 * interrupt exploitation structures to their initial state. This 1385 * means losing all previously set interrupt state set via 1386 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1387 * 1388 * Parameters: 1389 * Input: 1390 * - R4: "flags" 1391 * Bits 0-63: Reserved 1392 * 1393 * Output: 1394 * - None 1395 */ 1396 static target_ulong h_int_reset(PowerPCCPU *cpu, 1397 SpaprMachineState *spapr, 1398 target_ulong opcode, 1399 target_ulong *args) 1400 { 1401 SpaprXive *xive = spapr->xive; 1402 target_ulong flags = args[0]; 1403 1404 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1405 return H_FUNCTION; 1406 } 1407 1408 if (flags) { 1409 return H_PARAMETER; 1410 } 1411 1412 device_reset(DEVICE(xive)); 1413 return H_SUCCESS; 1414 } 1415 1416 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1417 { 1418 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1419 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1420 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1421 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1422 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1423 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1424 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1425 h_int_set_os_reporting_line); 1426 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1427 h_int_get_os_reporting_line); 1428 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1429 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1430 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1431 } 1432 1433 void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, 1434 uint32_t phandle) 1435 { 1436 SpaprXive *xive = spapr->xive; 1437 int node; 1438 uint64_t timas[2 * 2]; 1439 /* Interrupt number ranges for the IPIs */ 1440 uint32_t lisn_ranges[] = { 1441 cpu_to_be32(0), 1442 cpu_to_be32(nr_servers), 1443 }; 1444 /* 1445 * EQ size - the sizes of pages supported by the system 4K, 64K, 1446 * 2M, 16M. We only advertise 64K for the moment. 1447 */ 1448 uint32_t eq_sizes[] = { 1449 cpu_to_be32(16), /* 64K */ 1450 }; 1451 /* 1452 * The following array is in sync with the reserved priorities 1453 * defined by the 'spapr_xive_priority_is_reserved' routine. 1454 */ 1455 uint32_t plat_res_int_priorities[] = { 1456 cpu_to_be32(7), /* start */ 1457 cpu_to_be32(0xf8), /* count */ 1458 }; 1459 1460 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 1461 timas[0] = cpu_to_be64(xive->tm_base + 1462 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 1463 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 1464 timas[2] = cpu_to_be64(xive->tm_base + 1465 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 1466 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 1467 1468 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 1469 1470 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 1471 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 1472 1473 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 1474 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 1475 sizeof(eq_sizes))); 1476 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 1477 sizeof(lisn_ranges))); 1478 1479 /* For Linux to link the LSIs to the interrupt controller. */ 1480 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 1481 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 1482 1483 /* For SLOF */ 1484 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 1485 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 1486 1487 /* 1488 * The "ibm,plat-res-int-priorities" property defines the priority 1489 * ranges reserved by the hypervisor 1490 */ 1491 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 1492 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 1493 } 1494