1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "qemu/error-report.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "monitor/monitor.h" 17 #include "hw/ppc/fdt.h" 18 #include "hw/ppc/spapr.h" 19 #include "hw/ppc/spapr_cpu_core.h" 20 #include "hw/ppc/spapr_xive.h" 21 #include "hw/ppc/xive.h" 22 #include "hw/ppc/xive_regs.h" 23 24 /* 25 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 26 * use for the ESB pages and the TIMA pages 27 */ 28 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 29 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 30 31 /* 32 * The allocation of VP blocks is a complex operation in OPAL and the 33 * VP identifiers have a relation with the number of HW chips, the 34 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 35 * controller model does not have the same constraints and can use a 36 * simple mapping scheme of the CPU vcpu_id 37 * 38 * These identifiers are never returned to the OS. 39 */ 40 41 #define SPAPR_XIVE_NVT_BASE 0x400 42 43 /* 44 * The sPAPR machine has a unique XIVE IC device. Assign a fixed value 45 * to the controller block id value. It can nevertheless be changed 46 * for testing purpose. 47 */ 48 #define SPAPR_XIVE_BLOCK_ID 0x0 49 50 /* 51 * sPAPR NVT and END indexing helpers 52 */ 53 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 54 { 55 return nvt_idx - SPAPR_XIVE_NVT_BASE; 56 } 57 58 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 59 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 60 { 61 assert(cpu); 62 63 if (out_nvt_blk) { 64 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 65 } 66 67 if (out_nvt_blk) { 68 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 69 } 70 } 71 72 static int spapr_xive_target_to_nvt(uint32_t target, 73 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 74 { 75 PowerPCCPU *cpu = spapr_find_cpu(target); 76 77 if (!cpu) { 78 return -1; 79 } 80 81 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 82 return 0; 83 } 84 85 /* 86 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 87 * priorities per CPU 88 */ 89 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 90 uint8_t *out_end_blk, uint32_t *out_end_idx) 91 { 92 assert(cpu); 93 94 if (out_end_blk) { 95 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 96 } 97 98 if (out_end_idx) { 99 *out_end_idx = (cpu->vcpu_id << 3) + prio; 100 } 101 } 102 103 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 104 uint8_t *out_end_blk, uint32_t *out_end_idx) 105 { 106 PowerPCCPU *cpu = spapr_find_cpu(target); 107 108 if (!cpu) { 109 return -1; 110 } 111 112 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 113 return 0; 114 } 115 116 /* 117 * On sPAPR machines, use a simplified output for the XIVE END 118 * structure dumping only the information related to the OS EQ. 119 */ 120 static void spapr_xive_end_pic_print_info(sPAPRXive *xive, XiveEND *end, 121 Monitor *mon) 122 { 123 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 124 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 125 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 126 uint32_t qentries = 1 << (qsize + 10); 127 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 128 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 129 130 monitor_printf(mon, "%3d/%d % 6d/%5d ^%d", 131 spapr_xive_nvt_to_target(0, nvt), 132 priority, qindex, qentries, qgen); 133 134 xive_end_queue_pic_print_info(end, 6, mon); 135 monitor_printf(mon, "]"); 136 } 137 138 void spapr_xive_pic_print_info(sPAPRXive *xive, Monitor *mon) 139 { 140 XiveSource *xsrc = &xive->source; 141 int i; 142 143 monitor_printf(mon, " LSIN PQ EISN CPU/PRIO EQ\n"); 144 145 for (i = 0; i < xive->nr_irqs; i++) { 146 uint8_t pq = xive_source_esb_get(xsrc, i); 147 XiveEAS *eas = &xive->eat[i]; 148 149 if (!xive_eas_is_valid(eas)) { 150 continue; 151 } 152 153 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 154 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 155 pq & XIVE_ESB_VAL_P ? 'P' : '-', 156 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 157 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 158 xive_eas_is_masked(eas) ? "M" : " ", 159 (int) xive_get_field64(EAS_END_DATA, eas->w)); 160 161 if (!xive_eas_is_masked(eas)) { 162 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 163 XiveEND *end; 164 165 assert(end_idx < xive->nr_ends); 166 end = &xive->endt[end_idx]; 167 168 if (xive_end_is_valid(end)) { 169 spapr_xive_end_pic_print_info(xive, end, mon); 170 } 171 } 172 monitor_printf(mon, "\n"); 173 } 174 } 175 176 static void spapr_xive_map_mmio(sPAPRXive *xive) 177 { 178 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 179 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 180 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 181 } 182 183 void spapr_xive_mmio_set_enabled(sPAPRXive *xive, bool enable) 184 { 185 memory_region_set_enabled(&xive->source.esb_mmio, enable); 186 memory_region_set_enabled(&xive->tm_mmio, enable); 187 188 /* Disable the END ESBs until a guest OS makes use of them */ 189 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 190 } 191 192 /* 193 * When a Virtual Processor is scheduled to run on a HW thread, the 194 * hypervisor pushes its identifier in the OS CAM line. Emulate the 195 * same behavior under QEMU. 196 */ 197 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 198 { 199 uint8_t nvt_blk; 200 uint32_t nvt_idx; 201 uint32_t nvt_cam; 202 203 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 204 205 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 206 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 207 } 208 209 static void spapr_xive_end_reset(XiveEND *end) 210 { 211 memset(end, 0, sizeof(*end)); 212 213 /* switch off the escalation and notification ESBs */ 214 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 215 } 216 217 static void spapr_xive_reset(void *dev) 218 { 219 sPAPRXive *xive = SPAPR_XIVE(dev); 220 int i; 221 222 /* 223 * The XiveSource has its own reset handler, which mask off all 224 * IRQs (!P|Q) 225 */ 226 227 /* Mask all valid EASs in the IRQ number space. */ 228 for (i = 0; i < xive->nr_irqs; i++) { 229 XiveEAS *eas = &xive->eat[i]; 230 if (xive_eas_is_valid(eas)) { 231 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 232 } else { 233 eas->w = 0; 234 } 235 } 236 237 /* Clear all ENDs */ 238 for (i = 0; i < xive->nr_ends; i++) { 239 spapr_xive_end_reset(&xive->endt[i]); 240 } 241 } 242 243 static void spapr_xive_instance_init(Object *obj) 244 { 245 sPAPRXive *xive = SPAPR_XIVE(obj); 246 247 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 248 TYPE_XIVE_SOURCE, &error_abort, NULL); 249 250 object_initialize_child(obj, "end_source", &xive->end_source, 251 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 252 &error_abort, NULL); 253 } 254 255 static void spapr_xive_realize(DeviceState *dev, Error **errp) 256 { 257 sPAPRXive *xive = SPAPR_XIVE(dev); 258 XiveSource *xsrc = &xive->source; 259 XiveENDSource *end_xsrc = &xive->end_source; 260 Error *local_err = NULL; 261 262 if (!xive->nr_irqs) { 263 error_setg(errp, "Number of interrupt needs to be greater 0"); 264 return; 265 } 266 267 if (!xive->nr_ends) { 268 error_setg(errp, "Number of interrupt needs to be greater 0"); 269 return; 270 } 271 272 /* 273 * Initialize the internal sources, for IPIs and virtual devices. 274 */ 275 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 276 &error_fatal); 277 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 278 &error_fatal); 279 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 280 if (local_err) { 281 error_propagate(errp, local_err); 282 return; 283 } 284 285 /* 286 * Initialize the END ESB source 287 */ 288 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 289 &error_fatal); 290 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 291 &error_fatal); 292 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 293 if (local_err) { 294 error_propagate(errp, local_err); 295 return; 296 } 297 298 /* Set the mapping address of the END ESB pages after the source ESBs */ 299 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 300 301 /* 302 * Allocate the routing tables 303 */ 304 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 305 xive->endt = g_new0(XiveEND, xive->nr_ends); 306 307 /* TIMA initialization */ 308 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 309 "xive.tima", 4ull << TM_SHIFT); 310 311 /* Define all XIVE MMIO regions on SysBus */ 312 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 313 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 314 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 315 316 /* Map all regions */ 317 spapr_xive_map_mmio(xive); 318 319 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 320 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 321 322 qemu_register_reset(spapr_xive_reset, dev); 323 } 324 325 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 326 uint32_t eas_idx, XiveEAS *eas) 327 { 328 sPAPRXive *xive = SPAPR_XIVE(xrtr); 329 330 if (eas_idx >= xive->nr_irqs) { 331 return -1; 332 } 333 334 *eas = xive->eat[eas_idx]; 335 return 0; 336 } 337 338 static int spapr_xive_get_end(XiveRouter *xrtr, 339 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 340 { 341 sPAPRXive *xive = SPAPR_XIVE(xrtr); 342 343 if (end_idx >= xive->nr_ends) { 344 return -1; 345 } 346 347 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 348 return 0; 349 } 350 351 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 352 uint32_t end_idx, XiveEND *end, 353 uint8_t word_number) 354 { 355 sPAPRXive *xive = SPAPR_XIVE(xrtr); 356 357 if (end_idx >= xive->nr_ends) { 358 return -1; 359 } 360 361 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 362 return 0; 363 } 364 365 static int spapr_xive_get_nvt(XiveRouter *xrtr, 366 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 367 { 368 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 369 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 370 371 if (!cpu) { 372 /* TODO: should we assert() if we can find a NVT ? */ 373 return -1; 374 } 375 376 /* 377 * sPAPR does not maintain a NVT table. Return that the NVT is 378 * valid if we have found a matching CPU 379 */ 380 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 381 return 0; 382 } 383 384 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 385 uint32_t nvt_idx, XiveNVT *nvt, 386 uint8_t word_number) 387 { 388 /* 389 * We don't need to write back to the NVTs because the sPAPR 390 * machine should never hit a non-scheduled NVT. It should never 391 * get called. 392 */ 393 g_assert_not_reached(); 394 } 395 396 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 397 { 398 PowerPCCPU *cpu = POWERPC_CPU(cs); 399 400 return spapr_cpu_state(cpu)->tctx; 401 } 402 403 static const VMStateDescription vmstate_spapr_xive_end = { 404 .name = TYPE_SPAPR_XIVE "/end", 405 .version_id = 1, 406 .minimum_version_id = 1, 407 .fields = (VMStateField []) { 408 VMSTATE_UINT32(w0, XiveEND), 409 VMSTATE_UINT32(w1, XiveEND), 410 VMSTATE_UINT32(w2, XiveEND), 411 VMSTATE_UINT32(w3, XiveEND), 412 VMSTATE_UINT32(w4, XiveEND), 413 VMSTATE_UINT32(w5, XiveEND), 414 VMSTATE_UINT32(w6, XiveEND), 415 VMSTATE_UINT32(w7, XiveEND), 416 VMSTATE_END_OF_LIST() 417 }, 418 }; 419 420 static const VMStateDescription vmstate_spapr_xive_eas = { 421 .name = TYPE_SPAPR_XIVE "/eas", 422 .version_id = 1, 423 .minimum_version_id = 1, 424 .fields = (VMStateField []) { 425 VMSTATE_UINT64(w, XiveEAS), 426 VMSTATE_END_OF_LIST() 427 }, 428 }; 429 430 static const VMStateDescription vmstate_spapr_xive = { 431 .name = TYPE_SPAPR_XIVE, 432 .version_id = 1, 433 .minimum_version_id = 1, 434 .fields = (VMStateField[]) { 435 VMSTATE_UINT32_EQUAL(nr_irqs, sPAPRXive, NULL), 436 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, sPAPRXive, nr_irqs, 437 vmstate_spapr_xive_eas, XiveEAS), 438 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, sPAPRXive, nr_ends, 439 vmstate_spapr_xive_end, XiveEND), 440 VMSTATE_END_OF_LIST() 441 }, 442 }; 443 444 static Property spapr_xive_properties[] = { 445 DEFINE_PROP_UINT32("nr-irqs", sPAPRXive, nr_irqs, 0), 446 DEFINE_PROP_UINT32("nr-ends", sPAPRXive, nr_ends, 0), 447 DEFINE_PROP_UINT64("vc-base", sPAPRXive, vc_base, SPAPR_XIVE_VC_BASE), 448 DEFINE_PROP_UINT64("tm-base", sPAPRXive, tm_base, SPAPR_XIVE_TM_BASE), 449 DEFINE_PROP_END_OF_LIST(), 450 }; 451 452 static void spapr_xive_class_init(ObjectClass *klass, void *data) 453 { 454 DeviceClass *dc = DEVICE_CLASS(klass); 455 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 456 457 dc->desc = "sPAPR XIVE Interrupt Controller"; 458 dc->props = spapr_xive_properties; 459 dc->realize = spapr_xive_realize; 460 dc->vmsd = &vmstate_spapr_xive; 461 462 xrc->get_eas = spapr_xive_get_eas; 463 xrc->get_end = spapr_xive_get_end; 464 xrc->write_end = spapr_xive_write_end; 465 xrc->get_nvt = spapr_xive_get_nvt; 466 xrc->write_nvt = spapr_xive_write_nvt; 467 xrc->get_tctx = spapr_xive_get_tctx; 468 } 469 470 static const TypeInfo spapr_xive_info = { 471 .name = TYPE_SPAPR_XIVE, 472 .parent = TYPE_XIVE_ROUTER, 473 .instance_init = spapr_xive_instance_init, 474 .instance_size = sizeof(sPAPRXive), 475 .class_init = spapr_xive_class_init, 476 }; 477 478 static void spapr_xive_register_types(void) 479 { 480 type_register_static(&spapr_xive_info); 481 } 482 483 type_init(spapr_xive_register_types) 484 485 bool spapr_xive_irq_claim(sPAPRXive *xive, uint32_t lisn, bool lsi) 486 { 487 XiveSource *xsrc = &xive->source; 488 489 if (lisn >= xive->nr_irqs) { 490 return false; 491 } 492 493 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID); 494 if (lsi) { 495 xive_source_irq_set_lsi(xsrc, lisn); 496 } 497 return true; 498 } 499 500 bool spapr_xive_irq_free(sPAPRXive *xive, uint32_t lisn) 501 { 502 if (lisn >= xive->nr_irqs) { 503 return false; 504 } 505 506 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 507 return true; 508 } 509 510 /* 511 * XIVE hcalls 512 * 513 * The terminology used by the XIVE hcalls is the following : 514 * 515 * TARGET vCPU number 516 * EQ Event Queue assigned by OS to receive event data 517 * ESB page for source interrupt management 518 * LISN Logical Interrupt Source Number identifying a source in the 519 * machine 520 * EISN Effective Interrupt Source Number used by guest OS to 521 * identify source in the guest 522 * 523 * The EAS, END, NVT structures are not exposed. 524 */ 525 526 /* 527 * Linux hosts under OPAL reserve priority 7 for their own escalation 528 * interrupts (DD2.X POWER9). So we only allow the guest to use 529 * priorities [0..6]. 530 */ 531 static bool spapr_xive_priority_is_reserved(uint8_t priority) 532 { 533 switch (priority) { 534 case 0 ... 6: 535 return false; 536 case 7: /* OPAL escalation queue */ 537 default: 538 return true; 539 } 540 } 541 542 /* 543 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 544 * real address of the MMIO page through which the Event State Buffer 545 * entry associated with the value of the "lisn" parameter is managed. 546 * 547 * Parameters: 548 * Input 549 * - R4: "flags" 550 * Bits 0-63 reserved 551 * - R5: "lisn" is per "interrupts", "interrupt-map", or 552 * "ibm,xive-lisn-ranges" properties, or as returned by the 553 * ibm,query-interrupt-source-number RTAS call, or as returned 554 * by the H_ALLOCATE_VAS_WINDOW hcall 555 * 556 * Output 557 * - R4: "flags" 558 * Bits 0-59: Reserved 559 * Bit 60: H_INT_ESB must be used for Event State Buffer 560 * management 561 * Bit 61: 1 == LSI 0 == MSI 562 * Bit 62: the full function page supports trigger 563 * Bit 63: Store EOI Supported 564 * - R5: Logical Real address of full function Event State Buffer 565 * management page, -1 if H_INT_ESB hcall flag is set to 1. 566 * - R6: Logical Real Address of trigger only Event State Buffer 567 * management page or -1. 568 * - R7: Power of 2 page size for the ESB management pages returned in 569 * R5 and R6. 570 */ 571 572 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 573 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 574 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 575 on same page */ 576 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 577 578 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 579 sPAPRMachineState *spapr, 580 target_ulong opcode, 581 target_ulong *args) 582 { 583 sPAPRXive *xive = spapr->xive; 584 XiveSource *xsrc = &xive->source; 585 target_ulong flags = args[0]; 586 target_ulong lisn = args[1]; 587 588 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 589 return H_FUNCTION; 590 } 591 592 if (flags) { 593 return H_PARAMETER; 594 } 595 596 if (lisn >= xive->nr_irqs) { 597 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 598 lisn); 599 return H_P2; 600 } 601 602 if (!xive_eas_is_valid(&xive->eat[lisn])) { 603 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 604 lisn); 605 return H_P2; 606 } 607 608 /* 609 * All sources are emulated under the main XIVE object and share 610 * the same characteristics. 611 */ 612 args[0] = 0; 613 if (!xive_source_esb_has_2page(xsrc)) { 614 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 615 } 616 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 617 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 618 } 619 620 /* 621 * Force the use of the H_INT_ESB hcall in case of an LSI 622 * interrupt. This is necessary under KVM to re-trigger the 623 * interrupt if the level is still asserted 624 */ 625 if (xive_source_irq_is_lsi(xsrc, lisn)) { 626 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 627 } 628 629 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 630 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 631 } else { 632 args[1] = -1; 633 } 634 635 if (xive_source_esb_has_2page(xsrc) && 636 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 637 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 638 } else { 639 args[2] = -1; 640 } 641 642 if (xive_source_esb_has_2page(xsrc)) { 643 args[3] = xsrc->esb_shift - 1; 644 } else { 645 args[3] = xsrc->esb_shift; 646 } 647 648 return H_SUCCESS; 649 } 650 651 /* 652 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 653 * Interrupt Source to a target. The Logical Interrupt Source is 654 * designated with the "lisn" parameter and the target is designated 655 * with the "target" and "priority" parameters. Upon return from the 656 * hcall(), no additional interrupts will be directed to the old EQ. 657 * 658 * Parameters: 659 * Input: 660 * - R4: "flags" 661 * Bits 0-61: Reserved 662 * Bit 62: set the "eisn" in the EAS 663 * Bit 63: masks the interrupt source in the hardware interrupt 664 * control structure. An interrupt masked by this mechanism will 665 * be dropped, but it's source state bits will still be 666 * set. There is no race-free way of unmasking and restoring the 667 * source. Thus this should only be used in interrupts that are 668 * also masked at the source, and only in cases where the 669 * interrupt is not meant to be used for a large amount of time 670 * because no valid target exists for it for example 671 * - R5: "lisn" is per "interrupts", "interrupt-map", or 672 * "ibm,xive-lisn-ranges" properties, or as returned by the 673 * ibm,query-interrupt-source-number RTAS call, or as returned by 674 * the H_ALLOCATE_VAS_WINDOW hcall 675 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 676 * "ibm,ppc-interrupt-gserver#s" 677 * - R7: "priority" is a valid priority not in 678 * "ibm,plat-res-int-priorities" 679 * - R8: "eisn" is the guest EISN associated with the "lisn" 680 * 681 * Output: 682 * - None 683 */ 684 685 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 686 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 687 688 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 689 sPAPRMachineState *spapr, 690 target_ulong opcode, 691 target_ulong *args) 692 { 693 sPAPRXive *xive = spapr->xive; 694 XiveEAS eas, new_eas; 695 target_ulong flags = args[0]; 696 target_ulong lisn = args[1]; 697 target_ulong target = args[2]; 698 target_ulong priority = args[3]; 699 target_ulong eisn = args[4]; 700 uint8_t end_blk; 701 uint32_t end_idx; 702 703 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 704 return H_FUNCTION; 705 } 706 707 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 708 return H_PARAMETER; 709 } 710 711 if (lisn >= xive->nr_irqs) { 712 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 713 lisn); 714 return H_P2; 715 } 716 717 eas = xive->eat[lisn]; 718 if (!xive_eas_is_valid(&eas)) { 719 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 720 lisn); 721 return H_P2; 722 } 723 724 /* priority 0xff is used to reset the EAS */ 725 if (priority == 0xff) { 726 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 727 goto out; 728 } 729 730 if (flags & SPAPR_XIVE_SRC_MASK) { 731 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 732 } else { 733 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 734 } 735 736 if (spapr_xive_priority_is_reserved(priority)) { 737 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 738 " is reserved\n", priority); 739 return H_P4; 740 } 741 742 /* 743 * Validate that "target" is part of the list of threads allocated 744 * to the partition. For that, find the END corresponding to the 745 * target. 746 */ 747 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 748 return H_P3; 749 } 750 751 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 752 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 753 754 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 755 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 756 } 757 758 out: 759 xive->eat[lisn] = new_eas; 760 return H_SUCCESS; 761 } 762 763 /* 764 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 765 * target/priority pair is assigned to the specified Logical Interrupt 766 * Source. 767 * 768 * Parameters: 769 * Input: 770 * - R4: "flags" 771 * Bits 0-63 Reserved 772 * - R5: "lisn" is per "interrupts", "interrupt-map", or 773 * "ibm,xive-lisn-ranges" properties, or as returned by the 774 * ibm,query-interrupt-source-number RTAS call, or as 775 * returned by the H_ALLOCATE_VAS_WINDOW hcall 776 * 777 * Output: 778 * - R4: Target to which the specified Logical Interrupt Source is 779 * assigned 780 * - R5: Priority to which the specified Logical Interrupt Source is 781 * assigned 782 * - R6: EISN for the specified Logical Interrupt Source (this will be 783 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 784 */ 785 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 786 sPAPRMachineState *spapr, 787 target_ulong opcode, 788 target_ulong *args) 789 { 790 sPAPRXive *xive = spapr->xive; 791 target_ulong flags = args[0]; 792 target_ulong lisn = args[1]; 793 XiveEAS eas; 794 XiveEND *end; 795 uint8_t nvt_blk; 796 uint32_t end_idx, nvt_idx; 797 798 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 799 return H_FUNCTION; 800 } 801 802 if (flags) { 803 return H_PARAMETER; 804 } 805 806 if (lisn >= xive->nr_irqs) { 807 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 808 lisn); 809 return H_P2; 810 } 811 812 eas = xive->eat[lisn]; 813 if (!xive_eas_is_valid(&eas)) { 814 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 815 lisn); 816 return H_P2; 817 } 818 819 /* EAS_END_BLOCK is unused on sPAPR */ 820 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 821 822 assert(end_idx < xive->nr_ends); 823 end = &xive->endt[end_idx]; 824 825 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 826 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 827 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 828 829 if (xive_eas_is_masked(&eas)) { 830 args[1] = 0xff; 831 } else { 832 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 833 } 834 835 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 836 837 return H_SUCCESS; 838 } 839 840 /* 841 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 842 * address of the notification management page associated with the 843 * specified target and priority. 844 * 845 * Parameters: 846 * Input: 847 * - R4: "flags" 848 * Bits 0-63 Reserved 849 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 850 * "ibm,ppc-interrupt-gserver#s" 851 * - R6: "priority" is a valid priority not in 852 * "ibm,plat-res-int-priorities" 853 * 854 * Output: 855 * - R4: Logical real address of notification page 856 * - R5: Power of 2 page size of the notification page 857 */ 858 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 859 sPAPRMachineState *spapr, 860 target_ulong opcode, 861 target_ulong *args) 862 { 863 sPAPRXive *xive = spapr->xive; 864 XiveENDSource *end_xsrc = &xive->end_source; 865 target_ulong flags = args[0]; 866 target_ulong target = args[1]; 867 target_ulong priority = args[2]; 868 XiveEND *end; 869 uint8_t end_blk; 870 uint32_t end_idx; 871 872 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 873 return H_FUNCTION; 874 } 875 876 if (flags) { 877 return H_PARAMETER; 878 } 879 880 /* 881 * H_STATE should be returned if a H_INT_RESET is in progress. 882 * This is not needed when running the emulation under QEMU 883 */ 884 885 if (spapr_xive_priority_is_reserved(priority)) { 886 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 887 " is reserved\n", priority); 888 return H_P3; 889 } 890 891 /* 892 * Validate that "target" is part of the list of threads allocated 893 * to the partition. For that, find the END corresponding to the 894 * target. 895 */ 896 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 897 return H_P2; 898 } 899 900 assert(end_idx < xive->nr_ends); 901 end = &xive->endt[end_idx]; 902 903 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 904 if (xive_end_is_enqueue(end)) { 905 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 906 } else { 907 args[1] = 0; 908 } 909 910 return H_SUCCESS; 911 } 912 913 /* 914 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 915 * a given "target" and "priority". It is also used to set the 916 * notification config associated with the EQ. An EQ size of 0 is 917 * used to reset the EQ config for a given target and priority. If 918 * resetting the EQ config, the END associated with the given "target" 919 * and "priority" will be changed to disable queueing. 920 * 921 * Upon return from the hcall(), no additional interrupts will be 922 * directed to the old EQ (if one was set). The old EQ (if one was 923 * set) should be investigated for interrupts that occurred prior to 924 * or during the hcall(). 925 * 926 * Parameters: 927 * Input: 928 * - R4: "flags" 929 * Bits 0-62: Reserved 930 * Bit 63: Unconditional Notify (n) per the XIVE spec 931 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 932 * "ibm,ppc-interrupt-gserver#s" 933 * - R6: "priority" is a valid priority not in 934 * "ibm,plat-res-int-priorities" 935 * - R7: "eventQueue": The logical real address of the start of the EQ 936 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 937 * 938 * Output: 939 * - None 940 */ 941 942 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 943 944 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 945 sPAPRMachineState *spapr, 946 target_ulong opcode, 947 target_ulong *args) 948 { 949 sPAPRXive *xive = spapr->xive; 950 target_ulong flags = args[0]; 951 target_ulong target = args[1]; 952 target_ulong priority = args[2]; 953 target_ulong qpage = args[3]; 954 target_ulong qsize = args[4]; 955 XiveEND end; 956 uint8_t end_blk, nvt_blk; 957 uint32_t end_idx, nvt_idx; 958 959 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 960 return H_FUNCTION; 961 } 962 963 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 964 return H_PARAMETER; 965 } 966 967 /* 968 * H_STATE should be returned if a H_INT_RESET is in progress. 969 * This is not needed when running the emulation under QEMU 970 */ 971 972 if (spapr_xive_priority_is_reserved(priority)) { 973 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 974 " is reserved\n", priority); 975 return H_P3; 976 } 977 978 /* 979 * Validate that "target" is part of the list of threads allocated 980 * to the partition. For that, find the END corresponding to the 981 * target. 982 */ 983 984 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 985 return H_P2; 986 } 987 988 assert(end_idx < xive->nr_ends); 989 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 990 991 switch (qsize) { 992 case 12: 993 case 16: 994 case 21: 995 case 24: 996 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 997 end.w3 = cpu_to_be32(qpage & 0xffffffff); 998 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 999 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1000 break; 1001 case 0: 1002 /* reset queue and disable queueing */ 1003 spapr_xive_end_reset(&end); 1004 goto out; 1005 1006 default: 1007 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1008 qsize); 1009 return H_P5; 1010 } 1011 1012 if (qsize) { 1013 hwaddr plen = 1 << qsize; 1014 void *eq; 1015 1016 /* 1017 * Validate the guest EQ. We should also check that the queue 1018 * has been zeroed by the OS. 1019 */ 1020 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1021 MEMTXATTRS_UNSPECIFIED); 1022 if (plen != 1 << qsize) { 1023 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1024 HWADDR_PRIx "\n", qpage); 1025 return H_P4; 1026 } 1027 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1028 } 1029 1030 /* "target" should have been validated above */ 1031 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1032 g_assert_not_reached(); 1033 } 1034 1035 /* 1036 * Ensure the priority and target are correctly set (they will not 1037 * be right after allocation) 1038 */ 1039 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1040 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1041 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1042 1043 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1044 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1045 } else { 1046 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1047 } 1048 1049 /* 1050 * The generation bit for the END starts at 1 and The END page 1051 * offset counter starts at 0. 1052 */ 1053 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1054 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1055 end.w0 |= cpu_to_be32(END_W0_VALID); 1056 1057 /* 1058 * TODO: issue syncs required to ensure all in-flight interrupts 1059 * are complete on the old END 1060 */ 1061 1062 out: 1063 /* Update END */ 1064 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1065 return H_SUCCESS; 1066 } 1067 1068 /* 1069 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1070 * target and priority. 1071 * 1072 * Parameters: 1073 * Input: 1074 * - R4: "flags" 1075 * Bits 0-62: Reserved 1076 * Bit 63: Debug: Return debug data 1077 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1078 * "ibm,ppc-interrupt-gserver#s" 1079 * - R6: "priority" is a valid priority not in 1080 * "ibm,plat-res-int-priorities" 1081 * 1082 * Output: 1083 * - R4: "flags": 1084 * Bits 0-61: Reserved 1085 * Bit 62: The value of Event Queue Generation Number (g) per 1086 * the XIVE spec if "Debug" = 1 1087 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1088 * - R5: The logical real address of the start of the EQ 1089 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1090 * - R7: The value of Event Queue Offset Counter per XIVE spec 1091 * if "Debug" = 1, else 0 1092 * 1093 */ 1094 1095 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1096 1097 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1098 sPAPRMachineState *spapr, 1099 target_ulong opcode, 1100 target_ulong *args) 1101 { 1102 sPAPRXive *xive = spapr->xive; 1103 target_ulong flags = args[0]; 1104 target_ulong target = args[1]; 1105 target_ulong priority = args[2]; 1106 XiveEND *end; 1107 uint8_t end_blk; 1108 uint32_t end_idx; 1109 1110 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1111 return H_FUNCTION; 1112 } 1113 1114 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1115 return H_PARAMETER; 1116 } 1117 1118 /* 1119 * H_STATE should be returned if a H_INT_RESET is in progress. 1120 * This is not needed when running the emulation under QEMU 1121 */ 1122 1123 if (spapr_xive_priority_is_reserved(priority)) { 1124 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1125 " is reserved\n", priority); 1126 return H_P3; 1127 } 1128 1129 /* 1130 * Validate that "target" is part of the list of threads allocated 1131 * to the partition. For that, find the END corresponding to the 1132 * target. 1133 */ 1134 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1135 return H_P2; 1136 } 1137 1138 assert(end_idx < xive->nr_ends); 1139 end = &xive->endt[end_idx]; 1140 1141 args[0] = 0; 1142 if (xive_end_is_notify(end)) { 1143 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1144 } 1145 1146 if (xive_end_is_enqueue(end)) { 1147 args[1] = (uint64_t) be32_to_cpu(end->w2 & 0x0fffffff) << 32 1148 | be32_to_cpu(end->w3); 1149 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1150 } else { 1151 args[1] = 0; 1152 args[2] = 0; 1153 } 1154 1155 /* TODO: do we need any locking on the END ? */ 1156 if (flags & SPAPR_XIVE_END_DEBUG) { 1157 /* Load the event queue generation number into the return flags */ 1158 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1159 1160 /* Load R7 with the event queue offset counter */ 1161 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1162 } else { 1163 args[3] = 0; 1164 } 1165 1166 return H_SUCCESS; 1167 } 1168 1169 /* 1170 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1171 * reporting cache line pair for the calling thread. The reporting 1172 * cache lines will contain the OS interrupt context when the OS 1173 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1174 * interrupt. The reporting cache lines can be reset by inputting -1 1175 * in "reportingLine". Issuing the CI store byte without reporting 1176 * cache lines registered will result in the data not being accessible 1177 * to the OS. 1178 * 1179 * Parameters: 1180 * Input: 1181 * - R4: "flags" 1182 * Bits 0-63: Reserved 1183 * - R5: "reportingLine": The logical real address of the reporting cache 1184 * line pair 1185 * 1186 * Output: 1187 * - None 1188 */ 1189 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1190 sPAPRMachineState *spapr, 1191 target_ulong opcode, 1192 target_ulong *args) 1193 { 1194 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1195 return H_FUNCTION; 1196 } 1197 1198 /* 1199 * H_STATE should be returned if a H_INT_RESET is in progress. 1200 * This is not needed when running the emulation under QEMU 1201 */ 1202 1203 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1204 return H_FUNCTION; 1205 } 1206 1207 /* 1208 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1209 * real address of the reporting cache line pair set for the input 1210 * "target". If no reporting cache line pair has been set, -1 is 1211 * returned. 1212 * 1213 * Parameters: 1214 * Input: 1215 * - R4: "flags" 1216 * Bits 0-63: Reserved 1217 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1218 * "ibm,ppc-interrupt-gserver#s" 1219 * - R6: "reportingLine": The logical real address of the reporting 1220 * cache line pair 1221 * 1222 * Output: 1223 * - R4: The logical real address of the reporting line if set, else -1 1224 */ 1225 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1226 sPAPRMachineState *spapr, 1227 target_ulong opcode, 1228 target_ulong *args) 1229 { 1230 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1231 return H_FUNCTION; 1232 } 1233 1234 /* 1235 * H_STATE should be returned if a H_INT_RESET is in progress. 1236 * This is not needed when running the emulation under QEMU 1237 */ 1238 1239 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1240 return H_FUNCTION; 1241 } 1242 1243 /* 1244 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1245 * page for the input "lisn". This hcall is only supported for LISNs 1246 * that have the ESB hcall flag set to 1 when returned from hcall() 1247 * H_INT_GET_SOURCE_INFO. 1248 * 1249 * Parameters: 1250 * Input: 1251 * - R4: "flags" 1252 * Bits 0-62: Reserved 1253 * bit 63: Store: Store=1, store operation, else load operation 1254 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1255 * "ibm,xive-lisn-ranges" properties, or as returned by the 1256 * ibm,query-interrupt-source-number RTAS call, or as 1257 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1258 * - R6: "esbOffset" is the offset into the ESB page for the load or 1259 * store operation 1260 * - R7: "storeData" is the data to write for a store operation 1261 * 1262 * Output: 1263 * - R4: The value of the load if load operation, else -1 1264 */ 1265 1266 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1267 1268 static target_ulong h_int_esb(PowerPCCPU *cpu, 1269 sPAPRMachineState *spapr, 1270 target_ulong opcode, 1271 target_ulong *args) 1272 { 1273 sPAPRXive *xive = spapr->xive; 1274 XiveEAS eas; 1275 target_ulong flags = args[0]; 1276 target_ulong lisn = args[1]; 1277 target_ulong offset = args[2]; 1278 target_ulong data = args[3]; 1279 hwaddr mmio_addr; 1280 XiveSource *xsrc = &xive->source; 1281 1282 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1283 return H_FUNCTION; 1284 } 1285 1286 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1287 return H_PARAMETER; 1288 } 1289 1290 if (lisn >= xive->nr_irqs) { 1291 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1292 lisn); 1293 return H_P2; 1294 } 1295 1296 eas = xive->eat[lisn]; 1297 if (!xive_eas_is_valid(&eas)) { 1298 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1299 lisn); 1300 return H_P2; 1301 } 1302 1303 if (offset > (1ull << xsrc->esb_shift)) { 1304 return H_P3; 1305 } 1306 1307 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1308 1309 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1310 (flags & SPAPR_XIVE_ESB_STORE))) { 1311 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1312 HWADDR_PRIx "\n", mmio_addr); 1313 return H_HARDWARE; 1314 } 1315 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1316 return H_SUCCESS; 1317 } 1318 1319 /* 1320 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1321 * ensure any in flight events for the input lisn are in the event 1322 * queue. 1323 * 1324 * Parameters: 1325 * Input: 1326 * - R4: "flags" 1327 * Bits 0-63: Reserved 1328 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1329 * "ibm,xive-lisn-ranges" properties, or as returned by the 1330 * ibm,query-interrupt-source-number RTAS call, or as 1331 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1332 * 1333 * Output: 1334 * - None 1335 */ 1336 static target_ulong h_int_sync(PowerPCCPU *cpu, 1337 sPAPRMachineState *spapr, 1338 target_ulong opcode, 1339 target_ulong *args) 1340 { 1341 sPAPRXive *xive = spapr->xive; 1342 XiveEAS eas; 1343 target_ulong flags = args[0]; 1344 target_ulong lisn = args[1]; 1345 1346 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1347 return H_FUNCTION; 1348 } 1349 1350 if (flags) { 1351 return H_PARAMETER; 1352 } 1353 1354 if (lisn >= xive->nr_irqs) { 1355 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1356 lisn); 1357 return H_P2; 1358 } 1359 1360 eas = xive->eat[lisn]; 1361 if (!xive_eas_is_valid(&eas)) { 1362 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1363 lisn); 1364 return H_P2; 1365 } 1366 1367 /* 1368 * H_STATE should be returned if a H_INT_RESET is in progress. 1369 * This is not needed when running the emulation under QEMU 1370 */ 1371 1372 /* This is not real hardware. Nothing to be done */ 1373 return H_SUCCESS; 1374 } 1375 1376 /* 1377 * The H_INT_RESET hcall() is used to reset all of the partition's 1378 * interrupt exploitation structures to their initial state. This 1379 * means losing all previously set interrupt state set via 1380 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1381 * 1382 * Parameters: 1383 * Input: 1384 * - R4: "flags" 1385 * Bits 0-63: Reserved 1386 * 1387 * Output: 1388 * - None 1389 */ 1390 static target_ulong h_int_reset(PowerPCCPU *cpu, 1391 sPAPRMachineState *spapr, 1392 target_ulong opcode, 1393 target_ulong *args) 1394 { 1395 sPAPRXive *xive = spapr->xive; 1396 target_ulong flags = args[0]; 1397 1398 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1399 return H_FUNCTION; 1400 } 1401 1402 if (flags) { 1403 return H_PARAMETER; 1404 } 1405 1406 device_reset(DEVICE(xive)); 1407 return H_SUCCESS; 1408 } 1409 1410 void spapr_xive_hcall_init(sPAPRMachineState *spapr) 1411 { 1412 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1413 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1414 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1415 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1416 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1417 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1418 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1419 h_int_set_os_reporting_line); 1420 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1421 h_int_get_os_reporting_line); 1422 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1423 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1424 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1425 } 1426 1427 void spapr_dt_xive(sPAPRMachineState *spapr, uint32_t nr_servers, void *fdt, 1428 uint32_t phandle) 1429 { 1430 sPAPRXive *xive = spapr->xive; 1431 int node; 1432 uint64_t timas[2 * 2]; 1433 /* Interrupt number ranges for the IPIs */ 1434 uint32_t lisn_ranges[] = { 1435 cpu_to_be32(0), 1436 cpu_to_be32(nr_servers), 1437 }; 1438 /* 1439 * EQ size - the sizes of pages supported by the system 4K, 64K, 1440 * 2M, 16M. We only advertise 64K for the moment. 1441 */ 1442 uint32_t eq_sizes[] = { 1443 cpu_to_be32(16), /* 64K */ 1444 }; 1445 /* 1446 * The following array is in sync with the reserved priorities 1447 * defined by the 'spapr_xive_priority_is_reserved' routine. 1448 */ 1449 uint32_t plat_res_int_priorities[] = { 1450 cpu_to_be32(7), /* start */ 1451 cpu_to_be32(0xf8), /* count */ 1452 }; 1453 1454 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 1455 timas[0] = cpu_to_be64(xive->tm_base + 1456 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 1457 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 1458 timas[2] = cpu_to_be64(xive->tm_base + 1459 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 1460 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 1461 1462 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 1463 1464 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 1465 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 1466 1467 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 1468 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 1469 sizeof(eq_sizes))); 1470 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 1471 sizeof(lisn_ranges))); 1472 1473 /* For Linux to link the LSIs to the interrupt controller. */ 1474 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 1475 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 1476 1477 /* For SLOF */ 1478 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 1479 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 1480 1481 /* 1482 * The "ibm,plat-res-int-priorities" property defines the priority 1483 * ranges reserved by the hypervisor 1484 */ 1485 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 1486 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 1487 } 1488