1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 } 150 151 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 152 { 153 XiveSource *xsrc = &xive->source; 154 int i; 155 156 if (kvm_irqchip_in_kernel()) { 157 Error *local_err = NULL; 158 159 kvmppc_xive_synchronize_state(xive, &local_err); 160 if (local_err) { 161 error_report_err(local_err); 162 return; 163 } 164 } 165 166 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 167 168 for (i = 0; i < xive->nr_irqs; i++) { 169 uint8_t pq = xive_source_esb_get(xsrc, i); 170 XiveEAS *eas = &xive->eat[i]; 171 172 if (!xive_eas_is_valid(eas)) { 173 continue; 174 } 175 176 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 177 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 178 pq & XIVE_ESB_VAL_P ? 'P' : '-', 179 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 180 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 181 xive_eas_is_masked(eas) ? "M" : " ", 182 (int) xive_get_field64(EAS_END_DATA, eas->w)); 183 184 if (!xive_eas_is_masked(eas)) { 185 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 186 XiveEND *end; 187 188 assert(end_idx < xive->nr_ends); 189 end = &xive->endt[end_idx]; 190 191 if (xive_end_is_valid(end)) { 192 spapr_xive_end_pic_print_info(xive, end, mon); 193 } 194 } 195 monitor_printf(mon, "\n"); 196 } 197 } 198 199 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 200 { 201 memory_region_set_enabled(&xive->source.esb_mmio, enable); 202 memory_region_set_enabled(&xive->tm_mmio, enable); 203 204 /* Disable the END ESBs until a guest OS makes use of them */ 205 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 206 } 207 208 static void spapr_xive_end_reset(XiveEND *end) 209 { 210 memset(end, 0, sizeof(*end)); 211 212 /* switch off the escalation and notification ESBs */ 213 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 214 } 215 216 static void spapr_xive_reset(void *dev) 217 { 218 SpaprXive *xive = SPAPR_XIVE(dev); 219 int i; 220 221 /* 222 * The XiveSource has its own reset handler, which mask off all 223 * IRQs (!P|Q) 224 */ 225 226 /* Mask all valid EASs in the IRQ number space. */ 227 for (i = 0; i < xive->nr_irqs; i++) { 228 XiveEAS *eas = &xive->eat[i]; 229 if (xive_eas_is_valid(eas)) { 230 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 231 } else { 232 eas->w = 0; 233 } 234 } 235 236 /* Clear all ENDs */ 237 for (i = 0; i < xive->nr_ends; i++) { 238 spapr_xive_end_reset(&xive->endt[i]); 239 } 240 } 241 242 static void spapr_xive_instance_init(Object *obj) 243 { 244 SpaprXive *xive = SPAPR_XIVE(obj); 245 246 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 247 TYPE_XIVE_SOURCE, &error_abort, NULL); 248 249 object_initialize_child(obj, "end_source", &xive->end_source, 250 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 251 &error_abort, NULL); 252 253 /* Not connected to the KVM XIVE device */ 254 xive->fd = -1; 255 } 256 257 static void spapr_xive_realize(DeviceState *dev, Error **errp) 258 { 259 SpaprXive *xive = SPAPR_XIVE(dev); 260 XiveSource *xsrc = &xive->source; 261 XiveENDSource *end_xsrc = &xive->end_source; 262 Error *local_err = NULL; 263 264 if (!xive->nr_irqs) { 265 error_setg(errp, "Number of interrupt needs to be greater 0"); 266 return; 267 } 268 269 if (!xive->nr_ends) { 270 error_setg(errp, "Number of interrupt needs to be greater 0"); 271 return; 272 } 273 274 /* 275 * Initialize the internal sources, for IPIs and virtual devices. 276 */ 277 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 278 &error_fatal); 279 object_property_set_link(OBJECT(xsrc), OBJECT(xive), "xive", 280 &error_abort); 281 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 282 if (local_err) { 283 error_propagate(errp, local_err); 284 return; 285 } 286 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 287 288 /* 289 * Initialize the END ESB source 290 */ 291 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 292 &error_fatal); 293 object_property_set_link(OBJECT(end_xsrc), OBJECT(xive), "xive", 294 &error_abort); 295 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 296 if (local_err) { 297 error_propagate(errp, local_err); 298 return; 299 } 300 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 301 302 /* Set the mapping address of the END ESB pages after the source ESBs */ 303 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 304 305 /* 306 * Allocate the routing tables 307 */ 308 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 309 xive->endt = g_new0(XiveEND, xive->nr_ends); 310 311 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 312 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 313 314 qemu_register_reset(spapr_xive_reset, dev); 315 316 /* TIMA initialization */ 317 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 318 "xive.tima", 4ull << TM_SHIFT); 319 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 320 321 /* 322 * Map all regions. These will be enabled or disabled at reset and 323 * can also be overridden by KVM memory regions if active 324 */ 325 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 326 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 327 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 328 } 329 330 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 331 uint32_t eas_idx, XiveEAS *eas) 332 { 333 SpaprXive *xive = SPAPR_XIVE(xrtr); 334 335 if (eas_idx >= xive->nr_irqs) { 336 return -1; 337 } 338 339 *eas = xive->eat[eas_idx]; 340 return 0; 341 } 342 343 static int spapr_xive_get_end(XiveRouter *xrtr, 344 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 345 { 346 SpaprXive *xive = SPAPR_XIVE(xrtr); 347 348 if (end_idx >= xive->nr_ends) { 349 return -1; 350 } 351 352 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 353 return 0; 354 } 355 356 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 357 uint32_t end_idx, XiveEND *end, 358 uint8_t word_number) 359 { 360 SpaprXive *xive = SPAPR_XIVE(xrtr); 361 362 if (end_idx >= xive->nr_ends) { 363 return -1; 364 } 365 366 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 367 return 0; 368 } 369 370 static int spapr_xive_get_nvt(XiveRouter *xrtr, 371 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 372 { 373 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 374 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 375 376 if (!cpu) { 377 /* TODO: should we assert() if we can find a NVT ? */ 378 return -1; 379 } 380 381 /* 382 * sPAPR does not maintain a NVT table. Return that the NVT is 383 * valid if we have found a matching CPU 384 */ 385 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 386 return 0; 387 } 388 389 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 390 uint32_t nvt_idx, XiveNVT *nvt, 391 uint8_t word_number) 392 { 393 /* 394 * We don't need to write back to the NVTs because the sPAPR 395 * machine should never hit a non-scheduled NVT. It should never 396 * get called. 397 */ 398 g_assert_not_reached(); 399 } 400 401 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 402 { 403 PowerPCCPU *cpu = POWERPC_CPU(cs); 404 405 return spapr_cpu_state(cpu)->tctx; 406 } 407 408 static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, 409 uint8_t nvt_blk, uint32_t nvt_idx, 410 bool cam_ignore, uint8_t priority, 411 uint32_t logic_serv, XiveTCTXMatch *match) 412 { 413 CPUState *cs; 414 int count = 0; 415 416 CPU_FOREACH(cs) { 417 PowerPCCPU *cpu = POWERPC_CPU(cs); 418 XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx; 419 int ring; 420 421 /* 422 * Skip partially initialized vCPUs. This can happen when 423 * vCPUs are hotplugged. 424 */ 425 if (!tctx) { 426 continue; 427 } 428 429 /* 430 * Check the thread context CAM lines and record matches. 431 */ 432 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx, 433 cam_ignore, logic_serv); 434 /* 435 * Save the matching thread interrupt context and follow on to 436 * check for duplicates which are invalid. 437 */ 438 if (ring != -1) { 439 if (match->tctx) { 440 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread " 441 "context NVT %x/%x\n", nvt_blk, nvt_idx); 442 return -1; 443 } 444 445 match->ring = ring; 446 match->tctx = tctx; 447 count++; 448 } 449 } 450 451 return count; 452 } 453 454 static const VMStateDescription vmstate_spapr_xive_end = { 455 .name = TYPE_SPAPR_XIVE "/end", 456 .version_id = 1, 457 .minimum_version_id = 1, 458 .fields = (VMStateField []) { 459 VMSTATE_UINT32(w0, XiveEND), 460 VMSTATE_UINT32(w1, XiveEND), 461 VMSTATE_UINT32(w2, XiveEND), 462 VMSTATE_UINT32(w3, XiveEND), 463 VMSTATE_UINT32(w4, XiveEND), 464 VMSTATE_UINT32(w5, XiveEND), 465 VMSTATE_UINT32(w6, XiveEND), 466 VMSTATE_UINT32(w7, XiveEND), 467 VMSTATE_END_OF_LIST() 468 }, 469 }; 470 471 static const VMStateDescription vmstate_spapr_xive_eas = { 472 .name = TYPE_SPAPR_XIVE "/eas", 473 .version_id = 1, 474 .minimum_version_id = 1, 475 .fields = (VMStateField []) { 476 VMSTATE_UINT64(w, XiveEAS), 477 VMSTATE_END_OF_LIST() 478 }, 479 }; 480 481 static int vmstate_spapr_xive_pre_save(void *opaque) 482 { 483 if (kvm_irqchip_in_kernel()) { 484 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 485 } 486 487 return 0; 488 } 489 490 /* 491 * Called by the sPAPR IRQ backend 'post_load' method at the machine 492 * level. 493 */ 494 static int spapr_xive_post_load(SpaprInterruptController *intc, int version_id) 495 { 496 if (kvm_irqchip_in_kernel()) { 497 return kvmppc_xive_post_load(SPAPR_XIVE(intc), version_id); 498 } 499 500 return 0; 501 } 502 503 static const VMStateDescription vmstate_spapr_xive = { 504 .name = TYPE_SPAPR_XIVE, 505 .version_id = 1, 506 .minimum_version_id = 1, 507 .pre_save = vmstate_spapr_xive_pre_save, 508 .post_load = NULL, /* handled at the machine level */ 509 .fields = (VMStateField[]) { 510 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 511 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 512 vmstate_spapr_xive_eas, XiveEAS), 513 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 514 vmstate_spapr_xive_end, XiveEND), 515 VMSTATE_END_OF_LIST() 516 }, 517 }; 518 519 static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, 520 bool lsi, Error **errp) 521 { 522 SpaprXive *xive = SPAPR_XIVE(intc); 523 XiveSource *xsrc = &xive->source; 524 525 assert(lisn < xive->nr_irqs); 526 527 if (xive_eas_is_valid(&xive->eat[lisn])) { 528 error_setg(errp, "IRQ %d is not free", lisn); 529 return -EBUSY; 530 } 531 532 /* 533 * Set default values when allocating an IRQ number 534 */ 535 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); 536 if (lsi) { 537 xive_source_irq_set_lsi(xsrc, lisn); 538 } 539 540 if (kvm_irqchip_in_kernel()) { 541 return kvmppc_xive_source_reset_one(xsrc, lisn, errp); 542 } 543 544 return 0; 545 } 546 547 static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) 548 { 549 SpaprXive *xive = SPAPR_XIVE(intc); 550 assert(lisn < xive->nr_irqs); 551 552 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 553 } 554 555 static Property spapr_xive_properties[] = { 556 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 557 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 558 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 559 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 560 DEFINE_PROP_END_OF_LIST(), 561 }; 562 563 static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 564 PowerPCCPU *cpu, Error **errp) 565 { 566 SpaprXive *xive = SPAPR_XIVE(intc); 567 Object *obj; 568 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 569 570 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp); 571 if (!obj) { 572 return -1; 573 } 574 575 spapr_cpu->tctx = XIVE_TCTX(obj); 576 return 0; 577 } 578 579 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t os_cam) 580 { 581 uint32_t qw1w2 = cpu_to_be32(TM_QW1W2_VO | os_cam); 582 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 583 } 584 585 static void spapr_xive_cpu_intc_reset(SpaprInterruptController *intc, 586 PowerPCCPU *cpu) 587 { 588 XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx; 589 uint8_t nvt_blk; 590 uint32_t nvt_idx; 591 592 xive_tctx_reset(tctx); 593 594 /* 595 * When a Virtual Processor is scheduled to run on a HW thread, 596 * the hypervisor pushes its identifier in the OS CAM line. 597 * Emulate the same behavior under QEMU. 598 */ 599 spapr_xive_cpu_to_nvt(cpu, &nvt_blk, &nvt_idx); 600 601 xive_tctx_set_os_cam(tctx, xive_nvt_cam_line(nvt_blk, nvt_idx)); 602 } 603 604 static void spapr_xive_cpu_intc_destroy(SpaprInterruptController *intc, 605 PowerPCCPU *cpu) 606 { 607 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 608 609 xive_tctx_destroy(spapr_cpu->tctx); 610 spapr_cpu->tctx = NULL; 611 } 612 613 static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val) 614 { 615 SpaprXive *xive = SPAPR_XIVE(intc); 616 617 if (kvm_irqchip_in_kernel()) { 618 kvmppc_xive_source_set_irq(&xive->source, irq, val); 619 } else { 620 xive_source_set_irq(&xive->source, irq, val); 621 } 622 } 623 624 static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor *mon) 625 { 626 SpaprXive *xive = SPAPR_XIVE(intc); 627 CPUState *cs; 628 629 CPU_FOREACH(cs) { 630 PowerPCCPU *cpu = POWERPC_CPU(cs); 631 632 xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); 633 } 634 635 spapr_xive_pic_print_info(xive, mon); 636 } 637 638 static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers, 639 void *fdt, uint32_t phandle) 640 { 641 SpaprXive *xive = SPAPR_XIVE(intc); 642 int node; 643 uint64_t timas[2 * 2]; 644 /* Interrupt number ranges for the IPIs */ 645 uint32_t lisn_ranges[] = { 646 cpu_to_be32(0), 647 cpu_to_be32(nr_servers), 648 }; 649 /* 650 * EQ size - the sizes of pages supported by the system 4K, 64K, 651 * 2M, 16M. We only advertise 64K for the moment. 652 */ 653 uint32_t eq_sizes[] = { 654 cpu_to_be32(16), /* 64K */ 655 }; 656 /* 657 * The following array is in sync with the reserved priorities 658 * defined by the 'spapr_xive_priority_is_reserved' routine. 659 */ 660 uint32_t plat_res_int_priorities[] = { 661 cpu_to_be32(7), /* start */ 662 cpu_to_be32(0xf8), /* count */ 663 }; 664 665 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 666 timas[0] = cpu_to_be64(xive->tm_base + 667 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 668 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 669 timas[2] = cpu_to_be64(xive->tm_base + 670 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 671 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 672 673 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 674 675 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 676 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 677 678 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 679 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 680 sizeof(eq_sizes))); 681 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 682 sizeof(lisn_ranges))); 683 684 /* For Linux to link the LSIs to the interrupt controller. */ 685 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 686 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 687 688 /* For SLOF */ 689 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 690 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 691 692 /* 693 * The "ibm,plat-res-int-priorities" property defines the priority 694 * ranges reserved by the hypervisor 695 */ 696 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 697 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 698 } 699 700 static int spapr_xive_activate(SpaprInterruptController *intc, Error **errp) 701 { 702 SpaprXive *xive = SPAPR_XIVE(intc); 703 704 if (kvm_enabled()) { 705 int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, errp); 706 if (rc < 0) { 707 return rc; 708 } 709 } 710 711 /* Activate the XIVE MMIOs */ 712 spapr_xive_mmio_set_enabled(xive, true); 713 714 return 0; 715 } 716 717 static void spapr_xive_deactivate(SpaprInterruptController *intc) 718 { 719 SpaprXive *xive = SPAPR_XIVE(intc); 720 721 spapr_xive_mmio_set_enabled(xive, false); 722 723 if (kvm_irqchip_in_kernel()) { 724 kvmppc_xive_disconnect(intc); 725 } 726 } 727 728 static void spapr_xive_class_init(ObjectClass *klass, void *data) 729 { 730 DeviceClass *dc = DEVICE_CLASS(klass); 731 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 732 SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); 733 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 734 735 dc->desc = "sPAPR XIVE Interrupt Controller"; 736 dc->props = spapr_xive_properties; 737 dc->realize = spapr_xive_realize; 738 dc->vmsd = &vmstate_spapr_xive; 739 740 xrc->get_eas = spapr_xive_get_eas; 741 xrc->get_end = spapr_xive_get_end; 742 xrc->write_end = spapr_xive_write_end; 743 xrc->get_nvt = spapr_xive_get_nvt; 744 xrc->write_nvt = spapr_xive_write_nvt; 745 xrc->get_tctx = spapr_xive_get_tctx; 746 747 sicc->activate = spapr_xive_activate; 748 sicc->deactivate = spapr_xive_deactivate; 749 sicc->cpu_intc_create = spapr_xive_cpu_intc_create; 750 sicc->cpu_intc_reset = spapr_xive_cpu_intc_reset; 751 sicc->cpu_intc_destroy = spapr_xive_cpu_intc_destroy; 752 sicc->claim_irq = spapr_xive_claim_irq; 753 sicc->free_irq = spapr_xive_free_irq; 754 sicc->set_irq = spapr_xive_set_irq; 755 sicc->print_info = spapr_xive_print_info; 756 sicc->dt = spapr_xive_dt; 757 sicc->post_load = spapr_xive_post_load; 758 759 xpc->match_nvt = spapr_xive_match_nvt; 760 } 761 762 static const TypeInfo spapr_xive_info = { 763 .name = TYPE_SPAPR_XIVE, 764 .parent = TYPE_XIVE_ROUTER, 765 .instance_init = spapr_xive_instance_init, 766 .instance_size = sizeof(SpaprXive), 767 .class_init = spapr_xive_class_init, 768 .interfaces = (InterfaceInfo[]) { 769 { TYPE_SPAPR_INTC }, 770 { } 771 }, 772 }; 773 774 static void spapr_xive_register_types(void) 775 { 776 type_register_static(&spapr_xive_info); 777 } 778 779 type_init(spapr_xive_register_types) 780 781 /* 782 * XIVE hcalls 783 * 784 * The terminology used by the XIVE hcalls is the following : 785 * 786 * TARGET vCPU number 787 * EQ Event Queue assigned by OS to receive event data 788 * ESB page for source interrupt management 789 * LISN Logical Interrupt Source Number identifying a source in the 790 * machine 791 * EISN Effective Interrupt Source Number used by guest OS to 792 * identify source in the guest 793 * 794 * The EAS, END, NVT structures are not exposed. 795 */ 796 797 /* 798 * Linux hosts under OPAL reserve priority 7 for their own escalation 799 * interrupts (DD2.X POWER9). So we only allow the guest to use 800 * priorities [0..6]. 801 */ 802 static bool spapr_xive_priority_is_reserved(uint8_t priority) 803 { 804 switch (priority) { 805 case 0 ... 6: 806 return false; 807 case 7: /* OPAL escalation queue */ 808 default: 809 return true; 810 } 811 } 812 813 /* 814 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 815 * real address of the MMIO page through which the Event State Buffer 816 * entry associated with the value of the "lisn" parameter is managed. 817 * 818 * Parameters: 819 * Input 820 * - R4: "flags" 821 * Bits 0-63 reserved 822 * - R5: "lisn" is per "interrupts", "interrupt-map", or 823 * "ibm,xive-lisn-ranges" properties, or as returned by the 824 * ibm,query-interrupt-source-number RTAS call, or as returned 825 * by the H_ALLOCATE_VAS_WINDOW hcall 826 * 827 * Output 828 * - R4: "flags" 829 * Bits 0-59: Reserved 830 * Bit 60: H_INT_ESB must be used for Event State Buffer 831 * management 832 * Bit 61: 1 == LSI 0 == MSI 833 * Bit 62: the full function page supports trigger 834 * Bit 63: Store EOI Supported 835 * - R5: Logical Real address of full function Event State Buffer 836 * management page, -1 if H_INT_ESB hcall flag is set to 1. 837 * - R6: Logical Real Address of trigger only Event State Buffer 838 * management page or -1. 839 * - R7: Power of 2 page size for the ESB management pages returned in 840 * R5 and R6. 841 */ 842 843 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 844 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 845 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 846 on same page */ 847 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 848 849 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 850 SpaprMachineState *spapr, 851 target_ulong opcode, 852 target_ulong *args) 853 { 854 SpaprXive *xive = spapr->xive; 855 XiveSource *xsrc = &xive->source; 856 target_ulong flags = args[0]; 857 target_ulong lisn = args[1]; 858 859 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 860 return H_FUNCTION; 861 } 862 863 if (flags) { 864 return H_PARAMETER; 865 } 866 867 if (lisn >= xive->nr_irqs) { 868 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 869 lisn); 870 return H_P2; 871 } 872 873 if (!xive_eas_is_valid(&xive->eat[lisn])) { 874 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 875 lisn); 876 return H_P2; 877 } 878 879 /* 880 * All sources are emulated under the main XIVE object and share 881 * the same characteristics. 882 */ 883 args[0] = 0; 884 if (!xive_source_esb_has_2page(xsrc)) { 885 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 886 } 887 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 888 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 889 } 890 891 /* 892 * Force the use of the H_INT_ESB hcall in case of an LSI 893 * interrupt. This is necessary under KVM to re-trigger the 894 * interrupt if the level is still asserted 895 */ 896 if (xive_source_irq_is_lsi(xsrc, lisn)) { 897 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 898 } 899 900 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 901 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 902 } else { 903 args[1] = -1; 904 } 905 906 if (xive_source_esb_has_2page(xsrc) && 907 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 908 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 909 } else { 910 args[2] = -1; 911 } 912 913 if (xive_source_esb_has_2page(xsrc)) { 914 args[3] = xsrc->esb_shift - 1; 915 } else { 916 args[3] = xsrc->esb_shift; 917 } 918 919 return H_SUCCESS; 920 } 921 922 /* 923 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 924 * Interrupt Source to a target. The Logical Interrupt Source is 925 * designated with the "lisn" parameter and the target is designated 926 * with the "target" and "priority" parameters. Upon return from the 927 * hcall(), no additional interrupts will be directed to the old EQ. 928 * 929 * Parameters: 930 * Input: 931 * - R4: "flags" 932 * Bits 0-61: Reserved 933 * Bit 62: set the "eisn" in the EAS 934 * Bit 63: masks the interrupt source in the hardware interrupt 935 * control structure. An interrupt masked by this mechanism will 936 * be dropped, but it's source state bits will still be 937 * set. There is no race-free way of unmasking and restoring the 938 * source. Thus this should only be used in interrupts that are 939 * also masked at the source, and only in cases where the 940 * interrupt is not meant to be used for a large amount of time 941 * because no valid target exists for it for example 942 * - R5: "lisn" is per "interrupts", "interrupt-map", or 943 * "ibm,xive-lisn-ranges" properties, or as returned by the 944 * ibm,query-interrupt-source-number RTAS call, or as returned by 945 * the H_ALLOCATE_VAS_WINDOW hcall 946 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 947 * "ibm,ppc-interrupt-gserver#s" 948 * - R7: "priority" is a valid priority not in 949 * "ibm,plat-res-int-priorities" 950 * - R8: "eisn" is the guest EISN associated with the "lisn" 951 * 952 * Output: 953 * - None 954 */ 955 956 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 957 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 958 959 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 960 SpaprMachineState *spapr, 961 target_ulong opcode, 962 target_ulong *args) 963 { 964 SpaprXive *xive = spapr->xive; 965 XiveEAS eas, new_eas; 966 target_ulong flags = args[0]; 967 target_ulong lisn = args[1]; 968 target_ulong target = args[2]; 969 target_ulong priority = args[3]; 970 target_ulong eisn = args[4]; 971 uint8_t end_blk; 972 uint32_t end_idx; 973 974 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 975 return H_FUNCTION; 976 } 977 978 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 979 return H_PARAMETER; 980 } 981 982 if (lisn >= xive->nr_irqs) { 983 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 984 lisn); 985 return H_P2; 986 } 987 988 eas = xive->eat[lisn]; 989 if (!xive_eas_is_valid(&eas)) { 990 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 991 lisn); 992 return H_P2; 993 } 994 995 /* priority 0xff is used to reset the EAS */ 996 if (priority == 0xff) { 997 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 998 goto out; 999 } 1000 1001 if (flags & SPAPR_XIVE_SRC_MASK) { 1002 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 1003 } else { 1004 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 1005 } 1006 1007 if (spapr_xive_priority_is_reserved(priority)) { 1008 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1009 " is reserved\n", priority); 1010 return H_P4; 1011 } 1012 1013 /* 1014 * Validate that "target" is part of the list of threads allocated 1015 * to the partition. For that, find the END corresponding to the 1016 * target. 1017 */ 1018 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1019 return H_P3; 1020 } 1021 1022 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 1023 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 1024 1025 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 1026 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 1027 } 1028 1029 if (kvm_irqchip_in_kernel()) { 1030 Error *local_err = NULL; 1031 1032 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 1033 if (local_err) { 1034 error_report_err(local_err); 1035 return H_HARDWARE; 1036 } 1037 } 1038 1039 out: 1040 xive->eat[lisn] = new_eas; 1041 return H_SUCCESS; 1042 } 1043 1044 /* 1045 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 1046 * target/priority pair is assigned to the specified Logical Interrupt 1047 * Source. 1048 * 1049 * Parameters: 1050 * Input: 1051 * - R4: "flags" 1052 * Bits 0-63 Reserved 1053 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1054 * "ibm,xive-lisn-ranges" properties, or as returned by the 1055 * ibm,query-interrupt-source-number RTAS call, or as 1056 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1057 * 1058 * Output: 1059 * - R4: Target to which the specified Logical Interrupt Source is 1060 * assigned 1061 * - R5: Priority to which the specified Logical Interrupt Source is 1062 * assigned 1063 * - R6: EISN for the specified Logical Interrupt Source (this will be 1064 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 1065 */ 1066 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 1067 SpaprMachineState *spapr, 1068 target_ulong opcode, 1069 target_ulong *args) 1070 { 1071 SpaprXive *xive = spapr->xive; 1072 target_ulong flags = args[0]; 1073 target_ulong lisn = args[1]; 1074 XiveEAS eas; 1075 XiveEND *end; 1076 uint8_t nvt_blk; 1077 uint32_t end_idx, nvt_idx; 1078 1079 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1080 return H_FUNCTION; 1081 } 1082 1083 if (flags) { 1084 return H_PARAMETER; 1085 } 1086 1087 if (lisn >= xive->nr_irqs) { 1088 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1089 lisn); 1090 return H_P2; 1091 } 1092 1093 eas = xive->eat[lisn]; 1094 if (!xive_eas_is_valid(&eas)) { 1095 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1096 lisn); 1097 return H_P2; 1098 } 1099 1100 /* EAS_END_BLOCK is unused on sPAPR */ 1101 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 1102 1103 assert(end_idx < xive->nr_ends); 1104 end = &xive->endt[end_idx]; 1105 1106 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1107 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1108 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 1109 1110 if (xive_eas_is_masked(&eas)) { 1111 args[1] = 0xff; 1112 } else { 1113 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1114 } 1115 1116 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 1117 1118 return H_SUCCESS; 1119 } 1120 1121 /* 1122 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 1123 * address of the notification management page associated with the 1124 * specified target and priority. 1125 * 1126 * Parameters: 1127 * Input: 1128 * - R4: "flags" 1129 * Bits 0-63 Reserved 1130 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1131 * "ibm,ppc-interrupt-gserver#s" 1132 * - R6: "priority" is a valid priority not in 1133 * "ibm,plat-res-int-priorities" 1134 * 1135 * Output: 1136 * - R4: Logical real address of notification page 1137 * - R5: Power of 2 page size of the notification page 1138 */ 1139 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 1140 SpaprMachineState *spapr, 1141 target_ulong opcode, 1142 target_ulong *args) 1143 { 1144 SpaprXive *xive = spapr->xive; 1145 XiveENDSource *end_xsrc = &xive->end_source; 1146 target_ulong flags = args[0]; 1147 target_ulong target = args[1]; 1148 target_ulong priority = args[2]; 1149 XiveEND *end; 1150 uint8_t end_blk; 1151 uint32_t end_idx; 1152 1153 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1154 return H_FUNCTION; 1155 } 1156 1157 if (flags) { 1158 return H_PARAMETER; 1159 } 1160 1161 /* 1162 * H_STATE should be returned if a H_INT_RESET is in progress. 1163 * This is not needed when running the emulation under QEMU 1164 */ 1165 1166 if (spapr_xive_priority_is_reserved(priority)) { 1167 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1168 " is reserved\n", priority); 1169 return H_P3; 1170 } 1171 1172 /* 1173 * Validate that "target" is part of the list of threads allocated 1174 * to the partition. For that, find the END corresponding to the 1175 * target. 1176 */ 1177 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1178 return H_P2; 1179 } 1180 1181 assert(end_idx < xive->nr_ends); 1182 end = &xive->endt[end_idx]; 1183 1184 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 1185 if (xive_end_is_enqueue(end)) { 1186 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1187 } else { 1188 args[1] = 0; 1189 } 1190 1191 return H_SUCCESS; 1192 } 1193 1194 /* 1195 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 1196 * a given "target" and "priority". It is also used to set the 1197 * notification config associated with the EQ. An EQ size of 0 is 1198 * used to reset the EQ config for a given target and priority. If 1199 * resetting the EQ config, the END associated with the given "target" 1200 * and "priority" will be changed to disable queueing. 1201 * 1202 * Upon return from the hcall(), no additional interrupts will be 1203 * directed to the old EQ (if one was set). The old EQ (if one was 1204 * set) should be investigated for interrupts that occurred prior to 1205 * or during the hcall(). 1206 * 1207 * Parameters: 1208 * Input: 1209 * - R4: "flags" 1210 * Bits 0-62: Reserved 1211 * Bit 63: Unconditional Notify (n) per the XIVE spec 1212 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1213 * "ibm,ppc-interrupt-gserver#s" 1214 * - R6: "priority" is a valid priority not in 1215 * "ibm,plat-res-int-priorities" 1216 * - R7: "eventQueue": The logical real address of the start of the EQ 1217 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1218 * 1219 * Output: 1220 * - None 1221 */ 1222 1223 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1224 1225 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1226 SpaprMachineState *spapr, 1227 target_ulong opcode, 1228 target_ulong *args) 1229 { 1230 SpaprXive *xive = spapr->xive; 1231 target_ulong flags = args[0]; 1232 target_ulong target = args[1]; 1233 target_ulong priority = args[2]; 1234 target_ulong qpage = args[3]; 1235 target_ulong qsize = args[4]; 1236 XiveEND end; 1237 uint8_t end_blk, nvt_blk; 1238 uint32_t end_idx, nvt_idx; 1239 1240 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1241 return H_FUNCTION; 1242 } 1243 1244 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1245 return H_PARAMETER; 1246 } 1247 1248 /* 1249 * H_STATE should be returned if a H_INT_RESET is in progress. 1250 * This is not needed when running the emulation under QEMU 1251 */ 1252 1253 if (spapr_xive_priority_is_reserved(priority)) { 1254 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1255 " is reserved\n", priority); 1256 return H_P3; 1257 } 1258 1259 /* 1260 * Validate that "target" is part of the list of threads allocated 1261 * to the partition. For that, find the END corresponding to the 1262 * target. 1263 */ 1264 1265 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1266 return H_P2; 1267 } 1268 1269 assert(end_idx < xive->nr_ends); 1270 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1271 1272 switch (qsize) { 1273 case 12: 1274 case 16: 1275 case 21: 1276 case 24: 1277 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1278 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1279 " is not naturally aligned with %" HWADDR_PRIx "\n", 1280 qpage, (hwaddr)1 << qsize); 1281 return H_P4; 1282 } 1283 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1284 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1285 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1286 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1287 break; 1288 case 0: 1289 /* reset queue and disable queueing */ 1290 spapr_xive_end_reset(&end); 1291 goto out; 1292 1293 default: 1294 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1295 qsize); 1296 return H_P5; 1297 } 1298 1299 if (qsize) { 1300 hwaddr plen = 1 << qsize; 1301 void *eq; 1302 1303 /* 1304 * Validate the guest EQ. We should also check that the queue 1305 * has been zeroed by the OS. 1306 */ 1307 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1308 MEMTXATTRS_UNSPECIFIED); 1309 if (plen != 1 << qsize) { 1310 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1311 HWADDR_PRIx "\n", qpage); 1312 return H_P4; 1313 } 1314 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1315 } 1316 1317 /* "target" should have been validated above */ 1318 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1319 g_assert_not_reached(); 1320 } 1321 1322 /* 1323 * Ensure the priority and target are correctly set (they will not 1324 * be right after allocation) 1325 */ 1326 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1327 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1328 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1329 1330 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1331 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1332 } else { 1333 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1334 } 1335 1336 /* 1337 * The generation bit for the END starts at 1 and The END page 1338 * offset counter starts at 0. 1339 */ 1340 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1341 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1342 end.w0 |= cpu_to_be32(END_W0_VALID); 1343 1344 /* 1345 * TODO: issue syncs required to ensure all in-flight interrupts 1346 * are complete on the old END 1347 */ 1348 1349 out: 1350 if (kvm_irqchip_in_kernel()) { 1351 Error *local_err = NULL; 1352 1353 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1354 if (local_err) { 1355 error_report_err(local_err); 1356 return H_HARDWARE; 1357 } 1358 } 1359 1360 /* Update END */ 1361 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1362 return H_SUCCESS; 1363 } 1364 1365 /* 1366 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1367 * target and priority. 1368 * 1369 * Parameters: 1370 * Input: 1371 * - R4: "flags" 1372 * Bits 0-62: Reserved 1373 * Bit 63: Debug: Return debug data 1374 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1375 * "ibm,ppc-interrupt-gserver#s" 1376 * - R6: "priority" is a valid priority not in 1377 * "ibm,plat-res-int-priorities" 1378 * 1379 * Output: 1380 * - R4: "flags": 1381 * Bits 0-61: Reserved 1382 * Bit 62: The value of Event Queue Generation Number (g) per 1383 * the XIVE spec if "Debug" = 1 1384 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1385 * - R5: The logical real address of the start of the EQ 1386 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1387 * - R7: The value of Event Queue Offset Counter per XIVE spec 1388 * if "Debug" = 1, else 0 1389 * 1390 */ 1391 1392 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1393 1394 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1395 SpaprMachineState *spapr, 1396 target_ulong opcode, 1397 target_ulong *args) 1398 { 1399 SpaprXive *xive = spapr->xive; 1400 target_ulong flags = args[0]; 1401 target_ulong target = args[1]; 1402 target_ulong priority = args[2]; 1403 XiveEND *end; 1404 uint8_t end_blk; 1405 uint32_t end_idx; 1406 1407 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1408 return H_FUNCTION; 1409 } 1410 1411 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1412 return H_PARAMETER; 1413 } 1414 1415 /* 1416 * H_STATE should be returned if a H_INT_RESET is in progress. 1417 * This is not needed when running the emulation under QEMU 1418 */ 1419 1420 if (spapr_xive_priority_is_reserved(priority)) { 1421 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1422 " is reserved\n", priority); 1423 return H_P3; 1424 } 1425 1426 /* 1427 * Validate that "target" is part of the list of threads allocated 1428 * to the partition. For that, find the END corresponding to the 1429 * target. 1430 */ 1431 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1432 return H_P2; 1433 } 1434 1435 assert(end_idx < xive->nr_ends); 1436 end = &xive->endt[end_idx]; 1437 1438 args[0] = 0; 1439 if (xive_end_is_notify(end)) { 1440 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1441 } 1442 1443 if (xive_end_is_enqueue(end)) { 1444 args[1] = xive_end_qaddr(end); 1445 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1446 } else { 1447 args[1] = 0; 1448 args[2] = 0; 1449 } 1450 1451 if (kvm_irqchip_in_kernel()) { 1452 Error *local_err = NULL; 1453 1454 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1455 if (local_err) { 1456 error_report_err(local_err); 1457 return H_HARDWARE; 1458 } 1459 } 1460 1461 /* TODO: do we need any locking on the END ? */ 1462 if (flags & SPAPR_XIVE_END_DEBUG) { 1463 /* Load the event queue generation number into the return flags */ 1464 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1465 1466 /* Load R7 with the event queue offset counter */ 1467 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1468 } else { 1469 args[3] = 0; 1470 } 1471 1472 return H_SUCCESS; 1473 } 1474 1475 /* 1476 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1477 * reporting cache line pair for the calling thread. The reporting 1478 * cache lines will contain the OS interrupt context when the OS 1479 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1480 * interrupt. The reporting cache lines can be reset by inputting -1 1481 * in "reportingLine". Issuing the CI store byte without reporting 1482 * cache lines registered will result in the data not being accessible 1483 * to the OS. 1484 * 1485 * Parameters: 1486 * Input: 1487 * - R4: "flags" 1488 * Bits 0-63: Reserved 1489 * - R5: "reportingLine": The logical real address of the reporting cache 1490 * line pair 1491 * 1492 * Output: 1493 * - None 1494 */ 1495 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1496 SpaprMachineState *spapr, 1497 target_ulong opcode, 1498 target_ulong *args) 1499 { 1500 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1501 return H_FUNCTION; 1502 } 1503 1504 /* 1505 * H_STATE should be returned if a H_INT_RESET is in progress. 1506 * This is not needed when running the emulation under QEMU 1507 */ 1508 1509 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1510 return H_FUNCTION; 1511 } 1512 1513 /* 1514 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1515 * real address of the reporting cache line pair set for the input 1516 * "target". If no reporting cache line pair has been set, -1 is 1517 * returned. 1518 * 1519 * Parameters: 1520 * Input: 1521 * - R4: "flags" 1522 * Bits 0-63: Reserved 1523 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1524 * "ibm,ppc-interrupt-gserver#s" 1525 * - R6: "reportingLine": The logical real address of the reporting 1526 * cache line pair 1527 * 1528 * Output: 1529 * - R4: The logical real address of the reporting line if set, else -1 1530 */ 1531 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1532 SpaprMachineState *spapr, 1533 target_ulong opcode, 1534 target_ulong *args) 1535 { 1536 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1537 return H_FUNCTION; 1538 } 1539 1540 /* 1541 * H_STATE should be returned if a H_INT_RESET is in progress. 1542 * This is not needed when running the emulation under QEMU 1543 */ 1544 1545 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1546 return H_FUNCTION; 1547 } 1548 1549 /* 1550 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1551 * page for the input "lisn". This hcall is only supported for LISNs 1552 * that have the ESB hcall flag set to 1 when returned from hcall() 1553 * H_INT_GET_SOURCE_INFO. 1554 * 1555 * Parameters: 1556 * Input: 1557 * - R4: "flags" 1558 * Bits 0-62: Reserved 1559 * bit 63: Store: Store=1, store operation, else load operation 1560 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1561 * "ibm,xive-lisn-ranges" properties, or as returned by the 1562 * ibm,query-interrupt-source-number RTAS call, or as 1563 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1564 * - R6: "esbOffset" is the offset into the ESB page for the load or 1565 * store operation 1566 * - R7: "storeData" is the data to write for a store operation 1567 * 1568 * Output: 1569 * - R4: The value of the load if load operation, else -1 1570 */ 1571 1572 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1573 1574 static target_ulong h_int_esb(PowerPCCPU *cpu, 1575 SpaprMachineState *spapr, 1576 target_ulong opcode, 1577 target_ulong *args) 1578 { 1579 SpaprXive *xive = spapr->xive; 1580 XiveEAS eas; 1581 target_ulong flags = args[0]; 1582 target_ulong lisn = args[1]; 1583 target_ulong offset = args[2]; 1584 target_ulong data = args[3]; 1585 hwaddr mmio_addr; 1586 XiveSource *xsrc = &xive->source; 1587 1588 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1589 return H_FUNCTION; 1590 } 1591 1592 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1593 return H_PARAMETER; 1594 } 1595 1596 if (lisn >= xive->nr_irqs) { 1597 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1598 lisn); 1599 return H_P2; 1600 } 1601 1602 eas = xive->eat[lisn]; 1603 if (!xive_eas_is_valid(&eas)) { 1604 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1605 lisn); 1606 return H_P2; 1607 } 1608 1609 if (offset > (1ull << xsrc->esb_shift)) { 1610 return H_P3; 1611 } 1612 1613 if (kvm_irqchip_in_kernel()) { 1614 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1615 flags & SPAPR_XIVE_ESB_STORE); 1616 } else { 1617 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1618 1619 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1620 (flags & SPAPR_XIVE_ESB_STORE))) { 1621 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1622 HWADDR_PRIx "\n", mmio_addr); 1623 return H_HARDWARE; 1624 } 1625 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1626 } 1627 return H_SUCCESS; 1628 } 1629 1630 /* 1631 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1632 * ensure any in flight events for the input lisn are in the event 1633 * queue. 1634 * 1635 * Parameters: 1636 * Input: 1637 * - R4: "flags" 1638 * Bits 0-63: Reserved 1639 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1640 * "ibm,xive-lisn-ranges" properties, or as returned by the 1641 * ibm,query-interrupt-source-number RTAS call, or as 1642 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1643 * 1644 * Output: 1645 * - None 1646 */ 1647 static target_ulong h_int_sync(PowerPCCPU *cpu, 1648 SpaprMachineState *spapr, 1649 target_ulong opcode, 1650 target_ulong *args) 1651 { 1652 SpaprXive *xive = spapr->xive; 1653 XiveEAS eas; 1654 target_ulong flags = args[0]; 1655 target_ulong lisn = args[1]; 1656 1657 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1658 return H_FUNCTION; 1659 } 1660 1661 if (flags) { 1662 return H_PARAMETER; 1663 } 1664 1665 if (lisn >= xive->nr_irqs) { 1666 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1667 lisn); 1668 return H_P2; 1669 } 1670 1671 eas = xive->eat[lisn]; 1672 if (!xive_eas_is_valid(&eas)) { 1673 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1674 lisn); 1675 return H_P2; 1676 } 1677 1678 /* 1679 * H_STATE should be returned if a H_INT_RESET is in progress. 1680 * This is not needed when running the emulation under QEMU 1681 */ 1682 1683 /* 1684 * This is not real hardware. Nothing to be done unless when 1685 * under KVM 1686 */ 1687 1688 if (kvm_irqchip_in_kernel()) { 1689 Error *local_err = NULL; 1690 1691 kvmppc_xive_sync_source(xive, lisn, &local_err); 1692 if (local_err) { 1693 error_report_err(local_err); 1694 return H_HARDWARE; 1695 } 1696 } 1697 return H_SUCCESS; 1698 } 1699 1700 /* 1701 * The H_INT_RESET hcall() is used to reset all of the partition's 1702 * interrupt exploitation structures to their initial state. This 1703 * means losing all previously set interrupt state set via 1704 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1705 * 1706 * Parameters: 1707 * Input: 1708 * - R4: "flags" 1709 * Bits 0-63: Reserved 1710 * 1711 * Output: 1712 * - None 1713 */ 1714 static target_ulong h_int_reset(PowerPCCPU *cpu, 1715 SpaprMachineState *spapr, 1716 target_ulong opcode, 1717 target_ulong *args) 1718 { 1719 SpaprXive *xive = spapr->xive; 1720 target_ulong flags = args[0]; 1721 1722 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1723 return H_FUNCTION; 1724 } 1725 1726 if (flags) { 1727 return H_PARAMETER; 1728 } 1729 1730 device_reset(DEVICE(xive)); 1731 1732 if (kvm_irqchip_in_kernel()) { 1733 Error *local_err = NULL; 1734 1735 kvmppc_xive_reset(xive, &local_err); 1736 if (local_err) { 1737 error_report_err(local_err); 1738 return H_HARDWARE; 1739 } 1740 } 1741 return H_SUCCESS; 1742 } 1743 1744 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1745 { 1746 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1747 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1748 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1749 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1750 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1751 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1752 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1753 h_int_set_os_reporting_line); 1754 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1755 h_int_get_os_reporting_line); 1756 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1757 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1758 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1759 } 1760