1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 } 150 151 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 152 { 153 XiveSource *xsrc = &xive->source; 154 int i; 155 156 if (kvm_irqchip_in_kernel()) { 157 Error *local_err = NULL; 158 159 kvmppc_xive_synchronize_state(xive, &local_err); 160 if (local_err) { 161 error_report_err(local_err); 162 return; 163 } 164 } 165 166 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 167 168 for (i = 0; i < xive->nr_irqs; i++) { 169 uint8_t pq = xive_source_esb_get(xsrc, i); 170 XiveEAS *eas = &xive->eat[i]; 171 172 if (!xive_eas_is_valid(eas)) { 173 continue; 174 } 175 176 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 177 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 178 pq & XIVE_ESB_VAL_P ? 'P' : '-', 179 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 180 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 181 xive_eas_is_masked(eas) ? "M" : " ", 182 (int) xive_get_field64(EAS_END_DATA, eas->w)); 183 184 if (!xive_eas_is_masked(eas)) { 185 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 186 XiveEND *end; 187 188 assert(end_idx < xive->nr_ends); 189 end = &xive->endt[end_idx]; 190 191 if (xive_end_is_valid(end)) { 192 spapr_xive_end_pic_print_info(xive, end, mon); 193 } 194 } 195 monitor_printf(mon, "\n"); 196 } 197 } 198 199 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 200 { 201 memory_region_set_enabled(&xive->source.esb_mmio, enable); 202 memory_region_set_enabled(&xive->tm_mmio, enable); 203 204 /* Disable the END ESBs until a guest OS makes use of them */ 205 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 206 } 207 208 static void spapr_xive_tm_write(void *opaque, hwaddr offset, 209 uint64_t value, unsigned size) 210 { 211 XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; 212 213 xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); 214 } 215 216 static uint64_t spapr_xive_tm_read(void *opaque, hwaddr offset, unsigned size) 217 { 218 XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; 219 220 return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); 221 } 222 223 const MemoryRegionOps spapr_xive_tm_ops = { 224 .read = spapr_xive_tm_read, 225 .write = spapr_xive_tm_write, 226 .endianness = DEVICE_BIG_ENDIAN, 227 .valid = { 228 .min_access_size = 1, 229 .max_access_size = 8, 230 }, 231 .impl = { 232 .min_access_size = 1, 233 .max_access_size = 8, 234 }, 235 }; 236 237 static void spapr_xive_end_reset(XiveEND *end) 238 { 239 memset(end, 0, sizeof(*end)); 240 241 /* switch off the escalation and notification ESBs */ 242 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 243 } 244 245 static void spapr_xive_reset(void *dev) 246 { 247 SpaprXive *xive = SPAPR_XIVE(dev); 248 int i; 249 250 /* 251 * The XiveSource has its own reset handler, which mask off all 252 * IRQs (!P|Q) 253 */ 254 255 /* Mask all valid EASs in the IRQ number space. */ 256 for (i = 0; i < xive->nr_irqs; i++) { 257 XiveEAS *eas = &xive->eat[i]; 258 if (xive_eas_is_valid(eas)) { 259 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 260 } else { 261 eas->w = 0; 262 } 263 } 264 265 /* Clear all ENDs */ 266 for (i = 0; i < xive->nr_ends; i++) { 267 spapr_xive_end_reset(&xive->endt[i]); 268 } 269 } 270 271 static void spapr_xive_instance_init(Object *obj) 272 { 273 SpaprXive *xive = SPAPR_XIVE(obj); 274 275 object_initialize_child(obj, "source", &xive->source, TYPE_XIVE_SOURCE); 276 277 object_initialize_child(obj, "end_source", &xive->end_source, 278 TYPE_XIVE_END_SOURCE); 279 280 /* Not connected to the KVM XIVE device */ 281 xive->fd = -1; 282 } 283 284 static void spapr_xive_realize(DeviceState *dev, Error **errp) 285 { 286 SpaprXive *xive = SPAPR_XIVE(dev); 287 SpaprXiveClass *sxc = SPAPR_XIVE_GET_CLASS(xive); 288 XiveSource *xsrc = &xive->source; 289 XiveENDSource *end_xsrc = &xive->end_source; 290 Error *local_err = NULL; 291 292 sxc->parent_realize(dev, &local_err); 293 if (local_err) { 294 error_propagate(errp, local_err); 295 return; 296 } 297 298 if (!xive->nr_irqs) { 299 error_setg(errp, "Number of interrupt needs to be greater 0"); 300 return; 301 } 302 303 if (!xive->nr_ends) { 304 error_setg(errp, "Number of interrupt needs to be greater 0"); 305 return; 306 } 307 308 /* 309 * Initialize the internal sources, for IPIs and virtual devices. 310 */ 311 object_property_set_int(OBJECT(xsrc), "nr-irqs", xive->nr_irqs, 312 &error_fatal); 313 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), &error_abort); 314 if (!qdev_realize(DEVICE(xsrc), NULL, errp)) { 315 return; 316 } 317 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 318 319 /* 320 * Initialize the END ESB source 321 */ 322 object_property_set_int(OBJECT(end_xsrc), "nr-ends", xive->nr_irqs, 323 &error_fatal); 324 object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 325 &error_abort); 326 if (!qdev_realize(DEVICE(end_xsrc), NULL, errp)) { 327 return; 328 } 329 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 330 331 /* Set the mapping address of the END ESB pages after the source ESBs */ 332 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 333 334 /* 335 * Allocate the routing tables 336 */ 337 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 338 xive->endt = g_new0(XiveEND, xive->nr_ends); 339 340 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 341 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 342 343 qemu_register_reset(spapr_xive_reset, dev); 344 345 /* TIMA initialization */ 346 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &spapr_xive_tm_ops, 347 xive, "xive.tima", 4ull << TM_SHIFT); 348 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 349 350 /* 351 * Map all regions. These will be enabled or disabled at reset and 352 * can also be overridden by KVM memory regions if active 353 */ 354 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 355 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 356 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 357 } 358 359 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 360 uint32_t eas_idx, XiveEAS *eas) 361 { 362 SpaprXive *xive = SPAPR_XIVE(xrtr); 363 364 if (eas_idx >= xive->nr_irqs) { 365 return -1; 366 } 367 368 *eas = xive->eat[eas_idx]; 369 return 0; 370 } 371 372 static int spapr_xive_get_end(XiveRouter *xrtr, 373 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 374 { 375 SpaprXive *xive = SPAPR_XIVE(xrtr); 376 377 if (end_idx >= xive->nr_ends) { 378 return -1; 379 } 380 381 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 382 return 0; 383 } 384 385 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 386 uint32_t end_idx, XiveEND *end, 387 uint8_t word_number) 388 { 389 SpaprXive *xive = SPAPR_XIVE(xrtr); 390 391 if (end_idx >= xive->nr_ends) { 392 return -1; 393 } 394 395 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 396 return 0; 397 } 398 399 static int spapr_xive_get_nvt(XiveRouter *xrtr, 400 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 401 { 402 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 403 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 404 405 if (!cpu) { 406 /* TODO: should we assert() if we can find a NVT ? */ 407 return -1; 408 } 409 410 /* 411 * sPAPR does not maintain a NVT table. Return that the NVT is 412 * valid if we have found a matching CPU 413 */ 414 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 415 return 0; 416 } 417 418 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 419 uint32_t nvt_idx, XiveNVT *nvt, 420 uint8_t word_number) 421 { 422 /* 423 * We don't need to write back to the NVTs because the sPAPR 424 * machine should never hit a non-scheduled NVT. It should never 425 * get called. 426 */ 427 g_assert_not_reached(); 428 } 429 430 static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, 431 uint8_t nvt_blk, uint32_t nvt_idx, 432 bool cam_ignore, uint8_t priority, 433 uint32_t logic_serv, XiveTCTXMatch *match) 434 { 435 CPUState *cs; 436 int count = 0; 437 438 CPU_FOREACH(cs) { 439 PowerPCCPU *cpu = POWERPC_CPU(cs); 440 XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx; 441 int ring; 442 443 /* 444 * Skip partially initialized vCPUs. This can happen when 445 * vCPUs are hotplugged. 446 */ 447 if (!tctx) { 448 continue; 449 } 450 451 /* 452 * Check the thread context CAM lines and record matches. 453 */ 454 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx, 455 cam_ignore, logic_serv); 456 /* 457 * Save the matching thread interrupt context and follow on to 458 * check for duplicates which are invalid. 459 */ 460 if (ring != -1) { 461 if (match->tctx) { 462 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread " 463 "context NVT %x/%x\n", nvt_blk, nvt_idx); 464 return -1; 465 } 466 467 match->ring = ring; 468 match->tctx = tctx; 469 count++; 470 } 471 } 472 473 return count; 474 } 475 476 static uint8_t spapr_xive_get_block_id(XiveRouter *xrtr) 477 { 478 return SPAPR_XIVE_BLOCK_ID; 479 } 480 481 static const VMStateDescription vmstate_spapr_xive_end = { 482 .name = TYPE_SPAPR_XIVE "/end", 483 .version_id = 1, 484 .minimum_version_id = 1, 485 .fields = (VMStateField []) { 486 VMSTATE_UINT32(w0, XiveEND), 487 VMSTATE_UINT32(w1, XiveEND), 488 VMSTATE_UINT32(w2, XiveEND), 489 VMSTATE_UINT32(w3, XiveEND), 490 VMSTATE_UINT32(w4, XiveEND), 491 VMSTATE_UINT32(w5, XiveEND), 492 VMSTATE_UINT32(w6, XiveEND), 493 VMSTATE_UINT32(w7, XiveEND), 494 VMSTATE_END_OF_LIST() 495 }, 496 }; 497 498 static const VMStateDescription vmstate_spapr_xive_eas = { 499 .name = TYPE_SPAPR_XIVE "/eas", 500 .version_id = 1, 501 .minimum_version_id = 1, 502 .fields = (VMStateField []) { 503 VMSTATE_UINT64(w, XiveEAS), 504 VMSTATE_END_OF_LIST() 505 }, 506 }; 507 508 static int vmstate_spapr_xive_pre_save(void *opaque) 509 { 510 if (kvm_irqchip_in_kernel()) { 511 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 512 } 513 514 return 0; 515 } 516 517 /* 518 * Called by the sPAPR IRQ backend 'post_load' method at the machine 519 * level. 520 */ 521 static int spapr_xive_post_load(SpaprInterruptController *intc, int version_id) 522 { 523 if (kvm_irqchip_in_kernel()) { 524 return kvmppc_xive_post_load(SPAPR_XIVE(intc), version_id); 525 } 526 527 return 0; 528 } 529 530 static const VMStateDescription vmstate_spapr_xive = { 531 .name = TYPE_SPAPR_XIVE, 532 .version_id = 1, 533 .minimum_version_id = 1, 534 .pre_save = vmstate_spapr_xive_pre_save, 535 .post_load = NULL, /* handled at the machine level */ 536 .fields = (VMStateField[]) { 537 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 538 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 539 vmstate_spapr_xive_eas, XiveEAS), 540 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 541 vmstate_spapr_xive_end, XiveEND), 542 VMSTATE_END_OF_LIST() 543 }, 544 }; 545 546 static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, 547 bool lsi, Error **errp) 548 { 549 SpaprXive *xive = SPAPR_XIVE(intc); 550 XiveSource *xsrc = &xive->source; 551 552 assert(lisn < xive->nr_irqs); 553 554 if (xive_eas_is_valid(&xive->eat[lisn])) { 555 error_setg(errp, "IRQ %d is not free", lisn); 556 return -EBUSY; 557 } 558 559 /* 560 * Set default values when allocating an IRQ number 561 */ 562 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); 563 if (lsi) { 564 xive_source_irq_set_lsi(xsrc, lisn); 565 } 566 567 if (kvm_irqchip_in_kernel()) { 568 return kvmppc_xive_source_reset_one(xsrc, lisn, errp); 569 } 570 571 return 0; 572 } 573 574 static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) 575 { 576 SpaprXive *xive = SPAPR_XIVE(intc); 577 assert(lisn < xive->nr_irqs); 578 579 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 580 } 581 582 static Property spapr_xive_properties[] = { 583 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 584 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 585 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 586 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 587 DEFINE_PROP_END_OF_LIST(), 588 }; 589 590 static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 591 PowerPCCPU *cpu, Error **errp) 592 { 593 SpaprXive *xive = SPAPR_XIVE(intc); 594 Object *obj; 595 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 596 597 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(xive), errp); 598 if (!obj) { 599 return -1; 600 } 601 602 spapr_cpu->tctx = XIVE_TCTX(obj); 603 return 0; 604 } 605 606 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t os_cam) 607 { 608 uint32_t qw1w2 = cpu_to_be32(TM_QW1W2_VO | os_cam); 609 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 610 } 611 612 static void spapr_xive_cpu_intc_reset(SpaprInterruptController *intc, 613 PowerPCCPU *cpu) 614 { 615 XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx; 616 uint8_t nvt_blk; 617 uint32_t nvt_idx; 618 619 xive_tctx_reset(tctx); 620 621 /* 622 * When a Virtual Processor is scheduled to run on a HW thread, 623 * the hypervisor pushes its identifier in the OS CAM line. 624 * Emulate the same behavior under QEMU. 625 */ 626 spapr_xive_cpu_to_nvt(cpu, &nvt_blk, &nvt_idx); 627 628 xive_tctx_set_os_cam(tctx, xive_nvt_cam_line(nvt_blk, nvt_idx)); 629 } 630 631 static void spapr_xive_cpu_intc_destroy(SpaprInterruptController *intc, 632 PowerPCCPU *cpu) 633 { 634 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 635 636 xive_tctx_destroy(spapr_cpu->tctx); 637 spapr_cpu->tctx = NULL; 638 } 639 640 static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val) 641 { 642 SpaprXive *xive = SPAPR_XIVE(intc); 643 644 if (kvm_irqchip_in_kernel()) { 645 kvmppc_xive_source_set_irq(&xive->source, irq, val); 646 } else { 647 xive_source_set_irq(&xive->source, irq, val); 648 } 649 } 650 651 static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor *mon) 652 { 653 SpaprXive *xive = SPAPR_XIVE(intc); 654 CPUState *cs; 655 656 CPU_FOREACH(cs) { 657 PowerPCCPU *cpu = POWERPC_CPU(cs); 658 659 xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); 660 } 661 662 spapr_xive_pic_print_info(xive, mon); 663 } 664 665 static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers, 666 void *fdt, uint32_t phandle) 667 { 668 SpaprXive *xive = SPAPR_XIVE(intc); 669 int node; 670 uint64_t timas[2 * 2]; 671 /* Interrupt number ranges for the IPIs */ 672 uint32_t lisn_ranges[] = { 673 cpu_to_be32(SPAPR_IRQ_IPI), 674 cpu_to_be32(SPAPR_IRQ_IPI + nr_servers), 675 }; 676 /* 677 * EQ size - the sizes of pages supported by the system 4K, 64K, 678 * 2M, 16M. We only advertise 64K for the moment. 679 */ 680 uint32_t eq_sizes[] = { 681 cpu_to_be32(16), /* 64K */ 682 }; 683 /* 684 * The following array is in sync with the reserved priorities 685 * defined by the 'spapr_xive_priority_is_reserved' routine. 686 */ 687 uint32_t plat_res_int_priorities[] = { 688 cpu_to_be32(7), /* start */ 689 cpu_to_be32(0xf8), /* count */ 690 }; 691 692 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 693 timas[0] = cpu_to_be64(xive->tm_base + 694 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 695 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 696 timas[2] = cpu_to_be64(xive->tm_base + 697 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 698 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 699 700 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 701 702 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 703 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 704 705 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 706 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 707 sizeof(eq_sizes))); 708 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 709 sizeof(lisn_ranges))); 710 711 /* For Linux to link the LSIs to the interrupt controller. */ 712 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 713 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 714 715 /* For SLOF */ 716 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 717 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 718 719 /* 720 * The "ibm,plat-res-int-priorities" property defines the priority 721 * ranges reserved by the hypervisor 722 */ 723 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 724 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 725 } 726 727 static int spapr_xive_activate(SpaprInterruptController *intc, 728 uint32_t nr_servers, Error **errp) 729 { 730 SpaprXive *xive = SPAPR_XIVE(intc); 731 732 if (kvm_enabled()) { 733 int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, nr_servers, 734 errp); 735 if (rc < 0) { 736 return rc; 737 } 738 } 739 740 /* Activate the XIVE MMIOs */ 741 spapr_xive_mmio_set_enabled(xive, true); 742 743 return 0; 744 } 745 746 static void spapr_xive_deactivate(SpaprInterruptController *intc) 747 { 748 SpaprXive *xive = SPAPR_XIVE(intc); 749 750 spapr_xive_mmio_set_enabled(xive, false); 751 752 if (kvm_irqchip_in_kernel()) { 753 kvmppc_xive_disconnect(intc); 754 } 755 } 756 757 static void spapr_xive_class_init(ObjectClass *klass, void *data) 758 { 759 DeviceClass *dc = DEVICE_CLASS(klass); 760 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 761 SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); 762 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 763 SpaprXiveClass *sxc = SPAPR_XIVE_CLASS(klass); 764 765 dc->desc = "sPAPR XIVE Interrupt Controller"; 766 device_class_set_props(dc, spapr_xive_properties); 767 device_class_set_parent_realize(dc, spapr_xive_realize, 768 &sxc->parent_realize); 769 dc->vmsd = &vmstate_spapr_xive; 770 771 xrc->get_eas = spapr_xive_get_eas; 772 xrc->get_end = spapr_xive_get_end; 773 xrc->write_end = spapr_xive_write_end; 774 xrc->get_nvt = spapr_xive_get_nvt; 775 xrc->write_nvt = spapr_xive_write_nvt; 776 xrc->get_block_id = spapr_xive_get_block_id; 777 778 sicc->activate = spapr_xive_activate; 779 sicc->deactivate = spapr_xive_deactivate; 780 sicc->cpu_intc_create = spapr_xive_cpu_intc_create; 781 sicc->cpu_intc_reset = spapr_xive_cpu_intc_reset; 782 sicc->cpu_intc_destroy = spapr_xive_cpu_intc_destroy; 783 sicc->claim_irq = spapr_xive_claim_irq; 784 sicc->free_irq = spapr_xive_free_irq; 785 sicc->set_irq = spapr_xive_set_irq; 786 sicc->print_info = spapr_xive_print_info; 787 sicc->dt = spapr_xive_dt; 788 sicc->post_load = spapr_xive_post_load; 789 790 xpc->match_nvt = spapr_xive_match_nvt; 791 } 792 793 static const TypeInfo spapr_xive_info = { 794 .name = TYPE_SPAPR_XIVE, 795 .parent = TYPE_XIVE_ROUTER, 796 .instance_init = spapr_xive_instance_init, 797 .instance_size = sizeof(SpaprXive), 798 .class_init = spapr_xive_class_init, 799 .class_size = sizeof(SpaprXiveClass), 800 .interfaces = (InterfaceInfo[]) { 801 { TYPE_SPAPR_INTC }, 802 { } 803 }, 804 }; 805 806 static void spapr_xive_register_types(void) 807 { 808 type_register_static(&spapr_xive_info); 809 } 810 811 type_init(spapr_xive_register_types) 812 813 /* 814 * XIVE hcalls 815 * 816 * The terminology used by the XIVE hcalls is the following : 817 * 818 * TARGET vCPU number 819 * EQ Event Queue assigned by OS to receive event data 820 * ESB page for source interrupt management 821 * LISN Logical Interrupt Source Number identifying a source in the 822 * machine 823 * EISN Effective Interrupt Source Number used by guest OS to 824 * identify source in the guest 825 * 826 * The EAS, END, NVT structures are not exposed. 827 */ 828 829 /* 830 * Linux hosts under OPAL reserve priority 7 for their own escalation 831 * interrupts (DD2.X POWER9). So we only allow the guest to use 832 * priorities [0..6]. 833 */ 834 static bool spapr_xive_priority_is_reserved(uint8_t priority) 835 { 836 switch (priority) { 837 case 0 ... 6: 838 return false; 839 case 7: /* OPAL escalation queue */ 840 default: 841 return true; 842 } 843 } 844 845 /* 846 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 847 * real address of the MMIO page through which the Event State Buffer 848 * entry associated with the value of the "lisn" parameter is managed. 849 * 850 * Parameters: 851 * Input 852 * - R4: "flags" 853 * Bits 0-63 reserved 854 * - R5: "lisn" is per "interrupts", "interrupt-map", or 855 * "ibm,xive-lisn-ranges" properties, or as returned by the 856 * ibm,query-interrupt-source-number RTAS call, or as returned 857 * by the H_ALLOCATE_VAS_WINDOW hcall 858 * 859 * Output 860 * - R4: "flags" 861 * Bits 0-59: Reserved 862 * Bit 60: H_INT_ESB must be used for Event State Buffer 863 * management 864 * Bit 61: 1 == LSI 0 == MSI 865 * Bit 62: the full function page supports trigger 866 * Bit 63: Store EOI Supported 867 * - R5: Logical Real address of full function Event State Buffer 868 * management page, -1 if H_INT_ESB hcall flag is set to 1. 869 * - R6: Logical Real Address of trigger only Event State Buffer 870 * management page or -1. 871 * - R7: Power of 2 page size for the ESB management pages returned in 872 * R5 and R6. 873 */ 874 875 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 876 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 877 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 878 on same page */ 879 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 880 881 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 882 SpaprMachineState *spapr, 883 target_ulong opcode, 884 target_ulong *args) 885 { 886 SpaprXive *xive = spapr->xive; 887 XiveSource *xsrc = &xive->source; 888 target_ulong flags = args[0]; 889 target_ulong lisn = args[1]; 890 891 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 892 return H_FUNCTION; 893 } 894 895 if (flags) { 896 return H_PARAMETER; 897 } 898 899 if (lisn >= xive->nr_irqs) { 900 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 901 lisn); 902 return H_P2; 903 } 904 905 if (!xive_eas_is_valid(&xive->eat[lisn])) { 906 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 907 lisn); 908 return H_P2; 909 } 910 911 /* 912 * All sources are emulated under the main XIVE object and share 913 * the same characteristics. 914 */ 915 args[0] = 0; 916 if (!xive_source_esb_has_2page(xsrc)) { 917 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 918 } 919 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 920 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 921 } 922 923 /* 924 * Force the use of the H_INT_ESB hcall in case of an LSI 925 * interrupt. This is necessary under KVM to re-trigger the 926 * interrupt if the level is still asserted 927 */ 928 if (xive_source_irq_is_lsi(xsrc, lisn)) { 929 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 930 } 931 932 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 933 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 934 } else { 935 args[1] = -1; 936 } 937 938 if (xive_source_esb_has_2page(xsrc) && 939 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 940 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 941 } else { 942 args[2] = -1; 943 } 944 945 if (xive_source_esb_has_2page(xsrc)) { 946 args[3] = xsrc->esb_shift - 1; 947 } else { 948 args[3] = xsrc->esb_shift; 949 } 950 951 return H_SUCCESS; 952 } 953 954 /* 955 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 956 * Interrupt Source to a target. The Logical Interrupt Source is 957 * designated with the "lisn" parameter and the target is designated 958 * with the "target" and "priority" parameters. Upon return from the 959 * hcall(), no additional interrupts will be directed to the old EQ. 960 * 961 * Parameters: 962 * Input: 963 * - R4: "flags" 964 * Bits 0-61: Reserved 965 * Bit 62: set the "eisn" in the EAS 966 * Bit 63: masks the interrupt source in the hardware interrupt 967 * control structure. An interrupt masked by this mechanism will 968 * be dropped, but it's source state bits will still be 969 * set. There is no race-free way of unmasking and restoring the 970 * source. Thus this should only be used in interrupts that are 971 * also masked at the source, and only in cases where the 972 * interrupt is not meant to be used for a large amount of time 973 * because no valid target exists for it for example 974 * - R5: "lisn" is per "interrupts", "interrupt-map", or 975 * "ibm,xive-lisn-ranges" properties, or as returned by the 976 * ibm,query-interrupt-source-number RTAS call, or as returned by 977 * the H_ALLOCATE_VAS_WINDOW hcall 978 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 979 * "ibm,ppc-interrupt-gserver#s" 980 * - R7: "priority" is a valid priority not in 981 * "ibm,plat-res-int-priorities" 982 * - R8: "eisn" is the guest EISN associated with the "lisn" 983 * 984 * Output: 985 * - None 986 */ 987 988 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 989 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 990 991 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 992 SpaprMachineState *spapr, 993 target_ulong opcode, 994 target_ulong *args) 995 { 996 SpaprXive *xive = spapr->xive; 997 XiveEAS eas, new_eas; 998 target_ulong flags = args[0]; 999 target_ulong lisn = args[1]; 1000 target_ulong target = args[2]; 1001 target_ulong priority = args[3]; 1002 target_ulong eisn = args[4]; 1003 uint8_t end_blk; 1004 uint32_t end_idx; 1005 1006 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1007 return H_FUNCTION; 1008 } 1009 1010 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 1011 return H_PARAMETER; 1012 } 1013 1014 if (lisn >= xive->nr_irqs) { 1015 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1016 lisn); 1017 return H_P2; 1018 } 1019 1020 eas = xive->eat[lisn]; 1021 if (!xive_eas_is_valid(&eas)) { 1022 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1023 lisn); 1024 return H_P2; 1025 } 1026 1027 /* priority 0xff is used to reset the EAS */ 1028 if (priority == 0xff) { 1029 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 1030 goto out; 1031 } 1032 1033 if (flags & SPAPR_XIVE_SRC_MASK) { 1034 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 1035 } else { 1036 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 1037 } 1038 1039 if (spapr_xive_priority_is_reserved(priority)) { 1040 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1041 " is reserved\n", priority); 1042 return H_P4; 1043 } 1044 1045 /* 1046 * Validate that "target" is part of the list of threads allocated 1047 * to the partition. For that, find the END corresponding to the 1048 * target. 1049 */ 1050 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1051 return H_P3; 1052 } 1053 1054 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 1055 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 1056 1057 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 1058 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 1059 } 1060 1061 if (kvm_irqchip_in_kernel()) { 1062 Error *local_err = NULL; 1063 1064 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 1065 if (local_err) { 1066 error_report_err(local_err); 1067 return H_HARDWARE; 1068 } 1069 } 1070 1071 out: 1072 xive->eat[lisn] = new_eas; 1073 return H_SUCCESS; 1074 } 1075 1076 /* 1077 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 1078 * target/priority pair is assigned to the specified Logical Interrupt 1079 * Source. 1080 * 1081 * Parameters: 1082 * Input: 1083 * - R4: "flags" 1084 * Bits 0-63 Reserved 1085 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1086 * "ibm,xive-lisn-ranges" properties, or as returned by the 1087 * ibm,query-interrupt-source-number RTAS call, or as 1088 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1089 * 1090 * Output: 1091 * - R4: Target to which the specified Logical Interrupt Source is 1092 * assigned 1093 * - R5: Priority to which the specified Logical Interrupt Source is 1094 * assigned 1095 * - R6: EISN for the specified Logical Interrupt Source (this will be 1096 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 1097 */ 1098 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 1099 SpaprMachineState *spapr, 1100 target_ulong opcode, 1101 target_ulong *args) 1102 { 1103 SpaprXive *xive = spapr->xive; 1104 target_ulong flags = args[0]; 1105 target_ulong lisn = args[1]; 1106 XiveEAS eas; 1107 XiveEND *end; 1108 uint8_t nvt_blk; 1109 uint32_t end_idx, nvt_idx; 1110 1111 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1112 return H_FUNCTION; 1113 } 1114 1115 if (flags) { 1116 return H_PARAMETER; 1117 } 1118 1119 if (lisn >= xive->nr_irqs) { 1120 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1121 lisn); 1122 return H_P2; 1123 } 1124 1125 eas = xive->eat[lisn]; 1126 if (!xive_eas_is_valid(&eas)) { 1127 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1128 lisn); 1129 return H_P2; 1130 } 1131 1132 /* EAS_END_BLOCK is unused on sPAPR */ 1133 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 1134 1135 assert(end_idx < xive->nr_ends); 1136 end = &xive->endt[end_idx]; 1137 1138 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1139 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1140 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 1141 1142 if (xive_eas_is_masked(&eas)) { 1143 args[1] = 0xff; 1144 } else { 1145 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1146 } 1147 1148 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 1149 1150 return H_SUCCESS; 1151 } 1152 1153 /* 1154 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 1155 * address of the notification management page associated with the 1156 * specified target and priority. 1157 * 1158 * Parameters: 1159 * Input: 1160 * - R4: "flags" 1161 * Bits 0-63 Reserved 1162 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1163 * "ibm,ppc-interrupt-gserver#s" 1164 * - R6: "priority" is a valid priority not in 1165 * "ibm,plat-res-int-priorities" 1166 * 1167 * Output: 1168 * - R4: Logical real address of notification page 1169 * - R5: Power of 2 page size of the notification page 1170 */ 1171 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 1172 SpaprMachineState *spapr, 1173 target_ulong opcode, 1174 target_ulong *args) 1175 { 1176 SpaprXive *xive = spapr->xive; 1177 XiveENDSource *end_xsrc = &xive->end_source; 1178 target_ulong flags = args[0]; 1179 target_ulong target = args[1]; 1180 target_ulong priority = args[2]; 1181 XiveEND *end; 1182 uint8_t end_blk; 1183 uint32_t end_idx; 1184 1185 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1186 return H_FUNCTION; 1187 } 1188 1189 if (flags) { 1190 return H_PARAMETER; 1191 } 1192 1193 /* 1194 * H_STATE should be returned if a H_INT_RESET is in progress. 1195 * This is not needed when running the emulation under QEMU 1196 */ 1197 1198 if (spapr_xive_priority_is_reserved(priority)) { 1199 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1200 " is reserved\n", priority); 1201 return H_P3; 1202 } 1203 1204 /* 1205 * Validate that "target" is part of the list of threads allocated 1206 * to the partition. For that, find the END corresponding to the 1207 * target. 1208 */ 1209 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1210 return H_P2; 1211 } 1212 1213 assert(end_idx < xive->nr_ends); 1214 end = &xive->endt[end_idx]; 1215 1216 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 1217 if (xive_end_is_enqueue(end)) { 1218 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1219 } else { 1220 args[1] = 0; 1221 } 1222 1223 return H_SUCCESS; 1224 } 1225 1226 /* 1227 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 1228 * a given "target" and "priority". It is also used to set the 1229 * notification config associated with the EQ. An EQ size of 0 is 1230 * used to reset the EQ config for a given target and priority. If 1231 * resetting the EQ config, the END associated with the given "target" 1232 * and "priority" will be changed to disable queueing. 1233 * 1234 * Upon return from the hcall(), no additional interrupts will be 1235 * directed to the old EQ (if one was set). The old EQ (if one was 1236 * set) should be investigated for interrupts that occurred prior to 1237 * or during the hcall(). 1238 * 1239 * Parameters: 1240 * Input: 1241 * - R4: "flags" 1242 * Bits 0-62: Reserved 1243 * Bit 63: Unconditional Notify (n) per the XIVE spec 1244 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1245 * "ibm,ppc-interrupt-gserver#s" 1246 * - R6: "priority" is a valid priority not in 1247 * "ibm,plat-res-int-priorities" 1248 * - R7: "eventQueue": The logical real address of the start of the EQ 1249 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1250 * 1251 * Output: 1252 * - None 1253 */ 1254 1255 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1256 1257 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1258 SpaprMachineState *spapr, 1259 target_ulong opcode, 1260 target_ulong *args) 1261 { 1262 SpaprXive *xive = spapr->xive; 1263 target_ulong flags = args[0]; 1264 target_ulong target = args[1]; 1265 target_ulong priority = args[2]; 1266 target_ulong qpage = args[3]; 1267 target_ulong qsize = args[4]; 1268 XiveEND end; 1269 uint8_t end_blk, nvt_blk; 1270 uint32_t end_idx, nvt_idx; 1271 1272 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1273 return H_FUNCTION; 1274 } 1275 1276 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1277 return H_PARAMETER; 1278 } 1279 1280 /* 1281 * H_STATE should be returned if a H_INT_RESET is in progress. 1282 * This is not needed when running the emulation under QEMU 1283 */ 1284 1285 if (spapr_xive_priority_is_reserved(priority)) { 1286 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1287 " is reserved\n", priority); 1288 return H_P3; 1289 } 1290 1291 /* 1292 * Validate that "target" is part of the list of threads allocated 1293 * to the partition. For that, find the END corresponding to the 1294 * target. 1295 */ 1296 1297 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1298 return H_P2; 1299 } 1300 1301 assert(end_idx < xive->nr_ends); 1302 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1303 1304 switch (qsize) { 1305 case 12: 1306 case 16: 1307 case 21: 1308 case 24: 1309 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1310 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1311 " is not naturally aligned with %" HWADDR_PRIx "\n", 1312 qpage, (hwaddr)1 << qsize); 1313 return H_P4; 1314 } 1315 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1316 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1317 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1318 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1319 break; 1320 case 0: 1321 /* reset queue and disable queueing */ 1322 spapr_xive_end_reset(&end); 1323 goto out; 1324 1325 default: 1326 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1327 qsize); 1328 return H_P5; 1329 } 1330 1331 if (qsize) { 1332 hwaddr plen = 1 << qsize; 1333 void *eq; 1334 1335 /* 1336 * Validate the guest EQ. We should also check that the queue 1337 * has been zeroed by the OS. 1338 */ 1339 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1340 MEMTXATTRS_UNSPECIFIED); 1341 if (plen != 1 << qsize) { 1342 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1343 HWADDR_PRIx "\n", qpage); 1344 return H_P4; 1345 } 1346 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1347 } 1348 1349 /* "target" should have been validated above */ 1350 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1351 g_assert_not_reached(); 1352 } 1353 1354 /* 1355 * Ensure the priority and target are correctly set (they will not 1356 * be right after allocation) 1357 */ 1358 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1359 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1360 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1361 1362 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1363 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1364 } else { 1365 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1366 } 1367 1368 /* 1369 * The generation bit for the END starts at 1 and The END page 1370 * offset counter starts at 0. 1371 */ 1372 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1373 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1374 end.w0 |= cpu_to_be32(END_W0_VALID); 1375 1376 /* 1377 * TODO: issue syncs required to ensure all in-flight interrupts 1378 * are complete on the old END 1379 */ 1380 1381 out: 1382 if (kvm_irqchip_in_kernel()) { 1383 Error *local_err = NULL; 1384 1385 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1386 if (local_err) { 1387 error_report_err(local_err); 1388 return H_HARDWARE; 1389 } 1390 } 1391 1392 /* Update END */ 1393 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1394 return H_SUCCESS; 1395 } 1396 1397 /* 1398 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1399 * target and priority. 1400 * 1401 * Parameters: 1402 * Input: 1403 * - R4: "flags" 1404 * Bits 0-62: Reserved 1405 * Bit 63: Debug: Return debug data 1406 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1407 * "ibm,ppc-interrupt-gserver#s" 1408 * - R6: "priority" is a valid priority not in 1409 * "ibm,plat-res-int-priorities" 1410 * 1411 * Output: 1412 * - R4: "flags": 1413 * Bits 0-61: Reserved 1414 * Bit 62: The value of Event Queue Generation Number (g) per 1415 * the XIVE spec if "Debug" = 1 1416 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1417 * - R5: The logical real address of the start of the EQ 1418 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1419 * - R7: The value of Event Queue Offset Counter per XIVE spec 1420 * if "Debug" = 1, else 0 1421 * 1422 */ 1423 1424 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1425 1426 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1427 SpaprMachineState *spapr, 1428 target_ulong opcode, 1429 target_ulong *args) 1430 { 1431 SpaprXive *xive = spapr->xive; 1432 target_ulong flags = args[0]; 1433 target_ulong target = args[1]; 1434 target_ulong priority = args[2]; 1435 XiveEND *end; 1436 uint8_t end_blk; 1437 uint32_t end_idx; 1438 1439 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1440 return H_FUNCTION; 1441 } 1442 1443 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1444 return H_PARAMETER; 1445 } 1446 1447 /* 1448 * H_STATE should be returned if a H_INT_RESET is in progress. 1449 * This is not needed when running the emulation under QEMU 1450 */ 1451 1452 if (spapr_xive_priority_is_reserved(priority)) { 1453 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1454 " is reserved\n", priority); 1455 return H_P3; 1456 } 1457 1458 /* 1459 * Validate that "target" is part of the list of threads allocated 1460 * to the partition. For that, find the END corresponding to the 1461 * target. 1462 */ 1463 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1464 return H_P2; 1465 } 1466 1467 assert(end_idx < xive->nr_ends); 1468 end = &xive->endt[end_idx]; 1469 1470 args[0] = 0; 1471 if (xive_end_is_notify(end)) { 1472 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1473 } 1474 1475 if (xive_end_is_enqueue(end)) { 1476 args[1] = xive_end_qaddr(end); 1477 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1478 } else { 1479 args[1] = 0; 1480 args[2] = 0; 1481 } 1482 1483 if (kvm_irqchip_in_kernel()) { 1484 Error *local_err = NULL; 1485 1486 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1487 if (local_err) { 1488 error_report_err(local_err); 1489 return H_HARDWARE; 1490 } 1491 } 1492 1493 /* TODO: do we need any locking on the END ? */ 1494 if (flags & SPAPR_XIVE_END_DEBUG) { 1495 /* Load the event queue generation number into the return flags */ 1496 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1497 1498 /* Load R7 with the event queue offset counter */ 1499 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1500 } else { 1501 args[3] = 0; 1502 } 1503 1504 return H_SUCCESS; 1505 } 1506 1507 /* 1508 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1509 * reporting cache line pair for the calling thread. The reporting 1510 * cache lines will contain the OS interrupt context when the OS 1511 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1512 * interrupt. The reporting cache lines can be reset by inputting -1 1513 * in "reportingLine". Issuing the CI store byte without reporting 1514 * cache lines registered will result in the data not being accessible 1515 * to the OS. 1516 * 1517 * Parameters: 1518 * Input: 1519 * - R4: "flags" 1520 * Bits 0-63: Reserved 1521 * - R5: "reportingLine": The logical real address of the reporting cache 1522 * line pair 1523 * 1524 * Output: 1525 * - None 1526 */ 1527 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1528 SpaprMachineState *spapr, 1529 target_ulong opcode, 1530 target_ulong *args) 1531 { 1532 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1533 return H_FUNCTION; 1534 } 1535 1536 /* 1537 * H_STATE should be returned if a H_INT_RESET is in progress. 1538 * This is not needed when running the emulation under QEMU 1539 */ 1540 1541 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1542 return H_FUNCTION; 1543 } 1544 1545 /* 1546 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1547 * real address of the reporting cache line pair set for the input 1548 * "target". If no reporting cache line pair has been set, -1 is 1549 * returned. 1550 * 1551 * Parameters: 1552 * Input: 1553 * - R4: "flags" 1554 * Bits 0-63: Reserved 1555 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1556 * "ibm,ppc-interrupt-gserver#s" 1557 * - R6: "reportingLine": The logical real address of the reporting 1558 * cache line pair 1559 * 1560 * Output: 1561 * - R4: The logical real address of the reporting line if set, else -1 1562 */ 1563 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1564 SpaprMachineState *spapr, 1565 target_ulong opcode, 1566 target_ulong *args) 1567 { 1568 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1569 return H_FUNCTION; 1570 } 1571 1572 /* 1573 * H_STATE should be returned if a H_INT_RESET is in progress. 1574 * This is not needed when running the emulation under QEMU 1575 */ 1576 1577 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1578 return H_FUNCTION; 1579 } 1580 1581 /* 1582 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1583 * page for the input "lisn". This hcall is only supported for LISNs 1584 * that have the ESB hcall flag set to 1 when returned from hcall() 1585 * H_INT_GET_SOURCE_INFO. 1586 * 1587 * Parameters: 1588 * Input: 1589 * - R4: "flags" 1590 * Bits 0-62: Reserved 1591 * bit 63: Store: Store=1, store operation, else load operation 1592 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1593 * "ibm,xive-lisn-ranges" properties, or as returned by the 1594 * ibm,query-interrupt-source-number RTAS call, or as 1595 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1596 * - R6: "esbOffset" is the offset into the ESB page for the load or 1597 * store operation 1598 * - R7: "storeData" is the data to write for a store operation 1599 * 1600 * Output: 1601 * - R4: The value of the load if load operation, else -1 1602 */ 1603 1604 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1605 1606 static target_ulong h_int_esb(PowerPCCPU *cpu, 1607 SpaprMachineState *spapr, 1608 target_ulong opcode, 1609 target_ulong *args) 1610 { 1611 SpaprXive *xive = spapr->xive; 1612 XiveEAS eas; 1613 target_ulong flags = args[0]; 1614 target_ulong lisn = args[1]; 1615 target_ulong offset = args[2]; 1616 target_ulong data = args[3]; 1617 hwaddr mmio_addr; 1618 XiveSource *xsrc = &xive->source; 1619 1620 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1621 return H_FUNCTION; 1622 } 1623 1624 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1625 return H_PARAMETER; 1626 } 1627 1628 if (lisn >= xive->nr_irqs) { 1629 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1630 lisn); 1631 return H_P2; 1632 } 1633 1634 eas = xive->eat[lisn]; 1635 if (!xive_eas_is_valid(&eas)) { 1636 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1637 lisn); 1638 return H_P2; 1639 } 1640 1641 if (offset > (1ull << xsrc->esb_shift)) { 1642 return H_P3; 1643 } 1644 1645 if (kvm_irqchip_in_kernel()) { 1646 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1647 flags & SPAPR_XIVE_ESB_STORE); 1648 } else { 1649 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1650 1651 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1652 (flags & SPAPR_XIVE_ESB_STORE))) { 1653 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1654 HWADDR_PRIx "\n", mmio_addr); 1655 return H_HARDWARE; 1656 } 1657 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1658 } 1659 return H_SUCCESS; 1660 } 1661 1662 /* 1663 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1664 * ensure any in flight events for the input lisn are in the event 1665 * queue. 1666 * 1667 * Parameters: 1668 * Input: 1669 * - R4: "flags" 1670 * Bits 0-63: Reserved 1671 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1672 * "ibm,xive-lisn-ranges" properties, or as returned by the 1673 * ibm,query-interrupt-source-number RTAS call, or as 1674 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1675 * 1676 * Output: 1677 * - None 1678 */ 1679 static target_ulong h_int_sync(PowerPCCPU *cpu, 1680 SpaprMachineState *spapr, 1681 target_ulong opcode, 1682 target_ulong *args) 1683 { 1684 SpaprXive *xive = spapr->xive; 1685 XiveEAS eas; 1686 target_ulong flags = args[0]; 1687 target_ulong lisn = args[1]; 1688 1689 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1690 return H_FUNCTION; 1691 } 1692 1693 if (flags) { 1694 return H_PARAMETER; 1695 } 1696 1697 if (lisn >= xive->nr_irqs) { 1698 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1699 lisn); 1700 return H_P2; 1701 } 1702 1703 eas = xive->eat[lisn]; 1704 if (!xive_eas_is_valid(&eas)) { 1705 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1706 lisn); 1707 return H_P2; 1708 } 1709 1710 /* 1711 * H_STATE should be returned if a H_INT_RESET is in progress. 1712 * This is not needed when running the emulation under QEMU 1713 */ 1714 1715 /* 1716 * This is not real hardware. Nothing to be done unless when 1717 * under KVM 1718 */ 1719 1720 if (kvm_irqchip_in_kernel()) { 1721 Error *local_err = NULL; 1722 1723 kvmppc_xive_sync_source(xive, lisn, &local_err); 1724 if (local_err) { 1725 error_report_err(local_err); 1726 return H_HARDWARE; 1727 } 1728 } 1729 return H_SUCCESS; 1730 } 1731 1732 /* 1733 * The H_INT_RESET hcall() is used to reset all of the partition's 1734 * interrupt exploitation structures to their initial state. This 1735 * means losing all previously set interrupt state set via 1736 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1737 * 1738 * Parameters: 1739 * Input: 1740 * - R4: "flags" 1741 * Bits 0-63: Reserved 1742 * 1743 * Output: 1744 * - None 1745 */ 1746 static target_ulong h_int_reset(PowerPCCPU *cpu, 1747 SpaprMachineState *spapr, 1748 target_ulong opcode, 1749 target_ulong *args) 1750 { 1751 SpaprXive *xive = spapr->xive; 1752 target_ulong flags = args[0]; 1753 1754 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1755 return H_FUNCTION; 1756 } 1757 1758 if (flags) { 1759 return H_PARAMETER; 1760 } 1761 1762 device_legacy_reset(DEVICE(xive)); 1763 1764 if (kvm_irqchip_in_kernel()) { 1765 Error *local_err = NULL; 1766 1767 kvmppc_xive_reset(xive, &local_err); 1768 if (local_err) { 1769 error_report_err(local_err); 1770 return H_HARDWARE; 1771 } 1772 } 1773 return H_SUCCESS; 1774 } 1775 1776 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1777 { 1778 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1779 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1780 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1781 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1782 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1783 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1784 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1785 h_int_set_os_reporting_line); 1786 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1787 h_int_get_os_reporting_line); 1788 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1789 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1790 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1791 } 1792