1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 } 150 151 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 152 { 153 XiveSource *xsrc = &xive->source; 154 int i; 155 156 if (kvm_irqchip_in_kernel()) { 157 Error *local_err = NULL; 158 159 kvmppc_xive_synchronize_state(xive, &local_err); 160 if (local_err) { 161 error_report_err(local_err); 162 return; 163 } 164 } 165 166 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 167 168 for (i = 0; i < xive->nr_irqs; i++) { 169 uint8_t pq = xive_source_esb_get(xsrc, i); 170 XiveEAS *eas = &xive->eat[i]; 171 172 if (!xive_eas_is_valid(eas)) { 173 continue; 174 } 175 176 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 177 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 178 pq & XIVE_ESB_VAL_P ? 'P' : '-', 179 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 180 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 181 xive_eas_is_masked(eas) ? "M" : " ", 182 (int) xive_get_field64(EAS_END_DATA, eas->w)); 183 184 if (!xive_eas_is_masked(eas)) { 185 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 186 XiveEND *end; 187 188 assert(end_idx < xive->nr_ends); 189 end = &xive->endt[end_idx]; 190 191 if (xive_end_is_valid(end)) { 192 spapr_xive_end_pic_print_info(xive, end, mon); 193 } 194 } 195 monitor_printf(mon, "\n"); 196 } 197 } 198 199 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 200 { 201 memory_region_set_enabled(&xive->source.esb_mmio, enable); 202 memory_region_set_enabled(&xive->tm_mmio, enable); 203 204 /* Disable the END ESBs until a guest OS makes use of them */ 205 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 206 } 207 208 static void spapr_xive_end_reset(XiveEND *end) 209 { 210 memset(end, 0, sizeof(*end)); 211 212 /* switch off the escalation and notification ESBs */ 213 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 214 } 215 216 static void spapr_xive_reset(void *dev) 217 { 218 SpaprXive *xive = SPAPR_XIVE(dev); 219 int i; 220 221 /* 222 * The XiveSource has its own reset handler, which mask off all 223 * IRQs (!P|Q) 224 */ 225 226 /* Mask all valid EASs in the IRQ number space. */ 227 for (i = 0; i < xive->nr_irqs; i++) { 228 XiveEAS *eas = &xive->eat[i]; 229 if (xive_eas_is_valid(eas)) { 230 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 231 } else { 232 eas->w = 0; 233 } 234 } 235 236 /* Clear all ENDs */ 237 for (i = 0; i < xive->nr_ends; i++) { 238 spapr_xive_end_reset(&xive->endt[i]); 239 } 240 } 241 242 static void spapr_xive_instance_init(Object *obj) 243 { 244 SpaprXive *xive = SPAPR_XIVE(obj); 245 246 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 247 TYPE_XIVE_SOURCE, &error_abort, NULL); 248 249 object_initialize_child(obj, "end_source", &xive->end_source, 250 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 251 &error_abort, NULL); 252 253 /* Not connected to the KVM XIVE device */ 254 xive->fd = -1; 255 } 256 257 static void spapr_xive_realize(DeviceState *dev, Error **errp) 258 { 259 SpaprXive *xive = SPAPR_XIVE(dev); 260 XiveSource *xsrc = &xive->source; 261 XiveENDSource *end_xsrc = &xive->end_source; 262 Error *local_err = NULL; 263 264 if (!xive->nr_irqs) { 265 error_setg(errp, "Number of interrupt needs to be greater 0"); 266 return; 267 } 268 269 if (!xive->nr_ends) { 270 error_setg(errp, "Number of interrupt needs to be greater 0"); 271 return; 272 } 273 274 /* 275 * Initialize the internal sources, for IPIs and virtual devices. 276 */ 277 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 278 &error_fatal); 279 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 280 &error_fatal); 281 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 282 if (local_err) { 283 error_propagate(errp, local_err); 284 return; 285 } 286 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 287 288 /* 289 * Initialize the END ESB source 290 */ 291 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 292 &error_fatal); 293 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 294 &error_fatal); 295 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 296 if (local_err) { 297 error_propagate(errp, local_err); 298 return; 299 } 300 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 301 302 /* Set the mapping address of the END ESB pages after the source ESBs */ 303 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 304 305 /* 306 * Allocate the routing tables 307 */ 308 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 309 xive->endt = g_new0(XiveEND, xive->nr_ends); 310 311 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 312 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 313 314 qemu_register_reset(spapr_xive_reset, dev); 315 316 /* TIMA initialization */ 317 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 318 "xive.tima", 4ull << TM_SHIFT); 319 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 320 321 /* 322 * Map all regions. These will be enabled or disabled at reset and 323 * can also be overridden by KVM memory regions if active 324 */ 325 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 326 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 327 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 328 } 329 330 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 331 uint32_t eas_idx, XiveEAS *eas) 332 { 333 SpaprXive *xive = SPAPR_XIVE(xrtr); 334 335 if (eas_idx >= xive->nr_irqs) { 336 return -1; 337 } 338 339 *eas = xive->eat[eas_idx]; 340 return 0; 341 } 342 343 static int spapr_xive_get_end(XiveRouter *xrtr, 344 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 345 { 346 SpaprXive *xive = SPAPR_XIVE(xrtr); 347 348 if (end_idx >= xive->nr_ends) { 349 return -1; 350 } 351 352 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 353 return 0; 354 } 355 356 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 357 uint32_t end_idx, XiveEND *end, 358 uint8_t word_number) 359 { 360 SpaprXive *xive = SPAPR_XIVE(xrtr); 361 362 if (end_idx >= xive->nr_ends) { 363 return -1; 364 } 365 366 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 367 return 0; 368 } 369 370 static int spapr_xive_get_nvt(XiveRouter *xrtr, 371 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 372 { 373 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 374 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 375 376 if (!cpu) { 377 /* TODO: should we assert() if we can find a NVT ? */ 378 return -1; 379 } 380 381 /* 382 * sPAPR does not maintain a NVT table. Return that the NVT is 383 * valid if we have found a matching CPU 384 */ 385 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 386 return 0; 387 } 388 389 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 390 uint32_t nvt_idx, XiveNVT *nvt, 391 uint8_t word_number) 392 { 393 /* 394 * We don't need to write back to the NVTs because the sPAPR 395 * machine should never hit a non-scheduled NVT. It should never 396 * get called. 397 */ 398 g_assert_not_reached(); 399 } 400 401 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 402 { 403 PowerPCCPU *cpu = POWERPC_CPU(cs); 404 405 return spapr_cpu_state(cpu)->tctx; 406 } 407 408 static const VMStateDescription vmstate_spapr_xive_end = { 409 .name = TYPE_SPAPR_XIVE "/end", 410 .version_id = 1, 411 .minimum_version_id = 1, 412 .fields = (VMStateField []) { 413 VMSTATE_UINT32(w0, XiveEND), 414 VMSTATE_UINT32(w1, XiveEND), 415 VMSTATE_UINT32(w2, XiveEND), 416 VMSTATE_UINT32(w3, XiveEND), 417 VMSTATE_UINT32(w4, XiveEND), 418 VMSTATE_UINT32(w5, XiveEND), 419 VMSTATE_UINT32(w6, XiveEND), 420 VMSTATE_UINT32(w7, XiveEND), 421 VMSTATE_END_OF_LIST() 422 }, 423 }; 424 425 static const VMStateDescription vmstate_spapr_xive_eas = { 426 .name = TYPE_SPAPR_XIVE "/eas", 427 .version_id = 1, 428 .minimum_version_id = 1, 429 .fields = (VMStateField []) { 430 VMSTATE_UINT64(w, XiveEAS), 431 VMSTATE_END_OF_LIST() 432 }, 433 }; 434 435 static int vmstate_spapr_xive_pre_save(void *opaque) 436 { 437 if (kvm_irqchip_in_kernel()) { 438 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 439 } 440 441 return 0; 442 } 443 444 /* 445 * Called by the sPAPR IRQ backend 'post_load' method at the machine 446 * level. 447 */ 448 static int spapr_xive_post_load(SpaprInterruptController *intc, int version_id) 449 { 450 if (kvm_irqchip_in_kernel()) { 451 return kvmppc_xive_post_load(SPAPR_XIVE(intc), version_id); 452 } 453 454 return 0; 455 } 456 457 static const VMStateDescription vmstate_spapr_xive = { 458 .name = TYPE_SPAPR_XIVE, 459 .version_id = 1, 460 .minimum_version_id = 1, 461 .pre_save = vmstate_spapr_xive_pre_save, 462 .post_load = NULL, /* handled at the machine level */ 463 .fields = (VMStateField[]) { 464 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 465 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 466 vmstate_spapr_xive_eas, XiveEAS), 467 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 468 vmstate_spapr_xive_end, XiveEND), 469 VMSTATE_END_OF_LIST() 470 }, 471 }; 472 473 static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, 474 bool lsi, Error **errp) 475 { 476 SpaprXive *xive = SPAPR_XIVE(intc); 477 XiveSource *xsrc = &xive->source; 478 479 assert(lisn < xive->nr_irqs); 480 481 if (xive_eas_is_valid(&xive->eat[lisn])) { 482 error_setg(errp, "IRQ %d is not free", lisn); 483 return -EBUSY; 484 } 485 486 /* 487 * Set default values when allocating an IRQ number 488 */ 489 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); 490 if (lsi) { 491 xive_source_irq_set_lsi(xsrc, lisn); 492 } 493 494 if (kvm_irqchip_in_kernel()) { 495 return kvmppc_xive_source_reset_one(xsrc, lisn, errp); 496 } 497 498 return 0; 499 } 500 501 static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) 502 { 503 SpaprXive *xive = SPAPR_XIVE(intc); 504 assert(lisn < xive->nr_irqs); 505 506 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 507 } 508 509 static Property spapr_xive_properties[] = { 510 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 511 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 512 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 513 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 514 DEFINE_PROP_END_OF_LIST(), 515 }; 516 517 static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 518 PowerPCCPU *cpu, Error **errp) 519 { 520 SpaprXive *xive = SPAPR_XIVE(intc); 521 Object *obj; 522 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 523 524 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp); 525 if (!obj) { 526 return -1; 527 } 528 529 spapr_cpu->tctx = XIVE_TCTX(obj); 530 return 0; 531 } 532 533 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t os_cam) 534 { 535 uint32_t qw1w2 = cpu_to_be32(TM_QW1W2_VO | os_cam); 536 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 537 } 538 539 static void spapr_xive_cpu_intc_reset(SpaprInterruptController *intc, 540 PowerPCCPU *cpu) 541 { 542 XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx; 543 uint8_t nvt_blk; 544 uint32_t nvt_idx; 545 546 xive_tctx_reset(tctx); 547 548 /* 549 * When a Virtual Processor is scheduled to run on a HW thread, 550 * the hypervisor pushes its identifier in the OS CAM line. 551 * Emulate the same behavior under QEMU. 552 */ 553 spapr_xive_cpu_to_nvt(cpu, &nvt_blk, &nvt_idx); 554 555 xive_tctx_set_os_cam(tctx, xive_nvt_cam_line(nvt_blk, nvt_idx)); 556 } 557 558 static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val) 559 { 560 SpaprXive *xive = SPAPR_XIVE(intc); 561 562 if (kvm_irqchip_in_kernel()) { 563 kvmppc_xive_source_set_irq(&xive->source, irq, val); 564 } else { 565 xive_source_set_irq(&xive->source, irq, val); 566 } 567 } 568 569 static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor *mon) 570 { 571 SpaprXive *xive = SPAPR_XIVE(intc); 572 CPUState *cs; 573 574 CPU_FOREACH(cs) { 575 PowerPCCPU *cpu = POWERPC_CPU(cs); 576 577 xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); 578 } 579 580 spapr_xive_pic_print_info(xive, mon); 581 } 582 583 static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers, 584 void *fdt, uint32_t phandle) 585 { 586 SpaprXive *xive = SPAPR_XIVE(intc); 587 int node; 588 uint64_t timas[2 * 2]; 589 /* Interrupt number ranges for the IPIs */ 590 uint32_t lisn_ranges[] = { 591 cpu_to_be32(0), 592 cpu_to_be32(nr_servers), 593 }; 594 /* 595 * EQ size - the sizes of pages supported by the system 4K, 64K, 596 * 2M, 16M. We only advertise 64K for the moment. 597 */ 598 uint32_t eq_sizes[] = { 599 cpu_to_be32(16), /* 64K */ 600 }; 601 /* 602 * The following array is in sync with the reserved priorities 603 * defined by the 'spapr_xive_priority_is_reserved' routine. 604 */ 605 uint32_t plat_res_int_priorities[] = { 606 cpu_to_be32(7), /* start */ 607 cpu_to_be32(0xf8), /* count */ 608 }; 609 610 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 611 timas[0] = cpu_to_be64(xive->tm_base + 612 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 613 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 614 timas[2] = cpu_to_be64(xive->tm_base + 615 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 616 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 617 618 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 619 620 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 621 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 622 623 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 624 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 625 sizeof(eq_sizes))); 626 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 627 sizeof(lisn_ranges))); 628 629 /* For Linux to link the LSIs to the interrupt controller. */ 630 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 631 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 632 633 /* For SLOF */ 634 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 635 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 636 637 /* 638 * The "ibm,plat-res-int-priorities" property defines the priority 639 * ranges reserved by the hypervisor 640 */ 641 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 642 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 643 } 644 645 static int spapr_xive_activate(SpaprInterruptController *intc, Error **errp) 646 { 647 SpaprXive *xive = SPAPR_XIVE(intc); 648 649 if (kvm_enabled()) { 650 int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, errp); 651 if (rc < 0) { 652 return rc; 653 } 654 } 655 656 /* Activate the XIVE MMIOs */ 657 spapr_xive_mmio_set_enabled(xive, true); 658 659 return 0; 660 } 661 662 static void spapr_xive_deactivate(SpaprInterruptController *intc) 663 { 664 SpaprXive *xive = SPAPR_XIVE(intc); 665 666 spapr_xive_mmio_set_enabled(xive, false); 667 668 if (kvm_irqchip_in_kernel()) { 669 kvmppc_xive_disconnect(intc); 670 } 671 } 672 673 static void spapr_xive_class_init(ObjectClass *klass, void *data) 674 { 675 DeviceClass *dc = DEVICE_CLASS(klass); 676 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 677 SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); 678 679 dc->desc = "sPAPR XIVE Interrupt Controller"; 680 dc->props = spapr_xive_properties; 681 dc->realize = spapr_xive_realize; 682 dc->vmsd = &vmstate_spapr_xive; 683 684 xrc->get_eas = spapr_xive_get_eas; 685 xrc->get_end = spapr_xive_get_end; 686 xrc->write_end = spapr_xive_write_end; 687 xrc->get_nvt = spapr_xive_get_nvt; 688 xrc->write_nvt = spapr_xive_write_nvt; 689 xrc->get_tctx = spapr_xive_get_tctx; 690 691 sicc->activate = spapr_xive_activate; 692 sicc->deactivate = spapr_xive_deactivate; 693 sicc->cpu_intc_create = spapr_xive_cpu_intc_create; 694 sicc->cpu_intc_reset = spapr_xive_cpu_intc_reset; 695 sicc->claim_irq = spapr_xive_claim_irq; 696 sicc->free_irq = spapr_xive_free_irq; 697 sicc->set_irq = spapr_xive_set_irq; 698 sicc->print_info = spapr_xive_print_info; 699 sicc->dt = spapr_xive_dt; 700 sicc->post_load = spapr_xive_post_load; 701 } 702 703 static const TypeInfo spapr_xive_info = { 704 .name = TYPE_SPAPR_XIVE, 705 .parent = TYPE_XIVE_ROUTER, 706 .instance_init = spapr_xive_instance_init, 707 .instance_size = sizeof(SpaprXive), 708 .class_init = spapr_xive_class_init, 709 .interfaces = (InterfaceInfo[]) { 710 { TYPE_SPAPR_INTC }, 711 { } 712 }, 713 }; 714 715 static void spapr_xive_register_types(void) 716 { 717 type_register_static(&spapr_xive_info); 718 } 719 720 type_init(spapr_xive_register_types) 721 722 /* 723 * XIVE hcalls 724 * 725 * The terminology used by the XIVE hcalls is the following : 726 * 727 * TARGET vCPU number 728 * EQ Event Queue assigned by OS to receive event data 729 * ESB page for source interrupt management 730 * LISN Logical Interrupt Source Number identifying a source in the 731 * machine 732 * EISN Effective Interrupt Source Number used by guest OS to 733 * identify source in the guest 734 * 735 * The EAS, END, NVT structures are not exposed. 736 */ 737 738 /* 739 * Linux hosts under OPAL reserve priority 7 for their own escalation 740 * interrupts (DD2.X POWER9). So we only allow the guest to use 741 * priorities [0..6]. 742 */ 743 static bool spapr_xive_priority_is_reserved(uint8_t priority) 744 { 745 switch (priority) { 746 case 0 ... 6: 747 return false; 748 case 7: /* OPAL escalation queue */ 749 default: 750 return true; 751 } 752 } 753 754 /* 755 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 756 * real address of the MMIO page through which the Event State Buffer 757 * entry associated with the value of the "lisn" parameter is managed. 758 * 759 * Parameters: 760 * Input 761 * - R4: "flags" 762 * Bits 0-63 reserved 763 * - R5: "lisn" is per "interrupts", "interrupt-map", or 764 * "ibm,xive-lisn-ranges" properties, or as returned by the 765 * ibm,query-interrupt-source-number RTAS call, or as returned 766 * by the H_ALLOCATE_VAS_WINDOW hcall 767 * 768 * Output 769 * - R4: "flags" 770 * Bits 0-59: Reserved 771 * Bit 60: H_INT_ESB must be used for Event State Buffer 772 * management 773 * Bit 61: 1 == LSI 0 == MSI 774 * Bit 62: the full function page supports trigger 775 * Bit 63: Store EOI Supported 776 * - R5: Logical Real address of full function Event State Buffer 777 * management page, -1 if H_INT_ESB hcall flag is set to 1. 778 * - R6: Logical Real Address of trigger only Event State Buffer 779 * management page or -1. 780 * - R7: Power of 2 page size for the ESB management pages returned in 781 * R5 and R6. 782 */ 783 784 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 785 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 786 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 787 on same page */ 788 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 789 790 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 791 SpaprMachineState *spapr, 792 target_ulong opcode, 793 target_ulong *args) 794 { 795 SpaprXive *xive = spapr->xive; 796 XiveSource *xsrc = &xive->source; 797 target_ulong flags = args[0]; 798 target_ulong lisn = args[1]; 799 800 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 801 return H_FUNCTION; 802 } 803 804 if (flags) { 805 return H_PARAMETER; 806 } 807 808 if (lisn >= xive->nr_irqs) { 809 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 810 lisn); 811 return H_P2; 812 } 813 814 if (!xive_eas_is_valid(&xive->eat[lisn])) { 815 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 816 lisn); 817 return H_P2; 818 } 819 820 /* 821 * All sources are emulated under the main XIVE object and share 822 * the same characteristics. 823 */ 824 args[0] = 0; 825 if (!xive_source_esb_has_2page(xsrc)) { 826 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 827 } 828 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 829 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 830 } 831 832 /* 833 * Force the use of the H_INT_ESB hcall in case of an LSI 834 * interrupt. This is necessary under KVM to re-trigger the 835 * interrupt if the level is still asserted 836 */ 837 if (xive_source_irq_is_lsi(xsrc, lisn)) { 838 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 839 } 840 841 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 842 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 843 } else { 844 args[1] = -1; 845 } 846 847 if (xive_source_esb_has_2page(xsrc) && 848 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 849 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 850 } else { 851 args[2] = -1; 852 } 853 854 if (xive_source_esb_has_2page(xsrc)) { 855 args[3] = xsrc->esb_shift - 1; 856 } else { 857 args[3] = xsrc->esb_shift; 858 } 859 860 return H_SUCCESS; 861 } 862 863 /* 864 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 865 * Interrupt Source to a target. The Logical Interrupt Source is 866 * designated with the "lisn" parameter and the target is designated 867 * with the "target" and "priority" parameters. Upon return from the 868 * hcall(), no additional interrupts will be directed to the old EQ. 869 * 870 * Parameters: 871 * Input: 872 * - R4: "flags" 873 * Bits 0-61: Reserved 874 * Bit 62: set the "eisn" in the EAS 875 * Bit 63: masks the interrupt source in the hardware interrupt 876 * control structure. An interrupt masked by this mechanism will 877 * be dropped, but it's source state bits will still be 878 * set. There is no race-free way of unmasking and restoring the 879 * source. Thus this should only be used in interrupts that are 880 * also masked at the source, and only in cases where the 881 * interrupt is not meant to be used for a large amount of time 882 * because no valid target exists for it for example 883 * - R5: "lisn" is per "interrupts", "interrupt-map", or 884 * "ibm,xive-lisn-ranges" properties, or as returned by the 885 * ibm,query-interrupt-source-number RTAS call, or as returned by 886 * the H_ALLOCATE_VAS_WINDOW hcall 887 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 888 * "ibm,ppc-interrupt-gserver#s" 889 * - R7: "priority" is a valid priority not in 890 * "ibm,plat-res-int-priorities" 891 * - R8: "eisn" is the guest EISN associated with the "lisn" 892 * 893 * Output: 894 * - None 895 */ 896 897 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 898 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 899 900 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 901 SpaprMachineState *spapr, 902 target_ulong opcode, 903 target_ulong *args) 904 { 905 SpaprXive *xive = spapr->xive; 906 XiveEAS eas, new_eas; 907 target_ulong flags = args[0]; 908 target_ulong lisn = args[1]; 909 target_ulong target = args[2]; 910 target_ulong priority = args[3]; 911 target_ulong eisn = args[4]; 912 uint8_t end_blk; 913 uint32_t end_idx; 914 915 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 916 return H_FUNCTION; 917 } 918 919 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 920 return H_PARAMETER; 921 } 922 923 if (lisn >= xive->nr_irqs) { 924 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 925 lisn); 926 return H_P2; 927 } 928 929 eas = xive->eat[lisn]; 930 if (!xive_eas_is_valid(&eas)) { 931 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 932 lisn); 933 return H_P2; 934 } 935 936 /* priority 0xff is used to reset the EAS */ 937 if (priority == 0xff) { 938 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 939 goto out; 940 } 941 942 if (flags & SPAPR_XIVE_SRC_MASK) { 943 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 944 } else { 945 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 946 } 947 948 if (spapr_xive_priority_is_reserved(priority)) { 949 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 950 " is reserved\n", priority); 951 return H_P4; 952 } 953 954 /* 955 * Validate that "target" is part of the list of threads allocated 956 * to the partition. For that, find the END corresponding to the 957 * target. 958 */ 959 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 960 return H_P3; 961 } 962 963 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 964 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 965 966 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 967 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 968 } 969 970 if (kvm_irqchip_in_kernel()) { 971 Error *local_err = NULL; 972 973 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 974 if (local_err) { 975 error_report_err(local_err); 976 return H_HARDWARE; 977 } 978 } 979 980 out: 981 xive->eat[lisn] = new_eas; 982 return H_SUCCESS; 983 } 984 985 /* 986 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 987 * target/priority pair is assigned to the specified Logical Interrupt 988 * Source. 989 * 990 * Parameters: 991 * Input: 992 * - R4: "flags" 993 * Bits 0-63 Reserved 994 * - R5: "lisn" is per "interrupts", "interrupt-map", or 995 * "ibm,xive-lisn-ranges" properties, or as returned by the 996 * ibm,query-interrupt-source-number RTAS call, or as 997 * returned by the H_ALLOCATE_VAS_WINDOW hcall 998 * 999 * Output: 1000 * - R4: Target to which the specified Logical Interrupt Source is 1001 * assigned 1002 * - R5: Priority to which the specified Logical Interrupt Source is 1003 * assigned 1004 * - R6: EISN for the specified Logical Interrupt Source (this will be 1005 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 1006 */ 1007 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 1008 SpaprMachineState *spapr, 1009 target_ulong opcode, 1010 target_ulong *args) 1011 { 1012 SpaprXive *xive = spapr->xive; 1013 target_ulong flags = args[0]; 1014 target_ulong lisn = args[1]; 1015 XiveEAS eas; 1016 XiveEND *end; 1017 uint8_t nvt_blk; 1018 uint32_t end_idx, nvt_idx; 1019 1020 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1021 return H_FUNCTION; 1022 } 1023 1024 if (flags) { 1025 return H_PARAMETER; 1026 } 1027 1028 if (lisn >= xive->nr_irqs) { 1029 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1030 lisn); 1031 return H_P2; 1032 } 1033 1034 eas = xive->eat[lisn]; 1035 if (!xive_eas_is_valid(&eas)) { 1036 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1037 lisn); 1038 return H_P2; 1039 } 1040 1041 /* EAS_END_BLOCK is unused on sPAPR */ 1042 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 1043 1044 assert(end_idx < xive->nr_ends); 1045 end = &xive->endt[end_idx]; 1046 1047 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1048 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1049 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 1050 1051 if (xive_eas_is_masked(&eas)) { 1052 args[1] = 0xff; 1053 } else { 1054 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1055 } 1056 1057 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 1058 1059 return H_SUCCESS; 1060 } 1061 1062 /* 1063 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 1064 * address of the notification management page associated with the 1065 * specified target and priority. 1066 * 1067 * Parameters: 1068 * Input: 1069 * - R4: "flags" 1070 * Bits 0-63 Reserved 1071 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1072 * "ibm,ppc-interrupt-gserver#s" 1073 * - R6: "priority" is a valid priority not in 1074 * "ibm,plat-res-int-priorities" 1075 * 1076 * Output: 1077 * - R4: Logical real address of notification page 1078 * - R5: Power of 2 page size of the notification page 1079 */ 1080 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 1081 SpaprMachineState *spapr, 1082 target_ulong opcode, 1083 target_ulong *args) 1084 { 1085 SpaprXive *xive = spapr->xive; 1086 XiveENDSource *end_xsrc = &xive->end_source; 1087 target_ulong flags = args[0]; 1088 target_ulong target = args[1]; 1089 target_ulong priority = args[2]; 1090 XiveEND *end; 1091 uint8_t end_blk; 1092 uint32_t end_idx; 1093 1094 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1095 return H_FUNCTION; 1096 } 1097 1098 if (flags) { 1099 return H_PARAMETER; 1100 } 1101 1102 /* 1103 * H_STATE should be returned if a H_INT_RESET is in progress. 1104 * This is not needed when running the emulation under QEMU 1105 */ 1106 1107 if (spapr_xive_priority_is_reserved(priority)) { 1108 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1109 " is reserved\n", priority); 1110 return H_P3; 1111 } 1112 1113 /* 1114 * Validate that "target" is part of the list of threads allocated 1115 * to the partition. For that, find the END corresponding to the 1116 * target. 1117 */ 1118 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1119 return H_P2; 1120 } 1121 1122 assert(end_idx < xive->nr_ends); 1123 end = &xive->endt[end_idx]; 1124 1125 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 1126 if (xive_end_is_enqueue(end)) { 1127 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1128 } else { 1129 args[1] = 0; 1130 } 1131 1132 return H_SUCCESS; 1133 } 1134 1135 /* 1136 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 1137 * a given "target" and "priority". It is also used to set the 1138 * notification config associated with the EQ. An EQ size of 0 is 1139 * used to reset the EQ config for a given target and priority. If 1140 * resetting the EQ config, the END associated with the given "target" 1141 * and "priority" will be changed to disable queueing. 1142 * 1143 * Upon return from the hcall(), no additional interrupts will be 1144 * directed to the old EQ (if one was set). The old EQ (if one was 1145 * set) should be investigated for interrupts that occurred prior to 1146 * or during the hcall(). 1147 * 1148 * Parameters: 1149 * Input: 1150 * - R4: "flags" 1151 * Bits 0-62: Reserved 1152 * Bit 63: Unconditional Notify (n) per the XIVE spec 1153 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1154 * "ibm,ppc-interrupt-gserver#s" 1155 * - R6: "priority" is a valid priority not in 1156 * "ibm,plat-res-int-priorities" 1157 * - R7: "eventQueue": The logical real address of the start of the EQ 1158 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1159 * 1160 * Output: 1161 * - None 1162 */ 1163 1164 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1165 1166 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1167 SpaprMachineState *spapr, 1168 target_ulong opcode, 1169 target_ulong *args) 1170 { 1171 SpaprXive *xive = spapr->xive; 1172 target_ulong flags = args[0]; 1173 target_ulong target = args[1]; 1174 target_ulong priority = args[2]; 1175 target_ulong qpage = args[3]; 1176 target_ulong qsize = args[4]; 1177 XiveEND end; 1178 uint8_t end_blk, nvt_blk; 1179 uint32_t end_idx, nvt_idx; 1180 1181 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1182 return H_FUNCTION; 1183 } 1184 1185 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1186 return H_PARAMETER; 1187 } 1188 1189 /* 1190 * H_STATE should be returned if a H_INT_RESET is in progress. 1191 * This is not needed when running the emulation under QEMU 1192 */ 1193 1194 if (spapr_xive_priority_is_reserved(priority)) { 1195 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1196 " is reserved\n", priority); 1197 return H_P3; 1198 } 1199 1200 /* 1201 * Validate that "target" is part of the list of threads allocated 1202 * to the partition. For that, find the END corresponding to the 1203 * target. 1204 */ 1205 1206 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1207 return H_P2; 1208 } 1209 1210 assert(end_idx < xive->nr_ends); 1211 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1212 1213 switch (qsize) { 1214 case 12: 1215 case 16: 1216 case 21: 1217 case 24: 1218 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1219 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1220 " is not naturally aligned with %" HWADDR_PRIx "\n", 1221 qpage, (hwaddr)1 << qsize); 1222 return H_P4; 1223 } 1224 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1225 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1226 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1227 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1228 break; 1229 case 0: 1230 /* reset queue and disable queueing */ 1231 spapr_xive_end_reset(&end); 1232 goto out; 1233 1234 default: 1235 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1236 qsize); 1237 return H_P5; 1238 } 1239 1240 if (qsize) { 1241 hwaddr plen = 1 << qsize; 1242 void *eq; 1243 1244 /* 1245 * Validate the guest EQ. We should also check that the queue 1246 * has been zeroed by the OS. 1247 */ 1248 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1249 MEMTXATTRS_UNSPECIFIED); 1250 if (plen != 1 << qsize) { 1251 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1252 HWADDR_PRIx "\n", qpage); 1253 return H_P4; 1254 } 1255 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1256 } 1257 1258 /* "target" should have been validated above */ 1259 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1260 g_assert_not_reached(); 1261 } 1262 1263 /* 1264 * Ensure the priority and target are correctly set (they will not 1265 * be right after allocation) 1266 */ 1267 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1268 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1269 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1270 1271 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1272 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1273 } else { 1274 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1275 } 1276 1277 /* 1278 * The generation bit for the END starts at 1 and The END page 1279 * offset counter starts at 0. 1280 */ 1281 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1282 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1283 end.w0 |= cpu_to_be32(END_W0_VALID); 1284 1285 /* 1286 * TODO: issue syncs required to ensure all in-flight interrupts 1287 * are complete on the old END 1288 */ 1289 1290 out: 1291 if (kvm_irqchip_in_kernel()) { 1292 Error *local_err = NULL; 1293 1294 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1295 if (local_err) { 1296 error_report_err(local_err); 1297 return H_HARDWARE; 1298 } 1299 } 1300 1301 /* Update END */ 1302 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1303 return H_SUCCESS; 1304 } 1305 1306 /* 1307 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1308 * target and priority. 1309 * 1310 * Parameters: 1311 * Input: 1312 * - R4: "flags" 1313 * Bits 0-62: Reserved 1314 * Bit 63: Debug: Return debug data 1315 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1316 * "ibm,ppc-interrupt-gserver#s" 1317 * - R6: "priority" is a valid priority not in 1318 * "ibm,plat-res-int-priorities" 1319 * 1320 * Output: 1321 * - R4: "flags": 1322 * Bits 0-61: Reserved 1323 * Bit 62: The value of Event Queue Generation Number (g) per 1324 * the XIVE spec if "Debug" = 1 1325 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1326 * - R5: The logical real address of the start of the EQ 1327 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1328 * - R7: The value of Event Queue Offset Counter per XIVE spec 1329 * if "Debug" = 1, else 0 1330 * 1331 */ 1332 1333 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1334 1335 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1336 SpaprMachineState *spapr, 1337 target_ulong opcode, 1338 target_ulong *args) 1339 { 1340 SpaprXive *xive = spapr->xive; 1341 target_ulong flags = args[0]; 1342 target_ulong target = args[1]; 1343 target_ulong priority = args[2]; 1344 XiveEND *end; 1345 uint8_t end_blk; 1346 uint32_t end_idx; 1347 1348 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1349 return H_FUNCTION; 1350 } 1351 1352 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1353 return H_PARAMETER; 1354 } 1355 1356 /* 1357 * H_STATE should be returned if a H_INT_RESET is in progress. 1358 * This is not needed when running the emulation under QEMU 1359 */ 1360 1361 if (spapr_xive_priority_is_reserved(priority)) { 1362 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1363 " is reserved\n", priority); 1364 return H_P3; 1365 } 1366 1367 /* 1368 * Validate that "target" is part of the list of threads allocated 1369 * to the partition. For that, find the END corresponding to the 1370 * target. 1371 */ 1372 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1373 return H_P2; 1374 } 1375 1376 assert(end_idx < xive->nr_ends); 1377 end = &xive->endt[end_idx]; 1378 1379 args[0] = 0; 1380 if (xive_end_is_notify(end)) { 1381 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1382 } 1383 1384 if (xive_end_is_enqueue(end)) { 1385 args[1] = xive_end_qaddr(end); 1386 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1387 } else { 1388 args[1] = 0; 1389 args[2] = 0; 1390 } 1391 1392 if (kvm_irqchip_in_kernel()) { 1393 Error *local_err = NULL; 1394 1395 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1396 if (local_err) { 1397 error_report_err(local_err); 1398 return H_HARDWARE; 1399 } 1400 } 1401 1402 /* TODO: do we need any locking on the END ? */ 1403 if (flags & SPAPR_XIVE_END_DEBUG) { 1404 /* Load the event queue generation number into the return flags */ 1405 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1406 1407 /* Load R7 with the event queue offset counter */ 1408 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1409 } else { 1410 args[3] = 0; 1411 } 1412 1413 return H_SUCCESS; 1414 } 1415 1416 /* 1417 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1418 * reporting cache line pair for the calling thread. The reporting 1419 * cache lines will contain the OS interrupt context when the OS 1420 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1421 * interrupt. The reporting cache lines can be reset by inputting -1 1422 * in "reportingLine". Issuing the CI store byte without reporting 1423 * cache lines registered will result in the data not being accessible 1424 * to the OS. 1425 * 1426 * Parameters: 1427 * Input: 1428 * - R4: "flags" 1429 * Bits 0-63: Reserved 1430 * - R5: "reportingLine": The logical real address of the reporting cache 1431 * line pair 1432 * 1433 * Output: 1434 * - None 1435 */ 1436 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1437 SpaprMachineState *spapr, 1438 target_ulong opcode, 1439 target_ulong *args) 1440 { 1441 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1442 return H_FUNCTION; 1443 } 1444 1445 /* 1446 * H_STATE should be returned if a H_INT_RESET is in progress. 1447 * This is not needed when running the emulation under QEMU 1448 */ 1449 1450 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1451 return H_FUNCTION; 1452 } 1453 1454 /* 1455 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1456 * real address of the reporting cache line pair set for the input 1457 * "target". If no reporting cache line pair has been set, -1 is 1458 * returned. 1459 * 1460 * Parameters: 1461 * Input: 1462 * - R4: "flags" 1463 * Bits 0-63: Reserved 1464 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1465 * "ibm,ppc-interrupt-gserver#s" 1466 * - R6: "reportingLine": The logical real address of the reporting 1467 * cache line pair 1468 * 1469 * Output: 1470 * - R4: The logical real address of the reporting line if set, else -1 1471 */ 1472 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1473 SpaprMachineState *spapr, 1474 target_ulong opcode, 1475 target_ulong *args) 1476 { 1477 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1478 return H_FUNCTION; 1479 } 1480 1481 /* 1482 * H_STATE should be returned if a H_INT_RESET is in progress. 1483 * This is not needed when running the emulation under QEMU 1484 */ 1485 1486 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1487 return H_FUNCTION; 1488 } 1489 1490 /* 1491 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1492 * page for the input "lisn". This hcall is only supported for LISNs 1493 * that have the ESB hcall flag set to 1 when returned from hcall() 1494 * H_INT_GET_SOURCE_INFO. 1495 * 1496 * Parameters: 1497 * Input: 1498 * - R4: "flags" 1499 * Bits 0-62: Reserved 1500 * bit 63: Store: Store=1, store operation, else load operation 1501 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1502 * "ibm,xive-lisn-ranges" properties, or as returned by the 1503 * ibm,query-interrupt-source-number RTAS call, or as 1504 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1505 * - R6: "esbOffset" is the offset into the ESB page for the load or 1506 * store operation 1507 * - R7: "storeData" is the data to write for a store operation 1508 * 1509 * Output: 1510 * - R4: The value of the load if load operation, else -1 1511 */ 1512 1513 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1514 1515 static target_ulong h_int_esb(PowerPCCPU *cpu, 1516 SpaprMachineState *spapr, 1517 target_ulong opcode, 1518 target_ulong *args) 1519 { 1520 SpaprXive *xive = spapr->xive; 1521 XiveEAS eas; 1522 target_ulong flags = args[0]; 1523 target_ulong lisn = args[1]; 1524 target_ulong offset = args[2]; 1525 target_ulong data = args[3]; 1526 hwaddr mmio_addr; 1527 XiveSource *xsrc = &xive->source; 1528 1529 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1530 return H_FUNCTION; 1531 } 1532 1533 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1534 return H_PARAMETER; 1535 } 1536 1537 if (lisn >= xive->nr_irqs) { 1538 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1539 lisn); 1540 return H_P2; 1541 } 1542 1543 eas = xive->eat[lisn]; 1544 if (!xive_eas_is_valid(&eas)) { 1545 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1546 lisn); 1547 return H_P2; 1548 } 1549 1550 if (offset > (1ull << xsrc->esb_shift)) { 1551 return H_P3; 1552 } 1553 1554 if (kvm_irqchip_in_kernel()) { 1555 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1556 flags & SPAPR_XIVE_ESB_STORE); 1557 } else { 1558 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1559 1560 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1561 (flags & SPAPR_XIVE_ESB_STORE))) { 1562 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1563 HWADDR_PRIx "\n", mmio_addr); 1564 return H_HARDWARE; 1565 } 1566 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1567 } 1568 return H_SUCCESS; 1569 } 1570 1571 /* 1572 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1573 * ensure any in flight events for the input lisn are in the event 1574 * queue. 1575 * 1576 * Parameters: 1577 * Input: 1578 * - R4: "flags" 1579 * Bits 0-63: Reserved 1580 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1581 * "ibm,xive-lisn-ranges" properties, or as returned by the 1582 * ibm,query-interrupt-source-number RTAS call, or as 1583 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1584 * 1585 * Output: 1586 * - None 1587 */ 1588 static target_ulong h_int_sync(PowerPCCPU *cpu, 1589 SpaprMachineState *spapr, 1590 target_ulong opcode, 1591 target_ulong *args) 1592 { 1593 SpaprXive *xive = spapr->xive; 1594 XiveEAS eas; 1595 target_ulong flags = args[0]; 1596 target_ulong lisn = args[1]; 1597 1598 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1599 return H_FUNCTION; 1600 } 1601 1602 if (flags) { 1603 return H_PARAMETER; 1604 } 1605 1606 if (lisn >= xive->nr_irqs) { 1607 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1608 lisn); 1609 return H_P2; 1610 } 1611 1612 eas = xive->eat[lisn]; 1613 if (!xive_eas_is_valid(&eas)) { 1614 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1615 lisn); 1616 return H_P2; 1617 } 1618 1619 /* 1620 * H_STATE should be returned if a H_INT_RESET is in progress. 1621 * This is not needed when running the emulation under QEMU 1622 */ 1623 1624 /* 1625 * This is not real hardware. Nothing to be done unless when 1626 * under KVM 1627 */ 1628 1629 if (kvm_irqchip_in_kernel()) { 1630 Error *local_err = NULL; 1631 1632 kvmppc_xive_sync_source(xive, lisn, &local_err); 1633 if (local_err) { 1634 error_report_err(local_err); 1635 return H_HARDWARE; 1636 } 1637 } 1638 return H_SUCCESS; 1639 } 1640 1641 /* 1642 * The H_INT_RESET hcall() is used to reset all of the partition's 1643 * interrupt exploitation structures to their initial state. This 1644 * means losing all previously set interrupt state set via 1645 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1646 * 1647 * Parameters: 1648 * Input: 1649 * - R4: "flags" 1650 * Bits 0-63: Reserved 1651 * 1652 * Output: 1653 * - None 1654 */ 1655 static target_ulong h_int_reset(PowerPCCPU *cpu, 1656 SpaprMachineState *spapr, 1657 target_ulong opcode, 1658 target_ulong *args) 1659 { 1660 SpaprXive *xive = spapr->xive; 1661 target_ulong flags = args[0]; 1662 1663 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1664 return H_FUNCTION; 1665 } 1666 1667 if (flags) { 1668 return H_PARAMETER; 1669 } 1670 1671 device_reset(DEVICE(xive)); 1672 1673 if (kvm_irqchip_in_kernel()) { 1674 Error *local_err = NULL; 1675 1676 kvmppc_xive_reset(xive, &local_err); 1677 if (local_err) { 1678 error_report_err(local_err); 1679 return H_HARDWARE; 1680 } 1681 } 1682 return H_SUCCESS; 1683 } 1684 1685 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1686 { 1687 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1688 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1689 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1690 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1691 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1692 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1693 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1694 h_int_set_os_reporting_line); 1695 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1696 h_int_get_os_reporting_line); 1697 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1698 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1699 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1700 } 1701