1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 } 150 151 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 152 { 153 XiveSource *xsrc = &xive->source; 154 int i; 155 156 if (kvm_irqchip_in_kernel()) { 157 Error *local_err = NULL; 158 159 kvmppc_xive_synchronize_state(xive, &local_err); 160 if (local_err) { 161 error_report_err(local_err); 162 return; 163 } 164 } 165 166 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 167 168 for (i = 0; i < xive->nr_irqs; i++) { 169 uint8_t pq = xive_source_esb_get(xsrc, i); 170 XiveEAS *eas = &xive->eat[i]; 171 172 if (!xive_eas_is_valid(eas)) { 173 continue; 174 } 175 176 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 177 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 178 pq & XIVE_ESB_VAL_P ? 'P' : '-', 179 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 180 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 181 xive_eas_is_masked(eas) ? "M" : " ", 182 (int) xive_get_field64(EAS_END_DATA, eas->w)); 183 184 if (!xive_eas_is_masked(eas)) { 185 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 186 XiveEND *end; 187 188 assert(end_idx < xive->nr_ends); 189 end = &xive->endt[end_idx]; 190 191 if (xive_end_is_valid(end)) { 192 spapr_xive_end_pic_print_info(xive, end, mon); 193 } 194 } 195 monitor_printf(mon, "\n"); 196 } 197 } 198 199 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 200 { 201 memory_region_set_enabled(&xive->source.esb_mmio, enable); 202 memory_region_set_enabled(&xive->tm_mmio, enable); 203 204 /* Disable the END ESBs until a guest OS makes use of them */ 205 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 206 } 207 208 /* 209 * When a Virtual Processor is scheduled to run on a HW thread, the 210 * hypervisor pushes its identifier in the OS CAM line. Emulate the 211 * same behavior under QEMU. 212 */ 213 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 214 { 215 uint8_t nvt_blk; 216 uint32_t nvt_idx; 217 uint32_t nvt_cam; 218 219 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 220 221 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 222 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 223 } 224 225 static void spapr_xive_end_reset(XiveEND *end) 226 { 227 memset(end, 0, sizeof(*end)); 228 229 /* switch off the escalation and notification ESBs */ 230 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 231 } 232 233 static void spapr_xive_reset(void *dev) 234 { 235 SpaprXive *xive = SPAPR_XIVE(dev); 236 int i; 237 238 /* 239 * The XiveSource has its own reset handler, which mask off all 240 * IRQs (!P|Q) 241 */ 242 243 /* Mask all valid EASs in the IRQ number space. */ 244 for (i = 0; i < xive->nr_irqs; i++) { 245 XiveEAS *eas = &xive->eat[i]; 246 if (xive_eas_is_valid(eas)) { 247 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 248 } else { 249 eas->w = 0; 250 } 251 } 252 253 /* Clear all ENDs */ 254 for (i = 0; i < xive->nr_ends; i++) { 255 spapr_xive_end_reset(&xive->endt[i]); 256 } 257 } 258 259 static void spapr_xive_instance_init(Object *obj) 260 { 261 SpaprXive *xive = SPAPR_XIVE(obj); 262 263 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 264 TYPE_XIVE_SOURCE, &error_abort, NULL); 265 266 object_initialize_child(obj, "end_source", &xive->end_source, 267 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 268 &error_abort, NULL); 269 270 /* Not connected to the KVM XIVE device */ 271 xive->fd = -1; 272 } 273 274 static void spapr_xive_realize(DeviceState *dev, Error **errp) 275 { 276 SpaprXive *xive = SPAPR_XIVE(dev); 277 XiveSource *xsrc = &xive->source; 278 XiveENDSource *end_xsrc = &xive->end_source; 279 Error *local_err = NULL; 280 281 if (!xive->nr_irqs) { 282 error_setg(errp, "Number of interrupt needs to be greater 0"); 283 return; 284 } 285 286 if (!xive->nr_ends) { 287 error_setg(errp, "Number of interrupt needs to be greater 0"); 288 return; 289 } 290 291 /* 292 * Initialize the internal sources, for IPIs and virtual devices. 293 */ 294 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 295 &error_fatal); 296 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 297 &error_fatal); 298 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 299 if (local_err) { 300 error_propagate(errp, local_err); 301 return; 302 } 303 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 304 305 /* 306 * Initialize the END ESB source 307 */ 308 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 309 &error_fatal); 310 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 311 &error_fatal); 312 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 313 if (local_err) { 314 error_propagate(errp, local_err); 315 return; 316 } 317 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 318 319 /* Set the mapping address of the END ESB pages after the source ESBs */ 320 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 321 322 /* 323 * Allocate the routing tables 324 */ 325 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 326 xive->endt = g_new0(XiveEND, xive->nr_ends); 327 328 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 329 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 330 331 qemu_register_reset(spapr_xive_reset, dev); 332 333 /* TIMA initialization */ 334 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 335 "xive.tima", 4ull << TM_SHIFT); 336 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 337 338 /* 339 * Map all regions. These will be enabled or disabled at reset and 340 * can also be overridden by KVM memory regions if active 341 */ 342 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 343 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 344 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 345 } 346 347 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 348 uint32_t eas_idx, XiveEAS *eas) 349 { 350 SpaprXive *xive = SPAPR_XIVE(xrtr); 351 352 if (eas_idx >= xive->nr_irqs) { 353 return -1; 354 } 355 356 *eas = xive->eat[eas_idx]; 357 return 0; 358 } 359 360 static int spapr_xive_get_end(XiveRouter *xrtr, 361 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 362 { 363 SpaprXive *xive = SPAPR_XIVE(xrtr); 364 365 if (end_idx >= xive->nr_ends) { 366 return -1; 367 } 368 369 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 370 return 0; 371 } 372 373 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 374 uint32_t end_idx, XiveEND *end, 375 uint8_t word_number) 376 { 377 SpaprXive *xive = SPAPR_XIVE(xrtr); 378 379 if (end_idx >= xive->nr_ends) { 380 return -1; 381 } 382 383 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 384 return 0; 385 } 386 387 static int spapr_xive_get_nvt(XiveRouter *xrtr, 388 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 389 { 390 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 391 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 392 393 if (!cpu) { 394 /* TODO: should we assert() if we can find a NVT ? */ 395 return -1; 396 } 397 398 /* 399 * sPAPR does not maintain a NVT table. Return that the NVT is 400 * valid if we have found a matching CPU 401 */ 402 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 403 return 0; 404 } 405 406 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 407 uint32_t nvt_idx, XiveNVT *nvt, 408 uint8_t word_number) 409 { 410 /* 411 * We don't need to write back to the NVTs because the sPAPR 412 * machine should never hit a non-scheduled NVT. It should never 413 * get called. 414 */ 415 g_assert_not_reached(); 416 } 417 418 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 419 { 420 PowerPCCPU *cpu = POWERPC_CPU(cs); 421 422 return spapr_cpu_state(cpu)->tctx; 423 } 424 425 static const VMStateDescription vmstate_spapr_xive_end = { 426 .name = TYPE_SPAPR_XIVE "/end", 427 .version_id = 1, 428 .minimum_version_id = 1, 429 .fields = (VMStateField []) { 430 VMSTATE_UINT32(w0, XiveEND), 431 VMSTATE_UINT32(w1, XiveEND), 432 VMSTATE_UINT32(w2, XiveEND), 433 VMSTATE_UINT32(w3, XiveEND), 434 VMSTATE_UINT32(w4, XiveEND), 435 VMSTATE_UINT32(w5, XiveEND), 436 VMSTATE_UINT32(w6, XiveEND), 437 VMSTATE_UINT32(w7, XiveEND), 438 VMSTATE_END_OF_LIST() 439 }, 440 }; 441 442 static const VMStateDescription vmstate_spapr_xive_eas = { 443 .name = TYPE_SPAPR_XIVE "/eas", 444 .version_id = 1, 445 .minimum_version_id = 1, 446 .fields = (VMStateField []) { 447 VMSTATE_UINT64(w, XiveEAS), 448 VMSTATE_END_OF_LIST() 449 }, 450 }; 451 452 static int vmstate_spapr_xive_pre_save(void *opaque) 453 { 454 if (kvm_irqchip_in_kernel()) { 455 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 456 } 457 458 return 0; 459 } 460 461 /* 462 * Called by the sPAPR IRQ backend 'post_load' method at the machine 463 * level. 464 */ 465 int spapr_xive_post_load(SpaprXive *xive, int version_id) 466 { 467 if (kvm_irqchip_in_kernel()) { 468 return kvmppc_xive_post_load(xive, version_id); 469 } 470 471 return 0; 472 } 473 474 static const VMStateDescription vmstate_spapr_xive = { 475 .name = TYPE_SPAPR_XIVE, 476 .version_id = 1, 477 .minimum_version_id = 1, 478 .pre_save = vmstate_spapr_xive_pre_save, 479 .post_load = NULL, /* handled at the machine level */ 480 .fields = (VMStateField[]) { 481 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 482 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 483 vmstate_spapr_xive_eas, XiveEAS), 484 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 485 vmstate_spapr_xive_end, XiveEND), 486 VMSTATE_END_OF_LIST() 487 }, 488 }; 489 490 static Property spapr_xive_properties[] = { 491 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 492 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 493 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 494 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 495 DEFINE_PROP_END_OF_LIST(), 496 }; 497 498 static void spapr_xive_class_init(ObjectClass *klass, void *data) 499 { 500 DeviceClass *dc = DEVICE_CLASS(klass); 501 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 502 503 dc->desc = "sPAPR XIVE Interrupt Controller"; 504 dc->props = spapr_xive_properties; 505 dc->realize = spapr_xive_realize; 506 dc->vmsd = &vmstate_spapr_xive; 507 508 xrc->get_eas = spapr_xive_get_eas; 509 xrc->get_end = spapr_xive_get_end; 510 xrc->write_end = spapr_xive_write_end; 511 xrc->get_nvt = spapr_xive_get_nvt; 512 xrc->write_nvt = spapr_xive_write_nvt; 513 xrc->get_tctx = spapr_xive_get_tctx; 514 } 515 516 static const TypeInfo spapr_xive_info = { 517 .name = TYPE_SPAPR_XIVE, 518 .parent = TYPE_XIVE_ROUTER, 519 .instance_init = spapr_xive_instance_init, 520 .instance_size = sizeof(SpaprXive), 521 .class_init = spapr_xive_class_init, 522 }; 523 524 static void spapr_xive_register_types(void) 525 { 526 type_register_static(&spapr_xive_info); 527 } 528 529 type_init(spapr_xive_register_types) 530 531 int spapr_xive_irq_claim(SpaprXive *xive, int lisn, bool lsi, Error **errp) 532 { 533 XiveSource *xsrc = &xive->source; 534 535 assert(lisn < xive->nr_irqs); 536 537 if (xive_eas_is_valid(&xive->eat[lisn])) { 538 error_setg(errp, "IRQ %d is not free", lisn); 539 return -EBUSY; 540 } 541 542 /* 543 * Set default values when allocating an IRQ number 544 */ 545 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); 546 if (lsi) { 547 xive_source_irq_set_lsi(xsrc, lisn); 548 } 549 550 if (kvm_irqchip_in_kernel()) { 551 return kvmppc_xive_source_reset_one(xsrc, lisn, errp); 552 } 553 554 return 0; 555 } 556 557 void spapr_xive_irq_free(SpaprXive *xive, int lisn) 558 { 559 assert(lisn < xive->nr_irqs); 560 561 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 562 } 563 564 /* 565 * XIVE hcalls 566 * 567 * The terminology used by the XIVE hcalls is the following : 568 * 569 * TARGET vCPU number 570 * EQ Event Queue assigned by OS to receive event data 571 * ESB page for source interrupt management 572 * LISN Logical Interrupt Source Number identifying a source in the 573 * machine 574 * EISN Effective Interrupt Source Number used by guest OS to 575 * identify source in the guest 576 * 577 * The EAS, END, NVT structures are not exposed. 578 */ 579 580 /* 581 * Linux hosts under OPAL reserve priority 7 for their own escalation 582 * interrupts (DD2.X POWER9). So we only allow the guest to use 583 * priorities [0..6]. 584 */ 585 static bool spapr_xive_priority_is_reserved(uint8_t priority) 586 { 587 switch (priority) { 588 case 0 ... 6: 589 return false; 590 case 7: /* OPAL escalation queue */ 591 default: 592 return true; 593 } 594 } 595 596 /* 597 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 598 * real address of the MMIO page through which the Event State Buffer 599 * entry associated with the value of the "lisn" parameter is managed. 600 * 601 * Parameters: 602 * Input 603 * - R4: "flags" 604 * Bits 0-63 reserved 605 * - R5: "lisn" is per "interrupts", "interrupt-map", or 606 * "ibm,xive-lisn-ranges" properties, or as returned by the 607 * ibm,query-interrupt-source-number RTAS call, or as returned 608 * by the H_ALLOCATE_VAS_WINDOW hcall 609 * 610 * Output 611 * - R4: "flags" 612 * Bits 0-59: Reserved 613 * Bit 60: H_INT_ESB must be used for Event State Buffer 614 * management 615 * Bit 61: 1 == LSI 0 == MSI 616 * Bit 62: the full function page supports trigger 617 * Bit 63: Store EOI Supported 618 * - R5: Logical Real address of full function Event State Buffer 619 * management page, -1 if H_INT_ESB hcall flag is set to 1. 620 * - R6: Logical Real Address of trigger only Event State Buffer 621 * management page or -1. 622 * - R7: Power of 2 page size for the ESB management pages returned in 623 * R5 and R6. 624 */ 625 626 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 627 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 628 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 629 on same page */ 630 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 631 632 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 633 SpaprMachineState *spapr, 634 target_ulong opcode, 635 target_ulong *args) 636 { 637 SpaprXive *xive = spapr->xive; 638 XiveSource *xsrc = &xive->source; 639 target_ulong flags = args[0]; 640 target_ulong lisn = args[1]; 641 642 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 643 return H_FUNCTION; 644 } 645 646 if (flags) { 647 return H_PARAMETER; 648 } 649 650 if (lisn >= xive->nr_irqs) { 651 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 652 lisn); 653 return H_P2; 654 } 655 656 if (!xive_eas_is_valid(&xive->eat[lisn])) { 657 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 658 lisn); 659 return H_P2; 660 } 661 662 /* 663 * All sources are emulated under the main XIVE object and share 664 * the same characteristics. 665 */ 666 args[0] = 0; 667 if (!xive_source_esb_has_2page(xsrc)) { 668 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 669 } 670 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 671 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 672 } 673 674 /* 675 * Force the use of the H_INT_ESB hcall in case of an LSI 676 * interrupt. This is necessary under KVM to re-trigger the 677 * interrupt if the level is still asserted 678 */ 679 if (xive_source_irq_is_lsi(xsrc, lisn)) { 680 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 681 } 682 683 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 684 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 685 } else { 686 args[1] = -1; 687 } 688 689 if (xive_source_esb_has_2page(xsrc) && 690 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 691 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 692 } else { 693 args[2] = -1; 694 } 695 696 if (xive_source_esb_has_2page(xsrc)) { 697 args[3] = xsrc->esb_shift - 1; 698 } else { 699 args[3] = xsrc->esb_shift; 700 } 701 702 return H_SUCCESS; 703 } 704 705 /* 706 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 707 * Interrupt Source to a target. The Logical Interrupt Source is 708 * designated with the "lisn" parameter and the target is designated 709 * with the "target" and "priority" parameters. Upon return from the 710 * hcall(), no additional interrupts will be directed to the old EQ. 711 * 712 * Parameters: 713 * Input: 714 * - R4: "flags" 715 * Bits 0-61: Reserved 716 * Bit 62: set the "eisn" in the EAS 717 * Bit 63: masks the interrupt source in the hardware interrupt 718 * control structure. An interrupt masked by this mechanism will 719 * be dropped, but it's source state bits will still be 720 * set. There is no race-free way of unmasking and restoring the 721 * source. Thus this should only be used in interrupts that are 722 * also masked at the source, and only in cases where the 723 * interrupt is not meant to be used for a large amount of time 724 * because no valid target exists for it for example 725 * - R5: "lisn" is per "interrupts", "interrupt-map", or 726 * "ibm,xive-lisn-ranges" properties, or as returned by the 727 * ibm,query-interrupt-source-number RTAS call, or as returned by 728 * the H_ALLOCATE_VAS_WINDOW hcall 729 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 730 * "ibm,ppc-interrupt-gserver#s" 731 * - R7: "priority" is a valid priority not in 732 * "ibm,plat-res-int-priorities" 733 * - R8: "eisn" is the guest EISN associated with the "lisn" 734 * 735 * Output: 736 * - None 737 */ 738 739 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 740 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 741 742 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 743 SpaprMachineState *spapr, 744 target_ulong opcode, 745 target_ulong *args) 746 { 747 SpaprXive *xive = spapr->xive; 748 XiveEAS eas, new_eas; 749 target_ulong flags = args[0]; 750 target_ulong lisn = args[1]; 751 target_ulong target = args[2]; 752 target_ulong priority = args[3]; 753 target_ulong eisn = args[4]; 754 uint8_t end_blk; 755 uint32_t end_idx; 756 757 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 758 return H_FUNCTION; 759 } 760 761 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 762 return H_PARAMETER; 763 } 764 765 if (lisn >= xive->nr_irqs) { 766 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 767 lisn); 768 return H_P2; 769 } 770 771 eas = xive->eat[lisn]; 772 if (!xive_eas_is_valid(&eas)) { 773 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 774 lisn); 775 return H_P2; 776 } 777 778 /* priority 0xff is used to reset the EAS */ 779 if (priority == 0xff) { 780 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 781 goto out; 782 } 783 784 if (flags & SPAPR_XIVE_SRC_MASK) { 785 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 786 } else { 787 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 788 } 789 790 if (spapr_xive_priority_is_reserved(priority)) { 791 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 792 " is reserved\n", priority); 793 return H_P4; 794 } 795 796 /* 797 * Validate that "target" is part of the list of threads allocated 798 * to the partition. For that, find the END corresponding to the 799 * target. 800 */ 801 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 802 return H_P3; 803 } 804 805 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 806 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 807 808 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 809 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 810 } 811 812 if (kvm_irqchip_in_kernel()) { 813 Error *local_err = NULL; 814 815 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 816 if (local_err) { 817 error_report_err(local_err); 818 return H_HARDWARE; 819 } 820 } 821 822 out: 823 xive->eat[lisn] = new_eas; 824 return H_SUCCESS; 825 } 826 827 /* 828 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 829 * target/priority pair is assigned to the specified Logical Interrupt 830 * Source. 831 * 832 * Parameters: 833 * Input: 834 * - R4: "flags" 835 * Bits 0-63 Reserved 836 * - R5: "lisn" is per "interrupts", "interrupt-map", or 837 * "ibm,xive-lisn-ranges" properties, or as returned by the 838 * ibm,query-interrupt-source-number RTAS call, or as 839 * returned by the H_ALLOCATE_VAS_WINDOW hcall 840 * 841 * Output: 842 * - R4: Target to which the specified Logical Interrupt Source is 843 * assigned 844 * - R5: Priority to which the specified Logical Interrupt Source is 845 * assigned 846 * - R6: EISN for the specified Logical Interrupt Source (this will be 847 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 848 */ 849 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 850 SpaprMachineState *spapr, 851 target_ulong opcode, 852 target_ulong *args) 853 { 854 SpaprXive *xive = spapr->xive; 855 target_ulong flags = args[0]; 856 target_ulong lisn = args[1]; 857 XiveEAS eas; 858 XiveEND *end; 859 uint8_t nvt_blk; 860 uint32_t end_idx, nvt_idx; 861 862 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 863 return H_FUNCTION; 864 } 865 866 if (flags) { 867 return H_PARAMETER; 868 } 869 870 if (lisn >= xive->nr_irqs) { 871 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 872 lisn); 873 return H_P2; 874 } 875 876 eas = xive->eat[lisn]; 877 if (!xive_eas_is_valid(&eas)) { 878 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 879 lisn); 880 return H_P2; 881 } 882 883 /* EAS_END_BLOCK is unused on sPAPR */ 884 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 885 886 assert(end_idx < xive->nr_ends); 887 end = &xive->endt[end_idx]; 888 889 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 890 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 891 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 892 893 if (xive_eas_is_masked(&eas)) { 894 args[1] = 0xff; 895 } else { 896 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 897 } 898 899 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 900 901 return H_SUCCESS; 902 } 903 904 /* 905 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 906 * address of the notification management page associated with the 907 * specified target and priority. 908 * 909 * Parameters: 910 * Input: 911 * - R4: "flags" 912 * Bits 0-63 Reserved 913 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 914 * "ibm,ppc-interrupt-gserver#s" 915 * - R6: "priority" is a valid priority not in 916 * "ibm,plat-res-int-priorities" 917 * 918 * Output: 919 * - R4: Logical real address of notification page 920 * - R5: Power of 2 page size of the notification page 921 */ 922 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 923 SpaprMachineState *spapr, 924 target_ulong opcode, 925 target_ulong *args) 926 { 927 SpaprXive *xive = spapr->xive; 928 XiveENDSource *end_xsrc = &xive->end_source; 929 target_ulong flags = args[0]; 930 target_ulong target = args[1]; 931 target_ulong priority = args[2]; 932 XiveEND *end; 933 uint8_t end_blk; 934 uint32_t end_idx; 935 936 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 937 return H_FUNCTION; 938 } 939 940 if (flags) { 941 return H_PARAMETER; 942 } 943 944 /* 945 * H_STATE should be returned if a H_INT_RESET is in progress. 946 * This is not needed when running the emulation under QEMU 947 */ 948 949 if (spapr_xive_priority_is_reserved(priority)) { 950 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 951 " is reserved\n", priority); 952 return H_P3; 953 } 954 955 /* 956 * Validate that "target" is part of the list of threads allocated 957 * to the partition. For that, find the END corresponding to the 958 * target. 959 */ 960 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 961 return H_P2; 962 } 963 964 assert(end_idx < xive->nr_ends); 965 end = &xive->endt[end_idx]; 966 967 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 968 if (xive_end_is_enqueue(end)) { 969 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 970 } else { 971 args[1] = 0; 972 } 973 974 return H_SUCCESS; 975 } 976 977 /* 978 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 979 * a given "target" and "priority". It is also used to set the 980 * notification config associated with the EQ. An EQ size of 0 is 981 * used to reset the EQ config for a given target and priority. If 982 * resetting the EQ config, the END associated with the given "target" 983 * and "priority" will be changed to disable queueing. 984 * 985 * Upon return from the hcall(), no additional interrupts will be 986 * directed to the old EQ (if one was set). The old EQ (if one was 987 * set) should be investigated for interrupts that occurred prior to 988 * or during the hcall(). 989 * 990 * Parameters: 991 * Input: 992 * - R4: "flags" 993 * Bits 0-62: Reserved 994 * Bit 63: Unconditional Notify (n) per the XIVE spec 995 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 996 * "ibm,ppc-interrupt-gserver#s" 997 * - R6: "priority" is a valid priority not in 998 * "ibm,plat-res-int-priorities" 999 * - R7: "eventQueue": The logical real address of the start of the EQ 1000 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1001 * 1002 * Output: 1003 * - None 1004 */ 1005 1006 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1007 1008 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1009 SpaprMachineState *spapr, 1010 target_ulong opcode, 1011 target_ulong *args) 1012 { 1013 SpaprXive *xive = spapr->xive; 1014 target_ulong flags = args[0]; 1015 target_ulong target = args[1]; 1016 target_ulong priority = args[2]; 1017 target_ulong qpage = args[3]; 1018 target_ulong qsize = args[4]; 1019 XiveEND end; 1020 uint8_t end_blk, nvt_blk; 1021 uint32_t end_idx, nvt_idx; 1022 1023 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1024 return H_FUNCTION; 1025 } 1026 1027 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1028 return H_PARAMETER; 1029 } 1030 1031 /* 1032 * H_STATE should be returned if a H_INT_RESET is in progress. 1033 * This is not needed when running the emulation under QEMU 1034 */ 1035 1036 if (spapr_xive_priority_is_reserved(priority)) { 1037 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1038 " is reserved\n", priority); 1039 return H_P3; 1040 } 1041 1042 /* 1043 * Validate that "target" is part of the list of threads allocated 1044 * to the partition. For that, find the END corresponding to the 1045 * target. 1046 */ 1047 1048 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1049 return H_P2; 1050 } 1051 1052 assert(end_idx < xive->nr_ends); 1053 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1054 1055 switch (qsize) { 1056 case 12: 1057 case 16: 1058 case 21: 1059 case 24: 1060 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1061 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1062 " is not naturally aligned with %" HWADDR_PRIx "\n", 1063 qpage, (hwaddr)1 << qsize); 1064 return H_P4; 1065 } 1066 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1067 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1068 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1069 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1070 break; 1071 case 0: 1072 /* reset queue and disable queueing */ 1073 spapr_xive_end_reset(&end); 1074 goto out; 1075 1076 default: 1077 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1078 qsize); 1079 return H_P5; 1080 } 1081 1082 if (qsize) { 1083 hwaddr plen = 1 << qsize; 1084 void *eq; 1085 1086 /* 1087 * Validate the guest EQ. We should also check that the queue 1088 * has been zeroed by the OS. 1089 */ 1090 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1091 MEMTXATTRS_UNSPECIFIED); 1092 if (plen != 1 << qsize) { 1093 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1094 HWADDR_PRIx "\n", qpage); 1095 return H_P4; 1096 } 1097 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1098 } 1099 1100 /* "target" should have been validated above */ 1101 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1102 g_assert_not_reached(); 1103 } 1104 1105 /* 1106 * Ensure the priority and target are correctly set (they will not 1107 * be right after allocation) 1108 */ 1109 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1110 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1111 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1112 1113 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1114 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1115 } else { 1116 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1117 } 1118 1119 /* 1120 * The generation bit for the END starts at 1 and The END page 1121 * offset counter starts at 0. 1122 */ 1123 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1124 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1125 end.w0 |= cpu_to_be32(END_W0_VALID); 1126 1127 /* 1128 * TODO: issue syncs required to ensure all in-flight interrupts 1129 * are complete on the old END 1130 */ 1131 1132 out: 1133 if (kvm_irqchip_in_kernel()) { 1134 Error *local_err = NULL; 1135 1136 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1137 if (local_err) { 1138 error_report_err(local_err); 1139 return H_HARDWARE; 1140 } 1141 } 1142 1143 /* Update END */ 1144 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1145 return H_SUCCESS; 1146 } 1147 1148 /* 1149 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1150 * target and priority. 1151 * 1152 * Parameters: 1153 * Input: 1154 * - R4: "flags" 1155 * Bits 0-62: Reserved 1156 * Bit 63: Debug: Return debug data 1157 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1158 * "ibm,ppc-interrupt-gserver#s" 1159 * - R6: "priority" is a valid priority not in 1160 * "ibm,plat-res-int-priorities" 1161 * 1162 * Output: 1163 * - R4: "flags": 1164 * Bits 0-61: Reserved 1165 * Bit 62: The value of Event Queue Generation Number (g) per 1166 * the XIVE spec if "Debug" = 1 1167 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1168 * - R5: The logical real address of the start of the EQ 1169 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1170 * - R7: The value of Event Queue Offset Counter per XIVE spec 1171 * if "Debug" = 1, else 0 1172 * 1173 */ 1174 1175 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1176 1177 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1178 SpaprMachineState *spapr, 1179 target_ulong opcode, 1180 target_ulong *args) 1181 { 1182 SpaprXive *xive = spapr->xive; 1183 target_ulong flags = args[0]; 1184 target_ulong target = args[1]; 1185 target_ulong priority = args[2]; 1186 XiveEND *end; 1187 uint8_t end_blk; 1188 uint32_t end_idx; 1189 1190 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1191 return H_FUNCTION; 1192 } 1193 1194 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1195 return H_PARAMETER; 1196 } 1197 1198 /* 1199 * H_STATE should be returned if a H_INT_RESET is in progress. 1200 * This is not needed when running the emulation under QEMU 1201 */ 1202 1203 if (spapr_xive_priority_is_reserved(priority)) { 1204 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1205 " is reserved\n", priority); 1206 return H_P3; 1207 } 1208 1209 /* 1210 * Validate that "target" is part of the list of threads allocated 1211 * to the partition. For that, find the END corresponding to the 1212 * target. 1213 */ 1214 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1215 return H_P2; 1216 } 1217 1218 assert(end_idx < xive->nr_ends); 1219 end = &xive->endt[end_idx]; 1220 1221 args[0] = 0; 1222 if (xive_end_is_notify(end)) { 1223 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1224 } 1225 1226 if (xive_end_is_enqueue(end)) { 1227 args[1] = xive_end_qaddr(end); 1228 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1229 } else { 1230 args[1] = 0; 1231 args[2] = 0; 1232 } 1233 1234 if (kvm_irqchip_in_kernel()) { 1235 Error *local_err = NULL; 1236 1237 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1238 if (local_err) { 1239 error_report_err(local_err); 1240 return H_HARDWARE; 1241 } 1242 } 1243 1244 /* TODO: do we need any locking on the END ? */ 1245 if (flags & SPAPR_XIVE_END_DEBUG) { 1246 /* Load the event queue generation number into the return flags */ 1247 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1248 1249 /* Load R7 with the event queue offset counter */ 1250 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1251 } else { 1252 args[3] = 0; 1253 } 1254 1255 return H_SUCCESS; 1256 } 1257 1258 /* 1259 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1260 * reporting cache line pair for the calling thread. The reporting 1261 * cache lines will contain the OS interrupt context when the OS 1262 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1263 * interrupt. The reporting cache lines can be reset by inputting -1 1264 * in "reportingLine". Issuing the CI store byte without reporting 1265 * cache lines registered will result in the data not being accessible 1266 * to the OS. 1267 * 1268 * Parameters: 1269 * Input: 1270 * - R4: "flags" 1271 * Bits 0-63: Reserved 1272 * - R5: "reportingLine": The logical real address of the reporting cache 1273 * line pair 1274 * 1275 * Output: 1276 * - None 1277 */ 1278 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1279 SpaprMachineState *spapr, 1280 target_ulong opcode, 1281 target_ulong *args) 1282 { 1283 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1284 return H_FUNCTION; 1285 } 1286 1287 /* 1288 * H_STATE should be returned if a H_INT_RESET is in progress. 1289 * This is not needed when running the emulation under QEMU 1290 */ 1291 1292 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1293 return H_FUNCTION; 1294 } 1295 1296 /* 1297 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1298 * real address of the reporting cache line pair set for the input 1299 * "target". If no reporting cache line pair has been set, -1 is 1300 * returned. 1301 * 1302 * Parameters: 1303 * Input: 1304 * - R4: "flags" 1305 * Bits 0-63: Reserved 1306 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1307 * "ibm,ppc-interrupt-gserver#s" 1308 * - R6: "reportingLine": The logical real address of the reporting 1309 * cache line pair 1310 * 1311 * Output: 1312 * - R4: The logical real address of the reporting line if set, else -1 1313 */ 1314 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1315 SpaprMachineState *spapr, 1316 target_ulong opcode, 1317 target_ulong *args) 1318 { 1319 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1320 return H_FUNCTION; 1321 } 1322 1323 /* 1324 * H_STATE should be returned if a H_INT_RESET is in progress. 1325 * This is not needed when running the emulation under QEMU 1326 */ 1327 1328 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1329 return H_FUNCTION; 1330 } 1331 1332 /* 1333 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1334 * page for the input "lisn". This hcall is only supported for LISNs 1335 * that have the ESB hcall flag set to 1 when returned from hcall() 1336 * H_INT_GET_SOURCE_INFO. 1337 * 1338 * Parameters: 1339 * Input: 1340 * - R4: "flags" 1341 * Bits 0-62: Reserved 1342 * bit 63: Store: Store=1, store operation, else load operation 1343 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1344 * "ibm,xive-lisn-ranges" properties, or as returned by the 1345 * ibm,query-interrupt-source-number RTAS call, or as 1346 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1347 * - R6: "esbOffset" is the offset into the ESB page for the load or 1348 * store operation 1349 * - R7: "storeData" is the data to write for a store operation 1350 * 1351 * Output: 1352 * - R4: The value of the load if load operation, else -1 1353 */ 1354 1355 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1356 1357 static target_ulong h_int_esb(PowerPCCPU *cpu, 1358 SpaprMachineState *spapr, 1359 target_ulong opcode, 1360 target_ulong *args) 1361 { 1362 SpaprXive *xive = spapr->xive; 1363 XiveEAS eas; 1364 target_ulong flags = args[0]; 1365 target_ulong lisn = args[1]; 1366 target_ulong offset = args[2]; 1367 target_ulong data = args[3]; 1368 hwaddr mmio_addr; 1369 XiveSource *xsrc = &xive->source; 1370 1371 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1372 return H_FUNCTION; 1373 } 1374 1375 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1376 return H_PARAMETER; 1377 } 1378 1379 if (lisn >= xive->nr_irqs) { 1380 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1381 lisn); 1382 return H_P2; 1383 } 1384 1385 eas = xive->eat[lisn]; 1386 if (!xive_eas_is_valid(&eas)) { 1387 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1388 lisn); 1389 return H_P2; 1390 } 1391 1392 if (offset > (1ull << xsrc->esb_shift)) { 1393 return H_P3; 1394 } 1395 1396 if (kvm_irqchip_in_kernel()) { 1397 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1398 flags & SPAPR_XIVE_ESB_STORE); 1399 } else { 1400 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1401 1402 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1403 (flags & SPAPR_XIVE_ESB_STORE))) { 1404 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1405 HWADDR_PRIx "\n", mmio_addr); 1406 return H_HARDWARE; 1407 } 1408 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1409 } 1410 return H_SUCCESS; 1411 } 1412 1413 /* 1414 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1415 * ensure any in flight events for the input lisn are in the event 1416 * queue. 1417 * 1418 * Parameters: 1419 * Input: 1420 * - R4: "flags" 1421 * Bits 0-63: Reserved 1422 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1423 * "ibm,xive-lisn-ranges" properties, or as returned by the 1424 * ibm,query-interrupt-source-number RTAS call, or as 1425 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1426 * 1427 * Output: 1428 * - None 1429 */ 1430 static target_ulong h_int_sync(PowerPCCPU *cpu, 1431 SpaprMachineState *spapr, 1432 target_ulong opcode, 1433 target_ulong *args) 1434 { 1435 SpaprXive *xive = spapr->xive; 1436 XiveEAS eas; 1437 target_ulong flags = args[0]; 1438 target_ulong lisn = args[1]; 1439 1440 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1441 return H_FUNCTION; 1442 } 1443 1444 if (flags) { 1445 return H_PARAMETER; 1446 } 1447 1448 if (lisn >= xive->nr_irqs) { 1449 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1450 lisn); 1451 return H_P2; 1452 } 1453 1454 eas = xive->eat[lisn]; 1455 if (!xive_eas_is_valid(&eas)) { 1456 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1457 lisn); 1458 return H_P2; 1459 } 1460 1461 /* 1462 * H_STATE should be returned if a H_INT_RESET is in progress. 1463 * This is not needed when running the emulation under QEMU 1464 */ 1465 1466 /* 1467 * This is not real hardware. Nothing to be done unless when 1468 * under KVM 1469 */ 1470 1471 if (kvm_irqchip_in_kernel()) { 1472 Error *local_err = NULL; 1473 1474 kvmppc_xive_sync_source(xive, lisn, &local_err); 1475 if (local_err) { 1476 error_report_err(local_err); 1477 return H_HARDWARE; 1478 } 1479 } 1480 return H_SUCCESS; 1481 } 1482 1483 /* 1484 * The H_INT_RESET hcall() is used to reset all of the partition's 1485 * interrupt exploitation structures to their initial state. This 1486 * means losing all previously set interrupt state set via 1487 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1488 * 1489 * Parameters: 1490 * Input: 1491 * - R4: "flags" 1492 * Bits 0-63: Reserved 1493 * 1494 * Output: 1495 * - None 1496 */ 1497 static target_ulong h_int_reset(PowerPCCPU *cpu, 1498 SpaprMachineState *spapr, 1499 target_ulong opcode, 1500 target_ulong *args) 1501 { 1502 SpaprXive *xive = spapr->xive; 1503 target_ulong flags = args[0]; 1504 1505 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1506 return H_FUNCTION; 1507 } 1508 1509 if (flags) { 1510 return H_PARAMETER; 1511 } 1512 1513 device_reset(DEVICE(xive)); 1514 1515 if (kvm_irqchip_in_kernel()) { 1516 Error *local_err = NULL; 1517 1518 kvmppc_xive_reset(xive, &local_err); 1519 if (local_err) { 1520 error_report_err(local_err); 1521 return H_HARDWARE; 1522 } 1523 } 1524 return H_SUCCESS; 1525 } 1526 1527 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1528 { 1529 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1530 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1531 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1532 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1533 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1534 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1535 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1536 h_int_set_os_reporting_line); 1537 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1538 h_int_get_os_reporting_line); 1539 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1540 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1541 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1542 } 1543 1544 void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, 1545 uint32_t phandle) 1546 { 1547 SpaprXive *xive = spapr->xive; 1548 int node; 1549 uint64_t timas[2 * 2]; 1550 /* Interrupt number ranges for the IPIs */ 1551 uint32_t lisn_ranges[] = { 1552 cpu_to_be32(0), 1553 cpu_to_be32(nr_servers), 1554 }; 1555 /* 1556 * EQ size - the sizes of pages supported by the system 4K, 64K, 1557 * 2M, 16M. We only advertise 64K for the moment. 1558 */ 1559 uint32_t eq_sizes[] = { 1560 cpu_to_be32(16), /* 64K */ 1561 }; 1562 /* 1563 * The following array is in sync with the reserved priorities 1564 * defined by the 'spapr_xive_priority_is_reserved' routine. 1565 */ 1566 uint32_t plat_res_int_priorities[] = { 1567 cpu_to_be32(7), /* start */ 1568 cpu_to_be32(0xf8), /* count */ 1569 }; 1570 1571 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 1572 timas[0] = cpu_to_be64(xive->tm_base + 1573 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 1574 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 1575 timas[2] = cpu_to_be64(xive->tm_base + 1576 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 1577 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 1578 1579 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 1580 1581 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 1582 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 1583 1584 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 1585 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 1586 sizeof(eq_sizes))); 1587 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 1588 sizeof(lisn_ranges))); 1589 1590 /* For Linux to link the LSIs to the interrupt controller. */ 1591 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 1592 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 1593 1594 /* For SLOF */ 1595 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 1596 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 1597 1598 /* 1599 * The "ibm,plat-res-int-priorities" property defines the priority 1600 * ranges reserved by the hypervisor 1601 */ 1602 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 1603 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 1604 } 1605