1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 } 150 151 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 152 { 153 XiveSource *xsrc = &xive->source; 154 int i; 155 156 if (kvm_irqchip_in_kernel()) { 157 Error *local_err = NULL; 158 159 kvmppc_xive_synchronize_state(xive, &local_err); 160 if (local_err) { 161 error_report_err(local_err); 162 return; 163 } 164 } 165 166 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 167 168 for (i = 0; i < xive->nr_irqs; i++) { 169 uint8_t pq = xive_source_esb_get(xsrc, i); 170 XiveEAS *eas = &xive->eat[i]; 171 172 if (!xive_eas_is_valid(eas)) { 173 continue; 174 } 175 176 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 177 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 178 pq & XIVE_ESB_VAL_P ? 'P' : '-', 179 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 180 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 181 xive_eas_is_masked(eas) ? "M" : " ", 182 (int) xive_get_field64(EAS_END_DATA, eas->w)); 183 184 if (!xive_eas_is_masked(eas)) { 185 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 186 XiveEND *end; 187 188 assert(end_idx < xive->nr_ends); 189 end = &xive->endt[end_idx]; 190 191 if (xive_end_is_valid(end)) { 192 spapr_xive_end_pic_print_info(xive, end, mon); 193 } 194 } 195 monitor_printf(mon, "\n"); 196 } 197 } 198 199 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 200 { 201 memory_region_set_enabled(&xive->source.esb_mmio, enable); 202 memory_region_set_enabled(&xive->tm_mmio, enable); 203 204 /* Disable the END ESBs until a guest OS makes use of them */ 205 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 206 } 207 208 /* 209 * When a Virtual Processor is scheduled to run on a HW thread, the 210 * hypervisor pushes its identifier in the OS CAM line. Emulate the 211 * same behavior under QEMU. 212 */ 213 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 214 { 215 uint8_t nvt_blk; 216 uint32_t nvt_idx; 217 uint32_t nvt_cam; 218 219 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 220 221 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 222 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 223 } 224 225 static void spapr_xive_end_reset(XiveEND *end) 226 { 227 memset(end, 0, sizeof(*end)); 228 229 /* switch off the escalation and notification ESBs */ 230 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 231 } 232 233 static void spapr_xive_reset(void *dev) 234 { 235 SpaprXive *xive = SPAPR_XIVE(dev); 236 int i; 237 238 /* 239 * The XiveSource has its own reset handler, which mask off all 240 * IRQs (!P|Q) 241 */ 242 243 /* Mask all valid EASs in the IRQ number space. */ 244 for (i = 0; i < xive->nr_irqs; i++) { 245 XiveEAS *eas = &xive->eat[i]; 246 if (xive_eas_is_valid(eas)) { 247 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 248 } else { 249 eas->w = 0; 250 } 251 } 252 253 /* Clear all ENDs */ 254 for (i = 0; i < xive->nr_ends; i++) { 255 spapr_xive_end_reset(&xive->endt[i]); 256 } 257 } 258 259 static void spapr_xive_instance_init(Object *obj) 260 { 261 SpaprXive *xive = SPAPR_XIVE(obj); 262 263 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 264 TYPE_XIVE_SOURCE, &error_abort, NULL); 265 266 object_initialize_child(obj, "end_source", &xive->end_source, 267 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 268 &error_abort, NULL); 269 270 /* Not connected to the KVM XIVE device */ 271 xive->fd = -1; 272 } 273 274 static void spapr_xive_realize(DeviceState *dev, Error **errp) 275 { 276 SpaprXive *xive = SPAPR_XIVE(dev); 277 XiveSource *xsrc = &xive->source; 278 XiveENDSource *end_xsrc = &xive->end_source; 279 Error *local_err = NULL; 280 281 if (!xive->nr_irqs) { 282 error_setg(errp, "Number of interrupt needs to be greater 0"); 283 return; 284 } 285 286 if (!xive->nr_ends) { 287 error_setg(errp, "Number of interrupt needs to be greater 0"); 288 return; 289 } 290 291 /* 292 * Initialize the internal sources, for IPIs and virtual devices. 293 */ 294 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 295 &error_fatal); 296 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 297 &error_fatal); 298 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 299 if (local_err) { 300 error_propagate(errp, local_err); 301 return; 302 } 303 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 304 305 /* 306 * Initialize the END ESB source 307 */ 308 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 309 &error_fatal); 310 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 311 &error_fatal); 312 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 313 if (local_err) { 314 error_propagate(errp, local_err); 315 return; 316 } 317 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 318 319 /* Set the mapping address of the END ESB pages after the source ESBs */ 320 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 321 322 /* 323 * Allocate the routing tables 324 */ 325 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 326 xive->endt = g_new0(XiveEND, xive->nr_ends); 327 328 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 329 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 330 331 qemu_register_reset(spapr_xive_reset, dev); 332 333 /* TIMA initialization */ 334 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 335 "xive.tima", 4ull << TM_SHIFT); 336 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 337 338 /* 339 * Map all regions. These will be enabled or disabled at reset and 340 * can also be overridden by KVM memory regions if active 341 */ 342 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 343 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 344 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 345 } 346 347 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 348 uint32_t eas_idx, XiveEAS *eas) 349 { 350 SpaprXive *xive = SPAPR_XIVE(xrtr); 351 352 if (eas_idx >= xive->nr_irqs) { 353 return -1; 354 } 355 356 *eas = xive->eat[eas_idx]; 357 return 0; 358 } 359 360 static int spapr_xive_get_end(XiveRouter *xrtr, 361 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 362 { 363 SpaprXive *xive = SPAPR_XIVE(xrtr); 364 365 if (end_idx >= xive->nr_ends) { 366 return -1; 367 } 368 369 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 370 return 0; 371 } 372 373 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 374 uint32_t end_idx, XiveEND *end, 375 uint8_t word_number) 376 { 377 SpaprXive *xive = SPAPR_XIVE(xrtr); 378 379 if (end_idx >= xive->nr_ends) { 380 return -1; 381 } 382 383 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 384 return 0; 385 } 386 387 static int spapr_xive_get_nvt(XiveRouter *xrtr, 388 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 389 { 390 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 391 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 392 393 if (!cpu) { 394 /* TODO: should we assert() if we can find a NVT ? */ 395 return -1; 396 } 397 398 /* 399 * sPAPR does not maintain a NVT table. Return that the NVT is 400 * valid if we have found a matching CPU 401 */ 402 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 403 return 0; 404 } 405 406 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 407 uint32_t nvt_idx, XiveNVT *nvt, 408 uint8_t word_number) 409 { 410 /* 411 * We don't need to write back to the NVTs because the sPAPR 412 * machine should never hit a non-scheduled NVT. It should never 413 * get called. 414 */ 415 g_assert_not_reached(); 416 } 417 418 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 419 { 420 PowerPCCPU *cpu = POWERPC_CPU(cs); 421 422 return spapr_cpu_state(cpu)->tctx; 423 } 424 425 static const VMStateDescription vmstate_spapr_xive_end = { 426 .name = TYPE_SPAPR_XIVE "/end", 427 .version_id = 1, 428 .minimum_version_id = 1, 429 .fields = (VMStateField []) { 430 VMSTATE_UINT32(w0, XiveEND), 431 VMSTATE_UINT32(w1, XiveEND), 432 VMSTATE_UINT32(w2, XiveEND), 433 VMSTATE_UINT32(w3, XiveEND), 434 VMSTATE_UINT32(w4, XiveEND), 435 VMSTATE_UINT32(w5, XiveEND), 436 VMSTATE_UINT32(w6, XiveEND), 437 VMSTATE_UINT32(w7, XiveEND), 438 VMSTATE_END_OF_LIST() 439 }, 440 }; 441 442 static const VMStateDescription vmstate_spapr_xive_eas = { 443 .name = TYPE_SPAPR_XIVE "/eas", 444 .version_id = 1, 445 .minimum_version_id = 1, 446 .fields = (VMStateField []) { 447 VMSTATE_UINT64(w, XiveEAS), 448 VMSTATE_END_OF_LIST() 449 }, 450 }; 451 452 static int vmstate_spapr_xive_pre_save(void *opaque) 453 { 454 if (kvm_irqchip_in_kernel()) { 455 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 456 } 457 458 return 0; 459 } 460 461 /* 462 * Called by the sPAPR IRQ backend 'post_load' method at the machine 463 * level. 464 */ 465 static int spapr_xive_post_load(SpaprInterruptController *intc, int version_id) 466 { 467 if (kvm_irqchip_in_kernel()) { 468 return kvmppc_xive_post_load(SPAPR_XIVE(intc), version_id); 469 } 470 471 return 0; 472 } 473 474 static const VMStateDescription vmstate_spapr_xive = { 475 .name = TYPE_SPAPR_XIVE, 476 .version_id = 1, 477 .minimum_version_id = 1, 478 .pre_save = vmstate_spapr_xive_pre_save, 479 .post_load = NULL, /* handled at the machine level */ 480 .fields = (VMStateField[]) { 481 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 482 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 483 vmstate_spapr_xive_eas, XiveEAS), 484 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 485 vmstate_spapr_xive_end, XiveEND), 486 VMSTATE_END_OF_LIST() 487 }, 488 }; 489 490 static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, 491 bool lsi, Error **errp) 492 { 493 SpaprXive *xive = SPAPR_XIVE(intc); 494 XiveSource *xsrc = &xive->source; 495 496 assert(lisn < xive->nr_irqs); 497 498 if (xive_eas_is_valid(&xive->eat[lisn])) { 499 error_setg(errp, "IRQ %d is not free", lisn); 500 return -EBUSY; 501 } 502 503 /* 504 * Set default values when allocating an IRQ number 505 */ 506 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); 507 if (lsi) { 508 xive_source_irq_set_lsi(xsrc, lisn); 509 } 510 511 if (kvm_irqchip_in_kernel()) { 512 return kvmppc_xive_source_reset_one(xsrc, lisn, errp); 513 } 514 515 return 0; 516 } 517 518 static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) 519 { 520 SpaprXive *xive = SPAPR_XIVE(intc); 521 assert(lisn < xive->nr_irqs); 522 523 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 524 } 525 526 static Property spapr_xive_properties[] = { 527 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 528 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 529 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 530 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 531 DEFINE_PROP_END_OF_LIST(), 532 }; 533 534 static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 535 PowerPCCPU *cpu, Error **errp) 536 { 537 SpaprXive *xive = SPAPR_XIVE(intc); 538 Object *obj; 539 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 540 541 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp); 542 if (!obj) { 543 return -1; 544 } 545 546 spapr_cpu->tctx = XIVE_TCTX(obj); 547 548 /* 549 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they 550 * don't beneficiate from the reset of the XIVE IRQ backend 551 */ 552 spapr_xive_set_tctx_os_cam(spapr_cpu->tctx); 553 return 0; 554 } 555 556 static void spapr_xive_cpu_intc_reset(SpaprInterruptController *intc, 557 PowerPCCPU *cpu) 558 { 559 XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx; 560 561 xive_tctx_reset(tctx); 562 } 563 564 static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val) 565 { 566 SpaprXive *xive = SPAPR_XIVE(intc); 567 568 if (kvm_irqchip_in_kernel()) { 569 kvmppc_xive_source_set_irq(&xive->source, irq, val); 570 } else { 571 xive_source_set_irq(&xive->source, irq, val); 572 } 573 } 574 575 static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor *mon) 576 { 577 SpaprXive *xive = SPAPR_XIVE(intc); 578 CPUState *cs; 579 580 CPU_FOREACH(cs) { 581 PowerPCCPU *cpu = POWERPC_CPU(cs); 582 583 xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); 584 } 585 586 spapr_xive_pic_print_info(xive, mon); 587 } 588 589 static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers, 590 void *fdt, uint32_t phandle) 591 { 592 SpaprXive *xive = SPAPR_XIVE(intc); 593 int node; 594 uint64_t timas[2 * 2]; 595 /* Interrupt number ranges for the IPIs */ 596 uint32_t lisn_ranges[] = { 597 cpu_to_be32(0), 598 cpu_to_be32(nr_servers), 599 }; 600 /* 601 * EQ size - the sizes of pages supported by the system 4K, 64K, 602 * 2M, 16M. We only advertise 64K for the moment. 603 */ 604 uint32_t eq_sizes[] = { 605 cpu_to_be32(16), /* 64K */ 606 }; 607 /* 608 * The following array is in sync with the reserved priorities 609 * defined by the 'spapr_xive_priority_is_reserved' routine. 610 */ 611 uint32_t plat_res_int_priorities[] = { 612 cpu_to_be32(7), /* start */ 613 cpu_to_be32(0xf8), /* count */ 614 }; 615 616 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 617 timas[0] = cpu_to_be64(xive->tm_base + 618 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 619 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 620 timas[2] = cpu_to_be64(xive->tm_base + 621 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 622 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 623 624 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 625 626 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 627 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 628 629 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 630 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 631 sizeof(eq_sizes))); 632 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 633 sizeof(lisn_ranges))); 634 635 /* For Linux to link the LSIs to the interrupt controller. */ 636 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 637 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 638 639 /* For SLOF */ 640 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 641 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 642 643 /* 644 * The "ibm,plat-res-int-priorities" property defines the priority 645 * ranges reserved by the hypervisor 646 */ 647 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 648 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 649 } 650 651 static int spapr_xive_activate(SpaprInterruptController *intc, Error **errp) 652 { 653 SpaprXive *xive = SPAPR_XIVE(intc); 654 CPUState *cs; 655 656 CPU_FOREACH(cs) { 657 PowerPCCPU *cpu = POWERPC_CPU(cs); 658 659 /* (TCG) Set the OS CAM line of the thread interrupt context. */ 660 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx); 661 } 662 663 if (kvm_enabled()) { 664 int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, errp); 665 if (rc < 0) { 666 return rc; 667 } 668 } 669 670 /* Activate the XIVE MMIOs */ 671 spapr_xive_mmio_set_enabled(xive, true); 672 673 return 0; 674 } 675 676 static void spapr_xive_deactivate(SpaprInterruptController *intc) 677 { 678 SpaprXive *xive = SPAPR_XIVE(intc); 679 680 spapr_xive_mmio_set_enabled(xive, false); 681 682 if (kvm_irqchip_in_kernel()) { 683 kvmppc_xive_disconnect(intc); 684 } 685 } 686 687 static void spapr_xive_class_init(ObjectClass *klass, void *data) 688 { 689 DeviceClass *dc = DEVICE_CLASS(klass); 690 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 691 SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); 692 693 dc->desc = "sPAPR XIVE Interrupt Controller"; 694 dc->props = spapr_xive_properties; 695 dc->realize = spapr_xive_realize; 696 dc->vmsd = &vmstate_spapr_xive; 697 698 xrc->get_eas = spapr_xive_get_eas; 699 xrc->get_end = spapr_xive_get_end; 700 xrc->write_end = spapr_xive_write_end; 701 xrc->get_nvt = spapr_xive_get_nvt; 702 xrc->write_nvt = spapr_xive_write_nvt; 703 xrc->get_tctx = spapr_xive_get_tctx; 704 705 sicc->activate = spapr_xive_activate; 706 sicc->deactivate = spapr_xive_deactivate; 707 sicc->cpu_intc_create = spapr_xive_cpu_intc_create; 708 sicc->cpu_intc_reset = spapr_xive_cpu_intc_reset; 709 sicc->claim_irq = spapr_xive_claim_irq; 710 sicc->free_irq = spapr_xive_free_irq; 711 sicc->set_irq = spapr_xive_set_irq; 712 sicc->print_info = spapr_xive_print_info; 713 sicc->dt = spapr_xive_dt; 714 sicc->post_load = spapr_xive_post_load; 715 } 716 717 static const TypeInfo spapr_xive_info = { 718 .name = TYPE_SPAPR_XIVE, 719 .parent = TYPE_XIVE_ROUTER, 720 .instance_init = spapr_xive_instance_init, 721 .instance_size = sizeof(SpaprXive), 722 .class_init = spapr_xive_class_init, 723 .interfaces = (InterfaceInfo[]) { 724 { TYPE_SPAPR_INTC }, 725 { } 726 }, 727 }; 728 729 static void spapr_xive_register_types(void) 730 { 731 type_register_static(&spapr_xive_info); 732 } 733 734 type_init(spapr_xive_register_types) 735 736 /* 737 * XIVE hcalls 738 * 739 * The terminology used by the XIVE hcalls is the following : 740 * 741 * TARGET vCPU number 742 * EQ Event Queue assigned by OS to receive event data 743 * ESB page for source interrupt management 744 * LISN Logical Interrupt Source Number identifying a source in the 745 * machine 746 * EISN Effective Interrupt Source Number used by guest OS to 747 * identify source in the guest 748 * 749 * The EAS, END, NVT structures are not exposed. 750 */ 751 752 /* 753 * Linux hosts under OPAL reserve priority 7 for their own escalation 754 * interrupts (DD2.X POWER9). So we only allow the guest to use 755 * priorities [0..6]. 756 */ 757 static bool spapr_xive_priority_is_reserved(uint8_t priority) 758 { 759 switch (priority) { 760 case 0 ... 6: 761 return false; 762 case 7: /* OPAL escalation queue */ 763 default: 764 return true; 765 } 766 } 767 768 /* 769 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 770 * real address of the MMIO page through which the Event State Buffer 771 * entry associated with the value of the "lisn" parameter is managed. 772 * 773 * Parameters: 774 * Input 775 * - R4: "flags" 776 * Bits 0-63 reserved 777 * - R5: "lisn" is per "interrupts", "interrupt-map", or 778 * "ibm,xive-lisn-ranges" properties, or as returned by the 779 * ibm,query-interrupt-source-number RTAS call, or as returned 780 * by the H_ALLOCATE_VAS_WINDOW hcall 781 * 782 * Output 783 * - R4: "flags" 784 * Bits 0-59: Reserved 785 * Bit 60: H_INT_ESB must be used for Event State Buffer 786 * management 787 * Bit 61: 1 == LSI 0 == MSI 788 * Bit 62: the full function page supports trigger 789 * Bit 63: Store EOI Supported 790 * - R5: Logical Real address of full function Event State Buffer 791 * management page, -1 if H_INT_ESB hcall flag is set to 1. 792 * - R6: Logical Real Address of trigger only Event State Buffer 793 * management page or -1. 794 * - R7: Power of 2 page size for the ESB management pages returned in 795 * R5 and R6. 796 */ 797 798 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 799 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 800 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 801 on same page */ 802 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 803 804 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 805 SpaprMachineState *spapr, 806 target_ulong opcode, 807 target_ulong *args) 808 { 809 SpaprXive *xive = spapr->xive; 810 XiveSource *xsrc = &xive->source; 811 target_ulong flags = args[0]; 812 target_ulong lisn = args[1]; 813 814 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 815 return H_FUNCTION; 816 } 817 818 if (flags) { 819 return H_PARAMETER; 820 } 821 822 if (lisn >= xive->nr_irqs) { 823 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 824 lisn); 825 return H_P2; 826 } 827 828 if (!xive_eas_is_valid(&xive->eat[lisn])) { 829 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 830 lisn); 831 return H_P2; 832 } 833 834 /* 835 * All sources are emulated under the main XIVE object and share 836 * the same characteristics. 837 */ 838 args[0] = 0; 839 if (!xive_source_esb_has_2page(xsrc)) { 840 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 841 } 842 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 843 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 844 } 845 846 /* 847 * Force the use of the H_INT_ESB hcall in case of an LSI 848 * interrupt. This is necessary under KVM to re-trigger the 849 * interrupt if the level is still asserted 850 */ 851 if (xive_source_irq_is_lsi(xsrc, lisn)) { 852 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 853 } 854 855 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 856 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 857 } else { 858 args[1] = -1; 859 } 860 861 if (xive_source_esb_has_2page(xsrc) && 862 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 863 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 864 } else { 865 args[2] = -1; 866 } 867 868 if (xive_source_esb_has_2page(xsrc)) { 869 args[3] = xsrc->esb_shift - 1; 870 } else { 871 args[3] = xsrc->esb_shift; 872 } 873 874 return H_SUCCESS; 875 } 876 877 /* 878 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 879 * Interrupt Source to a target. The Logical Interrupt Source is 880 * designated with the "lisn" parameter and the target is designated 881 * with the "target" and "priority" parameters. Upon return from the 882 * hcall(), no additional interrupts will be directed to the old EQ. 883 * 884 * Parameters: 885 * Input: 886 * - R4: "flags" 887 * Bits 0-61: Reserved 888 * Bit 62: set the "eisn" in the EAS 889 * Bit 63: masks the interrupt source in the hardware interrupt 890 * control structure. An interrupt masked by this mechanism will 891 * be dropped, but it's source state bits will still be 892 * set. There is no race-free way of unmasking and restoring the 893 * source. Thus this should only be used in interrupts that are 894 * also masked at the source, and only in cases where the 895 * interrupt is not meant to be used for a large amount of time 896 * because no valid target exists for it for example 897 * - R5: "lisn" is per "interrupts", "interrupt-map", or 898 * "ibm,xive-lisn-ranges" properties, or as returned by the 899 * ibm,query-interrupt-source-number RTAS call, or as returned by 900 * the H_ALLOCATE_VAS_WINDOW hcall 901 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 902 * "ibm,ppc-interrupt-gserver#s" 903 * - R7: "priority" is a valid priority not in 904 * "ibm,plat-res-int-priorities" 905 * - R8: "eisn" is the guest EISN associated with the "lisn" 906 * 907 * Output: 908 * - None 909 */ 910 911 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 912 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 913 914 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 915 SpaprMachineState *spapr, 916 target_ulong opcode, 917 target_ulong *args) 918 { 919 SpaprXive *xive = spapr->xive; 920 XiveEAS eas, new_eas; 921 target_ulong flags = args[0]; 922 target_ulong lisn = args[1]; 923 target_ulong target = args[2]; 924 target_ulong priority = args[3]; 925 target_ulong eisn = args[4]; 926 uint8_t end_blk; 927 uint32_t end_idx; 928 929 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 930 return H_FUNCTION; 931 } 932 933 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 934 return H_PARAMETER; 935 } 936 937 if (lisn >= xive->nr_irqs) { 938 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 939 lisn); 940 return H_P2; 941 } 942 943 eas = xive->eat[lisn]; 944 if (!xive_eas_is_valid(&eas)) { 945 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 946 lisn); 947 return H_P2; 948 } 949 950 /* priority 0xff is used to reset the EAS */ 951 if (priority == 0xff) { 952 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 953 goto out; 954 } 955 956 if (flags & SPAPR_XIVE_SRC_MASK) { 957 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 958 } else { 959 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 960 } 961 962 if (spapr_xive_priority_is_reserved(priority)) { 963 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 964 " is reserved\n", priority); 965 return H_P4; 966 } 967 968 /* 969 * Validate that "target" is part of the list of threads allocated 970 * to the partition. For that, find the END corresponding to the 971 * target. 972 */ 973 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 974 return H_P3; 975 } 976 977 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 978 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 979 980 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 981 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 982 } 983 984 if (kvm_irqchip_in_kernel()) { 985 Error *local_err = NULL; 986 987 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 988 if (local_err) { 989 error_report_err(local_err); 990 return H_HARDWARE; 991 } 992 } 993 994 out: 995 xive->eat[lisn] = new_eas; 996 return H_SUCCESS; 997 } 998 999 /* 1000 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 1001 * target/priority pair is assigned to the specified Logical Interrupt 1002 * Source. 1003 * 1004 * Parameters: 1005 * Input: 1006 * - R4: "flags" 1007 * Bits 0-63 Reserved 1008 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1009 * "ibm,xive-lisn-ranges" properties, or as returned by the 1010 * ibm,query-interrupt-source-number RTAS call, or as 1011 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1012 * 1013 * Output: 1014 * - R4: Target to which the specified Logical Interrupt Source is 1015 * assigned 1016 * - R5: Priority to which the specified Logical Interrupt Source is 1017 * assigned 1018 * - R6: EISN for the specified Logical Interrupt Source (this will be 1019 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 1020 */ 1021 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 1022 SpaprMachineState *spapr, 1023 target_ulong opcode, 1024 target_ulong *args) 1025 { 1026 SpaprXive *xive = spapr->xive; 1027 target_ulong flags = args[0]; 1028 target_ulong lisn = args[1]; 1029 XiveEAS eas; 1030 XiveEND *end; 1031 uint8_t nvt_blk; 1032 uint32_t end_idx, nvt_idx; 1033 1034 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1035 return H_FUNCTION; 1036 } 1037 1038 if (flags) { 1039 return H_PARAMETER; 1040 } 1041 1042 if (lisn >= xive->nr_irqs) { 1043 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1044 lisn); 1045 return H_P2; 1046 } 1047 1048 eas = xive->eat[lisn]; 1049 if (!xive_eas_is_valid(&eas)) { 1050 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1051 lisn); 1052 return H_P2; 1053 } 1054 1055 /* EAS_END_BLOCK is unused on sPAPR */ 1056 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 1057 1058 assert(end_idx < xive->nr_ends); 1059 end = &xive->endt[end_idx]; 1060 1061 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1062 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1063 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 1064 1065 if (xive_eas_is_masked(&eas)) { 1066 args[1] = 0xff; 1067 } else { 1068 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1069 } 1070 1071 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 1072 1073 return H_SUCCESS; 1074 } 1075 1076 /* 1077 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 1078 * address of the notification management page associated with the 1079 * specified target and priority. 1080 * 1081 * Parameters: 1082 * Input: 1083 * - R4: "flags" 1084 * Bits 0-63 Reserved 1085 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1086 * "ibm,ppc-interrupt-gserver#s" 1087 * - R6: "priority" is a valid priority not in 1088 * "ibm,plat-res-int-priorities" 1089 * 1090 * Output: 1091 * - R4: Logical real address of notification page 1092 * - R5: Power of 2 page size of the notification page 1093 */ 1094 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 1095 SpaprMachineState *spapr, 1096 target_ulong opcode, 1097 target_ulong *args) 1098 { 1099 SpaprXive *xive = spapr->xive; 1100 XiveENDSource *end_xsrc = &xive->end_source; 1101 target_ulong flags = args[0]; 1102 target_ulong target = args[1]; 1103 target_ulong priority = args[2]; 1104 XiveEND *end; 1105 uint8_t end_blk; 1106 uint32_t end_idx; 1107 1108 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1109 return H_FUNCTION; 1110 } 1111 1112 if (flags) { 1113 return H_PARAMETER; 1114 } 1115 1116 /* 1117 * H_STATE should be returned if a H_INT_RESET is in progress. 1118 * This is not needed when running the emulation under QEMU 1119 */ 1120 1121 if (spapr_xive_priority_is_reserved(priority)) { 1122 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1123 " is reserved\n", priority); 1124 return H_P3; 1125 } 1126 1127 /* 1128 * Validate that "target" is part of the list of threads allocated 1129 * to the partition. For that, find the END corresponding to the 1130 * target. 1131 */ 1132 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1133 return H_P2; 1134 } 1135 1136 assert(end_idx < xive->nr_ends); 1137 end = &xive->endt[end_idx]; 1138 1139 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 1140 if (xive_end_is_enqueue(end)) { 1141 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1142 } else { 1143 args[1] = 0; 1144 } 1145 1146 return H_SUCCESS; 1147 } 1148 1149 /* 1150 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 1151 * a given "target" and "priority". It is also used to set the 1152 * notification config associated with the EQ. An EQ size of 0 is 1153 * used to reset the EQ config for a given target and priority. If 1154 * resetting the EQ config, the END associated with the given "target" 1155 * and "priority" will be changed to disable queueing. 1156 * 1157 * Upon return from the hcall(), no additional interrupts will be 1158 * directed to the old EQ (if one was set). The old EQ (if one was 1159 * set) should be investigated for interrupts that occurred prior to 1160 * or during the hcall(). 1161 * 1162 * Parameters: 1163 * Input: 1164 * - R4: "flags" 1165 * Bits 0-62: Reserved 1166 * Bit 63: Unconditional Notify (n) per the XIVE spec 1167 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1168 * "ibm,ppc-interrupt-gserver#s" 1169 * - R6: "priority" is a valid priority not in 1170 * "ibm,plat-res-int-priorities" 1171 * - R7: "eventQueue": The logical real address of the start of the EQ 1172 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1173 * 1174 * Output: 1175 * - None 1176 */ 1177 1178 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1179 1180 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1181 SpaprMachineState *spapr, 1182 target_ulong opcode, 1183 target_ulong *args) 1184 { 1185 SpaprXive *xive = spapr->xive; 1186 target_ulong flags = args[0]; 1187 target_ulong target = args[1]; 1188 target_ulong priority = args[2]; 1189 target_ulong qpage = args[3]; 1190 target_ulong qsize = args[4]; 1191 XiveEND end; 1192 uint8_t end_blk, nvt_blk; 1193 uint32_t end_idx, nvt_idx; 1194 1195 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1196 return H_FUNCTION; 1197 } 1198 1199 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1200 return H_PARAMETER; 1201 } 1202 1203 /* 1204 * H_STATE should be returned if a H_INT_RESET is in progress. 1205 * This is not needed when running the emulation under QEMU 1206 */ 1207 1208 if (spapr_xive_priority_is_reserved(priority)) { 1209 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1210 " is reserved\n", priority); 1211 return H_P3; 1212 } 1213 1214 /* 1215 * Validate that "target" is part of the list of threads allocated 1216 * to the partition. For that, find the END corresponding to the 1217 * target. 1218 */ 1219 1220 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1221 return H_P2; 1222 } 1223 1224 assert(end_idx < xive->nr_ends); 1225 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1226 1227 switch (qsize) { 1228 case 12: 1229 case 16: 1230 case 21: 1231 case 24: 1232 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1233 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1234 " is not naturally aligned with %" HWADDR_PRIx "\n", 1235 qpage, (hwaddr)1 << qsize); 1236 return H_P4; 1237 } 1238 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1239 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1240 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1241 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1242 break; 1243 case 0: 1244 /* reset queue and disable queueing */ 1245 spapr_xive_end_reset(&end); 1246 goto out; 1247 1248 default: 1249 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1250 qsize); 1251 return H_P5; 1252 } 1253 1254 if (qsize) { 1255 hwaddr plen = 1 << qsize; 1256 void *eq; 1257 1258 /* 1259 * Validate the guest EQ. We should also check that the queue 1260 * has been zeroed by the OS. 1261 */ 1262 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1263 MEMTXATTRS_UNSPECIFIED); 1264 if (plen != 1 << qsize) { 1265 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1266 HWADDR_PRIx "\n", qpage); 1267 return H_P4; 1268 } 1269 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1270 } 1271 1272 /* "target" should have been validated above */ 1273 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1274 g_assert_not_reached(); 1275 } 1276 1277 /* 1278 * Ensure the priority and target are correctly set (they will not 1279 * be right after allocation) 1280 */ 1281 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1282 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1283 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1284 1285 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1286 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1287 } else { 1288 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1289 } 1290 1291 /* 1292 * The generation bit for the END starts at 1 and The END page 1293 * offset counter starts at 0. 1294 */ 1295 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1296 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1297 end.w0 |= cpu_to_be32(END_W0_VALID); 1298 1299 /* 1300 * TODO: issue syncs required to ensure all in-flight interrupts 1301 * are complete on the old END 1302 */ 1303 1304 out: 1305 if (kvm_irqchip_in_kernel()) { 1306 Error *local_err = NULL; 1307 1308 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1309 if (local_err) { 1310 error_report_err(local_err); 1311 return H_HARDWARE; 1312 } 1313 } 1314 1315 /* Update END */ 1316 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1317 return H_SUCCESS; 1318 } 1319 1320 /* 1321 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1322 * target and priority. 1323 * 1324 * Parameters: 1325 * Input: 1326 * - R4: "flags" 1327 * Bits 0-62: Reserved 1328 * Bit 63: Debug: Return debug data 1329 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1330 * "ibm,ppc-interrupt-gserver#s" 1331 * - R6: "priority" is a valid priority not in 1332 * "ibm,plat-res-int-priorities" 1333 * 1334 * Output: 1335 * - R4: "flags": 1336 * Bits 0-61: Reserved 1337 * Bit 62: The value of Event Queue Generation Number (g) per 1338 * the XIVE spec if "Debug" = 1 1339 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1340 * - R5: The logical real address of the start of the EQ 1341 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1342 * - R7: The value of Event Queue Offset Counter per XIVE spec 1343 * if "Debug" = 1, else 0 1344 * 1345 */ 1346 1347 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1348 1349 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1350 SpaprMachineState *spapr, 1351 target_ulong opcode, 1352 target_ulong *args) 1353 { 1354 SpaprXive *xive = spapr->xive; 1355 target_ulong flags = args[0]; 1356 target_ulong target = args[1]; 1357 target_ulong priority = args[2]; 1358 XiveEND *end; 1359 uint8_t end_blk; 1360 uint32_t end_idx; 1361 1362 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1363 return H_FUNCTION; 1364 } 1365 1366 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1367 return H_PARAMETER; 1368 } 1369 1370 /* 1371 * H_STATE should be returned if a H_INT_RESET is in progress. 1372 * This is not needed when running the emulation under QEMU 1373 */ 1374 1375 if (spapr_xive_priority_is_reserved(priority)) { 1376 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1377 " is reserved\n", priority); 1378 return H_P3; 1379 } 1380 1381 /* 1382 * Validate that "target" is part of the list of threads allocated 1383 * to the partition. For that, find the END corresponding to the 1384 * target. 1385 */ 1386 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1387 return H_P2; 1388 } 1389 1390 assert(end_idx < xive->nr_ends); 1391 end = &xive->endt[end_idx]; 1392 1393 args[0] = 0; 1394 if (xive_end_is_notify(end)) { 1395 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1396 } 1397 1398 if (xive_end_is_enqueue(end)) { 1399 args[1] = xive_end_qaddr(end); 1400 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1401 } else { 1402 args[1] = 0; 1403 args[2] = 0; 1404 } 1405 1406 if (kvm_irqchip_in_kernel()) { 1407 Error *local_err = NULL; 1408 1409 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1410 if (local_err) { 1411 error_report_err(local_err); 1412 return H_HARDWARE; 1413 } 1414 } 1415 1416 /* TODO: do we need any locking on the END ? */ 1417 if (flags & SPAPR_XIVE_END_DEBUG) { 1418 /* Load the event queue generation number into the return flags */ 1419 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1420 1421 /* Load R7 with the event queue offset counter */ 1422 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1423 } else { 1424 args[3] = 0; 1425 } 1426 1427 return H_SUCCESS; 1428 } 1429 1430 /* 1431 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1432 * reporting cache line pair for the calling thread. The reporting 1433 * cache lines will contain the OS interrupt context when the OS 1434 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1435 * interrupt. The reporting cache lines can be reset by inputting -1 1436 * in "reportingLine". Issuing the CI store byte without reporting 1437 * cache lines registered will result in the data not being accessible 1438 * to the OS. 1439 * 1440 * Parameters: 1441 * Input: 1442 * - R4: "flags" 1443 * Bits 0-63: Reserved 1444 * - R5: "reportingLine": The logical real address of the reporting cache 1445 * line pair 1446 * 1447 * Output: 1448 * - None 1449 */ 1450 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1451 SpaprMachineState *spapr, 1452 target_ulong opcode, 1453 target_ulong *args) 1454 { 1455 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1456 return H_FUNCTION; 1457 } 1458 1459 /* 1460 * H_STATE should be returned if a H_INT_RESET is in progress. 1461 * This is not needed when running the emulation under QEMU 1462 */ 1463 1464 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1465 return H_FUNCTION; 1466 } 1467 1468 /* 1469 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1470 * real address of the reporting cache line pair set for the input 1471 * "target". If no reporting cache line pair has been set, -1 is 1472 * returned. 1473 * 1474 * Parameters: 1475 * Input: 1476 * - R4: "flags" 1477 * Bits 0-63: Reserved 1478 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1479 * "ibm,ppc-interrupt-gserver#s" 1480 * - R6: "reportingLine": The logical real address of the reporting 1481 * cache line pair 1482 * 1483 * Output: 1484 * - R4: The logical real address of the reporting line if set, else -1 1485 */ 1486 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1487 SpaprMachineState *spapr, 1488 target_ulong opcode, 1489 target_ulong *args) 1490 { 1491 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1492 return H_FUNCTION; 1493 } 1494 1495 /* 1496 * H_STATE should be returned if a H_INT_RESET is in progress. 1497 * This is not needed when running the emulation under QEMU 1498 */ 1499 1500 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1501 return H_FUNCTION; 1502 } 1503 1504 /* 1505 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1506 * page for the input "lisn". This hcall is only supported for LISNs 1507 * that have the ESB hcall flag set to 1 when returned from hcall() 1508 * H_INT_GET_SOURCE_INFO. 1509 * 1510 * Parameters: 1511 * Input: 1512 * - R4: "flags" 1513 * Bits 0-62: Reserved 1514 * bit 63: Store: Store=1, store operation, else load operation 1515 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1516 * "ibm,xive-lisn-ranges" properties, or as returned by the 1517 * ibm,query-interrupt-source-number RTAS call, or as 1518 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1519 * - R6: "esbOffset" is the offset into the ESB page for the load or 1520 * store operation 1521 * - R7: "storeData" is the data to write for a store operation 1522 * 1523 * Output: 1524 * - R4: The value of the load if load operation, else -1 1525 */ 1526 1527 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1528 1529 static target_ulong h_int_esb(PowerPCCPU *cpu, 1530 SpaprMachineState *spapr, 1531 target_ulong opcode, 1532 target_ulong *args) 1533 { 1534 SpaprXive *xive = spapr->xive; 1535 XiveEAS eas; 1536 target_ulong flags = args[0]; 1537 target_ulong lisn = args[1]; 1538 target_ulong offset = args[2]; 1539 target_ulong data = args[3]; 1540 hwaddr mmio_addr; 1541 XiveSource *xsrc = &xive->source; 1542 1543 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1544 return H_FUNCTION; 1545 } 1546 1547 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1548 return H_PARAMETER; 1549 } 1550 1551 if (lisn >= xive->nr_irqs) { 1552 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1553 lisn); 1554 return H_P2; 1555 } 1556 1557 eas = xive->eat[lisn]; 1558 if (!xive_eas_is_valid(&eas)) { 1559 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1560 lisn); 1561 return H_P2; 1562 } 1563 1564 if (offset > (1ull << xsrc->esb_shift)) { 1565 return H_P3; 1566 } 1567 1568 if (kvm_irqchip_in_kernel()) { 1569 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1570 flags & SPAPR_XIVE_ESB_STORE); 1571 } else { 1572 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1573 1574 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1575 (flags & SPAPR_XIVE_ESB_STORE))) { 1576 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1577 HWADDR_PRIx "\n", mmio_addr); 1578 return H_HARDWARE; 1579 } 1580 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1581 } 1582 return H_SUCCESS; 1583 } 1584 1585 /* 1586 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1587 * ensure any in flight events for the input lisn are in the event 1588 * queue. 1589 * 1590 * Parameters: 1591 * Input: 1592 * - R4: "flags" 1593 * Bits 0-63: Reserved 1594 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1595 * "ibm,xive-lisn-ranges" properties, or as returned by the 1596 * ibm,query-interrupt-source-number RTAS call, or as 1597 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1598 * 1599 * Output: 1600 * - None 1601 */ 1602 static target_ulong h_int_sync(PowerPCCPU *cpu, 1603 SpaprMachineState *spapr, 1604 target_ulong opcode, 1605 target_ulong *args) 1606 { 1607 SpaprXive *xive = spapr->xive; 1608 XiveEAS eas; 1609 target_ulong flags = args[0]; 1610 target_ulong lisn = args[1]; 1611 1612 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1613 return H_FUNCTION; 1614 } 1615 1616 if (flags) { 1617 return H_PARAMETER; 1618 } 1619 1620 if (lisn >= xive->nr_irqs) { 1621 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1622 lisn); 1623 return H_P2; 1624 } 1625 1626 eas = xive->eat[lisn]; 1627 if (!xive_eas_is_valid(&eas)) { 1628 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1629 lisn); 1630 return H_P2; 1631 } 1632 1633 /* 1634 * H_STATE should be returned if a H_INT_RESET is in progress. 1635 * This is not needed when running the emulation under QEMU 1636 */ 1637 1638 /* 1639 * This is not real hardware. Nothing to be done unless when 1640 * under KVM 1641 */ 1642 1643 if (kvm_irqchip_in_kernel()) { 1644 Error *local_err = NULL; 1645 1646 kvmppc_xive_sync_source(xive, lisn, &local_err); 1647 if (local_err) { 1648 error_report_err(local_err); 1649 return H_HARDWARE; 1650 } 1651 } 1652 return H_SUCCESS; 1653 } 1654 1655 /* 1656 * The H_INT_RESET hcall() is used to reset all of the partition's 1657 * interrupt exploitation structures to their initial state. This 1658 * means losing all previously set interrupt state set via 1659 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1660 * 1661 * Parameters: 1662 * Input: 1663 * - R4: "flags" 1664 * Bits 0-63: Reserved 1665 * 1666 * Output: 1667 * - None 1668 */ 1669 static target_ulong h_int_reset(PowerPCCPU *cpu, 1670 SpaprMachineState *spapr, 1671 target_ulong opcode, 1672 target_ulong *args) 1673 { 1674 SpaprXive *xive = spapr->xive; 1675 target_ulong flags = args[0]; 1676 1677 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1678 return H_FUNCTION; 1679 } 1680 1681 if (flags) { 1682 return H_PARAMETER; 1683 } 1684 1685 device_reset(DEVICE(xive)); 1686 1687 if (kvm_irqchip_in_kernel()) { 1688 Error *local_err = NULL; 1689 1690 kvmppc_xive_reset(xive, &local_err); 1691 if (local_err) { 1692 error_report_err(local_err); 1693 return H_HARDWARE; 1694 } 1695 } 1696 return H_SUCCESS; 1697 } 1698 1699 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1700 { 1701 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1702 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1703 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1704 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1705 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1706 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1707 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1708 h_int_set_os_reporting_line); 1709 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1710 h_int_get_os_reporting_line); 1711 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1712 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1713 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1714 } 1715