1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "qemu/error-report.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "monitor/monitor.h" 17 #include "hw/ppc/fdt.h" 18 #include "hw/ppc/spapr.h" 19 #include "hw/ppc/spapr_cpu_core.h" 20 #include "hw/ppc/spapr_xive.h" 21 #include "hw/ppc/xive.h" 22 #include "hw/ppc/xive_regs.h" 23 24 /* 25 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 26 * use for the ESB pages and the TIMA pages 27 */ 28 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 29 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 30 31 /* 32 * The allocation of VP blocks is a complex operation in OPAL and the 33 * VP identifiers have a relation with the number of HW chips, the 34 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 35 * controller model does not have the same constraints and can use a 36 * simple mapping scheme of the CPU vcpu_id 37 * 38 * These identifiers are never returned to the OS. 39 */ 40 41 #define SPAPR_XIVE_NVT_BASE 0x400 42 43 /* 44 * The sPAPR machine has a unique XIVE IC device. Assign a fixed value 45 * to the controller block id value. It can nevertheless be changed 46 * for testing purpose. 47 */ 48 #define SPAPR_XIVE_BLOCK_ID 0x0 49 50 /* 51 * sPAPR NVT and END indexing helpers 52 */ 53 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 54 { 55 return nvt_idx - SPAPR_XIVE_NVT_BASE; 56 } 57 58 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 59 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 60 { 61 assert(cpu); 62 63 if (out_nvt_blk) { 64 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 65 } 66 67 if (out_nvt_blk) { 68 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 69 } 70 } 71 72 static int spapr_xive_target_to_nvt(uint32_t target, 73 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 74 { 75 PowerPCCPU *cpu = spapr_find_cpu(target); 76 77 if (!cpu) { 78 return -1; 79 } 80 81 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 82 return 0; 83 } 84 85 /* 86 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 87 * priorities per CPU 88 */ 89 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 90 uint8_t *out_end_blk, uint32_t *out_end_idx) 91 { 92 assert(cpu); 93 94 if (out_end_blk) { 95 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 96 } 97 98 if (out_end_idx) { 99 *out_end_idx = (cpu->vcpu_id << 3) + prio; 100 } 101 } 102 103 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 104 uint8_t *out_end_blk, uint32_t *out_end_idx) 105 { 106 PowerPCCPU *cpu = spapr_find_cpu(target); 107 108 if (!cpu) { 109 return -1; 110 } 111 112 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 113 return 0; 114 } 115 116 /* 117 * On sPAPR machines, use a simplified output for the XIVE END 118 * structure dumping only the information related to the OS EQ. 119 */ 120 static void spapr_xive_end_pic_print_info(sPAPRXive *xive, XiveEND *end, 121 Monitor *mon) 122 { 123 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 124 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 125 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 126 uint32_t qentries = 1 << (qsize + 10); 127 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 128 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 129 130 monitor_printf(mon, "%3d/%d % 6d/%5d ^%d", 131 spapr_xive_nvt_to_target(0, nvt), 132 priority, qindex, qentries, qgen); 133 134 xive_end_queue_pic_print_info(end, 6, mon); 135 monitor_printf(mon, "]"); 136 } 137 138 void spapr_xive_pic_print_info(sPAPRXive *xive, Monitor *mon) 139 { 140 XiveSource *xsrc = &xive->source; 141 int i; 142 143 monitor_printf(mon, " LSIN PQ EISN CPU/PRIO EQ\n"); 144 145 for (i = 0; i < xive->nr_irqs; i++) { 146 uint8_t pq = xive_source_esb_get(xsrc, i); 147 XiveEAS *eas = &xive->eat[i]; 148 149 if (!xive_eas_is_valid(eas)) { 150 continue; 151 } 152 153 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 154 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 155 pq & XIVE_ESB_VAL_P ? 'P' : '-', 156 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 157 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 158 xive_eas_is_masked(eas) ? "M" : " ", 159 (int) xive_get_field64(EAS_END_DATA, eas->w)); 160 161 if (!xive_eas_is_masked(eas)) { 162 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 163 XiveEND *end; 164 165 assert(end_idx < xive->nr_ends); 166 end = &xive->endt[end_idx]; 167 168 if (xive_end_is_valid(end)) { 169 spapr_xive_end_pic_print_info(xive, end, mon); 170 } 171 } 172 monitor_printf(mon, "\n"); 173 } 174 } 175 176 static void spapr_xive_map_mmio(sPAPRXive *xive) 177 { 178 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 179 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 180 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 181 } 182 183 void spapr_xive_mmio_set_enabled(sPAPRXive *xive, bool enable) 184 { 185 memory_region_set_enabled(&xive->source.esb_mmio, enable); 186 memory_region_set_enabled(&xive->tm_mmio, enable); 187 188 /* Disable the END ESBs until a guest OS makes use of them */ 189 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 190 } 191 192 /* 193 * When a Virtual Processor is scheduled to run on a HW thread, the 194 * hypervisor pushes its identifier in the OS CAM line. Emulate the 195 * same behavior under QEMU. 196 */ 197 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 198 { 199 uint8_t nvt_blk; 200 uint32_t nvt_idx; 201 uint32_t nvt_cam; 202 203 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 204 205 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 206 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 207 } 208 209 static void spapr_xive_end_reset(XiveEND *end) 210 { 211 memset(end, 0, sizeof(*end)); 212 213 /* switch off the escalation and notification ESBs */ 214 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 215 } 216 217 static void spapr_xive_reset(void *dev) 218 { 219 sPAPRXive *xive = SPAPR_XIVE(dev); 220 int i; 221 222 /* 223 * The XiveSource has its own reset handler, which mask off all 224 * IRQs (!P|Q) 225 */ 226 227 /* Mask all valid EASs in the IRQ number space. */ 228 for (i = 0; i < xive->nr_irqs; i++) { 229 XiveEAS *eas = &xive->eat[i]; 230 if (xive_eas_is_valid(eas)) { 231 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 232 } else { 233 eas->w = 0; 234 } 235 } 236 237 /* Clear all ENDs */ 238 for (i = 0; i < xive->nr_ends; i++) { 239 spapr_xive_end_reset(&xive->endt[i]); 240 } 241 } 242 243 static void spapr_xive_instance_init(Object *obj) 244 { 245 sPAPRXive *xive = SPAPR_XIVE(obj); 246 247 object_initialize(&xive->source, sizeof(xive->source), TYPE_XIVE_SOURCE); 248 object_property_add_child(obj, "source", OBJECT(&xive->source), NULL); 249 250 object_initialize(&xive->end_source, sizeof(xive->end_source), 251 TYPE_XIVE_END_SOURCE); 252 object_property_add_child(obj, "end_source", OBJECT(&xive->end_source), 253 NULL); 254 } 255 256 static void spapr_xive_realize(DeviceState *dev, Error **errp) 257 { 258 sPAPRXive *xive = SPAPR_XIVE(dev); 259 XiveSource *xsrc = &xive->source; 260 XiveENDSource *end_xsrc = &xive->end_source; 261 Error *local_err = NULL; 262 263 if (!xive->nr_irqs) { 264 error_setg(errp, "Number of interrupt needs to be greater 0"); 265 return; 266 } 267 268 if (!xive->nr_ends) { 269 error_setg(errp, "Number of interrupt needs to be greater 0"); 270 return; 271 } 272 273 /* 274 * Initialize the internal sources, for IPIs and virtual devices. 275 */ 276 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 277 &error_fatal); 278 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 279 &error_fatal); 280 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 281 if (local_err) { 282 error_propagate(errp, local_err); 283 return; 284 } 285 286 /* 287 * Initialize the END ESB source 288 */ 289 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 290 &error_fatal); 291 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 292 &error_fatal); 293 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 294 if (local_err) { 295 error_propagate(errp, local_err); 296 return; 297 } 298 299 /* Set the mapping address of the END ESB pages after the source ESBs */ 300 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 301 302 /* 303 * Allocate the routing tables 304 */ 305 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 306 xive->endt = g_new0(XiveEND, xive->nr_ends); 307 308 /* TIMA initialization */ 309 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 310 "xive.tima", 4ull << TM_SHIFT); 311 312 /* Define all XIVE MMIO regions on SysBus */ 313 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 314 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 315 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 316 317 /* Map all regions */ 318 spapr_xive_map_mmio(xive); 319 320 qemu_register_reset(spapr_xive_reset, dev); 321 } 322 323 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 324 uint32_t eas_idx, XiveEAS *eas) 325 { 326 sPAPRXive *xive = SPAPR_XIVE(xrtr); 327 328 if (eas_idx >= xive->nr_irqs) { 329 return -1; 330 } 331 332 *eas = xive->eat[eas_idx]; 333 return 0; 334 } 335 336 static int spapr_xive_get_end(XiveRouter *xrtr, 337 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 338 { 339 sPAPRXive *xive = SPAPR_XIVE(xrtr); 340 341 if (end_idx >= xive->nr_ends) { 342 return -1; 343 } 344 345 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 346 return 0; 347 } 348 349 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 350 uint32_t end_idx, XiveEND *end, 351 uint8_t word_number) 352 { 353 sPAPRXive *xive = SPAPR_XIVE(xrtr); 354 355 if (end_idx >= xive->nr_ends) { 356 return -1; 357 } 358 359 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 360 return 0; 361 } 362 363 static int spapr_xive_get_nvt(XiveRouter *xrtr, 364 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 365 { 366 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 367 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 368 369 if (!cpu) { 370 /* TODO: should we assert() if we can find a NVT ? */ 371 return -1; 372 } 373 374 /* 375 * sPAPR does not maintain a NVT table. Return that the NVT is 376 * valid if we have found a matching CPU 377 */ 378 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 379 return 0; 380 } 381 382 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 383 uint32_t nvt_idx, XiveNVT *nvt, 384 uint8_t word_number) 385 { 386 /* 387 * We don't need to write back to the NVTs because the sPAPR 388 * machine should never hit a non-scheduled NVT. It should never 389 * get called. 390 */ 391 g_assert_not_reached(); 392 } 393 394 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 395 { 396 PowerPCCPU *cpu = POWERPC_CPU(cs); 397 398 return spapr_cpu_state(cpu)->tctx; 399 } 400 401 static const VMStateDescription vmstate_spapr_xive_end = { 402 .name = TYPE_SPAPR_XIVE "/end", 403 .version_id = 1, 404 .minimum_version_id = 1, 405 .fields = (VMStateField []) { 406 VMSTATE_UINT32(w0, XiveEND), 407 VMSTATE_UINT32(w1, XiveEND), 408 VMSTATE_UINT32(w2, XiveEND), 409 VMSTATE_UINT32(w3, XiveEND), 410 VMSTATE_UINT32(w4, XiveEND), 411 VMSTATE_UINT32(w5, XiveEND), 412 VMSTATE_UINT32(w6, XiveEND), 413 VMSTATE_UINT32(w7, XiveEND), 414 VMSTATE_END_OF_LIST() 415 }, 416 }; 417 418 static const VMStateDescription vmstate_spapr_xive_eas = { 419 .name = TYPE_SPAPR_XIVE "/eas", 420 .version_id = 1, 421 .minimum_version_id = 1, 422 .fields = (VMStateField []) { 423 VMSTATE_UINT64(w, XiveEAS), 424 VMSTATE_END_OF_LIST() 425 }, 426 }; 427 428 static const VMStateDescription vmstate_spapr_xive = { 429 .name = TYPE_SPAPR_XIVE, 430 .version_id = 1, 431 .minimum_version_id = 1, 432 .fields = (VMStateField[]) { 433 VMSTATE_UINT32_EQUAL(nr_irqs, sPAPRXive, NULL), 434 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, sPAPRXive, nr_irqs, 435 vmstate_spapr_xive_eas, XiveEAS), 436 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, sPAPRXive, nr_ends, 437 vmstate_spapr_xive_end, XiveEND), 438 VMSTATE_END_OF_LIST() 439 }, 440 }; 441 442 static Property spapr_xive_properties[] = { 443 DEFINE_PROP_UINT32("nr-irqs", sPAPRXive, nr_irqs, 0), 444 DEFINE_PROP_UINT32("nr-ends", sPAPRXive, nr_ends, 0), 445 DEFINE_PROP_UINT64("vc-base", sPAPRXive, vc_base, SPAPR_XIVE_VC_BASE), 446 DEFINE_PROP_UINT64("tm-base", sPAPRXive, tm_base, SPAPR_XIVE_TM_BASE), 447 DEFINE_PROP_END_OF_LIST(), 448 }; 449 450 static void spapr_xive_class_init(ObjectClass *klass, void *data) 451 { 452 DeviceClass *dc = DEVICE_CLASS(klass); 453 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 454 455 dc->desc = "sPAPR XIVE Interrupt Controller"; 456 dc->props = spapr_xive_properties; 457 dc->realize = spapr_xive_realize; 458 dc->vmsd = &vmstate_spapr_xive; 459 460 xrc->get_eas = spapr_xive_get_eas; 461 xrc->get_end = spapr_xive_get_end; 462 xrc->write_end = spapr_xive_write_end; 463 xrc->get_nvt = spapr_xive_get_nvt; 464 xrc->write_nvt = spapr_xive_write_nvt; 465 xrc->get_tctx = spapr_xive_get_tctx; 466 } 467 468 static const TypeInfo spapr_xive_info = { 469 .name = TYPE_SPAPR_XIVE, 470 .parent = TYPE_XIVE_ROUTER, 471 .instance_init = spapr_xive_instance_init, 472 .instance_size = sizeof(sPAPRXive), 473 .class_init = spapr_xive_class_init, 474 }; 475 476 static void spapr_xive_register_types(void) 477 { 478 type_register_static(&spapr_xive_info); 479 } 480 481 type_init(spapr_xive_register_types) 482 483 bool spapr_xive_irq_claim(sPAPRXive *xive, uint32_t lisn, bool lsi) 484 { 485 XiveSource *xsrc = &xive->source; 486 487 if (lisn >= xive->nr_irqs) { 488 return false; 489 } 490 491 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID); 492 xive_source_irq_set(xsrc, lisn, lsi); 493 return true; 494 } 495 496 bool spapr_xive_irq_free(sPAPRXive *xive, uint32_t lisn) 497 { 498 XiveSource *xsrc = &xive->source; 499 500 if (lisn >= xive->nr_irqs) { 501 return false; 502 } 503 504 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 505 xive_source_irq_set(xsrc, lisn, false); 506 return true; 507 } 508 509 /* 510 * XIVE hcalls 511 * 512 * The terminology used by the XIVE hcalls is the following : 513 * 514 * TARGET vCPU number 515 * EQ Event Queue assigned by OS to receive event data 516 * ESB page for source interrupt management 517 * LISN Logical Interrupt Source Number identifying a source in the 518 * machine 519 * EISN Effective Interrupt Source Number used by guest OS to 520 * identify source in the guest 521 * 522 * The EAS, END, NVT structures are not exposed. 523 */ 524 525 /* 526 * Linux hosts under OPAL reserve priority 7 for their own escalation 527 * interrupts (DD2.X POWER9). So we only allow the guest to use 528 * priorities [0..6]. 529 */ 530 static bool spapr_xive_priority_is_reserved(uint8_t priority) 531 { 532 switch (priority) { 533 case 0 ... 6: 534 return false; 535 case 7: /* OPAL escalation queue */ 536 default: 537 return true; 538 } 539 } 540 541 /* 542 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 543 * real address of the MMIO page through which the Event State Buffer 544 * entry associated with the value of the "lisn" parameter is managed. 545 * 546 * Parameters: 547 * Input 548 * - R4: "flags" 549 * Bits 0-63 reserved 550 * - R5: "lisn" is per "interrupts", "interrupt-map", or 551 * "ibm,xive-lisn-ranges" properties, or as returned by the 552 * ibm,query-interrupt-source-number RTAS call, or as returned 553 * by the H_ALLOCATE_VAS_WINDOW hcall 554 * 555 * Output 556 * - R4: "flags" 557 * Bits 0-59: Reserved 558 * Bit 60: H_INT_ESB must be used for Event State Buffer 559 * management 560 * Bit 61: 1 == LSI 0 == MSI 561 * Bit 62: the full function page supports trigger 562 * Bit 63: Store EOI Supported 563 * - R5: Logical Real address of full function Event State Buffer 564 * management page, -1 if H_INT_ESB hcall flag is set to 1. 565 * - R6: Logical Real Address of trigger only Event State Buffer 566 * management page or -1. 567 * - R7: Power of 2 page size for the ESB management pages returned in 568 * R5 and R6. 569 */ 570 571 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 572 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 573 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 574 on same page */ 575 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 576 577 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 578 sPAPRMachineState *spapr, 579 target_ulong opcode, 580 target_ulong *args) 581 { 582 sPAPRXive *xive = spapr->xive; 583 XiveSource *xsrc = &xive->source; 584 target_ulong flags = args[0]; 585 target_ulong lisn = args[1]; 586 587 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 588 return H_FUNCTION; 589 } 590 591 if (flags) { 592 return H_PARAMETER; 593 } 594 595 if (lisn >= xive->nr_irqs) { 596 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 597 lisn); 598 return H_P2; 599 } 600 601 if (!xive_eas_is_valid(&xive->eat[lisn])) { 602 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 603 lisn); 604 return H_P2; 605 } 606 607 /* 608 * All sources are emulated under the main XIVE object and share 609 * the same characteristics. 610 */ 611 args[0] = 0; 612 if (!xive_source_esb_has_2page(xsrc)) { 613 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 614 } 615 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 616 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 617 } 618 619 /* 620 * Force the use of the H_INT_ESB hcall in case of an LSI 621 * interrupt. This is necessary under KVM to re-trigger the 622 * interrupt if the level is still asserted 623 */ 624 if (xive_source_irq_is_lsi(xsrc, lisn)) { 625 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 626 } 627 628 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 629 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 630 } else { 631 args[1] = -1; 632 } 633 634 if (xive_source_esb_has_2page(xsrc) && 635 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 636 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 637 } else { 638 args[2] = -1; 639 } 640 641 if (xive_source_esb_has_2page(xsrc)) { 642 args[3] = xsrc->esb_shift - 1; 643 } else { 644 args[3] = xsrc->esb_shift; 645 } 646 647 return H_SUCCESS; 648 } 649 650 /* 651 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 652 * Interrupt Source to a target. The Logical Interrupt Source is 653 * designated with the "lisn" parameter and the target is designated 654 * with the "target" and "priority" parameters. Upon return from the 655 * hcall(), no additional interrupts will be directed to the old EQ. 656 * 657 * Parameters: 658 * Input: 659 * - R4: "flags" 660 * Bits 0-61: Reserved 661 * Bit 62: set the "eisn" in the EAS 662 * Bit 63: masks the interrupt source in the hardware interrupt 663 * control structure. An interrupt masked by this mechanism will 664 * be dropped, but it's source state bits will still be 665 * set. There is no race-free way of unmasking and restoring the 666 * source. Thus this should only be used in interrupts that are 667 * also masked at the source, and only in cases where the 668 * interrupt is not meant to be used for a large amount of time 669 * because no valid target exists for it for example 670 * - R5: "lisn" is per "interrupts", "interrupt-map", or 671 * "ibm,xive-lisn-ranges" properties, or as returned by the 672 * ibm,query-interrupt-source-number RTAS call, or as returned by 673 * the H_ALLOCATE_VAS_WINDOW hcall 674 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 675 * "ibm,ppc-interrupt-gserver#s" 676 * - R7: "priority" is a valid priority not in 677 * "ibm,plat-res-int-priorities" 678 * - R8: "eisn" is the guest EISN associated with the "lisn" 679 * 680 * Output: 681 * - None 682 */ 683 684 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 685 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 686 687 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 688 sPAPRMachineState *spapr, 689 target_ulong opcode, 690 target_ulong *args) 691 { 692 sPAPRXive *xive = spapr->xive; 693 XiveEAS eas, new_eas; 694 target_ulong flags = args[0]; 695 target_ulong lisn = args[1]; 696 target_ulong target = args[2]; 697 target_ulong priority = args[3]; 698 target_ulong eisn = args[4]; 699 uint8_t end_blk; 700 uint32_t end_idx; 701 702 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 703 return H_FUNCTION; 704 } 705 706 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 707 return H_PARAMETER; 708 } 709 710 if (lisn >= xive->nr_irqs) { 711 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 712 lisn); 713 return H_P2; 714 } 715 716 eas = xive->eat[lisn]; 717 if (!xive_eas_is_valid(&eas)) { 718 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 719 lisn); 720 return H_P2; 721 } 722 723 /* priority 0xff is used to reset the EAS */ 724 if (priority == 0xff) { 725 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 726 goto out; 727 } 728 729 if (flags & SPAPR_XIVE_SRC_MASK) { 730 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 731 } else { 732 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 733 } 734 735 if (spapr_xive_priority_is_reserved(priority)) { 736 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 737 " is reserved\n", priority); 738 return H_P4; 739 } 740 741 /* 742 * Validate that "target" is part of the list of threads allocated 743 * to the partition. For that, find the END corresponding to the 744 * target. 745 */ 746 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 747 return H_P3; 748 } 749 750 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 751 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 752 753 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 754 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 755 } 756 757 out: 758 xive->eat[lisn] = new_eas; 759 return H_SUCCESS; 760 } 761 762 /* 763 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 764 * target/priority pair is assigned to the specified Logical Interrupt 765 * Source. 766 * 767 * Parameters: 768 * Input: 769 * - R4: "flags" 770 * Bits 0-63 Reserved 771 * - R5: "lisn" is per "interrupts", "interrupt-map", or 772 * "ibm,xive-lisn-ranges" properties, or as returned by the 773 * ibm,query-interrupt-source-number RTAS call, or as 774 * returned by the H_ALLOCATE_VAS_WINDOW hcall 775 * 776 * Output: 777 * - R4: Target to which the specified Logical Interrupt Source is 778 * assigned 779 * - R5: Priority to which the specified Logical Interrupt Source is 780 * assigned 781 * - R6: EISN for the specified Logical Interrupt Source (this will be 782 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 783 */ 784 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 785 sPAPRMachineState *spapr, 786 target_ulong opcode, 787 target_ulong *args) 788 { 789 sPAPRXive *xive = spapr->xive; 790 target_ulong flags = args[0]; 791 target_ulong lisn = args[1]; 792 XiveEAS eas; 793 XiveEND *end; 794 uint8_t nvt_blk; 795 uint32_t end_idx, nvt_idx; 796 797 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 798 return H_FUNCTION; 799 } 800 801 if (flags) { 802 return H_PARAMETER; 803 } 804 805 if (lisn >= xive->nr_irqs) { 806 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 807 lisn); 808 return H_P2; 809 } 810 811 eas = xive->eat[lisn]; 812 if (!xive_eas_is_valid(&eas)) { 813 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 814 lisn); 815 return H_P2; 816 } 817 818 /* EAS_END_BLOCK is unused on sPAPR */ 819 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 820 821 assert(end_idx < xive->nr_ends); 822 end = &xive->endt[end_idx]; 823 824 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 825 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 826 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 827 828 if (xive_eas_is_masked(&eas)) { 829 args[1] = 0xff; 830 } else { 831 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 832 } 833 834 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 835 836 return H_SUCCESS; 837 } 838 839 /* 840 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 841 * address of the notification management page associated with the 842 * specified target and priority. 843 * 844 * Parameters: 845 * Input: 846 * - R4: "flags" 847 * Bits 0-63 Reserved 848 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 849 * "ibm,ppc-interrupt-gserver#s" 850 * - R6: "priority" is a valid priority not in 851 * "ibm,plat-res-int-priorities" 852 * 853 * Output: 854 * - R4: Logical real address of notification page 855 * - R5: Power of 2 page size of the notification page 856 */ 857 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 858 sPAPRMachineState *spapr, 859 target_ulong opcode, 860 target_ulong *args) 861 { 862 sPAPRXive *xive = spapr->xive; 863 XiveENDSource *end_xsrc = &xive->end_source; 864 target_ulong flags = args[0]; 865 target_ulong target = args[1]; 866 target_ulong priority = args[2]; 867 XiveEND *end; 868 uint8_t end_blk; 869 uint32_t end_idx; 870 871 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 872 return H_FUNCTION; 873 } 874 875 if (flags) { 876 return H_PARAMETER; 877 } 878 879 /* 880 * H_STATE should be returned if a H_INT_RESET is in progress. 881 * This is not needed when running the emulation under QEMU 882 */ 883 884 if (spapr_xive_priority_is_reserved(priority)) { 885 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 886 " is reserved\n", priority); 887 return H_P3; 888 } 889 890 /* 891 * Validate that "target" is part of the list of threads allocated 892 * to the partition. For that, find the END corresponding to the 893 * target. 894 */ 895 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 896 return H_P2; 897 } 898 899 assert(end_idx < xive->nr_ends); 900 end = &xive->endt[end_idx]; 901 902 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 903 if (xive_end_is_enqueue(end)) { 904 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 905 } else { 906 args[1] = 0; 907 } 908 909 return H_SUCCESS; 910 } 911 912 /* 913 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 914 * a given "target" and "priority". It is also used to set the 915 * notification config associated with the EQ. An EQ size of 0 is 916 * used to reset the EQ config for a given target and priority. If 917 * resetting the EQ config, the END associated with the given "target" 918 * and "priority" will be changed to disable queueing. 919 * 920 * Upon return from the hcall(), no additional interrupts will be 921 * directed to the old EQ (if one was set). The old EQ (if one was 922 * set) should be investigated for interrupts that occurred prior to 923 * or during the hcall(). 924 * 925 * Parameters: 926 * Input: 927 * - R4: "flags" 928 * Bits 0-62: Reserved 929 * Bit 63: Unconditional Notify (n) per the XIVE spec 930 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 931 * "ibm,ppc-interrupt-gserver#s" 932 * - R6: "priority" is a valid priority not in 933 * "ibm,plat-res-int-priorities" 934 * - R7: "eventQueue": The logical real address of the start of the EQ 935 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 936 * 937 * Output: 938 * - None 939 */ 940 941 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 942 943 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 944 sPAPRMachineState *spapr, 945 target_ulong opcode, 946 target_ulong *args) 947 { 948 sPAPRXive *xive = spapr->xive; 949 target_ulong flags = args[0]; 950 target_ulong target = args[1]; 951 target_ulong priority = args[2]; 952 target_ulong qpage = args[3]; 953 target_ulong qsize = args[4]; 954 XiveEND end; 955 uint8_t end_blk, nvt_blk; 956 uint32_t end_idx, nvt_idx; 957 958 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 959 return H_FUNCTION; 960 } 961 962 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 963 return H_PARAMETER; 964 } 965 966 /* 967 * H_STATE should be returned if a H_INT_RESET is in progress. 968 * This is not needed when running the emulation under QEMU 969 */ 970 971 if (spapr_xive_priority_is_reserved(priority)) { 972 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 973 " is reserved\n", priority); 974 return H_P3; 975 } 976 977 /* 978 * Validate that "target" is part of the list of threads allocated 979 * to the partition. For that, find the END corresponding to the 980 * target. 981 */ 982 983 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 984 return H_P2; 985 } 986 987 assert(end_idx < xive->nr_ends); 988 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 989 990 switch (qsize) { 991 case 12: 992 case 16: 993 case 21: 994 case 24: 995 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 996 end.w3 = cpu_to_be32(qpage & 0xffffffff); 997 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 998 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 999 break; 1000 case 0: 1001 /* reset queue and disable queueing */ 1002 spapr_xive_end_reset(&end); 1003 goto out; 1004 1005 default: 1006 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1007 qsize); 1008 return H_P5; 1009 } 1010 1011 if (qsize) { 1012 hwaddr plen = 1 << qsize; 1013 void *eq; 1014 1015 /* 1016 * Validate the guest EQ. We should also check that the queue 1017 * has been zeroed by the OS. 1018 */ 1019 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1020 MEMTXATTRS_UNSPECIFIED); 1021 if (plen != 1 << qsize) { 1022 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1023 HWADDR_PRIx "\n", qpage); 1024 return H_P4; 1025 } 1026 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1027 } 1028 1029 /* "target" should have been validated above */ 1030 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1031 g_assert_not_reached(); 1032 } 1033 1034 /* 1035 * Ensure the priority and target are correctly set (they will not 1036 * be right after allocation) 1037 */ 1038 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1039 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1040 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1041 1042 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1043 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1044 } else { 1045 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1046 } 1047 1048 /* 1049 * The generation bit for the END starts at 1 and The END page 1050 * offset counter starts at 0. 1051 */ 1052 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1053 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1054 end.w0 |= cpu_to_be32(END_W0_VALID); 1055 1056 /* 1057 * TODO: issue syncs required to ensure all in-flight interrupts 1058 * are complete on the old END 1059 */ 1060 1061 out: 1062 /* Update END */ 1063 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1064 return H_SUCCESS; 1065 } 1066 1067 /* 1068 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1069 * target and priority. 1070 * 1071 * Parameters: 1072 * Input: 1073 * - R4: "flags" 1074 * Bits 0-62: Reserved 1075 * Bit 63: Debug: Return debug data 1076 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1077 * "ibm,ppc-interrupt-gserver#s" 1078 * - R6: "priority" is a valid priority not in 1079 * "ibm,plat-res-int-priorities" 1080 * 1081 * Output: 1082 * - R4: "flags": 1083 * Bits 0-61: Reserved 1084 * Bit 62: The value of Event Queue Generation Number (g) per 1085 * the XIVE spec if "Debug" = 1 1086 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1087 * - R5: The logical real address of the start of the EQ 1088 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1089 * - R7: The value of Event Queue Offset Counter per XIVE spec 1090 * if "Debug" = 1, else 0 1091 * 1092 */ 1093 1094 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1095 1096 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1097 sPAPRMachineState *spapr, 1098 target_ulong opcode, 1099 target_ulong *args) 1100 { 1101 sPAPRXive *xive = spapr->xive; 1102 target_ulong flags = args[0]; 1103 target_ulong target = args[1]; 1104 target_ulong priority = args[2]; 1105 XiveEND *end; 1106 uint8_t end_blk; 1107 uint32_t end_idx; 1108 1109 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1110 return H_FUNCTION; 1111 } 1112 1113 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1114 return H_PARAMETER; 1115 } 1116 1117 /* 1118 * H_STATE should be returned if a H_INT_RESET is in progress. 1119 * This is not needed when running the emulation under QEMU 1120 */ 1121 1122 if (spapr_xive_priority_is_reserved(priority)) { 1123 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1124 " is reserved\n", priority); 1125 return H_P3; 1126 } 1127 1128 /* 1129 * Validate that "target" is part of the list of threads allocated 1130 * to the partition. For that, find the END corresponding to the 1131 * target. 1132 */ 1133 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1134 return H_P2; 1135 } 1136 1137 assert(end_idx < xive->nr_ends); 1138 end = &xive->endt[end_idx]; 1139 1140 args[0] = 0; 1141 if (xive_end_is_notify(end)) { 1142 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1143 } 1144 1145 if (xive_end_is_enqueue(end)) { 1146 args[1] = (uint64_t) be32_to_cpu(end->w2 & 0x0fffffff) << 32 1147 | be32_to_cpu(end->w3); 1148 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1149 } else { 1150 args[1] = 0; 1151 args[2] = 0; 1152 } 1153 1154 /* TODO: do we need any locking on the END ? */ 1155 if (flags & SPAPR_XIVE_END_DEBUG) { 1156 /* Load the event queue generation number into the return flags */ 1157 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1158 1159 /* Load R7 with the event queue offset counter */ 1160 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1161 } else { 1162 args[3] = 0; 1163 } 1164 1165 return H_SUCCESS; 1166 } 1167 1168 /* 1169 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1170 * reporting cache line pair for the calling thread. The reporting 1171 * cache lines will contain the OS interrupt context when the OS 1172 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1173 * interrupt. The reporting cache lines can be reset by inputting -1 1174 * in "reportingLine". Issuing the CI store byte without reporting 1175 * cache lines registered will result in the data not being accessible 1176 * to the OS. 1177 * 1178 * Parameters: 1179 * Input: 1180 * - R4: "flags" 1181 * Bits 0-63: Reserved 1182 * - R5: "reportingLine": The logical real address of the reporting cache 1183 * line pair 1184 * 1185 * Output: 1186 * - None 1187 */ 1188 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1189 sPAPRMachineState *spapr, 1190 target_ulong opcode, 1191 target_ulong *args) 1192 { 1193 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1194 return H_FUNCTION; 1195 } 1196 1197 /* 1198 * H_STATE should be returned if a H_INT_RESET is in progress. 1199 * This is not needed when running the emulation under QEMU 1200 */ 1201 1202 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1203 return H_FUNCTION; 1204 } 1205 1206 /* 1207 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1208 * real address of the reporting cache line pair set for the input 1209 * "target". If no reporting cache line pair has been set, -1 is 1210 * returned. 1211 * 1212 * Parameters: 1213 * Input: 1214 * - R4: "flags" 1215 * Bits 0-63: Reserved 1216 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1217 * "ibm,ppc-interrupt-gserver#s" 1218 * - R6: "reportingLine": The logical real address of the reporting 1219 * cache line pair 1220 * 1221 * Output: 1222 * - R4: The logical real address of the reporting line if set, else -1 1223 */ 1224 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1225 sPAPRMachineState *spapr, 1226 target_ulong opcode, 1227 target_ulong *args) 1228 { 1229 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1230 return H_FUNCTION; 1231 } 1232 1233 /* 1234 * H_STATE should be returned if a H_INT_RESET is in progress. 1235 * This is not needed when running the emulation under QEMU 1236 */ 1237 1238 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1239 return H_FUNCTION; 1240 } 1241 1242 /* 1243 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1244 * page for the input "lisn". This hcall is only supported for LISNs 1245 * that have the ESB hcall flag set to 1 when returned from hcall() 1246 * H_INT_GET_SOURCE_INFO. 1247 * 1248 * Parameters: 1249 * Input: 1250 * - R4: "flags" 1251 * Bits 0-62: Reserved 1252 * bit 63: Store: Store=1, store operation, else load operation 1253 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1254 * "ibm,xive-lisn-ranges" properties, or as returned by the 1255 * ibm,query-interrupt-source-number RTAS call, or as 1256 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1257 * - R6: "esbOffset" is the offset into the ESB page for the load or 1258 * store operation 1259 * - R7: "storeData" is the data to write for a store operation 1260 * 1261 * Output: 1262 * - R4: The value of the load if load operation, else -1 1263 */ 1264 1265 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1266 1267 static target_ulong h_int_esb(PowerPCCPU *cpu, 1268 sPAPRMachineState *spapr, 1269 target_ulong opcode, 1270 target_ulong *args) 1271 { 1272 sPAPRXive *xive = spapr->xive; 1273 XiveEAS eas; 1274 target_ulong flags = args[0]; 1275 target_ulong lisn = args[1]; 1276 target_ulong offset = args[2]; 1277 target_ulong data = args[3]; 1278 hwaddr mmio_addr; 1279 XiveSource *xsrc = &xive->source; 1280 1281 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1282 return H_FUNCTION; 1283 } 1284 1285 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1286 return H_PARAMETER; 1287 } 1288 1289 if (lisn >= xive->nr_irqs) { 1290 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1291 lisn); 1292 return H_P2; 1293 } 1294 1295 eas = xive->eat[lisn]; 1296 if (!xive_eas_is_valid(&eas)) { 1297 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1298 lisn); 1299 return H_P2; 1300 } 1301 1302 if (offset > (1ull << xsrc->esb_shift)) { 1303 return H_P3; 1304 } 1305 1306 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1307 1308 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1309 (flags & SPAPR_XIVE_ESB_STORE))) { 1310 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1311 HWADDR_PRIx "\n", mmio_addr); 1312 return H_HARDWARE; 1313 } 1314 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1315 return H_SUCCESS; 1316 } 1317 1318 /* 1319 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1320 * ensure any in flight events for the input lisn are in the event 1321 * queue. 1322 * 1323 * Parameters: 1324 * Input: 1325 * - R4: "flags" 1326 * Bits 0-63: Reserved 1327 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1328 * "ibm,xive-lisn-ranges" properties, or as returned by the 1329 * ibm,query-interrupt-source-number RTAS call, or as 1330 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1331 * 1332 * Output: 1333 * - None 1334 */ 1335 static target_ulong h_int_sync(PowerPCCPU *cpu, 1336 sPAPRMachineState *spapr, 1337 target_ulong opcode, 1338 target_ulong *args) 1339 { 1340 sPAPRXive *xive = spapr->xive; 1341 XiveEAS eas; 1342 target_ulong flags = args[0]; 1343 target_ulong lisn = args[1]; 1344 1345 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1346 return H_FUNCTION; 1347 } 1348 1349 if (flags) { 1350 return H_PARAMETER; 1351 } 1352 1353 if (lisn >= xive->nr_irqs) { 1354 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1355 lisn); 1356 return H_P2; 1357 } 1358 1359 eas = xive->eat[lisn]; 1360 if (!xive_eas_is_valid(&eas)) { 1361 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1362 lisn); 1363 return H_P2; 1364 } 1365 1366 /* 1367 * H_STATE should be returned if a H_INT_RESET is in progress. 1368 * This is not needed when running the emulation under QEMU 1369 */ 1370 1371 /* This is not real hardware. Nothing to be done */ 1372 return H_SUCCESS; 1373 } 1374 1375 /* 1376 * The H_INT_RESET hcall() is used to reset all of the partition's 1377 * interrupt exploitation structures to their initial state. This 1378 * means losing all previously set interrupt state set via 1379 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1380 * 1381 * Parameters: 1382 * Input: 1383 * - R4: "flags" 1384 * Bits 0-63: Reserved 1385 * 1386 * Output: 1387 * - None 1388 */ 1389 static target_ulong h_int_reset(PowerPCCPU *cpu, 1390 sPAPRMachineState *spapr, 1391 target_ulong opcode, 1392 target_ulong *args) 1393 { 1394 sPAPRXive *xive = spapr->xive; 1395 target_ulong flags = args[0]; 1396 1397 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1398 return H_FUNCTION; 1399 } 1400 1401 if (flags) { 1402 return H_PARAMETER; 1403 } 1404 1405 device_reset(DEVICE(xive)); 1406 return H_SUCCESS; 1407 } 1408 1409 void spapr_xive_hcall_init(sPAPRMachineState *spapr) 1410 { 1411 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1412 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1413 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1414 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1415 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1416 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1417 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1418 h_int_set_os_reporting_line); 1419 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1420 h_int_get_os_reporting_line); 1421 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1422 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1423 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1424 } 1425 1426 void spapr_dt_xive(sPAPRMachineState *spapr, uint32_t nr_servers, void *fdt, 1427 uint32_t phandle) 1428 { 1429 sPAPRXive *xive = spapr->xive; 1430 int node; 1431 uint64_t timas[2 * 2]; 1432 /* Interrupt number ranges for the IPIs */ 1433 uint32_t lisn_ranges[] = { 1434 cpu_to_be32(0), 1435 cpu_to_be32(nr_servers), 1436 }; 1437 /* 1438 * EQ size - the sizes of pages supported by the system 4K, 64K, 1439 * 2M, 16M. We only advertise 64K for the moment. 1440 */ 1441 uint32_t eq_sizes[] = { 1442 cpu_to_be32(16), /* 64K */ 1443 }; 1444 /* 1445 * The following array is in sync with the reserved priorities 1446 * defined by the 'spapr_xive_priority_is_reserved' routine. 1447 */ 1448 uint32_t plat_res_int_priorities[] = { 1449 cpu_to_be32(7), /* start */ 1450 cpu_to_be32(0xf8), /* count */ 1451 }; 1452 gchar *nodename; 1453 1454 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 1455 timas[0] = cpu_to_be64(xive->tm_base + 1456 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 1457 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 1458 timas[2] = cpu_to_be64(xive->tm_base + 1459 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 1460 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 1461 1462 nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 1463 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 1464 _FDT(node = fdt_add_subnode(fdt, 0, nodename)); 1465 g_free(nodename); 1466 1467 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 1468 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 1469 1470 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 1471 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 1472 sizeof(eq_sizes))); 1473 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 1474 sizeof(lisn_ranges))); 1475 1476 /* For Linux to link the LSIs to the interrupt controller. */ 1477 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 1478 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 1479 1480 /* For SLOF */ 1481 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 1482 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 1483 1484 /* 1485 * The "ibm,plat-res-int-priorities" property defines the priority 1486 * ranges reserved by the hypervisor 1487 */ 1488 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 1489 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 1490 } 1491