1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 } 150 151 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 152 { 153 XiveSource *xsrc = &xive->source; 154 int i; 155 156 if (kvm_irqchip_in_kernel()) { 157 Error *local_err = NULL; 158 159 kvmppc_xive_synchronize_state(xive, &local_err); 160 if (local_err) { 161 error_report_err(local_err); 162 return; 163 } 164 } 165 166 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 167 168 for (i = 0; i < xive->nr_irqs; i++) { 169 uint8_t pq = xive_source_esb_get(xsrc, i); 170 XiveEAS *eas = &xive->eat[i]; 171 172 if (!xive_eas_is_valid(eas)) { 173 continue; 174 } 175 176 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 177 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 178 pq & XIVE_ESB_VAL_P ? 'P' : '-', 179 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 180 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 181 xive_eas_is_masked(eas) ? "M" : " ", 182 (int) xive_get_field64(EAS_END_DATA, eas->w)); 183 184 if (!xive_eas_is_masked(eas)) { 185 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 186 XiveEND *end; 187 188 assert(end_idx < xive->nr_ends); 189 end = &xive->endt[end_idx]; 190 191 if (xive_end_is_valid(end)) { 192 spapr_xive_end_pic_print_info(xive, end, mon); 193 } 194 } 195 monitor_printf(mon, "\n"); 196 } 197 } 198 199 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 200 { 201 memory_region_set_enabled(&xive->source.esb_mmio, enable); 202 memory_region_set_enabled(&xive->tm_mmio, enable); 203 204 /* Disable the END ESBs until a guest OS makes use of them */ 205 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 206 } 207 208 static void spapr_xive_tm_write(void *opaque, hwaddr offset, 209 uint64_t value, unsigned size) 210 { 211 XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; 212 213 xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); 214 } 215 216 static uint64_t spapr_xive_tm_read(void *opaque, hwaddr offset, unsigned size) 217 { 218 XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; 219 220 return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); 221 } 222 223 const MemoryRegionOps spapr_xive_tm_ops = { 224 .read = spapr_xive_tm_read, 225 .write = spapr_xive_tm_write, 226 .endianness = DEVICE_BIG_ENDIAN, 227 .valid = { 228 .min_access_size = 1, 229 .max_access_size = 8, 230 }, 231 .impl = { 232 .min_access_size = 1, 233 .max_access_size = 8, 234 }, 235 }; 236 237 static void spapr_xive_end_reset(XiveEND *end) 238 { 239 memset(end, 0, sizeof(*end)); 240 241 /* switch off the escalation and notification ESBs */ 242 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 243 } 244 245 static void spapr_xive_reset(void *dev) 246 { 247 SpaprXive *xive = SPAPR_XIVE(dev); 248 int i; 249 250 /* 251 * The XiveSource has its own reset handler, which mask off all 252 * IRQs (!P|Q) 253 */ 254 255 /* Mask all valid EASs in the IRQ number space. */ 256 for (i = 0; i < xive->nr_irqs; i++) { 257 XiveEAS *eas = &xive->eat[i]; 258 if (xive_eas_is_valid(eas)) { 259 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 260 } else { 261 eas->w = 0; 262 } 263 } 264 265 /* Clear all ENDs */ 266 for (i = 0; i < xive->nr_ends; i++) { 267 spapr_xive_end_reset(&xive->endt[i]); 268 } 269 } 270 271 static void spapr_xive_instance_init(Object *obj) 272 { 273 SpaprXive *xive = SPAPR_XIVE(obj); 274 275 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 276 TYPE_XIVE_SOURCE, &error_abort, NULL); 277 278 object_initialize_child(obj, "end_source", &xive->end_source, 279 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 280 &error_abort, NULL); 281 282 /* Not connected to the KVM XIVE device */ 283 xive->fd = -1; 284 } 285 286 static void spapr_xive_realize(DeviceState *dev, Error **errp) 287 { 288 SpaprXive *xive = SPAPR_XIVE(dev); 289 XiveSource *xsrc = &xive->source; 290 XiveENDSource *end_xsrc = &xive->end_source; 291 Error *local_err = NULL; 292 293 if (!xive->nr_irqs) { 294 error_setg(errp, "Number of interrupt needs to be greater 0"); 295 return; 296 } 297 298 if (!xive->nr_ends) { 299 error_setg(errp, "Number of interrupt needs to be greater 0"); 300 return; 301 } 302 303 /* 304 * Initialize the internal sources, for IPIs and virtual devices. 305 */ 306 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 307 &error_fatal); 308 object_property_set_link(OBJECT(xsrc), OBJECT(xive), "xive", 309 &error_abort); 310 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 311 if (local_err) { 312 error_propagate(errp, local_err); 313 return; 314 } 315 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 316 317 /* 318 * Initialize the END ESB source 319 */ 320 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 321 &error_fatal); 322 object_property_set_link(OBJECT(end_xsrc), OBJECT(xive), "xive", 323 &error_abort); 324 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 325 if (local_err) { 326 error_propagate(errp, local_err); 327 return; 328 } 329 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 330 331 /* Set the mapping address of the END ESB pages after the source ESBs */ 332 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 333 334 /* 335 * Allocate the routing tables 336 */ 337 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 338 xive->endt = g_new0(XiveEND, xive->nr_ends); 339 340 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 341 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 342 343 qemu_register_reset(spapr_xive_reset, dev); 344 345 /* TIMA initialization */ 346 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &spapr_xive_tm_ops, 347 xive, "xive.tima", 4ull << TM_SHIFT); 348 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 349 350 /* 351 * Map all regions. These will be enabled or disabled at reset and 352 * can also be overridden by KVM memory regions if active 353 */ 354 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 355 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 356 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 357 } 358 359 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 360 uint32_t eas_idx, XiveEAS *eas) 361 { 362 SpaprXive *xive = SPAPR_XIVE(xrtr); 363 364 if (eas_idx >= xive->nr_irqs) { 365 return -1; 366 } 367 368 *eas = xive->eat[eas_idx]; 369 return 0; 370 } 371 372 static int spapr_xive_get_end(XiveRouter *xrtr, 373 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 374 { 375 SpaprXive *xive = SPAPR_XIVE(xrtr); 376 377 if (end_idx >= xive->nr_ends) { 378 return -1; 379 } 380 381 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 382 return 0; 383 } 384 385 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 386 uint32_t end_idx, XiveEND *end, 387 uint8_t word_number) 388 { 389 SpaprXive *xive = SPAPR_XIVE(xrtr); 390 391 if (end_idx >= xive->nr_ends) { 392 return -1; 393 } 394 395 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 396 return 0; 397 } 398 399 static int spapr_xive_get_nvt(XiveRouter *xrtr, 400 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 401 { 402 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 403 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 404 405 if (!cpu) { 406 /* TODO: should we assert() if we can find a NVT ? */ 407 return -1; 408 } 409 410 /* 411 * sPAPR does not maintain a NVT table. Return that the NVT is 412 * valid if we have found a matching CPU 413 */ 414 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 415 return 0; 416 } 417 418 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 419 uint32_t nvt_idx, XiveNVT *nvt, 420 uint8_t word_number) 421 { 422 /* 423 * We don't need to write back to the NVTs because the sPAPR 424 * machine should never hit a non-scheduled NVT. It should never 425 * get called. 426 */ 427 g_assert_not_reached(); 428 } 429 430 static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, 431 uint8_t nvt_blk, uint32_t nvt_idx, 432 bool cam_ignore, uint8_t priority, 433 uint32_t logic_serv, XiveTCTXMatch *match) 434 { 435 CPUState *cs; 436 int count = 0; 437 438 CPU_FOREACH(cs) { 439 PowerPCCPU *cpu = POWERPC_CPU(cs); 440 XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx; 441 int ring; 442 443 /* 444 * Skip partially initialized vCPUs. This can happen when 445 * vCPUs are hotplugged. 446 */ 447 if (!tctx) { 448 continue; 449 } 450 451 /* 452 * Check the thread context CAM lines and record matches. 453 */ 454 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx, 455 cam_ignore, logic_serv); 456 /* 457 * Save the matching thread interrupt context and follow on to 458 * check for duplicates which are invalid. 459 */ 460 if (ring != -1) { 461 if (match->tctx) { 462 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread " 463 "context NVT %x/%x\n", nvt_blk, nvt_idx); 464 return -1; 465 } 466 467 match->ring = ring; 468 match->tctx = tctx; 469 count++; 470 } 471 } 472 473 return count; 474 } 475 476 static const VMStateDescription vmstate_spapr_xive_end = { 477 .name = TYPE_SPAPR_XIVE "/end", 478 .version_id = 1, 479 .minimum_version_id = 1, 480 .fields = (VMStateField []) { 481 VMSTATE_UINT32(w0, XiveEND), 482 VMSTATE_UINT32(w1, XiveEND), 483 VMSTATE_UINT32(w2, XiveEND), 484 VMSTATE_UINT32(w3, XiveEND), 485 VMSTATE_UINT32(w4, XiveEND), 486 VMSTATE_UINT32(w5, XiveEND), 487 VMSTATE_UINT32(w6, XiveEND), 488 VMSTATE_UINT32(w7, XiveEND), 489 VMSTATE_END_OF_LIST() 490 }, 491 }; 492 493 static const VMStateDescription vmstate_spapr_xive_eas = { 494 .name = TYPE_SPAPR_XIVE "/eas", 495 .version_id = 1, 496 .minimum_version_id = 1, 497 .fields = (VMStateField []) { 498 VMSTATE_UINT64(w, XiveEAS), 499 VMSTATE_END_OF_LIST() 500 }, 501 }; 502 503 static int vmstate_spapr_xive_pre_save(void *opaque) 504 { 505 if (kvm_irqchip_in_kernel()) { 506 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 507 } 508 509 return 0; 510 } 511 512 /* 513 * Called by the sPAPR IRQ backend 'post_load' method at the machine 514 * level. 515 */ 516 static int spapr_xive_post_load(SpaprInterruptController *intc, int version_id) 517 { 518 if (kvm_irqchip_in_kernel()) { 519 return kvmppc_xive_post_load(SPAPR_XIVE(intc), version_id); 520 } 521 522 return 0; 523 } 524 525 static const VMStateDescription vmstate_spapr_xive = { 526 .name = TYPE_SPAPR_XIVE, 527 .version_id = 1, 528 .minimum_version_id = 1, 529 .pre_save = vmstate_spapr_xive_pre_save, 530 .post_load = NULL, /* handled at the machine level */ 531 .fields = (VMStateField[]) { 532 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 533 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 534 vmstate_spapr_xive_eas, XiveEAS), 535 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 536 vmstate_spapr_xive_end, XiveEND), 537 VMSTATE_END_OF_LIST() 538 }, 539 }; 540 541 static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, 542 bool lsi, Error **errp) 543 { 544 SpaprXive *xive = SPAPR_XIVE(intc); 545 XiveSource *xsrc = &xive->source; 546 547 assert(lisn < xive->nr_irqs); 548 549 if (xive_eas_is_valid(&xive->eat[lisn])) { 550 error_setg(errp, "IRQ %d is not free", lisn); 551 return -EBUSY; 552 } 553 554 /* 555 * Set default values when allocating an IRQ number 556 */ 557 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); 558 if (lsi) { 559 xive_source_irq_set_lsi(xsrc, lisn); 560 } 561 562 if (kvm_irqchip_in_kernel()) { 563 return kvmppc_xive_source_reset_one(xsrc, lisn, errp); 564 } 565 566 return 0; 567 } 568 569 static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) 570 { 571 SpaprXive *xive = SPAPR_XIVE(intc); 572 assert(lisn < xive->nr_irqs); 573 574 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 575 } 576 577 static Property spapr_xive_properties[] = { 578 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 579 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 580 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 581 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 582 DEFINE_PROP_END_OF_LIST(), 583 }; 584 585 static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 586 PowerPCCPU *cpu, Error **errp) 587 { 588 SpaprXive *xive = SPAPR_XIVE(intc); 589 Object *obj; 590 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 591 592 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp); 593 if (!obj) { 594 return -1; 595 } 596 597 spapr_cpu->tctx = XIVE_TCTX(obj); 598 return 0; 599 } 600 601 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t os_cam) 602 { 603 uint32_t qw1w2 = cpu_to_be32(TM_QW1W2_VO | os_cam); 604 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 605 } 606 607 static void spapr_xive_cpu_intc_reset(SpaprInterruptController *intc, 608 PowerPCCPU *cpu) 609 { 610 XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx; 611 uint8_t nvt_blk; 612 uint32_t nvt_idx; 613 614 xive_tctx_reset(tctx); 615 616 /* 617 * When a Virtual Processor is scheduled to run on a HW thread, 618 * the hypervisor pushes its identifier in the OS CAM line. 619 * Emulate the same behavior under QEMU. 620 */ 621 spapr_xive_cpu_to_nvt(cpu, &nvt_blk, &nvt_idx); 622 623 xive_tctx_set_os_cam(tctx, xive_nvt_cam_line(nvt_blk, nvt_idx)); 624 } 625 626 static void spapr_xive_cpu_intc_destroy(SpaprInterruptController *intc, 627 PowerPCCPU *cpu) 628 { 629 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 630 631 xive_tctx_destroy(spapr_cpu->tctx); 632 spapr_cpu->tctx = NULL; 633 } 634 635 static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val) 636 { 637 SpaprXive *xive = SPAPR_XIVE(intc); 638 639 if (kvm_irqchip_in_kernel()) { 640 kvmppc_xive_source_set_irq(&xive->source, irq, val); 641 } else { 642 xive_source_set_irq(&xive->source, irq, val); 643 } 644 } 645 646 static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor *mon) 647 { 648 SpaprXive *xive = SPAPR_XIVE(intc); 649 CPUState *cs; 650 651 CPU_FOREACH(cs) { 652 PowerPCCPU *cpu = POWERPC_CPU(cs); 653 654 xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); 655 } 656 657 spapr_xive_pic_print_info(xive, mon); 658 } 659 660 static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers, 661 void *fdt, uint32_t phandle) 662 { 663 SpaprXive *xive = SPAPR_XIVE(intc); 664 int node; 665 uint64_t timas[2 * 2]; 666 /* Interrupt number ranges for the IPIs */ 667 uint32_t lisn_ranges[] = { 668 cpu_to_be32(0), 669 cpu_to_be32(nr_servers), 670 }; 671 /* 672 * EQ size - the sizes of pages supported by the system 4K, 64K, 673 * 2M, 16M. We only advertise 64K for the moment. 674 */ 675 uint32_t eq_sizes[] = { 676 cpu_to_be32(16), /* 64K */ 677 }; 678 /* 679 * The following array is in sync with the reserved priorities 680 * defined by the 'spapr_xive_priority_is_reserved' routine. 681 */ 682 uint32_t plat_res_int_priorities[] = { 683 cpu_to_be32(7), /* start */ 684 cpu_to_be32(0xf8), /* count */ 685 }; 686 687 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 688 timas[0] = cpu_to_be64(xive->tm_base + 689 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 690 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 691 timas[2] = cpu_to_be64(xive->tm_base + 692 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 693 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 694 695 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 696 697 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 698 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 699 700 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 701 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 702 sizeof(eq_sizes))); 703 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 704 sizeof(lisn_ranges))); 705 706 /* For Linux to link the LSIs to the interrupt controller. */ 707 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 708 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 709 710 /* For SLOF */ 711 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 712 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 713 714 /* 715 * The "ibm,plat-res-int-priorities" property defines the priority 716 * ranges reserved by the hypervisor 717 */ 718 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 719 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 720 } 721 722 static int spapr_xive_activate(SpaprInterruptController *intc, 723 uint32_t nr_servers, Error **errp) 724 { 725 SpaprXive *xive = SPAPR_XIVE(intc); 726 727 if (kvm_enabled()) { 728 int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, nr_servers, 729 errp); 730 if (rc < 0) { 731 return rc; 732 } 733 } 734 735 /* Activate the XIVE MMIOs */ 736 spapr_xive_mmio_set_enabled(xive, true); 737 738 return 0; 739 } 740 741 static void spapr_xive_deactivate(SpaprInterruptController *intc) 742 { 743 SpaprXive *xive = SPAPR_XIVE(intc); 744 745 spapr_xive_mmio_set_enabled(xive, false); 746 747 if (kvm_irqchip_in_kernel()) { 748 kvmppc_xive_disconnect(intc); 749 } 750 } 751 752 static void spapr_xive_class_init(ObjectClass *klass, void *data) 753 { 754 DeviceClass *dc = DEVICE_CLASS(klass); 755 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 756 SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); 757 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 758 759 dc->desc = "sPAPR XIVE Interrupt Controller"; 760 dc->props = spapr_xive_properties; 761 dc->realize = spapr_xive_realize; 762 dc->vmsd = &vmstate_spapr_xive; 763 764 xrc->get_eas = spapr_xive_get_eas; 765 xrc->get_end = spapr_xive_get_end; 766 xrc->write_end = spapr_xive_write_end; 767 xrc->get_nvt = spapr_xive_get_nvt; 768 xrc->write_nvt = spapr_xive_write_nvt; 769 770 sicc->activate = spapr_xive_activate; 771 sicc->deactivate = spapr_xive_deactivate; 772 sicc->cpu_intc_create = spapr_xive_cpu_intc_create; 773 sicc->cpu_intc_reset = spapr_xive_cpu_intc_reset; 774 sicc->cpu_intc_destroy = spapr_xive_cpu_intc_destroy; 775 sicc->claim_irq = spapr_xive_claim_irq; 776 sicc->free_irq = spapr_xive_free_irq; 777 sicc->set_irq = spapr_xive_set_irq; 778 sicc->print_info = spapr_xive_print_info; 779 sicc->dt = spapr_xive_dt; 780 sicc->post_load = spapr_xive_post_load; 781 782 xpc->match_nvt = spapr_xive_match_nvt; 783 } 784 785 static const TypeInfo spapr_xive_info = { 786 .name = TYPE_SPAPR_XIVE, 787 .parent = TYPE_XIVE_ROUTER, 788 .instance_init = spapr_xive_instance_init, 789 .instance_size = sizeof(SpaprXive), 790 .class_init = spapr_xive_class_init, 791 .interfaces = (InterfaceInfo[]) { 792 { TYPE_SPAPR_INTC }, 793 { } 794 }, 795 }; 796 797 static void spapr_xive_register_types(void) 798 { 799 type_register_static(&spapr_xive_info); 800 } 801 802 type_init(spapr_xive_register_types) 803 804 /* 805 * XIVE hcalls 806 * 807 * The terminology used by the XIVE hcalls is the following : 808 * 809 * TARGET vCPU number 810 * EQ Event Queue assigned by OS to receive event data 811 * ESB page for source interrupt management 812 * LISN Logical Interrupt Source Number identifying a source in the 813 * machine 814 * EISN Effective Interrupt Source Number used by guest OS to 815 * identify source in the guest 816 * 817 * The EAS, END, NVT structures are not exposed. 818 */ 819 820 /* 821 * Linux hosts under OPAL reserve priority 7 for their own escalation 822 * interrupts (DD2.X POWER9). So we only allow the guest to use 823 * priorities [0..6]. 824 */ 825 static bool spapr_xive_priority_is_reserved(uint8_t priority) 826 { 827 switch (priority) { 828 case 0 ... 6: 829 return false; 830 case 7: /* OPAL escalation queue */ 831 default: 832 return true; 833 } 834 } 835 836 /* 837 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 838 * real address of the MMIO page through which the Event State Buffer 839 * entry associated with the value of the "lisn" parameter is managed. 840 * 841 * Parameters: 842 * Input 843 * - R4: "flags" 844 * Bits 0-63 reserved 845 * - R5: "lisn" is per "interrupts", "interrupt-map", or 846 * "ibm,xive-lisn-ranges" properties, or as returned by the 847 * ibm,query-interrupt-source-number RTAS call, or as returned 848 * by the H_ALLOCATE_VAS_WINDOW hcall 849 * 850 * Output 851 * - R4: "flags" 852 * Bits 0-59: Reserved 853 * Bit 60: H_INT_ESB must be used for Event State Buffer 854 * management 855 * Bit 61: 1 == LSI 0 == MSI 856 * Bit 62: the full function page supports trigger 857 * Bit 63: Store EOI Supported 858 * - R5: Logical Real address of full function Event State Buffer 859 * management page, -1 if H_INT_ESB hcall flag is set to 1. 860 * - R6: Logical Real Address of trigger only Event State Buffer 861 * management page or -1. 862 * - R7: Power of 2 page size for the ESB management pages returned in 863 * R5 and R6. 864 */ 865 866 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 867 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 868 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 869 on same page */ 870 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 871 872 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 873 SpaprMachineState *spapr, 874 target_ulong opcode, 875 target_ulong *args) 876 { 877 SpaprXive *xive = spapr->xive; 878 XiveSource *xsrc = &xive->source; 879 target_ulong flags = args[0]; 880 target_ulong lisn = args[1]; 881 882 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 883 return H_FUNCTION; 884 } 885 886 if (flags) { 887 return H_PARAMETER; 888 } 889 890 if (lisn >= xive->nr_irqs) { 891 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 892 lisn); 893 return H_P2; 894 } 895 896 if (!xive_eas_is_valid(&xive->eat[lisn])) { 897 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 898 lisn); 899 return H_P2; 900 } 901 902 /* 903 * All sources are emulated under the main XIVE object and share 904 * the same characteristics. 905 */ 906 args[0] = 0; 907 if (!xive_source_esb_has_2page(xsrc)) { 908 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 909 } 910 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 911 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 912 } 913 914 /* 915 * Force the use of the H_INT_ESB hcall in case of an LSI 916 * interrupt. This is necessary under KVM to re-trigger the 917 * interrupt if the level is still asserted 918 */ 919 if (xive_source_irq_is_lsi(xsrc, lisn)) { 920 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 921 } 922 923 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 924 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 925 } else { 926 args[1] = -1; 927 } 928 929 if (xive_source_esb_has_2page(xsrc) && 930 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 931 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 932 } else { 933 args[2] = -1; 934 } 935 936 if (xive_source_esb_has_2page(xsrc)) { 937 args[3] = xsrc->esb_shift - 1; 938 } else { 939 args[3] = xsrc->esb_shift; 940 } 941 942 return H_SUCCESS; 943 } 944 945 /* 946 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 947 * Interrupt Source to a target. The Logical Interrupt Source is 948 * designated with the "lisn" parameter and the target is designated 949 * with the "target" and "priority" parameters. Upon return from the 950 * hcall(), no additional interrupts will be directed to the old EQ. 951 * 952 * Parameters: 953 * Input: 954 * - R4: "flags" 955 * Bits 0-61: Reserved 956 * Bit 62: set the "eisn" in the EAS 957 * Bit 63: masks the interrupt source in the hardware interrupt 958 * control structure. An interrupt masked by this mechanism will 959 * be dropped, but it's source state bits will still be 960 * set. There is no race-free way of unmasking and restoring the 961 * source. Thus this should only be used in interrupts that are 962 * also masked at the source, and only in cases where the 963 * interrupt is not meant to be used for a large amount of time 964 * because no valid target exists for it for example 965 * - R5: "lisn" is per "interrupts", "interrupt-map", or 966 * "ibm,xive-lisn-ranges" properties, or as returned by the 967 * ibm,query-interrupt-source-number RTAS call, or as returned by 968 * the H_ALLOCATE_VAS_WINDOW hcall 969 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 970 * "ibm,ppc-interrupt-gserver#s" 971 * - R7: "priority" is a valid priority not in 972 * "ibm,plat-res-int-priorities" 973 * - R8: "eisn" is the guest EISN associated with the "lisn" 974 * 975 * Output: 976 * - None 977 */ 978 979 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 980 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 981 982 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 983 SpaprMachineState *spapr, 984 target_ulong opcode, 985 target_ulong *args) 986 { 987 SpaprXive *xive = spapr->xive; 988 XiveEAS eas, new_eas; 989 target_ulong flags = args[0]; 990 target_ulong lisn = args[1]; 991 target_ulong target = args[2]; 992 target_ulong priority = args[3]; 993 target_ulong eisn = args[4]; 994 uint8_t end_blk; 995 uint32_t end_idx; 996 997 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 998 return H_FUNCTION; 999 } 1000 1001 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 1002 return H_PARAMETER; 1003 } 1004 1005 if (lisn >= xive->nr_irqs) { 1006 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1007 lisn); 1008 return H_P2; 1009 } 1010 1011 eas = xive->eat[lisn]; 1012 if (!xive_eas_is_valid(&eas)) { 1013 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1014 lisn); 1015 return H_P2; 1016 } 1017 1018 /* priority 0xff is used to reset the EAS */ 1019 if (priority == 0xff) { 1020 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 1021 goto out; 1022 } 1023 1024 if (flags & SPAPR_XIVE_SRC_MASK) { 1025 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 1026 } else { 1027 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 1028 } 1029 1030 if (spapr_xive_priority_is_reserved(priority)) { 1031 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1032 " is reserved\n", priority); 1033 return H_P4; 1034 } 1035 1036 /* 1037 * Validate that "target" is part of the list of threads allocated 1038 * to the partition. For that, find the END corresponding to the 1039 * target. 1040 */ 1041 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1042 return H_P3; 1043 } 1044 1045 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 1046 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 1047 1048 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 1049 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 1050 } 1051 1052 if (kvm_irqchip_in_kernel()) { 1053 Error *local_err = NULL; 1054 1055 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 1056 if (local_err) { 1057 error_report_err(local_err); 1058 return H_HARDWARE; 1059 } 1060 } 1061 1062 out: 1063 xive->eat[lisn] = new_eas; 1064 return H_SUCCESS; 1065 } 1066 1067 /* 1068 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 1069 * target/priority pair is assigned to the specified Logical Interrupt 1070 * Source. 1071 * 1072 * Parameters: 1073 * Input: 1074 * - R4: "flags" 1075 * Bits 0-63 Reserved 1076 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1077 * "ibm,xive-lisn-ranges" properties, or as returned by the 1078 * ibm,query-interrupt-source-number RTAS call, or as 1079 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1080 * 1081 * Output: 1082 * - R4: Target to which the specified Logical Interrupt Source is 1083 * assigned 1084 * - R5: Priority to which the specified Logical Interrupt Source is 1085 * assigned 1086 * - R6: EISN for the specified Logical Interrupt Source (this will be 1087 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 1088 */ 1089 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 1090 SpaprMachineState *spapr, 1091 target_ulong opcode, 1092 target_ulong *args) 1093 { 1094 SpaprXive *xive = spapr->xive; 1095 target_ulong flags = args[0]; 1096 target_ulong lisn = args[1]; 1097 XiveEAS eas; 1098 XiveEND *end; 1099 uint8_t nvt_blk; 1100 uint32_t end_idx, nvt_idx; 1101 1102 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1103 return H_FUNCTION; 1104 } 1105 1106 if (flags) { 1107 return H_PARAMETER; 1108 } 1109 1110 if (lisn >= xive->nr_irqs) { 1111 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1112 lisn); 1113 return H_P2; 1114 } 1115 1116 eas = xive->eat[lisn]; 1117 if (!xive_eas_is_valid(&eas)) { 1118 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1119 lisn); 1120 return H_P2; 1121 } 1122 1123 /* EAS_END_BLOCK is unused on sPAPR */ 1124 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 1125 1126 assert(end_idx < xive->nr_ends); 1127 end = &xive->endt[end_idx]; 1128 1129 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1130 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1131 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 1132 1133 if (xive_eas_is_masked(&eas)) { 1134 args[1] = 0xff; 1135 } else { 1136 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1137 } 1138 1139 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 1140 1141 return H_SUCCESS; 1142 } 1143 1144 /* 1145 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 1146 * address of the notification management page associated with the 1147 * specified target and priority. 1148 * 1149 * Parameters: 1150 * Input: 1151 * - R4: "flags" 1152 * Bits 0-63 Reserved 1153 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1154 * "ibm,ppc-interrupt-gserver#s" 1155 * - R6: "priority" is a valid priority not in 1156 * "ibm,plat-res-int-priorities" 1157 * 1158 * Output: 1159 * - R4: Logical real address of notification page 1160 * - R5: Power of 2 page size of the notification page 1161 */ 1162 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 1163 SpaprMachineState *spapr, 1164 target_ulong opcode, 1165 target_ulong *args) 1166 { 1167 SpaprXive *xive = spapr->xive; 1168 XiveENDSource *end_xsrc = &xive->end_source; 1169 target_ulong flags = args[0]; 1170 target_ulong target = args[1]; 1171 target_ulong priority = args[2]; 1172 XiveEND *end; 1173 uint8_t end_blk; 1174 uint32_t end_idx; 1175 1176 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1177 return H_FUNCTION; 1178 } 1179 1180 if (flags) { 1181 return H_PARAMETER; 1182 } 1183 1184 /* 1185 * H_STATE should be returned if a H_INT_RESET is in progress. 1186 * This is not needed when running the emulation under QEMU 1187 */ 1188 1189 if (spapr_xive_priority_is_reserved(priority)) { 1190 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1191 " is reserved\n", priority); 1192 return H_P3; 1193 } 1194 1195 /* 1196 * Validate that "target" is part of the list of threads allocated 1197 * to the partition. For that, find the END corresponding to the 1198 * target. 1199 */ 1200 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1201 return H_P2; 1202 } 1203 1204 assert(end_idx < xive->nr_ends); 1205 end = &xive->endt[end_idx]; 1206 1207 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 1208 if (xive_end_is_enqueue(end)) { 1209 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1210 } else { 1211 args[1] = 0; 1212 } 1213 1214 return H_SUCCESS; 1215 } 1216 1217 /* 1218 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 1219 * a given "target" and "priority". It is also used to set the 1220 * notification config associated with the EQ. An EQ size of 0 is 1221 * used to reset the EQ config for a given target and priority. If 1222 * resetting the EQ config, the END associated with the given "target" 1223 * and "priority" will be changed to disable queueing. 1224 * 1225 * Upon return from the hcall(), no additional interrupts will be 1226 * directed to the old EQ (if one was set). The old EQ (if one was 1227 * set) should be investigated for interrupts that occurred prior to 1228 * or during the hcall(). 1229 * 1230 * Parameters: 1231 * Input: 1232 * - R4: "flags" 1233 * Bits 0-62: Reserved 1234 * Bit 63: Unconditional Notify (n) per the XIVE spec 1235 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1236 * "ibm,ppc-interrupt-gserver#s" 1237 * - R6: "priority" is a valid priority not in 1238 * "ibm,plat-res-int-priorities" 1239 * - R7: "eventQueue": The logical real address of the start of the EQ 1240 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1241 * 1242 * Output: 1243 * - None 1244 */ 1245 1246 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1247 1248 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1249 SpaprMachineState *spapr, 1250 target_ulong opcode, 1251 target_ulong *args) 1252 { 1253 SpaprXive *xive = spapr->xive; 1254 target_ulong flags = args[0]; 1255 target_ulong target = args[1]; 1256 target_ulong priority = args[2]; 1257 target_ulong qpage = args[3]; 1258 target_ulong qsize = args[4]; 1259 XiveEND end; 1260 uint8_t end_blk, nvt_blk; 1261 uint32_t end_idx, nvt_idx; 1262 1263 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1264 return H_FUNCTION; 1265 } 1266 1267 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1268 return H_PARAMETER; 1269 } 1270 1271 /* 1272 * H_STATE should be returned if a H_INT_RESET is in progress. 1273 * This is not needed when running the emulation under QEMU 1274 */ 1275 1276 if (spapr_xive_priority_is_reserved(priority)) { 1277 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1278 " is reserved\n", priority); 1279 return H_P3; 1280 } 1281 1282 /* 1283 * Validate that "target" is part of the list of threads allocated 1284 * to the partition. For that, find the END corresponding to the 1285 * target. 1286 */ 1287 1288 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1289 return H_P2; 1290 } 1291 1292 assert(end_idx < xive->nr_ends); 1293 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1294 1295 switch (qsize) { 1296 case 12: 1297 case 16: 1298 case 21: 1299 case 24: 1300 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1301 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1302 " is not naturally aligned with %" HWADDR_PRIx "\n", 1303 qpage, (hwaddr)1 << qsize); 1304 return H_P4; 1305 } 1306 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1307 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1308 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1309 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1310 break; 1311 case 0: 1312 /* reset queue and disable queueing */ 1313 spapr_xive_end_reset(&end); 1314 goto out; 1315 1316 default: 1317 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1318 qsize); 1319 return H_P5; 1320 } 1321 1322 if (qsize) { 1323 hwaddr plen = 1 << qsize; 1324 void *eq; 1325 1326 /* 1327 * Validate the guest EQ. We should also check that the queue 1328 * has been zeroed by the OS. 1329 */ 1330 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1331 MEMTXATTRS_UNSPECIFIED); 1332 if (plen != 1 << qsize) { 1333 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1334 HWADDR_PRIx "\n", qpage); 1335 return H_P4; 1336 } 1337 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1338 } 1339 1340 /* "target" should have been validated above */ 1341 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1342 g_assert_not_reached(); 1343 } 1344 1345 /* 1346 * Ensure the priority and target are correctly set (they will not 1347 * be right after allocation) 1348 */ 1349 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1350 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1351 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1352 1353 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1354 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1355 } else { 1356 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1357 } 1358 1359 /* 1360 * The generation bit for the END starts at 1 and The END page 1361 * offset counter starts at 0. 1362 */ 1363 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1364 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1365 end.w0 |= cpu_to_be32(END_W0_VALID); 1366 1367 /* 1368 * TODO: issue syncs required to ensure all in-flight interrupts 1369 * are complete on the old END 1370 */ 1371 1372 out: 1373 if (kvm_irqchip_in_kernel()) { 1374 Error *local_err = NULL; 1375 1376 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1377 if (local_err) { 1378 error_report_err(local_err); 1379 return H_HARDWARE; 1380 } 1381 } 1382 1383 /* Update END */ 1384 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1385 return H_SUCCESS; 1386 } 1387 1388 /* 1389 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1390 * target and priority. 1391 * 1392 * Parameters: 1393 * Input: 1394 * - R4: "flags" 1395 * Bits 0-62: Reserved 1396 * Bit 63: Debug: Return debug data 1397 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1398 * "ibm,ppc-interrupt-gserver#s" 1399 * - R6: "priority" is a valid priority not in 1400 * "ibm,plat-res-int-priorities" 1401 * 1402 * Output: 1403 * - R4: "flags": 1404 * Bits 0-61: Reserved 1405 * Bit 62: The value of Event Queue Generation Number (g) per 1406 * the XIVE spec if "Debug" = 1 1407 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1408 * - R5: The logical real address of the start of the EQ 1409 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1410 * - R7: The value of Event Queue Offset Counter per XIVE spec 1411 * if "Debug" = 1, else 0 1412 * 1413 */ 1414 1415 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1416 1417 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1418 SpaprMachineState *spapr, 1419 target_ulong opcode, 1420 target_ulong *args) 1421 { 1422 SpaprXive *xive = spapr->xive; 1423 target_ulong flags = args[0]; 1424 target_ulong target = args[1]; 1425 target_ulong priority = args[2]; 1426 XiveEND *end; 1427 uint8_t end_blk; 1428 uint32_t end_idx; 1429 1430 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1431 return H_FUNCTION; 1432 } 1433 1434 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1435 return H_PARAMETER; 1436 } 1437 1438 /* 1439 * H_STATE should be returned if a H_INT_RESET is in progress. 1440 * This is not needed when running the emulation under QEMU 1441 */ 1442 1443 if (spapr_xive_priority_is_reserved(priority)) { 1444 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1445 " is reserved\n", priority); 1446 return H_P3; 1447 } 1448 1449 /* 1450 * Validate that "target" is part of the list of threads allocated 1451 * to the partition. For that, find the END corresponding to the 1452 * target. 1453 */ 1454 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1455 return H_P2; 1456 } 1457 1458 assert(end_idx < xive->nr_ends); 1459 end = &xive->endt[end_idx]; 1460 1461 args[0] = 0; 1462 if (xive_end_is_notify(end)) { 1463 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1464 } 1465 1466 if (xive_end_is_enqueue(end)) { 1467 args[1] = xive_end_qaddr(end); 1468 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1469 } else { 1470 args[1] = 0; 1471 args[2] = 0; 1472 } 1473 1474 if (kvm_irqchip_in_kernel()) { 1475 Error *local_err = NULL; 1476 1477 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1478 if (local_err) { 1479 error_report_err(local_err); 1480 return H_HARDWARE; 1481 } 1482 } 1483 1484 /* TODO: do we need any locking on the END ? */ 1485 if (flags & SPAPR_XIVE_END_DEBUG) { 1486 /* Load the event queue generation number into the return flags */ 1487 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1488 1489 /* Load R7 with the event queue offset counter */ 1490 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1491 } else { 1492 args[3] = 0; 1493 } 1494 1495 return H_SUCCESS; 1496 } 1497 1498 /* 1499 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1500 * reporting cache line pair for the calling thread. The reporting 1501 * cache lines will contain the OS interrupt context when the OS 1502 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1503 * interrupt. The reporting cache lines can be reset by inputting -1 1504 * in "reportingLine". Issuing the CI store byte without reporting 1505 * cache lines registered will result in the data not being accessible 1506 * to the OS. 1507 * 1508 * Parameters: 1509 * Input: 1510 * - R4: "flags" 1511 * Bits 0-63: Reserved 1512 * - R5: "reportingLine": The logical real address of the reporting cache 1513 * line pair 1514 * 1515 * Output: 1516 * - None 1517 */ 1518 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1519 SpaprMachineState *spapr, 1520 target_ulong opcode, 1521 target_ulong *args) 1522 { 1523 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1524 return H_FUNCTION; 1525 } 1526 1527 /* 1528 * H_STATE should be returned if a H_INT_RESET is in progress. 1529 * This is not needed when running the emulation under QEMU 1530 */ 1531 1532 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1533 return H_FUNCTION; 1534 } 1535 1536 /* 1537 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1538 * real address of the reporting cache line pair set for the input 1539 * "target". If no reporting cache line pair has been set, -1 is 1540 * returned. 1541 * 1542 * Parameters: 1543 * Input: 1544 * - R4: "flags" 1545 * Bits 0-63: Reserved 1546 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1547 * "ibm,ppc-interrupt-gserver#s" 1548 * - R6: "reportingLine": The logical real address of the reporting 1549 * cache line pair 1550 * 1551 * Output: 1552 * - R4: The logical real address of the reporting line if set, else -1 1553 */ 1554 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1555 SpaprMachineState *spapr, 1556 target_ulong opcode, 1557 target_ulong *args) 1558 { 1559 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1560 return H_FUNCTION; 1561 } 1562 1563 /* 1564 * H_STATE should be returned if a H_INT_RESET is in progress. 1565 * This is not needed when running the emulation under QEMU 1566 */ 1567 1568 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1569 return H_FUNCTION; 1570 } 1571 1572 /* 1573 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1574 * page for the input "lisn". This hcall is only supported for LISNs 1575 * that have the ESB hcall flag set to 1 when returned from hcall() 1576 * H_INT_GET_SOURCE_INFO. 1577 * 1578 * Parameters: 1579 * Input: 1580 * - R4: "flags" 1581 * Bits 0-62: Reserved 1582 * bit 63: Store: Store=1, store operation, else load operation 1583 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1584 * "ibm,xive-lisn-ranges" properties, or as returned by the 1585 * ibm,query-interrupt-source-number RTAS call, or as 1586 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1587 * - R6: "esbOffset" is the offset into the ESB page for the load or 1588 * store operation 1589 * - R7: "storeData" is the data to write for a store operation 1590 * 1591 * Output: 1592 * - R4: The value of the load if load operation, else -1 1593 */ 1594 1595 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1596 1597 static target_ulong h_int_esb(PowerPCCPU *cpu, 1598 SpaprMachineState *spapr, 1599 target_ulong opcode, 1600 target_ulong *args) 1601 { 1602 SpaprXive *xive = spapr->xive; 1603 XiveEAS eas; 1604 target_ulong flags = args[0]; 1605 target_ulong lisn = args[1]; 1606 target_ulong offset = args[2]; 1607 target_ulong data = args[3]; 1608 hwaddr mmio_addr; 1609 XiveSource *xsrc = &xive->source; 1610 1611 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1612 return H_FUNCTION; 1613 } 1614 1615 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1616 return H_PARAMETER; 1617 } 1618 1619 if (lisn >= xive->nr_irqs) { 1620 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1621 lisn); 1622 return H_P2; 1623 } 1624 1625 eas = xive->eat[lisn]; 1626 if (!xive_eas_is_valid(&eas)) { 1627 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1628 lisn); 1629 return H_P2; 1630 } 1631 1632 if (offset > (1ull << xsrc->esb_shift)) { 1633 return H_P3; 1634 } 1635 1636 if (kvm_irqchip_in_kernel()) { 1637 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1638 flags & SPAPR_XIVE_ESB_STORE); 1639 } else { 1640 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1641 1642 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1643 (flags & SPAPR_XIVE_ESB_STORE))) { 1644 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1645 HWADDR_PRIx "\n", mmio_addr); 1646 return H_HARDWARE; 1647 } 1648 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1649 } 1650 return H_SUCCESS; 1651 } 1652 1653 /* 1654 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1655 * ensure any in flight events for the input lisn are in the event 1656 * queue. 1657 * 1658 * Parameters: 1659 * Input: 1660 * - R4: "flags" 1661 * Bits 0-63: Reserved 1662 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1663 * "ibm,xive-lisn-ranges" properties, or as returned by the 1664 * ibm,query-interrupt-source-number RTAS call, or as 1665 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1666 * 1667 * Output: 1668 * - None 1669 */ 1670 static target_ulong h_int_sync(PowerPCCPU *cpu, 1671 SpaprMachineState *spapr, 1672 target_ulong opcode, 1673 target_ulong *args) 1674 { 1675 SpaprXive *xive = spapr->xive; 1676 XiveEAS eas; 1677 target_ulong flags = args[0]; 1678 target_ulong lisn = args[1]; 1679 1680 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1681 return H_FUNCTION; 1682 } 1683 1684 if (flags) { 1685 return H_PARAMETER; 1686 } 1687 1688 if (lisn >= xive->nr_irqs) { 1689 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1690 lisn); 1691 return H_P2; 1692 } 1693 1694 eas = xive->eat[lisn]; 1695 if (!xive_eas_is_valid(&eas)) { 1696 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1697 lisn); 1698 return H_P2; 1699 } 1700 1701 /* 1702 * H_STATE should be returned if a H_INT_RESET is in progress. 1703 * This is not needed when running the emulation under QEMU 1704 */ 1705 1706 /* 1707 * This is not real hardware. Nothing to be done unless when 1708 * under KVM 1709 */ 1710 1711 if (kvm_irqchip_in_kernel()) { 1712 Error *local_err = NULL; 1713 1714 kvmppc_xive_sync_source(xive, lisn, &local_err); 1715 if (local_err) { 1716 error_report_err(local_err); 1717 return H_HARDWARE; 1718 } 1719 } 1720 return H_SUCCESS; 1721 } 1722 1723 /* 1724 * The H_INT_RESET hcall() is used to reset all of the partition's 1725 * interrupt exploitation structures to their initial state. This 1726 * means losing all previously set interrupt state set via 1727 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1728 * 1729 * Parameters: 1730 * Input: 1731 * - R4: "flags" 1732 * Bits 0-63: Reserved 1733 * 1734 * Output: 1735 * - None 1736 */ 1737 static target_ulong h_int_reset(PowerPCCPU *cpu, 1738 SpaprMachineState *spapr, 1739 target_ulong opcode, 1740 target_ulong *args) 1741 { 1742 SpaprXive *xive = spapr->xive; 1743 target_ulong flags = args[0]; 1744 1745 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1746 return H_FUNCTION; 1747 } 1748 1749 if (flags) { 1750 return H_PARAMETER; 1751 } 1752 1753 device_reset(DEVICE(xive)); 1754 1755 if (kvm_irqchip_in_kernel()) { 1756 Error *local_err = NULL; 1757 1758 kvmppc_xive_reset(xive, &local_err); 1759 if (local_err) { 1760 error_report_err(local_err); 1761 return H_HARDWARE; 1762 } 1763 } 1764 return H_SUCCESS; 1765 } 1766 1767 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1768 { 1769 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1770 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1771 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1772 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1773 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1774 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1775 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1776 h_int_set_os_reporting_line); 1777 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1778 h_int_get_os_reporting_line); 1779 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1780 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1781 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1782 } 1783