1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 } 150 151 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 152 { 153 XiveSource *xsrc = &xive->source; 154 int i; 155 156 if (kvm_irqchip_in_kernel()) { 157 Error *local_err = NULL; 158 159 kvmppc_xive_synchronize_state(xive, &local_err); 160 if (local_err) { 161 error_report_err(local_err); 162 return; 163 } 164 } 165 166 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 167 168 for (i = 0; i < xive->nr_irqs; i++) { 169 uint8_t pq = xive_source_esb_get(xsrc, i); 170 XiveEAS *eas = &xive->eat[i]; 171 172 if (!xive_eas_is_valid(eas)) { 173 continue; 174 } 175 176 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 177 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 178 pq & XIVE_ESB_VAL_P ? 'P' : '-', 179 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 180 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 181 xive_eas_is_masked(eas) ? "M" : " ", 182 (int) xive_get_field64(EAS_END_DATA, eas->w)); 183 184 if (!xive_eas_is_masked(eas)) { 185 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 186 XiveEND *end; 187 188 assert(end_idx < xive->nr_ends); 189 end = &xive->endt[end_idx]; 190 191 if (xive_end_is_valid(end)) { 192 spapr_xive_end_pic_print_info(xive, end, mon); 193 } 194 } 195 monitor_printf(mon, "\n"); 196 } 197 } 198 199 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 200 { 201 memory_region_set_enabled(&xive->source.esb_mmio, enable); 202 memory_region_set_enabled(&xive->tm_mmio, enable); 203 204 /* Disable the END ESBs until a guest OS makes use of them */ 205 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 206 } 207 208 /* 209 * When a Virtual Processor is scheduled to run on a HW thread, the 210 * hypervisor pushes its identifier in the OS CAM line. Emulate the 211 * same behavior under QEMU. 212 */ 213 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 214 { 215 uint8_t nvt_blk; 216 uint32_t nvt_idx; 217 uint32_t nvt_cam; 218 219 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 220 221 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 222 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 223 } 224 225 static void spapr_xive_end_reset(XiveEND *end) 226 { 227 memset(end, 0, sizeof(*end)); 228 229 /* switch off the escalation and notification ESBs */ 230 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 231 } 232 233 static void spapr_xive_reset(void *dev) 234 { 235 SpaprXive *xive = SPAPR_XIVE(dev); 236 int i; 237 238 /* 239 * The XiveSource has its own reset handler, which mask off all 240 * IRQs (!P|Q) 241 */ 242 243 /* Mask all valid EASs in the IRQ number space. */ 244 for (i = 0; i < xive->nr_irqs; i++) { 245 XiveEAS *eas = &xive->eat[i]; 246 if (xive_eas_is_valid(eas)) { 247 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 248 } else { 249 eas->w = 0; 250 } 251 } 252 253 /* Clear all ENDs */ 254 for (i = 0; i < xive->nr_ends; i++) { 255 spapr_xive_end_reset(&xive->endt[i]); 256 } 257 } 258 259 static void spapr_xive_instance_init(Object *obj) 260 { 261 SpaprXive *xive = SPAPR_XIVE(obj); 262 263 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 264 TYPE_XIVE_SOURCE, &error_abort, NULL); 265 266 object_initialize_child(obj, "end_source", &xive->end_source, 267 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 268 &error_abort, NULL); 269 270 /* Not connected to the KVM XIVE device */ 271 xive->fd = -1; 272 } 273 274 static void spapr_xive_realize(DeviceState *dev, Error **errp) 275 { 276 SpaprXive *xive = SPAPR_XIVE(dev); 277 XiveSource *xsrc = &xive->source; 278 XiveENDSource *end_xsrc = &xive->end_source; 279 Error *local_err = NULL; 280 281 if (!xive->nr_irqs) { 282 error_setg(errp, "Number of interrupt needs to be greater 0"); 283 return; 284 } 285 286 if (!xive->nr_ends) { 287 error_setg(errp, "Number of interrupt needs to be greater 0"); 288 return; 289 } 290 291 /* 292 * Initialize the internal sources, for IPIs and virtual devices. 293 */ 294 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 295 &error_fatal); 296 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 297 &error_fatal); 298 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 299 if (local_err) { 300 error_propagate(errp, local_err); 301 return; 302 } 303 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 304 305 /* 306 * Initialize the END ESB source 307 */ 308 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 309 &error_fatal); 310 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 311 &error_fatal); 312 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 313 if (local_err) { 314 error_propagate(errp, local_err); 315 return; 316 } 317 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 318 319 /* Set the mapping address of the END ESB pages after the source ESBs */ 320 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 321 322 /* 323 * Allocate the routing tables 324 */ 325 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 326 xive->endt = g_new0(XiveEND, xive->nr_ends); 327 328 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 329 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 330 331 qemu_register_reset(spapr_xive_reset, dev); 332 333 /* TIMA initialization */ 334 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 335 "xive.tima", 4ull << TM_SHIFT); 336 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 337 338 /* 339 * Map all regions. These will be enabled or disabled at reset and 340 * can also be overridden by KVM memory regions if active 341 */ 342 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 343 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 344 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 345 } 346 347 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 348 uint32_t eas_idx, XiveEAS *eas) 349 { 350 SpaprXive *xive = SPAPR_XIVE(xrtr); 351 352 if (eas_idx >= xive->nr_irqs) { 353 return -1; 354 } 355 356 *eas = xive->eat[eas_idx]; 357 return 0; 358 } 359 360 static int spapr_xive_get_end(XiveRouter *xrtr, 361 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 362 { 363 SpaprXive *xive = SPAPR_XIVE(xrtr); 364 365 if (end_idx >= xive->nr_ends) { 366 return -1; 367 } 368 369 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 370 return 0; 371 } 372 373 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 374 uint32_t end_idx, XiveEND *end, 375 uint8_t word_number) 376 { 377 SpaprXive *xive = SPAPR_XIVE(xrtr); 378 379 if (end_idx >= xive->nr_ends) { 380 return -1; 381 } 382 383 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 384 return 0; 385 } 386 387 static int spapr_xive_get_nvt(XiveRouter *xrtr, 388 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 389 { 390 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 391 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 392 393 if (!cpu) { 394 /* TODO: should we assert() if we can find a NVT ? */ 395 return -1; 396 } 397 398 /* 399 * sPAPR does not maintain a NVT table. Return that the NVT is 400 * valid if we have found a matching CPU 401 */ 402 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 403 return 0; 404 } 405 406 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 407 uint32_t nvt_idx, XiveNVT *nvt, 408 uint8_t word_number) 409 { 410 /* 411 * We don't need to write back to the NVTs because the sPAPR 412 * machine should never hit a non-scheduled NVT. It should never 413 * get called. 414 */ 415 g_assert_not_reached(); 416 } 417 418 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 419 { 420 PowerPCCPU *cpu = POWERPC_CPU(cs); 421 422 return spapr_cpu_state(cpu)->tctx; 423 } 424 425 static const VMStateDescription vmstate_spapr_xive_end = { 426 .name = TYPE_SPAPR_XIVE "/end", 427 .version_id = 1, 428 .minimum_version_id = 1, 429 .fields = (VMStateField []) { 430 VMSTATE_UINT32(w0, XiveEND), 431 VMSTATE_UINT32(w1, XiveEND), 432 VMSTATE_UINT32(w2, XiveEND), 433 VMSTATE_UINT32(w3, XiveEND), 434 VMSTATE_UINT32(w4, XiveEND), 435 VMSTATE_UINT32(w5, XiveEND), 436 VMSTATE_UINT32(w6, XiveEND), 437 VMSTATE_UINT32(w7, XiveEND), 438 VMSTATE_END_OF_LIST() 439 }, 440 }; 441 442 static const VMStateDescription vmstate_spapr_xive_eas = { 443 .name = TYPE_SPAPR_XIVE "/eas", 444 .version_id = 1, 445 .minimum_version_id = 1, 446 .fields = (VMStateField []) { 447 VMSTATE_UINT64(w, XiveEAS), 448 VMSTATE_END_OF_LIST() 449 }, 450 }; 451 452 static int vmstate_spapr_xive_pre_save(void *opaque) 453 { 454 if (kvm_irqchip_in_kernel()) { 455 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 456 } 457 458 return 0; 459 } 460 461 /* 462 * Called by the sPAPR IRQ backend 'post_load' method at the machine 463 * level. 464 */ 465 int spapr_xive_post_load(SpaprXive *xive, int version_id) 466 { 467 if (kvm_irqchip_in_kernel()) { 468 return kvmppc_xive_post_load(xive, version_id); 469 } 470 471 return 0; 472 } 473 474 static const VMStateDescription vmstate_spapr_xive = { 475 .name = TYPE_SPAPR_XIVE, 476 .version_id = 1, 477 .minimum_version_id = 1, 478 .pre_save = vmstate_spapr_xive_pre_save, 479 .post_load = NULL, /* handled at the machine level */ 480 .fields = (VMStateField[]) { 481 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 482 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 483 vmstate_spapr_xive_eas, XiveEAS), 484 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 485 vmstate_spapr_xive_end, XiveEND), 486 VMSTATE_END_OF_LIST() 487 }, 488 }; 489 490 static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, 491 bool lsi, Error **errp) 492 { 493 SpaprXive *xive = SPAPR_XIVE(intc); 494 XiveSource *xsrc = &xive->source; 495 496 assert(lisn < xive->nr_irqs); 497 498 if (xive_eas_is_valid(&xive->eat[lisn])) { 499 error_setg(errp, "IRQ %d is not free", lisn); 500 return -EBUSY; 501 } 502 503 /* 504 * Set default values when allocating an IRQ number 505 */ 506 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); 507 if (lsi) { 508 xive_source_irq_set_lsi(xsrc, lisn); 509 } 510 511 if (kvm_irqchip_in_kernel()) { 512 return kvmppc_xive_source_reset_one(xsrc, lisn, errp); 513 } 514 515 return 0; 516 } 517 518 static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) 519 { 520 SpaprXive *xive = SPAPR_XIVE(intc); 521 assert(lisn < xive->nr_irqs); 522 523 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 524 } 525 526 static Property spapr_xive_properties[] = { 527 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 528 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 529 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 530 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 531 DEFINE_PROP_END_OF_LIST(), 532 }; 533 534 static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 535 PowerPCCPU *cpu, Error **errp) 536 { 537 SpaprXive *xive = SPAPR_XIVE(intc); 538 Object *obj; 539 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 540 541 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp); 542 if (!obj) { 543 return -1; 544 } 545 546 spapr_cpu->tctx = XIVE_TCTX(obj); 547 548 /* 549 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they 550 * don't beneficiate from the reset of the XIVE IRQ backend 551 */ 552 spapr_xive_set_tctx_os_cam(spapr_cpu->tctx); 553 return 0; 554 } 555 556 static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val) 557 { 558 SpaprXive *xive = SPAPR_XIVE(intc); 559 560 if (kvm_irqchip_in_kernel()) { 561 kvmppc_xive_source_set_irq(&xive->source, irq, val); 562 } else { 563 xive_source_set_irq(&xive->source, irq, val); 564 } 565 } 566 567 static void spapr_xive_class_init(ObjectClass *klass, void *data) 568 { 569 DeviceClass *dc = DEVICE_CLASS(klass); 570 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 571 SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); 572 573 dc->desc = "sPAPR XIVE Interrupt Controller"; 574 dc->props = spapr_xive_properties; 575 dc->realize = spapr_xive_realize; 576 dc->vmsd = &vmstate_spapr_xive; 577 578 xrc->get_eas = spapr_xive_get_eas; 579 xrc->get_end = spapr_xive_get_end; 580 xrc->write_end = spapr_xive_write_end; 581 xrc->get_nvt = spapr_xive_get_nvt; 582 xrc->write_nvt = spapr_xive_write_nvt; 583 xrc->get_tctx = spapr_xive_get_tctx; 584 585 sicc->cpu_intc_create = spapr_xive_cpu_intc_create; 586 sicc->claim_irq = spapr_xive_claim_irq; 587 sicc->free_irq = spapr_xive_free_irq; 588 sicc->set_irq = spapr_xive_set_irq; 589 } 590 591 static const TypeInfo spapr_xive_info = { 592 .name = TYPE_SPAPR_XIVE, 593 .parent = TYPE_XIVE_ROUTER, 594 .instance_init = spapr_xive_instance_init, 595 .instance_size = sizeof(SpaprXive), 596 .class_init = spapr_xive_class_init, 597 .interfaces = (InterfaceInfo[]) { 598 { TYPE_SPAPR_INTC }, 599 { } 600 }, 601 }; 602 603 static void spapr_xive_register_types(void) 604 { 605 type_register_static(&spapr_xive_info); 606 } 607 608 type_init(spapr_xive_register_types) 609 610 /* 611 * XIVE hcalls 612 * 613 * The terminology used by the XIVE hcalls is the following : 614 * 615 * TARGET vCPU number 616 * EQ Event Queue assigned by OS to receive event data 617 * ESB page for source interrupt management 618 * LISN Logical Interrupt Source Number identifying a source in the 619 * machine 620 * EISN Effective Interrupt Source Number used by guest OS to 621 * identify source in the guest 622 * 623 * The EAS, END, NVT structures are not exposed. 624 */ 625 626 /* 627 * Linux hosts under OPAL reserve priority 7 for their own escalation 628 * interrupts (DD2.X POWER9). So we only allow the guest to use 629 * priorities [0..6]. 630 */ 631 static bool spapr_xive_priority_is_reserved(uint8_t priority) 632 { 633 switch (priority) { 634 case 0 ... 6: 635 return false; 636 case 7: /* OPAL escalation queue */ 637 default: 638 return true; 639 } 640 } 641 642 /* 643 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 644 * real address of the MMIO page through which the Event State Buffer 645 * entry associated with the value of the "lisn" parameter is managed. 646 * 647 * Parameters: 648 * Input 649 * - R4: "flags" 650 * Bits 0-63 reserved 651 * - R5: "lisn" is per "interrupts", "interrupt-map", or 652 * "ibm,xive-lisn-ranges" properties, or as returned by the 653 * ibm,query-interrupt-source-number RTAS call, or as returned 654 * by the H_ALLOCATE_VAS_WINDOW hcall 655 * 656 * Output 657 * - R4: "flags" 658 * Bits 0-59: Reserved 659 * Bit 60: H_INT_ESB must be used for Event State Buffer 660 * management 661 * Bit 61: 1 == LSI 0 == MSI 662 * Bit 62: the full function page supports trigger 663 * Bit 63: Store EOI Supported 664 * - R5: Logical Real address of full function Event State Buffer 665 * management page, -1 if H_INT_ESB hcall flag is set to 1. 666 * - R6: Logical Real Address of trigger only Event State Buffer 667 * management page or -1. 668 * - R7: Power of 2 page size for the ESB management pages returned in 669 * R5 and R6. 670 */ 671 672 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 673 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 674 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 675 on same page */ 676 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 677 678 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 679 SpaprMachineState *spapr, 680 target_ulong opcode, 681 target_ulong *args) 682 { 683 SpaprXive *xive = spapr->xive; 684 XiveSource *xsrc = &xive->source; 685 target_ulong flags = args[0]; 686 target_ulong lisn = args[1]; 687 688 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 689 return H_FUNCTION; 690 } 691 692 if (flags) { 693 return H_PARAMETER; 694 } 695 696 if (lisn >= xive->nr_irqs) { 697 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 698 lisn); 699 return H_P2; 700 } 701 702 if (!xive_eas_is_valid(&xive->eat[lisn])) { 703 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 704 lisn); 705 return H_P2; 706 } 707 708 /* 709 * All sources are emulated under the main XIVE object and share 710 * the same characteristics. 711 */ 712 args[0] = 0; 713 if (!xive_source_esb_has_2page(xsrc)) { 714 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 715 } 716 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 717 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 718 } 719 720 /* 721 * Force the use of the H_INT_ESB hcall in case of an LSI 722 * interrupt. This is necessary under KVM to re-trigger the 723 * interrupt if the level is still asserted 724 */ 725 if (xive_source_irq_is_lsi(xsrc, lisn)) { 726 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 727 } 728 729 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 730 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 731 } else { 732 args[1] = -1; 733 } 734 735 if (xive_source_esb_has_2page(xsrc) && 736 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 737 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 738 } else { 739 args[2] = -1; 740 } 741 742 if (xive_source_esb_has_2page(xsrc)) { 743 args[3] = xsrc->esb_shift - 1; 744 } else { 745 args[3] = xsrc->esb_shift; 746 } 747 748 return H_SUCCESS; 749 } 750 751 /* 752 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 753 * Interrupt Source to a target. The Logical Interrupt Source is 754 * designated with the "lisn" parameter and the target is designated 755 * with the "target" and "priority" parameters. Upon return from the 756 * hcall(), no additional interrupts will be directed to the old EQ. 757 * 758 * Parameters: 759 * Input: 760 * - R4: "flags" 761 * Bits 0-61: Reserved 762 * Bit 62: set the "eisn" in the EAS 763 * Bit 63: masks the interrupt source in the hardware interrupt 764 * control structure. An interrupt masked by this mechanism will 765 * be dropped, but it's source state bits will still be 766 * set. There is no race-free way of unmasking and restoring the 767 * source. Thus this should only be used in interrupts that are 768 * also masked at the source, and only in cases where the 769 * interrupt is not meant to be used for a large amount of time 770 * because no valid target exists for it for example 771 * - R5: "lisn" is per "interrupts", "interrupt-map", or 772 * "ibm,xive-lisn-ranges" properties, or as returned by the 773 * ibm,query-interrupt-source-number RTAS call, or as returned by 774 * the H_ALLOCATE_VAS_WINDOW hcall 775 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 776 * "ibm,ppc-interrupt-gserver#s" 777 * - R7: "priority" is a valid priority not in 778 * "ibm,plat-res-int-priorities" 779 * - R8: "eisn" is the guest EISN associated with the "lisn" 780 * 781 * Output: 782 * - None 783 */ 784 785 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 786 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 787 788 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 789 SpaprMachineState *spapr, 790 target_ulong opcode, 791 target_ulong *args) 792 { 793 SpaprXive *xive = spapr->xive; 794 XiveEAS eas, new_eas; 795 target_ulong flags = args[0]; 796 target_ulong lisn = args[1]; 797 target_ulong target = args[2]; 798 target_ulong priority = args[3]; 799 target_ulong eisn = args[4]; 800 uint8_t end_blk; 801 uint32_t end_idx; 802 803 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 804 return H_FUNCTION; 805 } 806 807 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 808 return H_PARAMETER; 809 } 810 811 if (lisn >= xive->nr_irqs) { 812 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 813 lisn); 814 return H_P2; 815 } 816 817 eas = xive->eat[lisn]; 818 if (!xive_eas_is_valid(&eas)) { 819 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 820 lisn); 821 return H_P2; 822 } 823 824 /* priority 0xff is used to reset the EAS */ 825 if (priority == 0xff) { 826 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 827 goto out; 828 } 829 830 if (flags & SPAPR_XIVE_SRC_MASK) { 831 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 832 } else { 833 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 834 } 835 836 if (spapr_xive_priority_is_reserved(priority)) { 837 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 838 " is reserved\n", priority); 839 return H_P4; 840 } 841 842 /* 843 * Validate that "target" is part of the list of threads allocated 844 * to the partition. For that, find the END corresponding to the 845 * target. 846 */ 847 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 848 return H_P3; 849 } 850 851 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 852 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 853 854 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 855 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 856 } 857 858 if (kvm_irqchip_in_kernel()) { 859 Error *local_err = NULL; 860 861 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 862 if (local_err) { 863 error_report_err(local_err); 864 return H_HARDWARE; 865 } 866 } 867 868 out: 869 xive->eat[lisn] = new_eas; 870 return H_SUCCESS; 871 } 872 873 /* 874 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 875 * target/priority pair is assigned to the specified Logical Interrupt 876 * Source. 877 * 878 * Parameters: 879 * Input: 880 * - R4: "flags" 881 * Bits 0-63 Reserved 882 * - R5: "lisn" is per "interrupts", "interrupt-map", or 883 * "ibm,xive-lisn-ranges" properties, or as returned by the 884 * ibm,query-interrupt-source-number RTAS call, or as 885 * returned by the H_ALLOCATE_VAS_WINDOW hcall 886 * 887 * Output: 888 * - R4: Target to which the specified Logical Interrupt Source is 889 * assigned 890 * - R5: Priority to which the specified Logical Interrupt Source is 891 * assigned 892 * - R6: EISN for the specified Logical Interrupt Source (this will be 893 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 894 */ 895 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 896 SpaprMachineState *spapr, 897 target_ulong opcode, 898 target_ulong *args) 899 { 900 SpaprXive *xive = spapr->xive; 901 target_ulong flags = args[0]; 902 target_ulong lisn = args[1]; 903 XiveEAS eas; 904 XiveEND *end; 905 uint8_t nvt_blk; 906 uint32_t end_idx, nvt_idx; 907 908 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 909 return H_FUNCTION; 910 } 911 912 if (flags) { 913 return H_PARAMETER; 914 } 915 916 if (lisn >= xive->nr_irqs) { 917 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 918 lisn); 919 return H_P2; 920 } 921 922 eas = xive->eat[lisn]; 923 if (!xive_eas_is_valid(&eas)) { 924 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 925 lisn); 926 return H_P2; 927 } 928 929 /* EAS_END_BLOCK is unused on sPAPR */ 930 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 931 932 assert(end_idx < xive->nr_ends); 933 end = &xive->endt[end_idx]; 934 935 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 936 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 937 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 938 939 if (xive_eas_is_masked(&eas)) { 940 args[1] = 0xff; 941 } else { 942 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 943 } 944 945 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 946 947 return H_SUCCESS; 948 } 949 950 /* 951 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 952 * address of the notification management page associated with the 953 * specified target and priority. 954 * 955 * Parameters: 956 * Input: 957 * - R4: "flags" 958 * Bits 0-63 Reserved 959 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 960 * "ibm,ppc-interrupt-gserver#s" 961 * - R6: "priority" is a valid priority not in 962 * "ibm,plat-res-int-priorities" 963 * 964 * Output: 965 * - R4: Logical real address of notification page 966 * - R5: Power of 2 page size of the notification page 967 */ 968 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 969 SpaprMachineState *spapr, 970 target_ulong opcode, 971 target_ulong *args) 972 { 973 SpaprXive *xive = spapr->xive; 974 XiveENDSource *end_xsrc = &xive->end_source; 975 target_ulong flags = args[0]; 976 target_ulong target = args[1]; 977 target_ulong priority = args[2]; 978 XiveEND *end; 979 uint8_t end_blk; 980 uint32_t end_idx; 981 982 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 983 return H_FUNCTION; 984 } 985 986 if (flags) { 987 return H_PARAMETER; 988 } 989 990 /* 991 * H_STATE should be returned if a H_INT_RESET is in progress. 992 * This is not needed when running the emulation under QEMU 993 */ 994 995 if (spapr_xive_priority_is_reserved(priority)) { 996 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 997 " is reserved\n", priority); 998 return H_P3; 999 } 1000 1001 /* 1002 * Validate that "target" is part of the list of threads allocated 1003 * to the partition. For that, find the END corresponding to the 1004 * target. 1005 */ 1006 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1007 return H_P2; 1008 } 1009 1010 assert(end_idx < xive->nr_ends); 1011 end = &xive->endt[end_idx]; 1012 1013 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 1014 if (xive_end_is_enqueue(end)) { 1015 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1016 } else { 1017 args[1] = 0; 1018 } 1019 1020 return H_SUCCESS; 1021 } 1022 1023 /* 1024 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 1025 * a given "target" and "priority". It is also used to set the 1026 * notification config associated with the EQ. An EQ size of 0 is 1027 * used to reset the EQ config for a given target and priority. If 1028 * resetting the EQ config, the END associated with the given "target" 1029 * and "priority" will be changed to disable queueing. 1030 * 1031 * Upon return from the hcall(), no additional interrupts will be 1032 * directed to the old EQ (if one was set). The old EQ (if one was 1033 * set) should be investigated for interrupts that occurred prior to 1034 * or during the hcall(). 1035 * 1036 * Parameters: 1037 * Input: 1038 * - R4: "flags" 1039 * Bits 0-62: Reserved 1040 * Bit 63: Unconditional Notify (n) per the XIVE spec 1041 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1042 * "ibm,ppc-interrupt-gserver#s" 1043 * - R6: "priority" is a valid priority not in 1044 * "ibm,plat-res-int-priorities" 1045 * - R7: "eventQueue": The logical real address of the start of the EQ 1046 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1047 * 1048 * Output: 1049 * - None 1050 */ 1051 1052 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1053 1054 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1055 SpaprMachineState *spapr, 1056 target_ulong opcode, 1057 target_ulong *args) 1058 { 1059 SpaprXive *xive = spapr->xive; 1060 target_ulong flags = args[0]; 1061 target_ulong target = args[1]; 1062 target_ulong priority = args[2]; 1063 target_ulong qpage = args[3]; 1064 target_ulong qsize = args[4]; 1065 XiveEND end; 1066 uint8_t end_blk, nvt_blk; 1067 uint32_t end_idx, nvt_idx; 1068 1069 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1070 return H_FUNCTION; 1071 } 1072 1073 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1074 return H_PARAMETER; 1075 } 1076 1077 /* 1078 * H_STATE should be returned if a H_INT_RESET is in progress. 1079 * This is not needed when running the emulation under QEMU 1080 */ 1081 1082 if (spapr_xive_priority_is_reserved(priority)) { 1083 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1084 " is reserved\n", priority); 1085 return H_P3; 1086 } 1087 1088 /* 1089 * Validate that "target" is part of the list of threads allocated 1090 * to the partition. For that, find the END corresponding to the 1091 * target. 1092 */ 1093 1094 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1095 return H_P2; 1096 } 1097 1098 assert(end_idx < xive->nr_ends); 1099 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1100 1101 switch (qsize) { 1102 case 12: 1103 case 16: 1104 case 21: 1105 case 24: 1106 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1107 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1108 " is not naturally aligned with %" HWADDR_PRIx "\n", 1109 qpage, (hwaddr)1 << qsize); 1110 return H_P4; 1111 } 1112 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1113 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1114 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1115 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1116 break; 1117 case 0: 1118 /* reset queue and disable queueing */ 1119 spapr_xive_end_reset(&end); 1120 goto out; 1121 1122 default: 1123 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1124 qsize); 1125 return H_P5; 1126 } 1127 1128 if (qsize) { 1129 hwaddr plen = 1 << qsize; 1130 void *eq; 1131 1132 /* 1133 * Validate the guest EQ. We should also check that the queue 1134 * has been zeroed by the OS. 1135 */ 1136 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1137 MEMTXATTRS_UNSPECIFIED); 1138 if (plen != 1 << qsize) { 1139 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1140 HWADDR_PRIx "\n", qpage); 1141 return H_P4; 1142 } 1143 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1144 } 1145 1146 /* "target" should have been validated above */ 1147 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1148 g_assert_not_reached(); 1149 } 1150 1151 /* 1152 * Ensure the priority and target are correctly set (they will not 1153 * be right after allocation) 1154 */ 1155 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1156 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1157 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1158 1159 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1160 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1161 } else { 1162 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1163 } 1164 1165 /* 1166 * The generation bit for the END starts at 1 and The END page 1167 * offset counter starts at 0. 1168 */ 1169 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1170 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1171 end.w0 |= cpu_to_be32(END_W0_VALID); 1172 1173 /* 1174 * TODO: issue syncs required to ensure all in-flight interrupts 1175 * are complete on the old END 1176 */ 1177 1178 out: 1179 if (kvm_irqchip_in_kernel()) { 1180 Error *local_err = NULL; 1181 1182 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1183 if (local_err) { 1184 error_report_err(local_err); 1185 return H_HARDWARE; 1186 } 1187 } 1188 1189 /* Update END */ 1190 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1191 return H_SUCCESS; 1192 } 1193 1194 /* 1195 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1196 * target and priority. 1197 * 1198 * Parameters: 1199 * Input: 1200 * - R4: "flags" 1201 * Bits 0-62: Reserved 1202 * Bit 63: Debug: Return debug data 1203 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1204 * "ibm,ppc-interrupt-gserver#s" 1205 * - R6: "priority" is a valid priority not in 1206 * "ibm,plat-res-int-priorities" 1207 * 1208 * Output: 1209 * - R4: "flags": 1210 * Bits 0-61: Reserved 1211 * Bit 62: The value of Event Queue Generation Number (g) per 1212 * the XIVE spec if "Debug" = 1 1213 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1214 * - R5: The logical real address of the start of the EQ 1215 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1216 * - R7: The value of Event Queue Offset Counter per XIVE spec 1217 * if "Debug" = 1, else 0 1218 * 1219 */ 1220 1221 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1222 1223 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1224 SpaprMachineState *spapr, 1225 target_ulong opcode, 1226 target_ulong *args) 1227 { 1228 SpaprXive *xive = spapr->xive; 1229 target_ulong flags = args[0]; 1230 target_ulong target = args[1]; 1231 target_ulong priority = args[2]; 1232 XiveEND *end; 1233 uint8_t end_blk; 1234 uint32_t end_idx; 1235 1236 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1237 return H_FUNCTION; 1238 } 1239 1240 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1241 return H_PARAMETER; 1242 } 1243 1244 /* 1245 * H_STATE should be returned if a H_INT_RESET is in progress. 1246 * This is not needed when running the emulation under QEMU 1247 */ 1248 1249 if (spapr_xive_priority_is_reserved(priority)) { 1250 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1251 " is reserved\n", priority); 1252 return H_P3; 1253 } 1254 1255 /* 1256 * Validate that "target" is part of the list of threads allocated 1257 * to the partition. For that, find the END corresponding to the 1258 * target. 1259 */ 1260 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1261 return H_P2; 1262 } 1263 1264 assert(end_idx < xive->nr_ends); 1265 end = &xive->endt[end_idx]; 1266 1267 args[0] = 0; 1268 if (xive_end_is_notify(end)) { 1269 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1270 } 1271 1272 if (xive_end_is_enqueue(end)) { 1273 args[1] = xive_end_qaddr(end); 1274 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1275 } else { 1276 args[1] = 0; 1277 args[2] = 0; 1278 } 1279 1280 if (kvm_irqchip_in_kernel()) { 1281 Error *local_err = NULL; 1282 1283 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1284 if (local_err) { 1285 error_report_err(local_err); 1286 return H_HARDWARE; 1287 } 1288 } 1289 1290 /* TODO: do we need any locking on the END ? */ 1291 if (flags & SPAPR_XIVE_END_DEBUG) { 1292 /* Load the event queue generation number into the return flags */ 1293 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1294 1295 /* Load R7 with the event queue offset counter */ 1296 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1297 } else { 1298 args[3] = 0; 1299 } 1300 1301 return H_SUCCESS; 1302 } 1303 1304 /* 1305 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1306 * reporting cache line pair for the calling thread. The reporting 1307 * cache lines will contain the OS interrupt context when the OS 1308 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1309 * interrupt. The reporting cache lines can be reset by inputting -1 1310 * in "reportingLine". Issuing the CI store byte without reporting 1311 * cache lines registered will result in the data not being accessible 1312 * to the OS. 1313 * 1314 * Parameters: 1315 * Input: 1316 * - R4: "flags" 1317 * Bits 0-63: Reserved 1318 * - R5: "reportingLine": The logical real address of the reporting cache 1319 * line pair 1320 * 1321 * Output: 1322 * - None 1323 */ 1324 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1325 SpaprMachineState *spapr, 1326 target_ulong opcode, 1327 target_ulong *args) 1328 { 1329 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1330 return H_FUNCTION; 1331 } 1332 1333 /* 1334 * H_STATE should be returned if a H_INT_RESET is in progress. 1335 * This is not needed when running the emulation under QEMU 1336 */ 1337 1338 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1339 return H_FUNCTION; 1340 } 1341 1342 /* 1343 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1344 * real address of the reporting cache line pair set for the input 1345 * "target". If no reporting cache line pair has been set, -1 is 1346 * returned. 1347 * 1348 * Parameters: 1349 * Input: 1350 * - R4: "flags" 1351 * Bits 0-63: Reserved 1352 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1353 * "ibm,ppc-interrupt-gserver#s" 1354 * - R6: "reportingLine": The logical real address of the reporting 1355 * cache line pair 1356 * 1357 * Output: 1358 * - R4: The logical real address of the reporting line if set, else -1 1359 */ 1360 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1361 SpaprMachineState *spapr, 1362 target_ulong opcode, 1363 target_ulong *args) 1364 { 1365 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1366 return H_FUNCTION; 1367 } 1368 1369 /* 1370 * H_STATE should be returned if a H_INT_RESET is in progress. 1371 * This is not needed when running the emulation under QEMU 1372 */ 1373 1374 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1375 return H_FUNCTION; 1376 } 1377 1378 /* 1379 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1380 * page for the input "lisn". This hcall is only supported for LISNs 1381 * that have the ESB hcall flag set to 1 when returned from hcall() 1382 * H_INT_GET_SOURCE_INFO. 1383 * 1384 * Parameters: 1385 * Input: 1386 * - R4: "flags" 1387 * Bits 0-62: Reserved 1388 * bit 63: Store: Store=1, store operation, else load operation 1389 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1390 * "ibm,xive-lisn-ranges" properties, or as returned by the 1391 * ibm,query-interrupt-source-number RTAS call, or as 1392 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1393 * - R6: "esbOffset" is the offset into the ESB page for the load or 1394 * store operation 1395 * - R7: "storeData" is the data to write for a store operation 1396 * 1397 * Output: 1398 * - R4: The value of the load if load operation, else -1 1399 */ 1400 1401 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1402 1403 static target_ulong h_int_esb(PowerPCCPU *cpu, 1404 SpaprMachineState *spapr, 1405 target_ulong opcode, 1406 target_ulong *args) 1407 { 1408 SpaprXive *xive = spapr->xive; 1409 XiveEAS eas; 1410 target_ulong flags = args[0]; 1411 target_ulong lisn = args[1]; 1412 target_ulong offset = args[2]; 1413 target_ulong data = args[3]; 1414 hwaddr mmio_addr; 1415 XiveSource *xsrc = &xive->source; 1416 1417 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1418 return H_FUNCTION; 1419 } 1420 1421 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1422 return H_PARAMETER; 1423 } 1424 1425 if (lisn >= xive->nr_irqs) { 1426 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1427 lisn); 1428 return H_P2; 1429 } 1430 1431 eas = xive->eat[lisn]; 1432 if (!xive_eas_is_valid(&eas)) { 1433 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1434 lisn); 1435 return H_P2; 1436 } 1437 1438 if (offset > (1ull << xsrc->esb_shift)) { 1439 return H_P3; 1440 } 1441 1442 if (kvm_irqchip_in_kernel()) { 1443 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1444 flags & SPAPR_XIVE_ESB_STORE); 1445 } else { 1446 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1447 1448 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1449 (flags & SPAPR_XIVE_ESB_STORE))) { 1450 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1451 HWADDR_PRIx "\n", mmio_addr); 1452 return H_HARDWARE; 1453 } 1454 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1455 } 1456 return H_SUCCESS; 1457 } 1458 1459 /* 1460 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1461 * ensure any in flight events for the input lisn are in the event 1462 * queue. 1463 * 1464 * Parameters: 1465 * Input: 1466 * - R4: "flags" 1467 * Bits 0-63: Reserved 1468 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1469 * "ibm,xive-lisn-ranges" properties, or as returned by the 1470 * ibm,query-interrupt-source-number RTAS call, or as 1471 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1472 * 1473 * Output: 1474 * - None 1475 */ 1476 static target_ulong h_int_sync(PowerPCCPU *cpu, 1477 SpaprMachineState *spapr, 1478 target_ulong opcode, 1479 target_ulong *args) 1480 { 1481 SpaprXive *xive = spapr->xive; 1482 XiveEAS eas; 1483 target_ulong flags = args[0]; 1484 target_ulong lisn = args[1]; 1485 1486 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1487 return H_FUNCTION; 1488 } 1489 1490 if (flags) { 1491 return H_PARAMETER; 1492 } 1493 1494 if (lisn >= xive->nr_irqs) { 1495 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1496 lisn); 1497 return H_P2; 1498 } 1499 1500 eas = xive->eat[lisn]; 1501 if (!xive_eas_is_valid(&eas)) { 1502 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1503 lisn); 1504 return H_P2; 1505 } 1506 1507 /* 1508 * H_STATE should be returned if a H_INT_RESET is in progress. 1509 * This is not needed when running the emulation under QEMU 1510 */ 1511 1512 /* 1513 * This is not real hardware. Nothing to be done unless when 1514 * under KVM 1515 */ 1516 1517 if (kvm_irqchip_in_kernel()) { 1518 Error *local_err = NULL; 1519 1520 kvmppc_xive_sync_source(xive, lisn, &local_err); 1521 if (local_err) { 1522 error_report_err(local_err); 1523 return H_HARDWARE; 1524 } 1525 } 1526 return H_SUCCESS; 1527 } 1528 1529 /* 1530 * The H_INT_RESET hcall() is used to reset all of the partition's 1531 * interrupt exploitation structures to their initial state. This 1532 * means losing all previously set interrupt state set via 1533 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1534 * 1535 * Parameters: 1536 * Input: 1537 * - R4: "flags" 1538 * Bits 0-63: Reserved 1539 * 1540 * Output: 1541 * - None 1542 */ 1543 static target_ulong h_int_reset(PowerPCCPU *cpu, 1544 SpaprMachineState *spapr, 1545 target_ulong opcode, 1546 target_ulong *args) 1547 { 1548 SpaprXive *xive = spapr->xive; 1549 target_ulong flags = args[0]; 1550 1551 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1552 return H_FUNCTION; 1553 } 1554 1555 if (flags) { 1556 return H_PARAMETER; 1557 } 1558 1559 device_reset(DEVICE(xive)); 1560 1561 if (kvm_irqchip_in_kernel()) { 1562 Error *local_err = NULL; 1563 1564 kvmppc_xive_reset(xive, &local_err); 1565 if (local_err) { 1566 error_report_err(local_err); 1567 return H_HARDWARE; 1568 } 1569 } 1570 return H_SUCCESS; 1571 } 1572 1573 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1574 { 1575 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1576 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1577 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1578 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1579 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1580 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1581 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1582 h_int_set_os_reporting_line); 1583 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1584 h_int_get_os_reporting_line); 1585 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1586 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1587 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1588 } 1589 1590 void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, 1591 uint32_t phandle) 1592 { 1593 SpaprXive *xive = spapr->xive; 1594 int node; 1595 uint64_t timas[2 * 2]; 1596 /* Interrupt number ranges for the IPIs */ 1597 uint32_t lisn_ranges[] = { 1598 cpu_to_be32(0), 1599 cpu_to_be32(nr_servers), 1600 }; 1601 /* 1602 * EQ size - the sizes of pages supported by the system 4K, 64K, 1603 * 2M, 16M. We only advertise 64K for the moment. 1604 */ 1605 uint32_t eq_sizes[] = { 1606 cpu_to_be32(16), /* 64K */ 1607 }; 1608 /* 1609 * The following array is in sync with the reserved priorities 1610 * defined by the 'spapr_xive_priority_is_reserved' routine. 1611 */ 1612 uint32_t plat_res_int_priorities[] = { 1613 cpu_to_be32(7), /* start */ 1614 cpu_to_be32(0xf8), /* count */ 1615 }; 1616 1617 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 1618 timas[0] = cpu_to_be64(xive->tm_base + 1619 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 1620 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 1621 timas[2] = cpu_to_be64(xive->tm_base + 1622 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 1623 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 1624 1625 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 1626 1627 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 1628 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 1629 1630 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 1631 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 1632 sizeof(eq_sizes))); 1633 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 1634 sizeof(lisn_ranges))); 1635 1636 /* For Linux to link the LSIs to the interrupt controller. */ 1637 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 1638 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 1639 1640 /* For SLOF */ 1641 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 1642 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 1643 1644 /* 1645 * The "ibm,plat-res-int-priorities" property defines the priority 1646 * ranges reserved by the hypervisor 1647 */ 1648 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 1649 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 1650 } 1651