1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 } 150 151 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 152 { 153 XiveSource *xsrc = &xive->source; 154 int i; 155 156 if (kvm_irqchip_in_kernel()) { 157 Error *local_err = NULL; 158 159 kvmppc_xive_synchronize_state(xive, &local_err); 160 if (local_err) { 161 error_report_err(local_err); 162 return; 163 } 164 } 165 166 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 167 168 for (i = 0; i < xive->nr_irqs; i++) { 169 uint8_t pq = xive_source_esb_get(xsrc, i); 170 XiveEAS *eas = &xive->eat[i]; 171 172 if (!xive_eas_is_valid(eas)) { 173 continue; 174 } 175 176 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 177 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 178 pq & XIVE_ESB_VAL_P ? 'P' : '-', 179 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 180 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 181 xive_eas_is_masked(eas) ? "M" : " ", 182 (int) xive_get_field64(EAS_END_DATA, eas->w)); 183 184 if (!xive_eas_is_masked(eas)) { 185 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 186 XiveEND *end; 187 188 assert(end_idx < xive->nr_ends); 189 end = &xive->endt[end_idx]; 190 191 if (xive_end_is_valid(end)) { 192 spapr_xive_end_pic_print_info(xive, end, mon); 193 } 194 } 195 monitor_printf(mon, "\n"); 196 } 197 } 198 199 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 200 { 201 memory_region_set_enabled(&xive->source.esb_mmio, enable); 202 memory_region_set_enabled(&xive->tm_mmio, enable); 203 204 /* Disable the END ESBs until a guest OS makes use of them */ 205 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 206 } 207 208 /* 209 * When a Virtual Processor is scheduled to run on a HW thread, the 210 * hypervisor pushes its identifier in the OS CAM line. Emulate the 211 * same behavior under QEMU. 212 */ 213 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 214 { 215 uint8_t nvt_blk; 216 uint32_t nvt_idx; 217 uint32_t nvt_cam; 218 219 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 220 221 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 222 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 223 } 224 225 static void spapr_xive_end_reset(XiveEND *end) 226 { 227 memset(end, 0, sizeof(*end)); 228 229 /* switch off the escalation and notification ESBs */ 230 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 231 } 232 233 static void spapr_xive_reset(void *dev) 234 { 235 SpaprXive *xive = SPAPR_XIVE(dev); 236 int i; 237 238 /* 239 * The XiveSource has its own reset handler, which mask off all 240 * IRQs (!P|Q) 241 */ 242 243 /* Mask all valid EASs in the IRQ number space. */ 244 for (i = 0; i < xive->nr_irqs; i++) { 245 XiveEAS *eas = &xive->eat[i]; 246 if (xive_eas_is_valid(eas)) { 247 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 248 } else { 249 eas->w = 0; 250 } 251 } 252 253 /* Clear all ENDs */ 254 for (i = 0; i < xive->nr_ends; i++) { 255 spapr_xive_end_reset(&xive->endt[i]); 256 } 257 } 258 259 static void spapr_xive_instance_init(Object *obj) 260 { 261 SpaprXive *xive = SPAPR_XIVE(obj); 262 263 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 264 TYPE_XIVE_SOURCE, &error_abort, NULL); 265 266 object_initialize_child(obj, "end_source", &xive->end_source, 267 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 268 &error_abort, NULL); 269 270 /* Not connected to the KVM XIVE device */ 271 xive->fd = -1; 272 } 273 274 static void spapr_xive_realize(DeviceState *dev, Error **errp) 275 { 276 SpaprXive *xive = SPAPR_XIVE(dev); 277 XiveSource *xsrc = &xive->source; 278 XiveENDSource *end_xsrc = &xive->end_source; 279 Error *local_err = NULL; 280 281 if (!xive->nr_irqs) { 282 error_setg(errp, "Number of interrupt needs to be greater 0"); 283 return; 284 } 285 286 if (!xive->nr_ends) { 287 error_setg(errp, "Number of interrupt needs to be greater 0"); 288 return; 289 } 290 291 /* 292 * Initialize the internal sources, for IPIs and virtual devices. 293 */ 294 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 295 &error_fatal); 296 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 297 &error_fatal); 298 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 299 if (local_err) { 300 error_propagate(errp, local_err); 301 return; 302 } 303 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 304 305 /* 306 * Initialize the END ESB source 307 */ 308 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 309 &error_fatal); 310 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 311 &error_fatal); 312 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 313 if (local_err) { 314 error_propagate(errp, local_err); 315 return; 316 } 317 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 318 319 /* Set the mapping address of the END ESB pages after the source ESBs */ 320 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 321 322 /* 323 * Allocate the routing tables 324 */ 325 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 326 xive->endt = g_new0(XiveEND, xive->nr_ends); 327 328 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 329 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 330 331 qemu_register_reset(spapr_xive_reset, dev); 332 333 /* TIMA initialization */ 334 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 335 "xive.tima", 4ull << TM_SHIFT); 336 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 337 338 /* 339 * Map all regions. These will be enabled or disabled at reset and 340 * can also be overridden by KVM memory regions if active 341 */ 342 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 343 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 344 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 345 } 346 347 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 348 uint32_t eas_idx, XiveEAS *eas) 349 { 350 SpaprXive *xive = SPAPR_XIVE(xrtr); 351 352 if (eas_idx >= xive->nr_irqs) { 353 return -1; 354 } 355 356 *eas = xive->eat[eas_idx]; 357 return 0; 358 } 359 360 static int spapr_xive_get_end(XiveRouter *xrtr, 361 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 362 { 363 SpaprXive *xive = SPAPR_XIVE(xrtr); 364 365 if (end_idx >= xive->nr_ends) { 366 return -1; 367 } 368 369 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 370 return 0; 371 } 372 373 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 374 uint32_t end_idx, XiveEND *end, 375 uint8_t word_number) 376 { 377 SpaprXive *xive = SPAPR_XIVE(xrtr); 378 379 if (end_idx >= xive->nr_ends) { 380 return -1; 381 } 382 383 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 384 return 0; 385 } 386 387 static int spapr_xive_get_nvt(XiveRouter *xrtr, 388 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 389 { 390 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 391 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 392 393 if (!cpu) { 394 /* TODO: should we assert() if we can find a NVT ? */ 395 return -1; 396 } 397 398 /* 399 * sPAPR does not maintain a NVT table. Return that the NVT is 400 * valid if we have found a matching CPU 401 */ 402 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 403 return 0; 404 } 405 406 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 407 uint32_t nvt_idx, XiveNVT *nvt, 408 uint8_t word_number) 409 { 410 /* 411 * We don't need to write back to the NVTs because the sPAPR 412 * machine should never hit a non-scheduled NVT. It should never 413 * get called. 414 */ 415 g_assert_not_reached(); 416 } 417 418 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 419 { 420 PowerPCCPU *cpu = POWERPC_CPU(cs); 421 422 return spapr_cpu_state(cpu)->tctx; 423 } 424 425 static const VMStateDescription vmstate_spapr_xive_end = { 426 .name = TYPE_SPAPR_XIVE "/end", 427 .version_id = 1, 428 .minimum_version_id = 1, 429 .fields = (VMStateField []) { 430 VMSTATE_UINT32(w0, XiveEND), 431 VMSTATE_UINT32(w1, XiveEND), 432 VMSTATE_UINT32(w2, XiveEND), 433 VMSTATE_UINT32(w3, XiveEND), 434 VMSTATE_UINT32(w4, XiveEND), 435 VMSTATE_UINT32(w5, XiveEND), 436 VMSTATE_UINT32(w6, XiveEND), 437 VMSTATE_UINT32(w7, XiveEND), 438 VMSTATE_END_OF_LIST() 439 }, 440 }; 441 442 static const VMStateDescription vmstate_spapr_xive_eas = { 443 .name = TYPE_SPAPR_XIVE "/eas", 444 .version_id = 1, 445 .minimum_version_id = 1, 446 .fields = (VMStateField []) { 447 VMSTATE_UINT64(w, XiveEAS), 448 VMSTATE_END_OF_LIST() 449 }, 450 }; 451 452 static int vmstate_spapr_xive_pre_save(void *opaque) 453 { 454 if (kvm_irqchip_in_kernel()) { 455 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 456 } 457 458 return 0; 459 } 460 461 /* 462 * Called by the sPAPR IRQ backend 'post_load' method at the machine 463 * level. 464 */ 465 static int spapr_xive_post_load(SpaprInterruptController *intc, int version_id) 466 { 467 if (kvm_irqchip_in_kernel()) { 468 return kvmppc_xive_post_load(SPAPR_XIVE(intc), version_id); 469 } 470 471 return 0; 472 } 473 474 static const VMStateDescription vmstate_spapr_xive = { 475 .name = TYPE_SPAPR_XIVE, 476 .version_id = 1, 477 .minimum_version_id = 1, 478 .pre_save = vmstate_spapr_xive_pre_save, 479 .post_load = NULL, /* handled at the machine level */ 480 .fields = (VMStateField[]) { 481 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 482 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 483 vmstate_spapr_xive_eas, XiveEAS), 484 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 485 vmstate_spapr_xive_end, XiveEND), 486 VMSTATE_END_OF_LIST() 487 }, 488 }; 489 490 static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, 491 bool lsi, Error **errp) 492 { 493 SpaprXive *xive = SPAPR_XIVE(intc); 494 XiveSource *xsrc = &xive->source; 495 496 assert(lisn < xive->nr_irqs); 497 498 if (xive_eas_is_valid(&xive->eat[lisn])) { 499 error_setg(errp, "IRQ %d is not free", lisn); 500 return -EBUSY; 501 } 502 503 /* 504 * Set default values when allocating an IRQ number 505 */ 506 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); 507 if (lsi) { 508 xive_source_irq_set_lsi(xsrc, lisn); 509 } 510 511 if (kvm_irqchip_in_kernel()) { 512 return kvmppc_xive_source_reset_one(xsrc, lisn, errp); 513 } 514 515 return 0; 516 } 517 518 static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) 519 { 520 SpaprXive *xive = SPAPR_XIVE(intc); 521 assert(lisn < xive->nr_irqs); 522 523 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 524 } 525 526 static Property spapr_xive_properties[] = { 527 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 528 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 529 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 530 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 531 DEFINE_PROP_END_OF_LIST(), 532 }; 533 534 static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 535 PowerPCCPU *cpu, Error **errp) 536 { 537 SpaprXive *xive = SPAPR_XIVE(intc); 538 Object *obj; 539 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 540 541 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp); 542 if (!obj) { 543 return -1; 544 } 545 546 spapr_cpu->tctx = XIVE_TCTX(obj); 547 548 /* 549 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they 550 * don't beneficiate from the reset of the XIVE IRQ backend 551 */ 552 spapr_xive_set_tctx_os_cam(spapr_cpu->tctx); 553 return 0; 554 } 555 556 static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val) 557 { 558 SpaprXive *xive = SPAPR_XIVE(intc); 559 560 if (kvm_irqchip_in_kernel()) { 561 kvmppc_xive_source_set_irq(&xive->source, irq, val); 562 } else { 563 xive_source_set_irq(&xive->source, irq, val); 564 } 565 } 566 567 static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor *mon) 568 { 569 SpaprXive *xive = SPAPR_XIVE(intc); 570 CPUState *cs; 571 572 CPU_FOREACH(cs) { 573 PowerPCCPU *cpu = POWERPC_CPU(cs); 574 575 xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); 576 } 577 578 spapr_xive_pic_print_info(xive, mon); 579 } 580 581 static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers, 582 void *fdt, uint32_t phandle) 583 { 584 SpaprXive *xive = SPAPR_XIVE(intc); 585 int node; 586 uint64_t timas[2 * 2]; 587 /* Interrupt number ranges for the IPIs */ 588 uint32_t lisn_ranges[] = { 589 cpu_to_be32(0), 590 cpu_to_be32(nr_servers), 591 }; 592 /* 593 * EQ size - the sizes of pages supported by the system 4K, 64K, 594 * 2M, 16M. We only advertise 64K for the moment. 595 */ 596 uint32_t eq_sizes[] = { 597 cpu_to_be32(16), /* 64K */ 598 }; 599 /* 600 * The following array is in sync with the reserved priorities 601 * defined by the 'spapr_xive_priority_is_reserved' routine. 602 */ 603 uint32_t plat_res_int_priorities[] = { 604 cpu_to_be32(7), /* start */ 605 cpu_to_be32(0xf8), /* count */ 606 }; 607 608 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 609 timas[0] = cpu_to_be64(xive->tm_base + 610 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 611 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 612 timas[2] = cpu_to_be64(xive->tm_base + 613 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 614 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 615 616 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 617 618 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 619 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 620 621 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 622 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 623 sizeof(eq_sizes))); 624 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 625 sizeof(lisn_ranges))); 626 627 /* For Linux to link the LSIs to the interrupt controller. */ 628 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 629 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 630 631 /* For SLOF */ 632 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 633 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 634 635 /* 636 * The "ibm,plat-res-int-priorities" property defines the priority 637 * ranges reserved by the hypervisor 638 */ 639 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 640 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 641 } 642 643 static int spapr_xive_activate(SpaprInterruptController *intc, Error **errp) 644 { 645 SpaprXive *xive = SPAPR_XIVE(intc); 646 CPUState *cs; 647 648 CPU_FOREACH(cs) { 649 PowerPCCPU *cpu = POWERPC_CPU(cs); 650 651 /* (TCG) Set the OS CAM line of the thread interrupt context. */ 652 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx); 653 } 654 655 if (kvm_enabled()) { 656 int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, errp); 657 if (rc < 0) { 658 return rc; 659 } 660 } 661 662 /* Activate the XIVE MMIOs */ 663 spapr_xive_mmio_set_enabled(xive, true); 664 665 return 0; 666 } 667 668 static void spapr_xive_deactivate(SpaprInterruptController *intc) 669 { 670 SpaprXive *xive = SPAPR_XIVE(intc); 671 672 spapr_xive_mmio_set_enabled(xive, false); 673 674 if (kvm_irqchip_in_kernel()) { 675 kvmppc_xive_disconnect(intc); 676 } 677 } 678 679 static void spapr_xive_class_init(ObjectClass *klass, void *data) 680 { 681 DeviceClass *dc = DEVICE_CLASS(klass); 682 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 683 SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); 684 685 dc->desc = "sPAPR XIVE Interrupt Controller"; 686 dc->props = spapr_xive_properties; 687 dc->realize = spapr_xive_realize; 688 dc->vmsd = &vmstate_spapr_xive; 689 690 xrc->get_eas = spapr_xive_get_eas; 691 xrc->get_end = spapr_xive_get_end; 692 xrc->write_end = spapr_xive_write_end; 693 xrc->get_nvt = spapr_xive_get_nvt; 694 xrc->write_nvt = spapr_xive_write_nvt; 695 xrc->get_tctx = spapr_xive_get_tctx; 696 697 sicc->activate = spapr_xive_activate; 698 sicc->deactivate = spapr_xive_deactivate; 699 sicc->cpu_intc_create = spapr_xive_cpu_intc_create; 700 sicc->claim_irq = spapr_xive_claim_irq; 701 sicc->free_irq = spapr_xive_free_irq; 702 sicc->set_irq = spapr_xive_set_irq; 703 sicc->print_info = spapr_xive_print_info; 704 sicc->dt = spapr_xive_dt; 705 sicc->post_load = spapr_xive_post_load; 706 } 707 708 static const TypeInfo spapr_xive_info = { 709 .name = TYPE_SPAPR_XIVE, 710 .parent = TYPE_XIVE_ROUTER, 711 .instance_init = spapr_xive_instance_init, 712 .instance_size = sizeof(SpaprXive), 713 .class_init = spapr_xive_class_init, 714 .interfaces = (InterfaceInfo[]) { 715 { TYPE_SPAPR_INTC }, 716 { } 717 }, 718 }; 719 720 static void spapr_xive_register_types(void) 721 { 722 type_register_static(&spapr_xive_info); 723 } 724 725 type_init(spapr_xive_register_types) 726 727 /* 728 * XIVE hcalls 729 * 730 * The terminology used by the XIVE hcalls is the following : 731 * 732 * TARGET vCPU number 733 * EQ Event Queue assigned by OS to receive event data 734 * ESB page for source interrupt management 735 * LISN Logical Interrupt Source Number identifying a source in the 736 * machine 737 * EISN Effective Interrupt Source Number used by guest OS to 738 * identify source in the guest 739 * 740 * The EAS, END, NVT structures are not exposed. 741 */ 742 743 /* 744 * Linux hosts under OPAL reserve priority 7 for their own escalation 745 * interrupts (DD2.X POWER9). So we only allow the guest to use 746 * priorities [0..6]. 747 */ 748 static bool spapr_xive_priority_is_reserved(uint8_t priority) 749 { 750 switch (priority) { 751 case 0 ... 6: 752 return false; 753 case 7: /* OPAL escalation queue */ 754 default: 755 return true; 756 } 757 } 758 759 /* 760 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 761 * real address of the MMIO page through which the Event State Buffer 762 * entry associated with the value of the "lisn" parameter is managed. 763 * 764 * Parameters: 765 * Input 766 * - R4: "flags" 767 * Bits 0-63 reserved 768 * - R5: "lisn" is per "interrupts", "interrupt-map", or 769 * "ibm,xive-lisn-ranges" properties, or as returned by the 770 * ibm,query-interrupt-source-number RTAS call, or as returned 771 * by the H_ALLOCATE_VAS_WINDOW hcall 772 * 773 * Output 774 * - R4: "flags" 775 * Bits 0-59: Reserved 776 * Bit 60: H_INT_ESB must be used for Event State Buffer 777 * management 778 * Bit 61: 1 == LSI 0 == MSI 779 * Bit 62: the full function page supports trigger 780 * Bit 63: Store EOI Supported 781 * - R5: Logical Real address of full function Event State Buffer 782 * management page, -1 if H_INT_ESB hcall flag is set to 1. 783 * - R6: Logical Real Address of trigger only Event State Buffer 784 * management page or -1. 785 * - R7: Power of 2 page size for the ESB management pages returned in 786 * R5 and R6. 787 */ 788 789 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 790 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 791 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 792 on same page */ 793 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 794 795 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 796 SpaprMachineState *spapr, 797 target_ulong opcode, 798 target_ulong *args) 799 { 800 SpaprXive *xive = spapr->xive; 801 XiveSource *xsrc = &xive->source; 802 target_ulong flags = args[0]; 803 target_ulong lisn = args[1]; 804 805 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 806 return H_FUNCTION; 807 } 808 809 if (flags) { 810 return H_PARAMETER; 811 } 812 813 if (lisn >= xive->nr_irqs) { 814 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 815 lisn); 816 return H_P2; 817 } 818 819 if (!xive_eas_is_valid(&xive->eat[lisn])) { 820 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 821 lisn); 822 return H_P2; 823 } 824 825 /* 826 * All sources are emulated under the main XIVE object and share 827 * the same characteristics. 828 */ 829 args[0] = 0; 830 if (!xive_source_esb_has_2page(xsrc)) { 831 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 832 } 833 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 834 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 835 } 836 837 /* 838 * Force the use of the H_INT_ESB hcall in case of an LSI 839 * interrupt. This is necessary under KVM to re-trigger the 840 * interrupt if the level is still asserted 841 */ 842 if (xive_source_irq_is_lsi(xsrc, lisn)) { 843 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 844 } 845 846 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 847 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 848 } else { 849 args[1] = -1; 850 } 851 852 if (xive_source_esb_has_2page(xsrc) && 853 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 854 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 855 } else { 856 args[2] = -1; 857 } 858 859 if (xive_source_esb_has_2page(xsrc)) { 860 args[3] = xsrc->esb_shift - 1; 861 } else { 862 args[3] = xsrc->esb_shift; 863 } 864 865 return H_SUCCESS; 866 } 867 868 /* 869 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 870 * Interrupt Source to a target. The Logical Interrupt Source is 871 * designated with the "lisn" parameter and the target is designated 872 * with the "target" and "priority" parameters. Upon return from the 873 * hcall(), no additional interrupts will be directed to the old EQ. 874 * 875 * Parameters: 876 * Input: 877 * - R4: "flags" 878 * Bits 0-61: Reserved 879 * Bit 62: set the "eisn" in the EAS 880 * Bit 63: masks the interrupt source in the hardware interrupt 881 * control structure. An interrupt masked by this mechanism will 882 * be dropped, but it's source state bits will still be 883 * set. There is no race-free way of unmasking and restoring the 884 * source. Thus this should only be used in interrupts that are 885 * also masked at the source, and only in cases where the 886 * interrupt is not meant to be used for a large amount of time 887 * because no valid target exists for it for example 888 * - R5: "lisn" is per "interrupts", "interrupt-map", or 889 * "ibm,xive-lisn-ranges" properties, or as returned by the 890 * ibm,query-interrupt-source-number RTAS call, or as returned by 891 * the H_ALLOCATE_VAS_WINDOW hcall 892 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 893 * "ibm,ppc-interrupt-gserver#s" 894 * - R7: "priority" is a valid priority not in 895 * "ibm,plat-res-int-priorities" 896 * - R8: "eisn" is the guest EISN associated with the "lisn" 897 * 898 * Output: 899 * - None 900 */ 901 902 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 903 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 904 905 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 906 SpaprMachineState *spapr, 907 target_ulong opcode, 908 target_ulong *args) 909 { 910 SpaprXive *xive = spapr->xive; 911 XiveEAS eas, new_eas; 912 target_ulong flags = args[0]; 913 target_ulong lisn = args[1]; 914 target_ulong target = args[2]; 915 target_ulong priority = args[3]; 916 target_ulong eisn = args[4]; 917 uint8_t end_blk; 918 uint32_t end_idx; 919 920 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 921 return H_FUNCTION; 922 } 923 924 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 925 return H_PARAMETER; 926 } 927 928 if (lisn >= xive->nr_irqs) { 929 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 930 lisn); 931 return H_P2; 932 } 933 934 eas = xive->eat[lisn]; 935 if (!xive_eas_is_valid(&eas)) { 936 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 937 lisn); 938 return H_P2; 939 } 940 941 /* priority 0xff is used to reset the EAS */ 942 if (priority == 0xff) { 943 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 944 goto out; 945 } 946 947 if (flags & SPAPR_XIVE_SRC_MASK) { 948 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 949 } else { 950 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 951 } 952 953 if (spapr_xive_priority_is_reserved(priority)) { 954 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 955 " is reserved\n", priority); 956 return H_P4; 957 } 958 959 /* 960 * Validate that "target" is part of the list of threads allocated 961 * to the partition. For that, find the END corresponding to the 962 * target. 963 */ 964 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 965 return H_P3; 966 } 967 968 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 969 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 970 971 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 972 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 973 } 974 975 if (kvm_irqchip_in_kernel()) { 976 Error *local_err = NULL; 977 978 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 979 if (local_err) { 980 error_report_err(local_err); 981 return H_HARDWARE; 982 } 983 } 984 985 out: 986 xive->eat[lisn] = new_eas; 987 return H_SUCCESS; 988 } 989 990 /* 991 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 992 * target/priority pair is assigned to the specified Logical Interrupt 993 * Source. 994 * 995 * Parameters: 996 * Input: 997 * - R4: "flags" 998 * Bits 0-63 Reserved 999 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1000 * "ibm,xive-lisn-ranges" properties, or as returned by the 1001 * ibm,query-interrupt-source-number RTAS call, or as 1002 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1003 * 1004 * Output: 1005 * - R4: Target to which the specified Logical Interrupt Source is 1006 * assigned 1007 * - R5: Priority to which the specified Logical Interrupt Source is 1008 * assigned 1009 * - R6: EISN for the specified Logical Interrupt Source (this will be 1010 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 1011 */ 1012 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 1013 SpaprMachineState *spapr, 1014 target_ulong opcode, 1015 target_ulong *args) 1016 { 1017 SpaprXive *xive = spapr->xive; 1018 target_ulong flags = args[0]; 1019 target_ulong lisn = args[1]; 1020 XiveEAS eas; 1021 XiveEND *end; 1022 uint8_t nvt_blk; 1023 uint32_t end_idx, nvt_idx; 1024 1025 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1026 return H_FUNCTION; 1027 } 1028 1029 if (flags) { 1030 return H_PARAMETER; 1031 } 1032 1033 if (lisn >= xive->nr_irqs) { 1034 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1035 lisn); 1036 return H_P2; 1037 } 1038 1039 eas = xive->eat[lisn]; 1040 if (!xive_eas_is_valid(&eas)) { 1041 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1042 lisn); 1043 return H_P2; 1044 } 1045 1046 /* EAS_END_BLOCK is unused on sPAPR */ 1047 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 1048 1049 assert(end_idx < xive->nr_ends); 1050 end = &xive->endt[end_idx]; 1051 1052 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1053 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1054 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 1055 1056 if (xive_eas_is_masked(&eas)) { 1057 args[1] = 0xff; 1058 } else { 1059 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1060 } 1061 1062 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 1063 1064 return H_SUCCESS; 1065 } 1066 1067 /* 1068 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 1069 * address of the notification management page associated with the 1070 * specified target and priority. 1071 * 1072 * Parameters: 1073 * Input: 1074 * - R4: "flags" 1075 * Bits 0-63 Reserved 1076 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1077 * "ibm,ppc-interrupt-gserver#s" 1078 * - R6: "priority" is a valid priority not in 1079 * "ibm,plat-res-int-priorities" 1080 * 1081 * Output: 1082 * - R4: Logical real address of notification page 1083 * - R5: Power of 2 page size of the notification page 1084 */ 1085 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 1086 SpaprMachineState *spapr, 1087 target_ulong opcode, 1088 target_ulong *args) 1089 { 1090 SpaprXive *xive = spapr->xive; 1091 XiveENDSource *end_xsrc = &xive->end_source; 1092 target_ulong flags = args[0]; 1093 target_ulong target = args[1]; 1094 target_ulong priority = args[2]; 1095 XiveEND *end; 1096 uint8_t end_blk; 1097 uint32_t end_idx; 1098 1099 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1100 return H_FUNCTION; 1101 } 1102 1103 if (flags) { 1104 return H_PARAMETER; 1105 } 1106 1107 /* 1108 * H_STATE should be returned if a H_INT_RESET is in progress. 1109 * This is not needed when running the emulation under QEMU 1110 */ 1111 1112 if (spapr_xive_priority_is_reserved(priority)) { 1113 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1114 " is reserved\n", priority); 1115 return H_P3; 1116 } 1117 1118 /* 1119 * Validate that "target" is part of the list of threads allocated 1120 * to the partition. For that, find the END corresponding to the 1121 * target. 1122 */ 1123 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1124 return H_P2; 1125 } 1126 1127 assert(end_idx < xive->nr_ends); 1128 end = &xive->endt[end_idx]; 1129 1130 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 1131 if (xive_end_is_enqueue(end)) { 1132 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1133 } else { 1134 args[1] = 0; 1135 } 1136 1137 return H_SUCCESS; 1138 } 1139 1140 /* 1141 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 1142 * a given "target" and "priority". It is also used to set the 1143 * notification config associated with the EQ. An EQ size of 0 is 1144 * used to reset the EQ config for a given target and priority. If 1145 * resetting the EQ config, the END associated with the given "target" 1146 * and "priority" will be changed to disable queueing. 1147 * 1148 * Upon return from the hcall(), no additional interrupts will be 1149 * directed to the old EQ (if one was set). The old EQ (if one was 1150 * set) should be investigated for interrupts that occurred prior to 1151 * or during the hcall(). 1152 * 1153 * Parameters: 1154 * Input: 1155 * - R4: "flags" 1156 * Bits 0-62: Reserved 1157 * Bit 63: Unconditional Notify (n) per the XIVE spec 1158 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1159 * "ibm,ppc-interrupt-gserver#s" 1160 * - R6: "priority" is a valid priority not in 1161 * "ibm,plat-res-int-priorities" 1162 * - R7: "eventQueue": The logical real address of the start of the EQ 1163 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1164 * 1165 * Output: 1166 * - None 1167 */ 1168 1169 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1170 1171 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1172 SpaprMachineState *spapr, 1173 target_ulong opcode, 1174 target_ulong *args) 1175 { 1176 SpaprXive *xive = spapr->xive; 1177 target_ulong flags = args[0]; 1178 target_ulong target = args[1]; 1179 target_ulong priority = args[2]; 1180 target_ulong qpage = args[3]; 1181 target_ulong qsize = args[4]; 1182 XiveEND end; 1183 uint8_t end_blk, nvt_blk; 1184 uint32_t end_idx, nvt_idx; 1185 1186 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1187 return H_FUNCTION; 1188 } 1189 1190 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1191 return H_PARAMETER; 1192 } 1193 1194 /* 1195 * H_STATE should be returned if a H_INT_RESET is in progress. 1196 * This is not needed when running the emulation under QEMU 1197 */ 1198 1199 if (spapr_xive_priority_is_reserved(priority)) { 1200 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1201 " is reserved\n", priority); 1202 return H_P3; 1203 } 1204 1205 /* 1206 * Validate that "target" is part of the list of threads allocated 1207 * to the partition. For that, find the END corresponding to the 1208 * target. 1209 */ 1210 1211 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1212 return H_P2; 1213 } 1214 1215 assert(end_idx < xive->nr_ends); 1216 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1217 1218 switch (qsize) { 1219 case 12: 1220 case 16: 1221 case 21: 1222 case 24: 1223 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1224 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1225 " is not naturally aligned with %" HWADDR_PRIx "\n", 1226 qpage, (hwaddr)1 << qsize); 1227 return H_P4; 1228 } 1229 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1230 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1231 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1232 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1233 break; 1234 case 0: 1235 /* reset queue and disable queueing */ 1236 spapr_xive_end_reset(&end); 1237 goto out; 1238 1239 default: 1240 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1241 qsize); 1242 return H_P5; 1243 } 1244 1245 if (qsize) { 1246 hwaddr plen = 1 << qsize; 1247 void *eq; 1248 1249 /* 1250 * Validate the guest EQ. We should also check that the queue 1251 * has been zeroed by the OS. 1252 */ 1253 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1254 MEMTXATTRS_UNSPECIFIED); 1255 if (plen != 1 << qsize) { 1256 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1257 HWADDR_PRIx "\n", qpage); 1258 return H_P4; 1259 } 1260 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1261 } 1262 1263 /* "target" should have been validated above */ 1264 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1265 g_assert_not_reached(); 1266 } 1267 1268 /* 1269 * Ensure the priority and target are correctly set (they will not 1270 * be right after allocation) 1271 */ 1272 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1273 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1274 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1275 1276 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1277 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1278 } else { 1279 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1280 } 1281 1282 /* 1283 * The generation bit for the END starts at 1 and The END page 1284 * offset counter starts at 0. 1285 */ 1286 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1287 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1288 end.w0 |= cpu_to_be32(END_W0_VALID); 1289 1290 /* 1291 * TODO: issue syncs required to ensure all in-flight interrupts 1292 * are complete on the old END 1293 */ 1294 1295 out: 1296 if (kvm_irqchip_in_kernel()) { 1297 Error *local_err = NULL; 1298 1299 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1300 if (local_err) { 1301 error_report_err(local_err); 1302 return H_HARDWARE; 1303 } 1304 } 1305 1306 /* Update END */ 1307 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1308 return H_SUCCESS; 1309 } 1310 1311 /* 1312 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1313 * target and priority. 1314 * 1315 * Parameters: 1316 * Input: 1317 * - R4: "flags" 1318 * Bits 0-62: Reserved 1319 * Bit 63: Debug: Return debug data 1320 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1321 * "ibm,ppc-interrupt-gserver#s" 1322 * - R6: "priority" is a valid priority not in 1323 * "ibm,plat-res-int-priorities" 1324 * 1325 * Output: 1326 * - R4: "flags": 1327 * Bits 0-61: Reserved 1328 * Bit 62: The value of Event Queue Generation Number (g) per 1329 * the XIVE spec if "Debug" = 1 1330 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1331 * - R5: The logical real address of the start of the EQ 1332 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1333 * - R7: The value of Event Queue Offset Counter per XIVE spec 1334 * if "Debug" = 1, else 0 1335 * 1336 */ 1337 1338 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1339 1340 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1341 SpaprMachineState *spapr, 1342 target_ulong opcode, 1343 target_ulong *args) 1344 { 1345 SpaprXive *xive = spapr->xive; 1346 target_ulong flags = args[0]; 1347 target_ulong target = args[1]; 1348 target_ulong priority = args[2]; 1349 XiveEND *end; 1350 uint8_t end_blk; 1351 uint32_t end_idx; 1352 1353 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1354 return H_FUNCTION; 1355 } 1356 1357 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1358 return H_PARAMETER; 1359 } 1360 1361 /* 1362 * H_STATE should be returned if a H_INT_RESET is in progress. 1363 * This is not needed when running the emulation under QEMU 1364 */ 1365 1366 if (spapr_xive_priority_is_reserved(priority)) { 1367 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1368 " is reserved\n", priority); 1369 return H_P3; 1370 } 1371 1372 /* 1373 * Validate that "target" is part of the list of threads allocated 1374 * to the partition. For that, find the END corresponding to the 1375 * target. 1376 */ 1377 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1378 return H_P2; 1379 } 1380 1381 assert(end_idx < xive->nr_ends); 1382 end = &xive->endt[end_idx]; 1383 1384 args[0] = 0; 1385 if (xive_end_is_notify(end)) { 1386 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1387 } 1388 1389 if (xive_end_is_enqueue(end)) { 1390 args[1] = xive_end_qaddr(end); 1391 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1392 } else { 1393 args[1] = 0; 1394 args[2] = 0; 1395 } 1396 1397 if (kvm_irqchip_in_kernel()) { 1398 Error *local_err = NULL; 1399 1400 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1401 if (local_err) { 1402 error_report_err(local_err); 1403 return H_HARDWARE; 1404 } 1405 } 1406 1407 /* TODO: do we need any locking on the END ? */ 1408 if (flags & SPAPR_XIVE_END_DEBUG) { 1409 /* Load the event queue generation number into the return flags */ 1410 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1411 1412 /* Load R7 with the event queue offset counter */ 1413 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1414 } else { 1415 args[3] = 0; 1416 } 1417 1418 return H_SUCCESS; 1419 } 1420 1421 /* 1422 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1423 * reporting cache line pair for the calling thread. The reporting 1424 * cache lines will contain the OS interrupt context when the OS 1425 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1426 * interrupt. The reporting cache lines can be reset by inputting -1 1427 * in "reportingLine". Issuing the CI store byte without reporting 1428 * cache lines registered will result in the data not being accessible 1429 * to the OS. 1430 * 1431 * Parameters: 1432 * Input: 1433 * - R4: "flags" 1434 * Bits 0-63: Reserved 1435 * - R5: "reportingLine": The logical real address of the reporting cache 1436 * line pair 1437 * 1438 * Output: 1439 * - None 1440 */ 1441 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1442 SpaprMachineState *spapr, 1443 target_ulong opcode, 1444 target_ulong *args) 1445 { 1446 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1447 return H_FUNCTION; 1448 } 1449 1450 /* 1451 * H_STATE should be returned if a H_INT_RESET is in progress. 1452 * This is not needed when running the emulation under QEMU 1453 */ 1454 1455 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1456 return H_FUNCTION; 1457 } 1458 1459 /* 1460 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1461 * real address of the reporting cache line pair set for the input 1462 * "target". If no reporting cache line pair has been set, -1 is 1463 * returned. 1464 * 1465 * Parameters: 1466 * Input: 1467 * - R4: "flags" 1468 * Bits 0-63: Reserved 1469 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1470 * "ibm,ppc-interrupt-gserver#s" 1471 * - R6: "reportingLine": The logical real address of the reporting 1472 * cache line pair 1473 * 1474 * Output: 1475 * - R4: The logical real address of the reporting line if set, else -1 1476 */ 1477 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1478 SpaprMachineState *spapr, 1479 target_ulong opcode, 1480 target_ulong *args) 1481 { 1482 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1483 return H_FUNCTION; 1484 } 1485 1486 /* 1487 * H_STATE should be returned if a H_INT_RESET is in progress. 1488 * This is not needed when running the emulation under QEMU 1489 */ 1490 1491 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1492 return H_FUNCTION; 1493 } 1494 1495 /* 1496 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1497 * page for the input "lisn". This hcall is only supported for LISNs 1498 * that have the ESB hcall flag set to 1 when returned from hcall() 1499 * H_INT_GET_SOURCE_INFO. 1500 * 1501 * Parameters: 1502 * Input: 1503 * - R4: "flags" 1504 * Bits 0-62: Reserved 1505 * bit 63: Store: Store=1, store operation, else load operation 1506 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1507 * "ibm,xive-lisn-ranges" properties, or as returned by the 1508 * ibm,query-interrupt-source-number RTAS call, or as 1509 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1510 * - R6: "esbOffset" is the offset into the ESB page for the load or 1511 * store operation 1512 * - R7: "storeData" is the data to write for a store operation 1513 * 1514 * Output: 1515 * - R4: The value of the load if load operation, else -1 1516 */ 1517 1518 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1519 1520 static target_ulong h_int_esb(PowerPCCPU *cpu, 1521 SpaprMachineState *spapr, 1522 target_ulong opcode, 1523 target_ulong *args) 1524 { 1525 SpaprXive *xive = spapr->xive; 1526 XiveEAS eas; 1527 target_ulong flags = args[0]; 1528 target_ulong lisn = args[1]; 1529 target_ulong offset = args[2]; 1530 target_ulong data = args[3]; 1531 hwaddr mmio_addr; 1532 XiveSource *xsrc = &xive->source; 1533 1534 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1535 return H_FUNCTION; 1536 } 1537 1538 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1539 return H_PARAMETER; 1540 } 1541 1542 if (lisn >= xive->nr_irqs) { 1543 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1544 lisn); 1545 return H_P2; 1546 } 1547 1548 eas = xive->eat[lisn]; 1549 if (!xive_eas_is_valid(&eas)) { 1550 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1551 lisn); 1552 return H_P2; 1553 } 1554 1555 if (offset > (1ull << xsrc->esb_shift)) { 1556 return H_P3; 1557 } 1558 1559 if (kvm_irqchip_in_kernel()) { 1560 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1561 flags & SPAPR_XIVE_ESB_STORE); 1562 } else { 1563 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1564 1565 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1566 (flags & SPAPR_XIVE_ESB_STORE))) { 1567 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1568 HWADDR_PRIx "\n", mmio_addr); 1569 return H_HARDWARE; 1570 } 1571 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1572 } 1573 return H_SUCCESS; 1574 } 1575 1576 /* 1577 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1578 * ensure any in flight events for the input lisn are in the event 1579 * queue. 1580 * 1581 * Parameters: 1582 * Input: 1583 * - R4: "flags" 1584 * Bits 0-63: Reserved 1585 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1586 * "ibm,xive-lisn-ranges" properties, or as returned by the 1587 * ibm,query-interrupt-source-number RTAS call, or as 1588 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1589 * 1590 * Output: 1591 * - None 1592 */ 1593 static target_ulong h_int_sync(PowerPCCPU *cpu, 1594 SpaprMachineState *spapr, 1595 target_ulong opcode, 1596 target_ulong *args) 1597 { 1598 SpaprXive *xive = spapr->xive; 1599 XiveEAS eas; 1600 target_ulong flags = args[0]; 1601 target_ulong lisn = args[1]; 1602 1603 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1604 return H_FUNCTION; 1605 } 1606 1607 if (flags) { 1608 return H_PARAMETER; 1609 } 1610 1611 if (lisn >= xive->nr_irqs) { 1612 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1613 lisn); 1614 return H_P2; 1615 } 1616 1617 eas = xive->eat[lisn]; 1618 if (!xive_eas_is_valid(&eas)) { 1619 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1620 lisn); 1621 return H_P2; 1622 } 1623 1624 /* 1625 * H_STATE should be returned if a H_INT_RESET is in progress. 1626 * This is not needed when running the emulation under QEMU 1627 */ 1628 1629 /* 1630 * This is not real hardware. Nothing to be done unless when 1631 * under KVM 1632 */ 1633 1634 if (kvm_irqchip_in_kernel()) { 1635 Error *local_err = NULL; 1636 1637 kvmppc_xive_sync_source(xive, lisn, &local_err); 1638 if (local_err) { 1639 error_report_err(local_err); 1640 return H_HARDWARE; 1641 } 1642 } 1643 return H_SUCCESS; 1644 } 1645 1646 /* 1647 * The H_INT_RESET hcall() is used to reset all of the partition's 1648 * interrupt exploitation structures to their initial state. This 1649 * means losing all previously set interrupt state set via 1650 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1651 * 1652 * Parameters: 1653 * Input: 1654 * - R4: "flags" 1655 * Bits 0-63: Reserved 1656 * 1657 * Output: 1658 * - None 1659 */ 1660 static target_ulong h_int_reset(PowerPCCPU *cpu, 1661 SpaprMachineState *spapr, 1662 target_ulong opcode, 1663 target_ulong *args) 1664 { 1665 SpaprXive *xive = spapr->xive; 1666 target_ulong flags = args[0]; 1667 1668 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1669 return H_FUNCTION; 1670 } 1671 1672 if (flags) { 1673 return H_PARAMETER; 1674 } 1675 1676 device_reset(DEVICE(xive)); 1677 1678 if (kvm_irqchip_in_kernel()) { 1679 Error *local_err = NULL; 1680 1681 kvmppc_xive_reset(xive, &local_err); 1682 if (local_err) { 1683 error_report_err(local_err); 1684 return H_HARDWARE; 1685 } 1686 } 1687 return H_SUCCESS; 1688 } 1689 1690 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1691 { 1692 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1693 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1694 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1695 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1696 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1697 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1698 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1699 h_int_set_os_reporting_line); 1700 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1701 h_int_get_os_reporting_line); 1702 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1703 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1704 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1705 } 1706