1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 monitor_printf(mon, "]"); 150 } 151 152 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 153 { 154 XiveSource *xsrc = &xive->source; 155 int i; 156 157 if (kvm_irqchip_in_kernel()) { 158 Error *local_err = NULL; 159 160 kvmppc_xive_synchronize_state(xive, &local_err); 161 if (local_err) { 162 error_report_err(local_err); 163 return; 164 } 165 } 166 167 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 168 169 for (i = 0; i < xive->nr_irqs; i++) { 170 uint8_t pq = xive_source_esb_get(xsrc, i); 171 XiveEAS *eas = &xive->eat[i]; 172 173 if (!xive_eas_is_valid(eas)) { 174 continue; 175 } 176 177 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 178 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 179 pq & XIVE_ESB_VAL_P ? 'P' : '-', 180 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 181 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 182 xive_eas_is_masked(eas) ? "M" : " ", 183 (int) xive_get_field64(EAS_END_DATA, eas->w)); 184 185 if (!xive_eas_is_masked(eas)) { 186 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 187 XiveEND *end; 188 189 assert(end_idx < xive->nr_ends); 190 end = &xive->endt[end_idx]; 191 192 if (xive_end_is_valid(end)) { 193 spapr_xive_end_pic_print_info(xive, end, mon); 194 } 195 } 196 monitor_printf(mon, "\n"); 197 } 198 } 199 200 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 201 { 202 memory_region_set_enabled(&xive->source.esb_mmio, enable); 203 memory_region_set_enabled(&xive->tm_mmio, enable); 204 205 /* Disable the END ESBs until a guest OS makes use of them */ 206 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 207 } 208 209 /* 210 * When a Virtual Processor is scheduled to run on a HW thread, the 211 * hypervisor pushes its identifier in the OS CAM line. Emulate the 212 * same behavior under QEMU. 213 */ 214 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 215 { 216 uint8_t nvt_blk; 217 uint32_t nvt_idx; 218 uint32_t nvt_cam; 219 220 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 221 222 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 223 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 224 } 225 226 static void spapr_xive_end_reset(XiveEND *end) 227 { 228 memset(end, 0, sizeof(*end)); 229 230 /* switch off the escalation and notification ESBs */ 231 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 232 } 233 234 static void spapr_xive_reset(void *dev) 235 { 236 SpaprXive *xive = SPAPR_XIVE(dev); 237 int i; 238 239 /* 240 * The XiveSource has its own reset handler, which mask off all 241 * IRQs (!P|Q) 242 */ 243 244 /* Mask all valid EASs in the IRQ number space. */ 245 for (i = 0; i < xive->nr_irqs; i++) { 246 XiveEAS *eas = &xive->eat[i]; 247 if (xive_eas_is_valid(eas)) { 248 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 249 } else { 250 eas->w = 0; 251 } 252 } 253 254 /* Clear all ENDs */ 255 for (i = 0; i < xive->nr_ends; i++) { 256 spapr_xive_end_reset(&xive->endt[i]); 257 } 258 } 259 260 static void spapr_xive_instance_init(Object *obj) 261 { 262 SpaprXive *xive = SPAPR_XIVE(obj); 263 264 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 265 TYPE_XIVE_SOURCE, &error_abort, NULL); 266 267 object_initialize_child(obj, "end_source", &xive->end_source, 268 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 269 &error_abort, NULL); 270 271 /* Not connected to the KVM XIVE device */ 272 xive->fd = -1; 273 } 274 275 static void spapr_xive_realize(DeviceState *dev, Error **errp) 276 { 277 SpaprXive *xive = SPAPR_XIVE(dev); 278 XiveSource *xsrc = &xive->source; 279 XiveENDSource *end_xsrc = &xive->end_source; 280 Error *local_err = NULL; 281 282 if (!xive->nr_irqs) { 283 error_setg(errp, "Number of interrupt needs to be greater 0"); 284 return; 285 } 286 287 if (!xive->nr_ends) { 288 error_setg(errp, "Number of interrupt needs to be greater 0"); 289 return; 290 } 291 292 /* 293 * Initialize the internal sources, for IPIs and virtual devices. 294 */ 295 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 296 &error_fatal); 297 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 298 &error_fatal); 299 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 300 if (local_err) { 301 error_propagate(errp, local_err); 302 return; 303 } 304 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 305 306 /* 307 * Initialize the END ESB source 308 */ 309 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 310 &error_fatal); 311 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 312 &error_fatal); 313 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 314 if (local_err) { 315 error_propagate(errp, local_err); 316 return; 317 } 318 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 319 320 /* Set the mapping address of the END ESB pages after the source ESBs */ 321 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 322 323 /* 324 * Allocate the routing tables 325 */ 326 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 327 xive->endt = g_new0(XiveEND, xive->nr_ends); 328 329 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 330 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 331 332 qemu_register_reset(spapr_xive_reset, dev); 333 334 /* TIMA initialization */ 335 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 336 "xive.tima", 4ull << TM_SHIFT); 337 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 338 339 /* 340 * Map all regions. These will be enabled or disabled at reset and 341 * can also be overridden by KVM memory regions if active 342 */ 343 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 344 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 345 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 346 } 347 348 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 349 uint32_t eas_idx, XiveEAS *eas) 350 { 351 SpaprXive *xive = SPAPR_XIVE(xrtr); 352 353 if (eas_idx >= xive->nr_irqs) { 354 return -1; 355 } 356 357 *eas = xive->eat[eas_idx]; 358 return 0; 359 } 360 361 static int spapr_xive_get_end(XiveRouter *xrtr, 362 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 363 { 364 SpaprXive *xive = SPAPR_XIVE(xrtr); 365 366 if (end_idx >= xive->nr_ends) { 367 return -1; 368 } 369 370 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 371 return 0; 372 } 373 374 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 375 uint32_t end_idx, XiveEND *end, 376 uint8_t word_number) 377 { 378 SpaprXive *xive = SPAPR_XIVE(xrtr); 379 380 if (end_idx >= xive->nr_ends) { 381 return -1; 382 } 383 384 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 385 return 0; 386 } 387 388 static int spapr_xive_get_nvt(XiveRouter *xrtr, 389 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 390 { 391 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 392 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 393 394 if (!cpu) { 395 /* TODO: should we assert() if we can find a NVT ? */ 396 return -1; 397 } 398 399 /* 400 * sPAPR does not maintain a NVT table. Return that the NVT is 401 * valid if we have found a matching CPU 402 */ 403 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 404 return 0; 405 } 406 407 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 408 uint32_t nvt_idx, XiveNVT *nvt, 409 uint8_t word_number) 410 { 411 /* 412 * We don't need to write back to the NVTs because the sPAPR 413 * machine should never hit a non-scheduled NVT. It should never 414 * get called. 415 */ 416 g_assert_not_reached(); 417 } 418 419 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 420 { 421 PowerPCCPU *cpu = POWERPC_CPU(cs); 422 423 return spapr_cpu_state(cpu)->tctx; 424 } 425 426 static const VMStateDescription vmstate_spapr_xive_end = { 427 .name = TYPE_SPAPR_XIVE "/end", 428 .version_id = 1, 429 .minimum_version_id = 1, 430 .fields = (VMStateField []) { 431 VMSTATE_UINT32(w0, XiveEND), 432 VMSTATE_UINT32(w1, XiveEND), 433 VMSTATE_UINT32(w2, XiveEND), 434 VMSTATE_UINT32(w3, XiveEND), 435 VMSTATE_UINT32(w4, XiveEND), 436 VMSTATE_UINT32(w5, XiveEND), 437 VMSTATE_UINT32(w6, XiveEND), 438 VMSTATE_UINT32(w7, XiveEND), 439 VMSTATE_END_OF_LIST() 440 }, 441 }; 442 443 static const VMStateDescription vmstate_spapr_xive_eas = { 444 .name = TYPE_SPAPR_XIVE "/eas", 445 .version_id = 1, 446 .minimum_version_id = 1, 447 .fields = (VMStateField []) { 448 VMSTATE_UINT64(w, XiveEAS), 449 VMSTATE_END_OF_LIST() 450 }, 451 }; 452 453 static int vmstate_spapr_xive_pre_save(void *opaque) 454 { 455 if (kvm_irqchip_in_kernel()) { 456 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 457 } 458 459 return 0; 460 } 461 462 /* 463 * Called by the sPAPR IRQ backend 'post_load' method at the machine 464 * level. 465 */ 466 int spapr_xive_post_load(SpaprXive *xive, int version_id) 467 { 468 if (kvm_irqchip_in_kernel()) { 469 return kvmppc_xive_post_load(xive, version_id); 470 } 471 472 return 0; 473 } 474 475 static const VMStateDescription vmstate_spapr_xive = { 476 .name = TYPE_SPAPR_XIVE, 477 .version_id = 1, 478 .minimum_version_id = 1, 479 .pre_save = vmstate_spapr_xive_pre_save, 480 .post_load = NULL, /* handled at the machine level */ 481 .fields = (VMStateField[]) { 482 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 483 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 484 vmstate_spapr_xive_eas, XiveEAS), 485 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 486 vmstate_spapr_xive_end, XiveEND), 487 VMSTATE_END_OF_LIST() 488 }, 489 }; 490 491 static Property spapr_xive_properties[] = { 492 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 493 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 494 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 495 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 496 DEFINE_PROP_END_OF_LIST(), 497 }; 498 499 static void spapr_xive_class_init(ObjectClass *klass, void *data) 500 { 501 DeviceClass *dc = DEVICE_CLASS(klass); 502 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 503 504 dc->desc = "sPAPR XIVE Interrupt Controller"; 505 dc->props = spapr_xive_properties; 506 dc->realize = spapr_xive_realize; 507 dc->vmsd = &vmstate_spapr_xive; 508 509 xrc->get_eas = spapr_xive_get_eas; 510 xrc->get_end = spapr_xive_get_end; 511 xrc->write_end = spapr_xive_write_end; 512 xrc->get_nvt = spapr_xive_get_nvt; 513 xrc->write_nvt = spapr_xive_write_nvt; 514 xrc->get_tctx = spapr_xive_get_tctx; 515 } 516 517 static const TypeInfo spapr_xive_info = { 518 .name = TYPE_SPAPR_XIVE, 519 .parent = TYPE_XIVE_ROUTER, 520 .instance_init = spapr_xive_instance_init, 521 .instance_size = sizeof(SpaprXive), 522 .class_init = spapr_xive_class_init, 523 }; 524 525 static void spapr_xive_register_types(void) 526 { 527 type_register_static(&spapr_xive_info); 528 } 529 530 type_init(spapr_xive_register_types) 531 532 bool spapr_xive_irq_claim(SpaprXive *xive, uint32_t lisn, bool lsi) 533 { 534 XiveSource *xsrc = &xive->source; 535 536 if (lisn >= xive->nr_irqs) { 537 return false; 538 } 539 540 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID); 541 if (lsi) { 542 xive_source_irq_set_lsi(xsrc, lisn); 543 } 544 545 if (kvm_irqchip_in_kernel()) { 546 Error *local_err = NULL; 547 548 kvmppc_xive_source_reset_one(xsrc, lisn, &local_err); 549 if (local_err) { 550 error_report_err(local_err); 551 return false; 552 } 553 } 554 555 return true; 556 } 557 558 bool spapr_xive_irq_free(SpaprXive *xive, uint32_t lisn) 559 { 560 if (lisn >= xive->nr_irqs) { 561 return false; 562 } 563 564 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 565 return true; 566 } 567 568 /* 569 * XIVE hcalls 570 * 571 * The terminology used by the XIVE hcalls is the following : 572 * 573 * TARGET vCPU number 574 * EQ Event Queue assigned by OS to receive event data 575 * ESB page for source interrupt management 576 * LISN Logical Interrupt Source Number identifying a source in the 577 * machine 578 * EISN Effective Interrupt Source Number used by guest OS to 579 * identify source in the guest 580 * 581 * The EAS, END, NVT structures are not exposed. 582 */ 583 584 /* 585 * Linux hosts under OPAL reserve priority 7 for their own escalation 586 * interrupts (DD2.X POWER9). So we only allow the guest to use 587 * priorities [0..6]. 588 */ 589 static bool spapr_xive_priority_is_reserved(uint8_t priority) 590 { 591 switch (priority) { 592 case 0 ... 6: 593 return false; 594 case 7: /* OPAL escalation queue */ 595 default: 596 return true; 597 } 598 } 599 600 /* 601 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 602 * real address of the MMIO page through which the Event State Buffer 603 * entry associated with the value of the "lisn" parameter is managed. 604 * 605 * Parameters: 606 * Input 607 * - R4: "flags" 608 * Bits 0-63 reserved 609 * - R5: "lisn" is per "interrupts", "interrupt-map", or 610 * "ibm,xive-lisn-ranges" properties, or as returned by the 611 * ibm,query-interrupt-source-number RTAS call, or as returned 612 * by the H_ALLOCATE_VAS_WINDOW hcall 613 * 614 * Output 615 * - R4: "flags" 616 * Bits 0-59: Reserved 617 * Bit 60: H_INT_ESB must be used for Event State Buffer 618 * management 619 * Bit 61: 1 == LSI 0 == MSI 620 * Bit 62: the full function page supports trigger 621 * Bit 63: Store EOI Supported 622 * - R5: Logical Real address of full function Event State Buffer 623 * management page, -1 if H_INT_ESB hcall flag is set to 1. 624 * - R6: Logical Real Address of trigger only Event State Buffer 625 * management page or -1. 626 * - R7: Power of 2 page size for the ESB management pages returned in 627 * R5 and R6. 628 */ 629 630 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 631 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 632 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 633 on same page */ 634 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 635 636 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 637 SpaprMachineState *spapr, 638 target_ulong opcode, 639 target_ulong *args) 640 { 641 SpaprXive *xive = spapr->xive; 642 XiveSource *xsrc = &xive->source; 643 target_ulong flags = args[0]; 644 target_ulong lisn = args[1]; 645 646 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 647 return H_FUNCTION; 648 } 649 650 if (flags) { 651 return H_PARAMETER; 652 } 653 654 if (lisn >= xive->nr_irqs) { 655 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 656 lisn); 657 return H_P2; 658 } 659 660 if (!xive_eas_is_valid(&xive->eat[lisn])) { 661 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 662 lisn); 663 return H_P2; 664 } 665 666 /* 667 * All sources are emulated under the main XIVE object and share 668 * the same characteristics. 669 */ 670 args[0] = 0; 671 if (!xive_source_esb_has_2page(xsrc)) { 672 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 673 } 674 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 675 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 676 } 677 678 /* 679 * Force the use of the H_INT_ESB hcall in case of an LSI 680 * interrupt. This is necessary under KVM to re-trigger the 681 * interrupt if the level is still asserted 682 */ 683 if (xive_source_irq_is_lsi(xsrc, lisn)) { 684 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 685 } 686 687 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 688 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 689 } else { 690 args[1] = -1; 691 } 692 693 if (xive_source_esb_has_2page(xsrc) && 694 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 695 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 696 } else { 697 args[2] = -1; 698 } 699 700 if (xive_source_esb_has_2page(xsrc)) { 701 args[3] = xsrc->esb_shift - 1; 702 } else { 703 args[3] = xsrc->esb_shift; 704 } 705 706 return H_SUCCESS; 707 } 708 709 /* 710 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 711 * Interrupt Source to a target. The Logical Interrupt Source is 712 * designated with the "lisn" parameter and the target is designated 713 * with the "target" and "priority" parameters. Upon return from the 714 * hcall(), no additional interrupts will be directed to the old EQ. 715 * 716 * Parameters: 717 * Input: 718 * - R4: "flags" 719 * Bits 0-61: Reserved 720 * Bit 62: set the "eisn" in the EAS 721 * Bit 63: masks the interrupt source in the hardware interrupt 722 * control structure. An interrupt masked by this mechanism will 723 * be dropped, but it's source state bits will still be 724 * set. There is no race-free way of unmasking and restoring the 725 * source. Thus this should only be used in interrupts that are 726 * also masked at the source, and only in cases where the 727 * interrupt is not meant to be used for a large amount of time 728 * because no valid target exists for it for example 729 * - R5: "lisn" is per "interrupts", "interrupt-map", or 730 * "ibm,xive-lisn-ranges" properties, or as returned by the 731 * ibm,query-interrupt-source-number RTAS call, or as returned by 732 * the H_ALLOCATE_VAS_WINDOW hcall 733 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 734 * "ibm,ppc-interrupt-gserver#s" 735 * - R7: "priority" is a valid priority not in 736 * "ibm,plat-res-int-priorities" 737 * - R8: "eisn" is the guest EISN associated with the "lisn" 738 * 739 * Output: 740 * - None 741 */ 742 743 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 744 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 745 746 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 747 SpaprMachineState *spapr, 748 target_ulong opcode, 749 target_ulong *args) 750 { 751 SpaprXive *xive = spapr->xive; 752 XiveEAS eas, new_eas; 753 target_ulong flags = args[0]; 754 target_ulong lisn = args[1]; 755 target_ulong target = args[2]; 756 target_ulong priority = args[3]; 757 target_ulong eisn = args[4]; 758 uint8_t end_blk; 759 uint32_t end_idx; 760 761 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 762 return H_FUNCTION; 763 } 764 765 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 766 return H_PARAMETER; 767 } 768 769 if (lisn >= xive->nr_irqs) { 770 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 771 lisn); 772 return H_P2; 773 } 774 775 eas = xive->eat[lisn]; 776 if (!xive_eas_is_valid(&eas)) { 777 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 778 lisn); 779 return H_P2; 780 } 781 782 /* priority 0xff is used to reset the EAS */ 783 if (priority == 0xff) { 784 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 785 goto out; 786 } 787 788 if (flags & SPAPR_XIVE_SRC_MASK) { 789 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 790 } else { 791 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 792 } 793 794 if (spapr_xive_priority_is_reserved(priority)) { 795 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 796 " is reserved\n", priority); 797 return H_P4; 798 } 799 800 /* 801 * Validate that "target" is part of the list of threads allocated 802 * to the partition. For that, find the END corresponding to the 803 * target. 804 */ 805 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 806 return H_P3; 807 } 808 809 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 810 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 811 812 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 813 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 814 } 815 816 if (kvm_irqchip_in_kernel()) { 817 Error *local_err = NULL; 818 819 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 820 if (local_err) { 821 error_report_err(local_err); 822 return H_HARDWARE; 823 } 824 } 825 826 out: 827 xive->eat[lisn] = new_eas; 828 return H_SUCCESS; 829 } 830 831 /* 832 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 833 * target/priority pair is assigned to the specified Logical Interrupt 834 * Source. 835 * 836 * Parameters: 837 * Input: 838 * - R4: "flags" 839 * Bits 0-63 Reserved 840 * - R5: "lisn" is per "interrupts", "interrupt-map", or 841 * "ibm,xive-lisn-ranges" properties, or as returned by the 842 * ibm,query-interrupt-source-number RTAS call, or as 843 * returned by the H_ALLOCATE_VAS_WINDOW hcall 844 * 845 * Output: 846 * - R4: Target to which the specified Logical Interrupt Source is 847 * assigned 848 * - R5: Priority to which the specified Logical Interrupt Source is 849 * assigned 850 * - R6: EISN for the specified Logical Interrupt Source (this will be 851 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 852 */ 853 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 854 SpaprMachineState *spapr, 855 target_ulong opcode, 856 target_ulong *args) 857 { 858 SpaprXive *xive = spapr->xive; 859 target_ulong flags = args[0]; 860 target_ulong lisn = args[1]; 861 XiveEAS eas; 862 XiveEND *end; 863 uint8_t nvt_blk; 864 uint32_t end_idx, nvt_idx; 865 866 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 867 return H_FUNCTION; 868 } 869 870 if (flags) { 871 return H_PARAMETER; 872 } 873 874 if (lisn >= xive->nr_irqs) { 875 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 876 lisn); 877 return H_P2; 878 } 879 880 eas = xive->eat[lisn]; 881 if (!xive_eas_is_valid(&eas)) { 882 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 883 lisn); 884 return H_P2; 885 } 886 887 /* EAS_END_BLOCK is unused on sPAPR */ 888 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 889 890 assert(end_idx < xive->nr_ends); 891 end = &xive->endt[end_idx]; 892 893 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 894 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 895 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 896 897 if (xive_eas_is_masked(&eas)) { 898 args[1] = 0xff; 899 } else { 900 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 901 } 902 903 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 904 905 return H_SUCCESS; 906 } 907 908 /* 909 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 910 * address of the notification management page associated with the 911 * specified target and priority. 912 * 913 * Parameters: 914 * Input: 915 * - R4: "flags" 916 * Bits 0-63 Reserved 917 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 918 * "ibm,ppc-interrupt-gserver#s" 919 * - R6: "priority" is a valid priority not in 920 * "ibm,plat-res-int-priorities" 921 * 922 * Output: 923 * - R4: Logical real address of notification page 924 * - R5: Power of 2 page size of the notification page 925 */ 926 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 927 SpaprMachineState *spapr, 928 target_ulong opcode, 929 target_ulong *args) 930 { 931 SpaprXive *xive = spapr->xive; 932 XiveENDSource *end_xsrc = &xive->end_source; 933 target_ulong flags = args[0]; 934 target_ulong target = args[1]; 935 target_ulong priority = args[2]; 936 XiveEND *end; 937 uint8_t end_blk; 938 uint32_t end_idx; 939 940 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 941 return H_FUNCTION; 942 } 943 944 if (flags) { 945 return H_PARAMETER; 946 } 947 948 /* 949 * H_STATE should be returned if a H_INT_RESET is in progress. 950 * This is not needed when running the emulation under QEMU 951 */ 952 953 if (spapr_xive_priority_is_reserved(priority)) { 954 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 955 " is reserved\n", priority); 956 return H_P3; 957 } 958 959 /* 960 * Validate that "target" is part of the list of threads allocated 961 * to the partition. For that, find the END corresponding to the 962 * target. 963 */ 964 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 965 return H_P2; 966 } 967 968 assert(end_idx < xive->nr_ends); 969 end = &xive->endt[end_idx]; 970 971 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 972 if (xive_end_is_enqueue(end)) { 973 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 974 } else { 975 args[1] = 0; 976 } 977 978 return H_SUCCESS; 979 } 980 981 /* 982 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 983 * a given "target" and "priority". It is also used to set the 984 * notification config associated with the EQ. An EQ size of 0 is 985 * used to reset the EQ config for a given target and priority. If 986 * resetting the EQ config, the END associated with the given "target" 987 * and "priority" will be changed to disable queueing. 988 * 989 * Upon return from the hcall(), no additional interrupts will be 990 * directed to the old EQ (if one was set). The old EQ (if one was 991 * set) should be investigated for interrupts that occurred prior to 992 * or during the hcall(). 993 * 994 * Parameters: 995 * Input: 996 * - R4: "flags" 997 * Bits 0-62: Reserved 998 * Bit 63: Unconditional Notify (n) per the XIVE spec 999 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1000 * "ibm,ppc-interrupt-gserver#s" 1001 * - R6: "priority" is a valid priority not in 1002 * "ibm,plat-res-int-priorities" 1003 * - R7: "eventQueue": The logical real address of the start of the EQ 1004 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1005 * 1006 * Output: 1007 * - None 1008 */ 1009 1010 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1011 1012 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1013 SpaprMachineState *spapr, 1014 target_ulong opcode, 1015 target_ulong *args) 1016 { 1017 SpaprXive *xive = spapr->xive; 1018 target_ulong flags = args[0]; 1019 target_ulong target = args[1]; 1020 target_ulong priority = args[2]; 1021 target_ulong qpage = args[3]; 1022 target_ulong qsize = args[4]; 1023 XiveEND end; 1024 uint8_t end_blk, nvt_blk; 1025 uint32_t end_idx, nvt_idx; 1026 1027 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1028 return H_FUNCTION; 1029 } 1030 1031 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1032 return H_PARAMETER; 1033 } 1034 1035 /* 1036 * H_STATE should be returned if a H_INT_RESET is in progress. 1037 * This is not needed when running the emulation under QEMU 1038 */ 1039 1040 if (spapr_xive_priority_is_reserved(priority)) { 1041 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1042 " is reserved\n", priority); 1043 return H_P3; 1044 } 1045 1046 /* 1047 * Validate that "target" is part of the list of threads allocated 1048 * to the partition. For that, find the END corresponding to the 1049 * target. 1050 */ 1051 1052 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1053 return H_P2; 1054 } 1055 1056 assert(end_idx < xive->nr_ends); 1057 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1058 1059 switch (qsize) { 1060 case 12: 1061 case 16: 1062 case 21: 1063 case 24: 1064 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1065 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1066 " is not naturally aligned with %" HWADDR_PRIx "\n", 1067 qpage, (hwaddr)1 << qsize); 1068 return H_P4; 1069 } 1070 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1071 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1072 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1073 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1074 break; 1075 case 0: 1076 /* reset queue and disable queueing */ 1077 spapr_xive_end_reset(&end); 1078 goto out; 1079 1080 default: 1081 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1082 qsize); 1083 return H_P5; 1084 } 1085 1086 if (qsize) { 1087 hwaddr plen = 1 << qsize; 1088 void *eq; 1089 1090 /* 1091 * Validate the guest EQ. We should also check that the queue 1092 * has been zeroed by the OS. 1093 */ 1094 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1095 MEMTXATTRS_UNSPECIFIED); 1096 if (plen != 1 << qsize) { 1097 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1098 HWADDR_PRIx "\n", qpage); 1099 return H_P4; 1100 } 1101 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1102 } 1103 1104 /* "target" should have been validated above */ 1105 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1106 g_assert_not_reached(); 1107 } 1108 1109 /* 1110 * Ensure the priority and target are correctly set (they will not 1111 * be right after allocation) 1112 */ 1113 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1114 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1115 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1116 1117 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1118 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1119 } else { 1120 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1121 } 1122 1123 /* 1124 * The generation bit for the END starts at 1 and The END page 1125 * offset counter starts at 0. 1126 */ 1127 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1128 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1129 end.w0 |= cpu_to_be32(END_W0_VALID); 1130 1131 /* 1132 * TODO: issue syncs required to ensure all in-flight interrupts 1133 * are complete on the old END 1134 */ 1135 1136 out: 1137 if (kvm_irqchip_in_kernel()) { 1138 Error *local_err = NULL; 1139 1140 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1141 if (local_err) { 1142 error_report_err(local_err); 1143 return H_HARDWARE; 1144 } 1145 } 1146 1147 /* Update END */ 1148 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1149 return H_SUCCESS; 1150 } 1151 1152 /* 1153 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1154 * target and priority. 1155 * 1156 * Parameters: 1157 * Input: 1158 * - R4: "flags" 1159 * Bits 0-62: Reserved 1160 * Bit 63: Debug: Return debug data 1161 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1162 * "ibm,ppc-interrupt-gserver#s" 1163 * - R6: "priority" is a valid priority not in 1164 * "ibm,plat-res-int-priorities" 1165 * 1166 * Output: 1167 * - R4: "flags": 1168 * Bits 0-61: Reserved 1169 * Bit 62: The value of Event Queue Generation Number (g) per 1170 * the XIVE spec if "Debug" = 1 1171 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1172 * - R5: The logical real address of the start of the EQ 1173 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1174 * - R7: The value of Event Queue Offset Counter per XIVE spec 1175 * if "Debug" = 1, else 0 1176 * 1177 */ 1178 1179 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1180 1181 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1182 SpaprMachineState *spapr, 1183 target_ulong opcode, 1184 target_ulong *args) 1185 { 1186 SpaprXive *xive = spapr->xive; 1187 target_ulong flags = args[0]; 1188 target_ulong target = args[1]; 1189 target_ulong priority = args[2]; 1190 XiveEND *end; 1191 uint8_t end_blk; 1192 uint32_t end_idx; 1193 1194 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1195 return H_FUNCTION; 1196 } 1197 1198 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1199 return H_PARAMETER; 1200 } 1201 1202 /* 1203 * H_STATE should be returned if a H_INT_RESET is in progress. 1204 * This is not needed when running the emulation under QEMU 1205 */ 1206 1207 if (spapr_xive_priority_is_reserved(priority)) { 1208 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1209 " is reserved\n", priority); 1210 return H_P3; 1211 } 1212 1213 /* 1214 * Validate that "target" is part of the list of threads allocated 1215 * to the partition. For that, find the END corresponding to the 1216 * target. 1217 */ 1218 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1219 return H_P2; 1220 } 1221 1222 assert(end_idx < xive->nr_ends); 1223 end = &xive->endt[end_idx]; 1224 1225 args[0] = 0; 1226 if (xive_end_is_notify(end)) { 1227 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1228 } 1229 1230 if (xive_end_is_enqueue(end)) { 1231 args[1] = xive_end_qaddr(end); 1232 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1233 } else { 1234 args[1] = 0; 1235 args[2] = 0; 1236 } 1237 1238 if (kvm_irqchip_in_kernel()) { 1239 Error *local_err = NULL; 1240 1241 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1242 if (local_err) { 1243 error_report_err(local_err); 1244 return H_HARDWARE; 1245 } 1246 } 1247 1248 /* TODO: do we need any locking on the END ? */ 1249 if (flags & SPAPR_XIVE_END_DEBUG) { 1250 /* Load the event queue generation number into the return flags */ 1251 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1252 1253 /* Load R7 with the event queue offset counter */ 1254 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1255 } else { 1256 args[3] = 0; 1257 } 1258 1259 return H_SUCCESS; 1260 } 1261 1262 /* 1263 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1264 * reporting cache line pair for the calling thread. The reporting 1265 * cache lines will contain the OS interrupt context when the OS 1266 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1267 * interrupt. The reporting cache lines can be reset by inputting -1 1268 * in "reportingLine". Issuing the CI store byte without reporting 1269 * cache lines registered will result in the data not being accessible 1270 * to the OS. 1271 * 1272 * Parameters: 1273 * Input: 1274 * - R4: "flags" 1275 * Bits 0-63: Reserved 1276 * - R5: "reportingLine": The logical real address of the reporting cache 1277 * line pair 1278 * 1279 * Output: 1280 * - None 1281 */ 1282 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1283 SpaprMachineState *spapr, 1284 target_ulong opcode, 1285 target_ulong *args) 1286 { 1287 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1288 return H_FUNCTION; 1289 } 1290 1291 /* 1292 * H_STATE should be returned if a H_INT_RESET is in progress. 1293 * This is not needed when running the emulation under QEMU 1294 */ 1295 1296 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1297 return H_FUNCTION; 1298 } 1299 1300 /* 1301 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1302 * real address of the reporting cache line pair set for the input 1303 * "target". If no reporting cache line pair has been set, -1 is 1304 * returned. 1305 * 1306 * Parameters: 1307 * Input: 1308 * - R4: "flags" 1309 * Bits 0-63: Reserved 1310 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1311 * "ibm,ppc-interrupt-gserver#s" 1312 * - R6: "reportingLine": The logical real address of the reporting 1313 * cache line pair 1314 * 1315 * Output: 1316 * - R4: The logical real address of the reporting line if set, else -1 1317 */ 1318 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1319 SpaprMachineState *spapr, 1320 target_ulong opcode, 1321 target_ulong *args) 1322 { 1323 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1324 return H_FUNCTION; 1325 } 1326 1327 /* 1328 * H_STATE should be returned if a H_INT_RESET is in progress. 1329 * This is not needed when running the emulation under QEMU 1330 */ 1331 1332 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1333 return H_FUNCTION; 1334 } 1335 1336 /* 1337 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1338 * page for the input "lisn". This hcall is only supported for LISNs 1339 * that have the ESB hcall flag set to 1 when returned from hcall() 1340 * H_INT_GET_SOURCE_INFO. 1341 * 1342 * Parameters: 1343 * Input: 1344 * - R4: "flags" 1345 * Bits 0-62: Reserved 1346 * bit 63: Store: Store=1, store operation, else load operation 1347 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1348 * "ibm,xive-lisn-ranges" properties, or as returned by the 1349 * ibm,query-interrupt-source-number RTAS call, or as 1350 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1351 * - R6: "esbOffset" is the offset into the ESB page for the load or 1352 * store operation 1353 * - R7: "storeData" is the data to write for a store operation 1354 * 1355 * Output: 1356 * - R4: The value of the load if load operation, else -1 1357 */ 1358 1359 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1360 1361 static target_ulong h_int_esb(PowerPCCPU *cpu, 1362 SpaprMachineState *spapr, 1363 target_ulong opcode, 1364 target_ulong *args) 1365 { 1366 SpaprXive *xive = spapr->xive; 1367 XiveEAS eas; 1368 target_ulong flags = args[0]; 1369 target_ulong lisn = args[1]; 1370 target_ulong offset = args[2]; 1371 target_ulong data = args[3]; 1372 hwaddr mmio_addr; 1373 XiveSource *xsrc = &xive->source; 1374 1375 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1376 return H_FUNCTION; 1377 } 1378 1379 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1380 return H_PARAMETER; 1381 } 1382 1383 if (lisn >= xive->nr_irqs) { 1384 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1385 lisn); 1386 return H_P2; 1387 } 1388 1389 eas = xive->eat[lisn]; 1390 if (!xive_eas_is_valid(&eas)) { 1391 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1392 lisn); 1393 return H_P2; 1394 } 1395 1396 if (offset > (1ull << xsrc->esb_shift)) { 1397 return H_P3; 1398 } 1399 1400 if (kvm_irqchip_in_kernel()) { 1401 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1402 flags & SPAPR_XIVE_ESB_STORE); 1403 } else { 1404 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1405 1406 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1407 (flags & SPAPR_XIVE_ESB_STORE))) { 1408 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1409 HWADDR_PRIx "\n", mmio_addr); 1410 return H_HARDWARE; 1411 } 1412 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1413 } 1414 return H_SUCCESS; 1415 } 1416 1417 /* 1418 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1419 * ensure any in flight events for the input lisn are in the event 1420 * queue. 1421 * 1422 * Parameters: 1423 * Input: 1424 * - R4: "flags" 1425 * Bits 0-63: Reserved 1426 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1427 * "ibm,xive-lisn-ranges" properties, or as returned by the 1428 * ibm,query-interrupt-source-number RTAS call, or as 1429 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1430 * 1431 * Output: 1432 * - None 1433 */ 1434 static target_ulong h_int_sync(PowerPCCPU *cpu, 1435 SpaprMachineState *spapr, 1436 target_ulong opcode, 1437 target_ulong *args) 1438 { 1439 SpaprXive *xive = spapr->xive; 1440 XiveEAS eas; 1441 target_ulong flags = args[0]; 1442 target_ulong lisn = args[1]; 1443 1444 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1445 return H_FUNCTION; 1446 } 1447 1448 if (flags) { 1449 return H_PARAMETER; 1450 } 1451 1452 if (lisn >= xive->nr_irqs) { 1453 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1454 lisn); 1455 return H_P2; 1456 } 1457 1458 eas = xive->eat[lisn]; 1459 if (!xive_eas_is_valid(&eas)) { 1460 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1461 lisn); 1462 return H_P2; 1463 } 1464 1465 /* 1466 * H_STATE should be returned if a H_INT_RESET is in progress. 1467 * This is not needed when running the emulation under QEMU 1468 */ 1469 1470 /* 1471 * This is not real hardware. Nothing to be done unless when 1472 * under KVM 1473 */ 1474 1475 if (kvm_irqchip_in_kernel()) { 1476 Error *local_err = NULL; 1477 1478 kvmppc_xive_sync_source(xive, lisn, &local_err); 1479 if (local_err) { 1480 error_report_err(local_err); 1481 return H_HARDWARE; 1482 } 1483 } 1484 return H_SUCCESS; 1485 } 1486 1487 /* 1488 * The H_INT_RESET hcall() is used to reset all of the partition's 1489 * interrupt exploitation structures to their initial state. This 1490 * means losing all previously set interrupt state set via 1491 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1492 * 1493 * Parameters: 1494 * Input: 1495 * - R4: "flags" 1496 * Bits 0-63: Reserved 1497 * 1498 * Output: 1499 * - None 1500 */ 1501 static target_ulong h_int_reset(PowerPCCPU *cpu, 1502 SpaprMachineState *spapr, 1503 target_ulong opcode, 1504 target_ulong *args) 1505 { 1506 SpaprXive *xive = spapr->xive; 1507 target_ulong flags = args[0]; 1508 1509 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1510 return H_FUNCTION; 1511 } 1512 1513 if (flags) { 1514 return H_PARAMETER; 1515 } 1516 1517 device_reset(DEVICE(xive)); 1518 1519 if (kvm_irqchip_in_kernel()) { 1520 Error *local_err = NULL; 1521 1522 kvmppc_xive_reset(xive, &local_err); 1523 if (local_err) { 1524 error_report_err(local_err); 1525 return H_HARDWARE; 1526 } 1527 } 1528 return H_SUCCESS; 1529 } 1530 1531 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1532 { 1533 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1534 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1535 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1536 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1537 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1538 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1539 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1540 h_int_set_os_reporting_line); 1541 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1542 h_int_get_os_reporting_line); 1543 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1544 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1545 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1546 } 1547 1548 void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, 1549 uint32_t phandle) 1550 { 1551 SpaprXive *xive = spapr->xive; 1552 int node; 1553 uint64_t timas[2 * 2]; 1554 /* Interrupt number ranges for the IPIs */ 1555 uint32_t lisn_ranges[] = { 1556 cpu_to_be32(0), 1557 cpu_to_be32(nr_servers), 1558 }; 1559 /* 1560 * EQ size - the sizes of pages supported by the system 4K, 64K, 1561 * 2M, 16M. We only advertise 64K for the moment. 1562 */ 1563 uint32_t eq_sizes[] = { 1564 cpu_to_be32(16), /* 64K */ 1565 }; 1566 /* 1567 * The following array is in sync with the reserved priorities 1568 * defined by the 'spapr_xive_priority_is_reserved' routine. 1569 */ 1570 uint32_t plat_res_int_priorities[] = { 1571 cpu_to_be32(7), /* start */ 1572 cpu_to_be32(0xf8), /* count */ 1573 }; 1574 1575 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 1576 timas[0] = cpu_to_be64(xive->tm_base + 1577 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 1578 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 1579 timas[2] = cpu_to_be64(xive->tm_base + 1580 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 1581 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 1582 1583 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 1584 1585 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 1586 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 1587 1588 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 1589 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 1590 sizeof(eq_sizes))); 1591 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 1592 sizeof(lisn_ranges))); 1593 1594 /* For Linux to link the LSIs to the interrupt controller. */ 1595 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 1596 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 1597 1598 /* For SLOF */ 1599 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 1600 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 1601 1602 /* 1603 * The "ibm,plat-res-int-priorities" property defines the priority 1604 * ranges reserved by the hypervisor 1605 */ 1606 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 1607 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 1608 } 1609