1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 } 150 151 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 152 { 153 XiveSource *xsrc = &xive->source; 154 int i; 155 156 if (kvm_irqchip_in_kernel()) { 157 Error *local_err = NULL; 158 159 kvmppc_xive_synchronize_state(xive, &local_err); 160 if (local_err) { 161 error_report_err(local_err); 162 return; 163 } 164 } 165 166 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 167 168 for (i = 0; i < xive->nr_irqs; i++) { 169 uint8_t pq = xive_source_esb_get(xsrc, i); 170 XiveEAS *eas = &xive->eat[i]; 171 172 if (!xive_eas_is_valid(eas)) { 173 continue; 174 } 175 176 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 177 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 178 pq & XIVE_ESB_VAL_P ? 'P' : '-', 179 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 180 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 181 xive_eas_is_masked(eas) ? "M" : " ", 182 (int) xive_get_field64(EAS_END_DATA, eas->w)); 183 184 if (!xive_eas_is_masked(eas)) { 185 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 186 XiveEND *end; 187 188 assert(end_idx < xive->nr_ends); 189 end = &xive->endt[end_idx]; 190 191 if (xive_end_is_valid(end)) { 192 spapr_xive_end_pic_print_info(xive, end, mon); 193 } 194 } 195 monitor_printf(mon, "\n"); 196 } 197 } 198 199 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 200 { 201 memory_region_set_enabled(&xive->source.esb_mmio, enable); 202 memory_region_set_enabled(&xive->tm_mmio, enable); 203 204 /* Disable the END ESBs until a guest OS makes use of them */ 205 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 206 } 207 208 /* 209 * When a Virtual Processor is scheduled to run on a HW thread, the 210 * hypervisor pushes its identifier in the OS CAM line. Emulate the 211 * same behavior under QEMU. 212 */ 213 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 214 { 215 uint8_t nvt_blk; 216 uint32_t nvt_idx; 217 uint32_t nvt_cam; 218 219 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 220 221 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 222 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 223 } 224 225 static void spapr_xive_end_reset(XiveEND *end) 226 { 227 memset(end, 0, sizeof(*end)); 228 229 /* switch off the escalation and notification ESBs */ 230 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 231 } 232 233 static void spapr_xive_reset(void *dev) 234 { 235 SpaprXive *xive = SPAPR_XIVE(dev); 236 int i; 237 238 /* 239 * The XiveSource has its own reset handler, which mask off all 240 * IRQs (!P|Q) 241 */ 242 243 /* Mask all valid EASs in the IRQ number space. */ 244 for (i = 0; i < xive->nr_irqs; i++) { 245 XiveEAS *eas = &xive->eat[i]; 246 if (xive_eas_is_valid(eas)) { 247 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 248 } else { 249 eas->w = 0; 250 } 251 } 252 253 /* Clear all ENDs */ 254 for (i = 0; i < xive->nr_ends; i++) { 255 spapr_xive_end_reset(&xive->endt[i]); 256 } 257 } 258 259 static void spapr_xive_instance_init(Object *obj) 260 { 261 SpaprXive *xive = SPAPR_XIVE(obj); 262 263 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 264 TYPE_XIVE_SOURCE, &error_abort, NULL); 265 266 object_initialize_child(obj, "end_source", &xive->end_source, 267 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 268 &error_abort, NULL); 269 270 /* Not connected to the KVM XIVE device */ 271 xive->fd = -1; 272 } 273 274 static void spapr_xive_realize(DeviceState *dev, Error **errp) 275 { 276 SpaprXive *xive = SPAPR_XIVE(dev); 277 XiveSource *xsrc = &xive->source; 278 XiveENDSource *end_xsrc = &xive->end_source; 279 Error *local_err = NULL; 280 281 if (!xive->nr_irqs) { 282 error_setg(errp, "Number of interrupt needs to be greater 0"); 283 return; 284 } 285 286 if (!xive->nr_ends) { 287 error_setg(errp, "Number of interrupt needs to be greater 0"); 288 return; 289 } 290 291 /* 292 * Initialize the internal sources, for IPIs and virtual devices. 293 */ 294 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 295 &error_fatal); 296 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 297 &error_fatal); 298 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 299 if (local_err) { 300 error_propagate(errp, local_err); 301 return; 302 } 303 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 304 305 /* 306 * Initialize the END ESB source 307 */ 308 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 309 &error_fatal); 310 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 311 &error_fatal); 312 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 313 if (local_err) { 314 error_propagate(errp, local_err); 315 return; 316 } 317 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 318 319 /* Set the mapping address of the END ESB pages after the source ESBs */ 320 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 321 322 /* 323 * Allocate the routing tables 324 */ 325 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 326 xive->endt = g_new0(XiveEND, xive->nr_ends); 327 328 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 329 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 330 331 qemu_register_reset(spapr_xive_reset, dev); 332 333 /* TIMA initialization */ 334 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 335 "xive.tima", 4ull << TM_SHIFT); 336 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 337 338 /* 339 * Map all regions. These will be enabled or disabled at reset and 340 * can also be overridden by KVM memory regions if active 341 */ 342 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 343 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 344 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 345 } 346 347 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 348 uint32_t eas_idx, XiveEAS *eas) 349 { 350 SpaprXive *xive = SPAPR_XIVE(xrtr); 351 352 if (eas_idx >= xive->nr_irqs) { 353 return -1; 354 } 355 356 *eas = xive->eat[eas_idx]; 357 return 0; 358 } 359 360 static int spapr_xive_get_end(XiveRouter *xrtr, 361 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 362 { 363 SpaprXive *xive = SPAPR_XIVE(xrtr); 364 365 if (end_idx >= xive->nr_ends) { 366 return -1; 367 } 368 369 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 370 return 0; 371 } 372 373 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 374 uint32_t end_idx, XiveEND *end, 375 uint8_t word_number) 376 { 377 SpaprXive *xive = SPAPR_XIVE(xrtr); 378 379 if (end_idx >= xive->nr_ends) { 380 return -1; 381 } 382 383 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 384 return 0; 385 } 386 387 static int spapr_xive_get_nvt(XiveRouter *xrtr, 388 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 389 { 390 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 391 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 392 393 if (!cpu) { 394 /* TODO: should we assert() if we can find a NVT ? */ 395 return -1; 396 } 397 398 /* 399 * sPAPR does not maintain a NVT table. Return that the NVT is 400 * valid if we have found a matching CPU 401 */ 402 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 403 return 0; 404 } 405 406 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 407 uint32_t nvt_idx, XiveNVT *nvt, 408 uint8_t word_number) 409 { 410 /* 411 * We don't need to write back to the NVTs because the sPAPR 412 * machine should never hit a non-scheduled NVT. It should never 413 * get called. 414 */ 415 g_assert_not_reached(); 416 } 417 418 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 419 { 420 PowerPCCPU *cpu = POWERPC_CPU(cs); 421 422 return spapr_cpu_state(cpu)->tctx; 423 } 424 425 static const VMStateDescription vmstate_spapr_xive_end = { 426 .name = TYPE_SPAPR_XIVE "/end", 427 .version_id = 1, 428 .minimum_version_id = 1, 429 .fields = (VMStateField []) { 430 VMSTATE_UINT32(w0, XiveEND), 431 VMSTATE_UINT32(w1, XiveEND), 432 VMSTATE_UINT32(w2, XiveEND), 433 VMSTATE_UINT32(w3, XiveEND), 434 VMSTATE_UINT32(w4, XiveEND), 435 VMSTATE_UINT32(w5, XiveEND), 436 VMSTATE_UINT32(w6, XiveEND), 437 VMSTATE_UINT32(w7, XiveEND), 438 VMSTATE_END_OF_LIST() 439 }, 440 }; 441 442 static const VMStateDescription vmstate_spapr_xive_eas = { 443 .name = TYPE_SPAPR_XIVE "/eas", 444 .version_id = 1, 445 .minimum_version_id = 1, 446 .fields = (VMStateField []) { 447 VMSTATE_UINT64(w, XiveEAS), 448 VMSTATE_END_OF_LIST() 449 }, 450 }; 451 452 static int vmstate_spapr_xive_pre_save(void *opaque) 453 { 454 if (kvm_irqchip_in_kernel()) { 455 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 456 } 457 458 return 0; 459 } 460 461 /* 462 * Called by the sPAPR IRQ backend 'post_load' method at the machine 463 * level. 464 */ 465 int spapr_xive_post_load(SpaprXive *xive, int version_id) 466 { 467 if (kvm_irqchip_in_kernel()) { 468 return kvmppc_xive_post_load(xive, version_id); 469 } 470 471 return 0; 472 } 473 474 static const VMStateDescription vmstate_spapr_xive = { 475 .name = TYPE_SPAPR_XIVE, 476 .version_id = 1, 477 .minimum_version_id = 1, 478 .pre_save = vmstate_spapr_xive_pre_save, 479 .post_load = NULL, /* handled at the machine level */ 480 .fields = (VMStateField[]) { 481 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 482 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 483 vmstate_spapr_xive_eas, XiveEAS), 484 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 485 vmstate_spapr_xive_end, XiveEND), 486 VMSTATE_END_OF_LIST() 487 }, 488 }; 489 490 static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, 491 bool lsi, Error **errp) 492 { 493 SpaprXive *xive = SPAPR_XIVE(intc); 494 XiveSource *xsrc = &xive->source; 495 496 assert(lisn < xive->nr_irqs); 497 498 if (xive_eas_is_valid(&xive->eat[lisn])) { 499 error_setg(errp, "IRQ %d is not free", lisn); 500 return -EBUSY; 501 } 502 503 /* 504 * Set default values when allocating an IRQ number 505 */ 506 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); 507 if (lsi) { 508 xive_source_irq_set_lsi(xsrc, lisn); 509 } 510 511 if (kvm_irqchip_in_kernel()) { 512 return kvmppc_xive_source_reset_one(xsrc, lisn, errp); 513 } 514 515 return 0; 516 } 517 518 static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) 519 { 520 SpaprXive *xive = SPAPR_XIVE(intc); 521 assert(lisn < xive->nr_irqs); 522 523 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 524 } 525 526 static Property spapr_xive_properties[] = { 527 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 528 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 529 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 530 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 531 DEFINE_PROP_END_OF_LIST(), 532 }; 533 534 static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 535 PowerPCCPU *cpu, Error **errp) 536 { 537 SpaprXive *xive = SPAPR_XIVE(intc); 538 Object *obj; 539 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 540 541 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp); 542 if (!obj) { 543 return -1; 544 } 545 546 spapr_cpu->tctx = XIVE_TCTX(obj); 547 548 /* 549 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they 550 * don't beneficiate from the reset of the XIVE IRQ backend 551 */ 552 spapr_xive_set_tctx_os_cam(spapr_cpu->tctx); 553 return 0; 554 } 555 556 static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val) 557 { 558 SpaprXive *xive = SPAPR_XIVE(intc); 559 560 if (kvm_irqchip_in_kernel()) { 561 kvmppc_xive_source_set_irq(&xive->source, irq, val); 562 } else { 563 xive_source_set_irq(&xive->source, irq, val); 564 } 565 } 566 567 static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor *mon) 568 { 569 SpaprXive *xive = SPAPR_XIVE(intc); 570 CPUState *cs; 571 572 CPU_FOREACH(cs) { 573 PowerPCCPU *cpu = POWERPC_CPU(cs); 574 575 xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); 576 } 577 578 spapr_xive_pic_print_info(xive, mon); 579 } 580 581 static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers, 582 void *fdt, uint32_t phandle) 583 { 584 SpaprXive *xive = SPAPR_XIVE(intc); 585 int node; 586 uint64_t timas[2 * 2]; 587 /* Interrupt number ranges for the IPIs */ 588 uint32_t lisn_ranges[] = { 589 cpu_to_be32(0), 590 cpu_to_be32(nr_servers), 591 }; 592 /* 593 * EQ size - the sizes of pages supported by the system 4K, 64K, 594 * 2M, 16M. We only advertise 64K for the moment. 595 */ 596 uint32_t eq_sizes[] = { 597 cpu_to_be32(16), /* 64K */ 598 }; 599 /* 600 * The following array is in sync with the reserved priorities 601 * defined by the 'spapr_xive_priority_is_reserved' routine. 602 */ 603 uint32_t plat_res_int_priorities[] = { 604 cpu_to_be32(7), /* start */ 605 cpu_to_be32(0xf8), /* count */ 606 }; 607 608 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 609 timas[0] = cpu_to_be64(xive->tm_base + 610 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 611 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 612 timas[2] = cpu_to_be64(xive->tm_base + 613 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 614 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 615 616 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 617 618 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 619 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 620 621 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 622 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 623 sizeof(eq_sizes))); 624 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 625 sizeof(lisn_ranges))); 626 627 /* For Linux to link the LSIs to the interrupt controller. */ 628 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 629 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 630 631 /* For SLOF */ 632 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 633 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 634 635 /* 636 * The "ibm,plat-res-int-priorities" property defines the priority 637 * ranges reserved by the hypervisor 638 */ 639 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 640 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 641 } 642 643 static int spapr_xive_activate(SpaprInterruptController *intc, Error **errp) 644 { 645 SpaprXive *xive = SPAPR_XIVE(intc); 646 CPUState *cs; 647 648 CPU_FOREACH(cs) { 649 PowerPCCPU *cpu = POWERPC_CPU(cs); 650 651 /* (TCG) Set the OS CAM line of the thread interrupt context. */ 652 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx); 653 } 654 655 if (kvm_enabled()) { 656 int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, errp); 657 if (rc < 0) { 658 return rc; 659 } 660 } 661 662 /* Activate the XIVE MMIOs */ 663 spapr_xive_mmio_set_enabled(xive, true); 664 665 return 0; 666 } 667 668 static void spapr_xive_deactivate(SpaprInterruptController *intc) 669 { 670 SpaprXive *xive = SPAPR_XIVE(intc); 671 672 spapr_xive_mmio_set_enabled(xive, false); 673 674 if (kvm_irqchip_in_kernel()) { 675 kvmppc_xive_disconnect(intc); 676 } 677 } 678 679 static void spapr_xive_class_init(ObjectClass *klass, void *data) 680 { 681 DeviceClass *dc = DEVICE_CLASS(klass); 682 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 683 SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); 684 685 dc->desc = "sPAPR XIVE Interrupt Controller"; 686 dc->props = spapr_xive_properties; 687 dc->realize = spapr_xive_realize; 688 dc->vmsd = &vmstate_spapr_xive; 689 690 xrc->get_eas = spapr_xive_get_eas; 691 xrc->get_end = spapr_xive_get_end; 692 xrc->write_end = spapr_xive_write_end; 693 xrc->get_nvt = spapr_xive_get_nvt; 694 xrc->write_nvt = spapr_xive_write_nvt; 695 xrc->get_tctx = spapr_xive_get_tctx; 696 697 sicc->activate = spapr_xive_activate; 698 sicc->deactivate = spapr_xive_deactivate; 699 sicc->cpu_intc_create = spapr_xive_cpu_intc_create; 700 sicc->claim_irq = spapr_xive_claim_irq; 701 sicc->free_irq = spapr_xive_free_irq; 702 sicc->set_irq = spapr_xive_set_irq; 703 sicc->print_info = spapr_xive_print_info; 704 sicc->dt = spapr_xive_dt; 705 } 706 707 static const TypeInfo spapr_xive_info = { 708 .name = TYPE_SPAPR_XIVE, 709 .parent = TYPE_XIVE_ROUTER, 710 .instance_init = spapr_xive_instance_init, 711 .instance_size = sizeof(SpaprXive), 712 .class_init = spapr_xive_class_init, 713 .interfaces = (InterfaceInfo[]) { 714 { TYPE_SPAPR_INTC }, 715 { } 716 }, 717 }; 718 719 static void spapr_xive_register_types(void) 720 { 721 type_register_static(&spapr_xive_info); 722 } 723 724 type_init(spapr_xive_register_types) 725 726 /* 727 * XIVE hcalls 728 * 729 * The terminology used by the XIVE hcalls is the following : 730 * 731 * TARGET vCPU number 732 * EQ Event Queue assigned by OS to receive event data 733 * ESB page for source interrupt management 734 * LISN Logical Interrupt Source Number identifying a source in the 735 * machine 736 * EISN Effective Interrupt Source Number used by guest OS to 737 * identify source in the guest 738 * 739 * The EAS, END, NVT structures are not exposed. 740 */ 741 742 /* 743 * Linux hosts under OPAL reserve priority 7 for their own escalation 744 * interrupts (DD2.X POWER9). So we only allow the guest to use 745 * priorities [0..6]. 746 */ 747 static bool spapr_xive_priority_is_reserved(uint8_t priority) 748 { 749 switch (priority) { 750 case 0 ... 6: 751 return false; 752 case 7: /* OPAL escalation queue */ 753 default: 754 return true; 755 } 756 } 757 758 /* 759 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 760 * real address of the MMIO page through which the Event State Buffer 761 * entry associated with the value of the "lisn" parameter is managed. 762 * 763 * Parameters: 764 * Input 765 * - R4: "flags" 766 * Bits 0-63 reserved 767 * - R5: "lisn" is per "interrupts", "interrupt-map", or 768 * "ibm,xive-lisn-ranges" properties, or as returned by the 769 * ibm,query-interrupt-source-number RTAS call, or as returned 770 * by the H_ALLOCATE_VAS_WINDOW hcall 771 * 772 * Output 773 * - R4: "flags" 774 * Bits 0-59: Reserved 775 * Bit 60: H_INT_ESB must be used for Event State Buffer 776 * management 777 * Bit 61: 1 == LSI 0 == MSI 778 * Bit 62: the full function page supports trigger 779 * Bit 63: Store EOI Supported 780 * - R5: Logical Real address of full function Event State Buffer 781 * management page, -1 if H_INT_ESB hcall flag is set to 1. 782 * - R6: Logical Real Address of trigger only Event State Buffer 783 * management page or -1. 784 * - R7: Power of 2 page size for the ESB management pages returned in 785 * R5 and R6. 786 */ 787 788 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 789 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 790 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 791 on same page */ 792 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 793 794 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 795 SpaprMachineState *spapr, 796 target_ulong opcode, 797 target_ulong *args) 798 { 799 SpaprXive *xive = spapr->xive; 800 XiveSource *xsrc = &xive->source; 801 target_ulong flags = args[0]; 802 target_ulong lisn = args[1]; 803 804 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 805 return H_FUNCTION; 806 } 807 808 if (flags) { 809 return H_PARAMETER; 810 } 811 812 if (lisn >= xive->nr_irqs) { 813 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 814 lisn); 815 return H_P2; 816 } 817 818 if (!xive_eas_is_valid(&xive->eat[lisn])) { 819 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 820 lisn); 821 return H_P2; 822 } 823 824 /* 825 * All sources are emulated under the main XIVE object and share 826 * the same characteristics. 827 */ 828 args[0] = 0; 829 if (!xive_source_esb_has_2page(xsrc)) { 830 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 831 } 832 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 833 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 834 } 835 836 /* 837 * Force the use of the H_INT_ESB hcall in case of an LSI 838 * interrupt. This is necessary under KVM to re-trigger the 839 * interrupt if the level is still asserted 840 */ 841 if (xive_source_irq_is_lsi(xsrc, lisn)) { 842 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 843 } 844 845 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 846 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 847 } else { 848 args[1] = -1; 849 } 850 851 if (xive_source_esb_has_2page(xsrc) && 852 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 853 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 854 } else { 855 args[2] = -1; 856 } 857 858 if (xive_source_esb_has_2page(xsrc)) { 859 args[3] = xsrc->esb_shift - 1; 860 } else { 861 args[3] = xsrc->esb_shift; 862 } 863 864 return H_SUCCESS; 865 } 866 867 /* 868 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 869 * Interrupt Source to a target. The Logical Interrupt Source is 870 * designated with the "lisn" parameter and the target is designated 871 * with the "target" and "priority" parameters. Upon return from the 872 * hcall(), no additional interrupts will be directed to the old EQ. 873 * 874 * Parameters: 875 * Input: 876 * - R4: "flags" 877 * Bits 0-61: Reserved 878 * Bit 62: set the "eisn" in the EAS 879 * Bit 63: masks the interrupt source in the hardware interrupt 880 * control structure. An interrupt masked by this mechanism will 881 * be dropped, but it's source state bits will still be 882 * set. There is no race-free way of unmasking and restoring the 883 * source. Thus this should only be used in interrupts that are 884 * also masked at the source, and only in cases where the 885 * interrupt is not meant to be used for a large amount of time 886 * because no valid target exists for it for example 887 * - R5: "lisn" is per "interrupts", "interrupt-map", or 888 * "ibm,xive-lisn-ranges" properties, or as returned by the 889 * ibm,query-interrupt-source-number RTAS call, or as returned by 890 * the H_ALLOCATE_VAS_WINDOW hcall 891 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 892 * "ibm,ppc-interrupt-gserver#s" 893 * - R7: "priority" is a valid priority not in 894 * "ibm,plat-res-int-priorities" 895 * - R8: "eisn" is the guest EISN associated with the "lisn" 896 * 897 * Output: 898 * - None 899 */ 900 901 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 902 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 903 904 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 905 SpaprMachineState *spapr, 906 target_ulong opcode, 907 target_ulong *args) 908 { 909 SpaprXive *xive = spapr->xive; 910 XiveEAS eas, new_eas; 911 target_ulong flags = args[0]; 912 target_ulong lisn = args[1]; 913 target_ulong target = args[2]; 914 target_ulong priority = args[3]; 915 target_ulong eisn = args[4]; 916 uint8_t end_blk; 917 uint32_t end_idx; 918 919 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 920 return H_FUNCTION; 921 } 922 923 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 924 return H_PARAMETER; 925 } 926 927 if (lisn >= xive->nr_irqs) { 928 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 929 lisn); 930 return H_P2; 931 } 932 933 eas = xive->eat[lisn]; 934 if (!xive_eas_is_valid(&eas)) { 935 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 936 lisn); 937 return H_P2; 938 } 939 940 /* priority 0xff is used to reset the EAS */ 941 if (priority == 0xff) { 942 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 943 goto out; 944 } 945 946 if (flags & SPAPR_XIVE_SRC_MASK) { 947 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 948 } else { 949 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 950 } 951 952 if (spapr_xive_priority_is_reserved(priority)) { 953 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 954 " is reserved\n", priority); 955 return H_P4; 956 } 957 958 /* 959 * Validate that "target" is part of the list of threads allocated 960 * to the partition. For that, find the END corresponding to the 961 * target. 962 */ 963 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 964 return H_P3; 965 } 966 967 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 968 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 969 970 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 971 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 972 } 973 974 if (kvm_irqchip_in_kernel()) { 975 Error *local_err = NULL; 976 977 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 978 if (local_err) { 979 error_report_err(local_err); 980 return H_HARDWARE; 981 } 982 } 983 984 out: 985 xive->eat[lisn] = new_eas; 986 return H_SUCCESS; 987 } 988 989 /* 990 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 991 * target/priority pair is assigned to the specified Logical Interrupt 992 * Source. 993 * 994 * Parameters: 995 * Input: 996 * - R4: "flags" 997 * Bits 0-63 Reserved 998 * - R5: "lisn" is per "interrupts", "interrupt-map", or 999 * "ibm,xive-lisn-ranges" properties, or as returned by the 1000 * ibm,query-interrupt-source-number RTAS call, or as 1001 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1002 * 1003 * Output: 1004 * - R4: Target to which the specified Logical Interrupt Source is 1005 * assigned 1006 * - R5: Priority to which the specified Logical Interrupt Source is 1007 * assigned 1008 * - R6: EISN for the specified Logical Interrupt Source (this will be 1009 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 1010 */ 1011 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 1012 SpaprMachineState *spapr, 1013 target_ulong opcode, 1014 target_ulong *args) 1015 { 1016 SpaprXive *xive = spapr->xive; 1017 target_ulong flags = args[0]; 1018 target_ulong lisn = args[1]; 1019 XiveEAS eas; 1020 XiveEND *end; 1021 uint8_t nvt_blk; 1022 uint32_t end_idx, nvt_idx; 1023 1024 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1025 return H_FUNCTION; 1026 } 1027 1028 if (flags) { 1029 return H_PARAMETER; 1030 } 1031 1032 if (lisn >= xive->nr_irqs) { 1033 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1034 lisn); 1035 return H_P2; 1036 } 1037 1038 eas = xive->eat[lisn]; 1039 if (!xive_eas_is_valid(&eas)) { 1040 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1041 lisn); 1042 return H_P2; 1043 } 1044 1045 /* EAS_END_BLOCK is unused on sPAPR */ 1046 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 1047 1048 assert(end_idx < xive->nr_ends); 1049 end = &xive->endt[end_idx]; 1050 1051 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1052 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1053 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 1054 1055 if (xive_eas_is_masked(&eas)) { 1056 args[1] = 0xff; 1057 } else { 1058 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1059 } 1060 1061 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 1062 1063 return H_SUCCESS; 1064 } 1065 1066 /* 1067 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 1068 * address of the notification management page associated with the 1069 * specified target and priority. 1070 * 1071 * Parameters: 1072 * Input: 1073 * - R4: "flags" 1074 * Bits 0-63 Reserved 1075 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1076 * "ibm,ppc-interrupt-gserver#s" 1077 * - R6: "priority" is a valid priority not in 1078 * "ibm,plat-res-int-priorities" 1079 * 1080 * Output: 1081 * - R4: Logical real address of notification page 1082 * - R5: Power of 2 page size of the notification page 1083 */ 1084 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 1085 SpaprMachineState *spapr, 1086 target_ulong opcode, 1087 target_ulong *args) 1088 { 1089 SpaprXive *xive = spapr->xive; 1090 XiveENDSource *end_xsrc = &xive->end_source; 1091 target_ulong flags = args[0]; 1092 target_ulong target = args[1]; 1093 target_ulong priority = args[2]; 1094 XiveEND *end; 1095 uint8_t end_blk; 1096 uint32_t end_idx; 1097 1098 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1099 return H_FUNCTION; 1100 } 1101 1102 if (flags) { 1103 return H_PARAMETER; 1104 } 1105 1106 /* 1107 * H_STATE should be returned if a H_INT_RESET is in progress. 1108 * This is not needed when running the emulation under QEMU 1109 */ 1110 1111 if (spapr_xive_priority_is_reserved(priority)) { 1112 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1113 " is reserved\n", priority); 1114 return H_P3; 1115 } 1116 1117 /* 1118 * Validate that "target" is part of the list of threads allocated 1119 * to the partition. For that, find the END corresponding to the 1120 * target. 1121 */ 1122 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1123 return H_P2; 1124 } 1125 1126 assert(end_idx < xive->nr_ends); 1127 end = &xive->endt[end_idx]; 1128 1129 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 1130 if (xive_end_is_enqueue(end)) { 1131 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1132 } else { 1133 args[1] = 0; 1134 } 1135 1136 return H_SUCCESS; 1137 } 1138 1139 /* 1140 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 1141 * a given "target" and "priority". It is also used to set the 1142 * notification config associated with the EQ. An EQ size of 0 is 1143 * used to reset the EQ config for a given target and priority. If 1144 * resetting the EQ config, the END associated with the given "target" 1145 * and "priority" will be changed to disable queueing. 1146 * 1147 * Upon return from the hcall(), no additional interrupts will be 1148 * directed to the old EQ (if one was set). The old EQ (if one was 1149 * set) should be investigated for interrupts that occurred prior to 1150 * or during the hcall(). 1151 * 1152 * Parameters: 1153 * Input: 1154 * - R4: "flags" 1155 * Bits 0-62: Reserved 1156 * Bit 63: Unconditional Notify (n) per the XIVE spec 1157 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1158 * "ibm,ppc-interrupt-gserver#s" 1159 * - R6: "priority" is a valid priority not in 1160 * "ibm,plat-res-int-priorities" 1161 * - R7: "eventQueue": The logical real address of the start of the EQ 1162 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1163 * 1164 * Output: 1165 * - None 1166 */ 1167 1168 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1169 1170 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1171 SpaprMachineState *spapr, 1172 target_ulong opcode, 1173 target_ulong *args) 1174 { 1175 SpaprXive *xive = spapr->xive; 1176 target_ulong flags = args[0]; 1177 target_ulong target = args[1]; 1178 target_ulong priority = args[2]; 1179 target_ulong qpage = args[3]; 1180 target_ulong qsize = args[4]; 1181 XiveEND end; 1182 uint8_t end_blk, nvt_blk; 1183 uint32_t end_idx, nvt_idx; 1184 1185 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1186 return H_FUNCTION; 1187 } 1188 1189 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1190 return H_PARAMETER; 1191 } 1192 1193 /* 1194 * H_STATE should be returned if a H_INT_RESET is in progress. 1195 * This is not needed when running the emulation under QEMU 1196 */ 1197 1198 if (spapr_xive_priority_is_reserved(priority)) { 1199 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1200 " is reserved\n", priority); 1201 return H_P3; 1202 } 1203 1204 /* 1205 * Validate that "target" is part of the list of threads allocated 1206 * to the partition. For that, find the END corresponding to the 1207 * target. 1208 */ 1209 1210 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1211 return H_P2; 1212 } 1213 1214 assert(end_idx < xive->nr_ends); 1215 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1216 1217 switch (qsize) { 1218 case 12: 1219 case 16: 1220 case 21: 1221 case 24: 1222 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1223 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1224 " is not naturally aligned with %" HWADDR_PRIx "\n", 1225 qpage, (hwaddr)1 << qsize); 1226 return H_P4; 1227 } 1228 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1229 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1230 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1231 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1232 break; 1233 case 0: 1234 /* reset queue and disable queueing */ 1235 spapr_xive_end_reset(&end); 1236 goto out; 1237 1238 default: 1239 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1240 qsize); 1241 return H_P5; 1242 } 1243 1244 if (qsize) { 1245 hwaddr plen = 1 << qsize; 1246 void *eq; 1247 1248 /* 1249 * Validate the guest EQ. We should also check that the queue 1250 * has been zeroed by the OS. 1251 */ 1252 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1253 MEMTXATTRS_UNSPECIFIED); 1254 if (plen != 1 << qsize) { 1255 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1256 HWADDR_PRIx "\n", qpage); 1257 return H_P4; 1258 } 1259 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1260 } 1261 1262 /* "target" should have been validated above */ 1263 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1264 g_assert_not_reached(); 1265 } 1266 1267 /* 1268 * Ensure the priority and target are correctly set (they will not 1269 * be right after allocation) 1270 */ 1271 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1272 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1273 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1274 1275 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1276 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1277 } else { 1278 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1279 } 1280 1281 /* 1282 * The generation bit for the END starts at 1 and The END page 1283 * offset counter starts at 0. 1284 */ 1285 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1286 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1287 end.w0 |= cpu_to_be32(END_W0_VALID); 1288 1289 /* 1290 * TODO: issue syncs required to ensure all in-flight interrupts 1291 * are complete on the old END 1292 */ 1293 1294 out: 1295 if (kvm_irqchip_in_kernel()) { 1296 Error *local_err = NULL; 1297 1298 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1299 if (local_err) { 1300 error_report_err(local_err); 1301 return H_HARDWARE; 1302 } 1303 } 1304 1305 /* Update END */ 1306 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1307 return H_SUCCESS; 1308 } 1309 1310 /* 1311 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1312 * target and priority. 1313 * 1314 * Parameters: 1315 * Input: 1316 * - R4: "flags" 1317 * Bits 0-62: Reserved 1318 * Bit 63: Debug: Return debug data 1319 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1320 * "ibm,ppc-interrupt-gserver#s" 1321 * - R6: "priority" is a valid priority not in 1322 * "ibm,plat-res-int-priorities" 1323 * 1324 * Output: 1325 * - R4: "flags": 1326 * Bits 0-61: Reserved 1327 * Bit 62: The value of Event Queue Generation Number (g) per 1328 * the XIVE spec if "Debug" = 1 1329 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1330 * - R5: The logical real address of the start of the EQ 1331 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1332 * - R7: The value of Event Queue Offset Counter per XIVE spec 1333 * if "Debug" = 1, else 0 1334 * 1335 */ 1336 1337 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1338 1339 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1340 SpaprMachineState *spapr, 1341 target_ulong opcode, 1342 target_ulong *args) 1343 { 1344 SpaprXive *xive = spapr->xive; 1345 target_ulong flags = args[0]; 1346 target_ulong target = args[1]; 1347 target_ulong priority = args[2]; 1348 XiveEND *end; 1349 uint8_t end_blk; 1350 uint32_t end_idx; 1351 1352 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1353 return H_FUNCTION; 1354 } 1355 1356 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1357 return H_PARAMETER; 1358 } 1359 1360 /* 1361 * H_STATE should be returned if a H_INT_RESET is in progress. 1362 * This is not needed when running the emulation under QEMU 1363 */ 1364 1365 if (spapr_xive_priority_is_reserved(priority)) { 1366 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1367 " is reserved\n", priority); 1368 return H_P3; 1369 } 1370 1371 /* 1372 * Validate that "target" is part of the list of threads allocated 1373 * to the partition. For that, find the END corresponding to the 1374 * target. 1375 */ 1376 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1377 return H_P2; 1378 } 1379 1380 assert(end_idx < xive->nr_ends); 1381 end = &xive->endt[end_idx]; 1382 1383 args[0] = 0; 1384 if (xive_end_is_notify(end)) { 1385 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1386 } 1387 1388 if (xive_end_is_enqueue(end)) { 1389 args[1] = xive_end_qaddr(end); 1390 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1391 } else { 1392 args[1] = 0; 1393 args[2] = 0; 1394 } 1395 1396 if (kvm_irqchip_in_kernel()) { 1397 Error *local_err = NULL; 1398 1399 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1400 if (local_err) { 1401 error_report_err(local_err); 1402 return H_HARDWARE; 1403 } 1404 } 1405 1406 /* TODO: do we need any locking on the END ? */ 1407 if (flags & SPAPR_XIVE_END_DEBUG) { 1408 /* Load the event queue generation number into the return flags */ 1409 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1410 1411 /* Load R7 with the event queue offset counter */ 1412 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1413 } else { 1414 args[3] = 0; 1415 } 1416 1417 return H_SUCCESS; 1418 } 1419 1420 /* 1421 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1422 * reporting cache line pair for the calling thread. The reporting 1423 * cache lines will contain the OS interrupt context when the OS 1424 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1425 * interrupt. The reporting cache lines can be reset by inputting -1 1426 * in "reportingLine". Issuing the CI store byte without reporting 1427 * cache lines registered will result in the data not being accessible 1428 * to the OS. 1429 * 1430 * Parameters: 1431 * Input: 1432 * - R4: "flags" 1433 * Bits 0-63: Reserved 1434 * - R5: "reportingLine": The logical real address of the reporting cache 1435 * line pair 1436 * 1437 * Output: 1438 * - None 1439 */ 1440 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1441 SpaprMachineState *spapr, 1442 target_ulong opcode, 1443 target_ulong *args) 1444 { 1445 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1446 return H_FUNCTION; 1447 } 1448 1449 /* 1450 * H_STATE should be returned if a H_INT_RESET is in progress. 1451 * This is not needed when running the emulation under QEMU 1452 */ 1453 1454 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1455 return H_FUNCTION; 1456 } 1457 1458 /* 1459 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1460 * real address of the reporting cache line pair set for the input 1461 * "target". If no reporting cache line pair has been set, -1 is 1462 * returned. 1463 * 1464 * Parameters: 1465 * Input: 1466 * - R4: "flags" 1467 * Bits 0-63: Reserved 1468 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1469 * "ibm,ppc-interrupt-gserver#s" 1470 * - R6: "reportingLine": The logical real address of the reporting 1471 * cache line pair 1472 * 1473 * Output: 1474 * - R4: The logical real address of the reporting line if set, else -1 1475 */ 1476 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1477 SpaprMachineState *spapr, 1478 target_ulong opcode, 1479 target_ulong *args) 1480 { 1481 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1482 return H_FUNCTION; 1483 } 1484 1485 /* 1486 * H_STATE should be returned if a H_INT_RESET is in progress. 1487 * This is not needed when running the emulation under QEMU 1488 */ 1489 1490 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1491 return H_FUNCTION; 1492 } 1493 1494 /* 1495 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1496 * page for the input "lisn". This hcall is only supported for LISNs 1497 * that have the ESB hcall flag set to 1 when returned from hcall() 1498 * H_INT_GET_SOURCE_INFO. 1499 * 1500 * Parameters: 1501 * Input: 1502 * - R4: "flags" 1503 * Bits 0-62: Reserved 1504 * bit 63: Store: Store=1, store operation, else load operation 1505 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1506 * "ibm,xive-lisn-ranges" properties, or as returned by the 1507 * ibm,query-interrupt-source-number RTAS call, or as 1508 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1509 * - R6: "esbOffset" is the offset into the ESB page for the load or 1510 * store operation 1511 * - R7: "storeData" is the data to write for a store operation 1512 * 1513 * Output: 1514 * - R4: The value of the load if load operation, else -1 1515 */ 1516 1517 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1518 1519 static target_ulong h_int_esb(PowerPCCPU *cpu, 1520 SpaprMachineState *spapr, 1521 target_ulong opcode, 1522 target_ulong *args) 1523 { 1524 SpaprXive *xive = spapr->xive; 1525 XiveEAS eas; 1526 target_ulong flags = args[0]; 1527 target_ulong lisn = args[1]; 1528 target_ulong offset = args[2]; 1529 target_ulong data = args[3]; 1530 hwaddr mmio_addr; 1531 XiveSource *xsrc = &xive->source; 1532 1533 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1534 return H_FUNCTION; 1535 } 1536 1537 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1538 return H_PARAMETER; 1539 } 1540 1541 if (lisn >= xive->nr_irqs) { 1542 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1543 lisn); 1544 return H_P2; 1545 } 1546 1547 eas = xive->eat[lisn]; 1548 if (!xive_eas_is_valid(&eas)) { 1549 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1550 lisn); 1551 return H_P2; 1552 } 1553 1554 if (offset > (1ull << xsrc->esb_shift)) { 1555 return H_P3; 1556 } 1557 1558 if (kvm_irqchip_in_kernel()) { 1559 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1560 flags & SPAPR_XIVE_ESB_STORE); 1561 } else { 1562 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1563 1564 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1565 (flags & SPAPR_XIVE_ESB_STORE))) { 1566 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1567 HWADDR_PRIx "\n", mmio_addr); 1568 return H_HARDWARE; 1569 } 1570 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1571 } 1572 return H_SUCCESS; 1573 } 1574 1575 /* 1576 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1577 * ensure any in flight events for the input lisn are in the event 1578 * queue. 1579 * 1580 * Parameters: 1581 * Input: 1582 * - R4: "flags" 1583 * Bits 0-63: Reserved 1584 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1585 * "ibm,xive-lisn-ranges" properties, or as returned by the 1586 * ibm,query-interrupt-source-number RTAS call, or as 1587 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1588 * 1589 * Output: 1590 * - None 1591 */ 1592 static target_ulong h_int_sync(PowerPCCPU *cpu, 1593 SpaprMachineState *spapr, 1594 target_ulong opcode, 1595 target_ulong *args) 1596 { 1597 SpaprXive *xive = spapr->xive; 1598 XiveEAS eas; 1599 target_ulong flags = args[0]; 1600 target_ulong lisn = args[1]; 1601 1602 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1603 return H_FUNCTION; 1604 } 1605 1606 if (flags) { 1607 return H_PARAMETER; 1608 } 1609 1610 if (lisn >= xive->nr_irqs) { 1611 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1612 lisn); 1613 return H_P2; 1614 } 1615 1616 eas = xive->eat[lisn]; 1617 if (!xive_eas_is_valid(&eas)) { 1618 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1619 lisn); 1620 return H_P2; 1621 } 1622 1623 /* 1624 * H_STATE should be returned if a H_INT_RESET is in progress. 1625 * This is not needed when running the emulation under QEMU 1626 */ 1627 1628 /* 1629 * This is not real hardware. Nothing to be done unless when 1630 * under KVM 1631 */ 1632 1633 if (kvm_irqchip_in_kernel()) { 1634 Error *local_err = NULL; 1635 1636 kvmppc_xive_sync_source(xive, lisn, &local_err); 1637 if (local_err) { 1638 error_report_err(local_err); 1639 return H_HARDWARE; 1640 } 1641 } 1642 return H_SUCCESS; 1643 } 1644 1645 /* 1646 * The H_INT_RESET hcall() is used to reset all of the partition's 1647 * interrupt exploitation structures to their initial state. This 1648 * means losing all previously set interrupt state set via 1649 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1650 * 1651 * Parameters: 1652 * Input: 1653 * - R4: "flags" 1654 * Bits 0-63: Reserved 1655 * 1656 * Output: 1657 * - None 1658 */ 1659 static target_ulong h_int_reset(PowerPCCPU *cpu, 1660 SpaprMachineState *spapr, 1661 target_ulong opcode, 1662 target_ulong *args) 1663 { 1664 SpaprXive *xive = spapr->xive; 1665 target_ulong flags = args[0]; 1666 1667 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1668 return H_FUNCTION; 1669 } 1670 1671 if (flags) { 1672 return H_PARAMETER; 1673 } 1674 1675 device_reset(DEVICE(xive)); 1676 1677 if (kvm_irqchip_in_kernel()) { 1678 Error *local_err = NULL; 1679 1680 kvmppc_xive_reset(xive, &local_err); 1681 if (local_err) { 1682 error_report_err(local_err); 1683 return H_HARDWARE; 1684 } 1685 } 1686 return H_SUCCESS; 1687 } 1688 1689 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1690 { 1691 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1692 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1693 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1694 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1695 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1696 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1697 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1698 h_int_set_os_reporting_line); 1699 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1700 h_int_get_os_reporting_line); 1701 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1702 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1703 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1704 } 1705