1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "qemu/error-report.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "monitor/monitor.h" 17 #include "hw/ppc/fdt.h" 18 #include "hw/ppc/spapr.h" 19 #include "hw/ppc/spapr_xive.h" 20 #include "hw/ppc/xive.h" 21 #include "hw/ppc/xive_regs.h" 22 23 /* 24 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 25 * use for the ESB pages and the TIMA pages 26 */ 27 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 28 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 29 30 /* 31 * The allocation of VP blocks is a complex operation in OPAL and the 32 * VP identifiers have a relation with the number of HW chips, the 33 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 34 * controller model does not have the same constraints and can use a 35 * simple mapping scheme of the CPU vcpu_id 36 * 37 * These identifiers are never returned to the OS. 38 */ 39 40 #define SPAPR_XIVE_NVT_BASE 0x400 41 42 /* 43 * The sPAPR machine has a unique XIVE IC device. Assign a fixed value 44 * to the controller block id value. It can nevertheless be changed 45 * for testing purpose. 46 */ 47 #define SPAPR_XIVE_BLOCK_ID 0x0 48 49 /* 50 * sPAPR NVT and END indexing helpers 51 */ 52 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 53 { 54 return nvt_idx - SPAPR_XIVE_NVT_BASE; 55 } 56 57 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 58 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 59 { 60 assert(cpu); 61 62 if (out_nvt_blk) { 63 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 64 } 65 66 if (out_nvt_blk) { 67 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 68 } 69 } 70 71 static int spapr_xive_target_to_nvt(uint32_t target, 72 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 73 { 74 PowerPCCPU *cpu = spapr_find_cpu(target); 75 76 if (!cpu) { 77 return -1; 78 } 79 80 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 81 return 0; 82 } 83 84 /* 85 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 86 * priorities per CPU 87 */ 88 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 89 uint8_t *out_end_blk, uint32_t *out_end_idx) 90 { 91 assert(cpu); 92 93 if (out_end_blk) { 94 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 95 } 96 97 if (out_end_idx) { 98 *out_end_idx = (cpu->vcpu_id << 3) + prio; 99 } 100 } 101 102 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 PowerPCCPU *cpu = spapr_find_cpu(target); 106 107 if (!cpu) { 108 return -1; 109 } 110 111 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 112 return 0; 113 } 114 115 /* 116 * On sPAPR machines, use a simplified output for the XIVE END 117 * structure dumping only the information related to the OS EQ. 118 */ 119 static void spapr_xive_end_pic_print_info(sPAPRXive *xive, XiveEND *end, 120 Monitor *mon) 121 { 122 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 123 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 124 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 125 uint32_t qentries = 1 << (qsize + 10); 126 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 127 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 128 129 monitor_printf(mon, "%3d/%d % 6d/%5d ^%d", 130 spapr_xive_nvt_to_target(0, nvt), 131 priority, qindex, qentries, qgen); 132 133 xive_end_queue_pic_print_info(end, 6, mon); 134 monitor_printf(mon, "]"); 135 } 136 137 void spapr_xive_pic_print_info(sPAPRXive *xive, Monitor *mon) 138 { 139 XiveSource *xsrc = &xive->source; 140 int i; 141 142 monitor_printf(mon, " LSIN PQ EISN CPU/PRIO EQ\n"); 143 144 for (i = 0; i < xive->nr_irqs; i++) { 145 uint8_t pq = xive_source_esb_get(xsrc, i); 146 XiveEAS *eas = &xive->eat[i]; 147 148 if (!xive_eas_is_valid(eas)) { 149 continue; 150 } 151 152 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 153 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 154 pq & XIVE_ESB_VAL_P ? 'P' : '-', 155 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 156 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 157 xive_eas_is_masked(eas) ? "M" : " ", 158 (int) xive_get_field64(EAS_END_DATA, eas->w)); 159 160 if (!xive_eas_is_masked(eas)) { 161 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 162 XiveEND *end; 163 164 assert(end_idx < xive->nr_ends); 165 end = &xive->endt[end_idx]; 166 167 if (xive_end_is_valid(end)) { 168 spapr_xive_end_pic_print_info(xive, end, mon); 169 } 170 } 171 monitor_printf(mon, "\n"); 172 } 173 } 174 175 static void spapr_xive_map_mmio(sPAPRXive *xive) 176 { 177 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 178 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 179 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 180 } 181 182 /* 183 * When a Virtual Processor is scheduled to run on a HW thread, the 184 * hypervisor pushes its identifier in the OS CAM line. Emulate the 185 * same behavior under QEMU. 186 */ 187 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 188 { 189 uint8_t nvt_blk; 190 uint32_t nvt_idx; 191 uint32_t nvt_cam; 192 193 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 194 195 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 196 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 197 } 198 199 static void spapr_xive_end_reset(XiveEND *end) 200 { 201 memset(end, 0, sizeof(*end)); 202 203 /* switch off the escalation and notification ESBs */ 204 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 205 } 206 207 static void spapr_xive_reset(void *dev) 208 { 209 sPAPRXive *xive = SPAPR_XIVE(dev); 210 int i; 211 212 /* 213 * The XiveSource has its own reset handler, which mask off all 214 * IRQs (!P|Q) 215 */ 216 217 /* Mask all valid EASs in the IRQ number space. */ 218 for (i = 0; i < xive->nr_irqs; i++) { 219 XiveEAS *eas = &xive->eat[i]; 220 if (xive_eas_is_valid(eas)) { 221 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 222 } else { 223 eas->w = 0; 224 } 225 } 226 227 /* Clear all ENDs */ 228 for (i = 0; i < xive->nr_ends; i++) { 229 spapr_xive_end_reset(&xive->endt[i]); 230 } 231 } 232 233 static void spapr_xive_instance_init(Object *obj) 234 { 235 sPAPRXive *xive = SPAPR_XIVE(obj); 236 237 object_initialize(&xive->source, sizeof(xive->source), TYPE_XIVE_SOURCE); 238 object_property_add_child(obj, "source", OBJECT(&xive->source), NULL); 239 240 object_initialize(&xive->end_source, sizeof(xive->end_source), 241 TYPE_XIVE_END_SOURCE); 242 object_property_add_child(obj, "end_source", OBJECT(&xive->end_source), 243 NULL); 244 } 245 246 static void spapr_xive_realize(DeviceState *dev, Error **errp) 247 { 248 sPAPRXive *xive = SPAPR_XIVE(dev); 249 XiveSource *xsrc = &xive->source; 250 XiveENDSource *end_xsrc = &xive->end_source; 251 Error *local_err = NULL; 252 253 if (!xive->nr_irqs) { 254 error_setg(errp, "Number of interrupt needs to be greater 0"); 255 return; 256 } 257 258 if (!xive->nr_ends) { 259 error_setg(errp, "Number of interrupt needs to be greater 0"); 260 return; 261 } 262 263 /* 264 * Initialize the internal sources, for IPIs and virtual devices. 265 */ 266 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 267 &error_fatal); 268 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 269 &error_fatal); 270 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 271 if (local_err) { 272 error_propagate(errp, local_err); 273 return; 274 } 275 276 /* 277 * Initialize the END ESB source 278 */ 279 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 280 &error_fatal); 281 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 282 &error_fatal); 283 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 284 if (local_err) { 285 error_propagate(errp, local_err); 286 return; 287 } 288 289 /* Set the mapping address of the END ESB pages after the source ESBs */ 290 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 291 292 /* 293 * Allocate the routing tables 294 */ 295 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 296 xive->endt = g_new0(XiveEND, xive->nr_ends); 297 298 /* TIMA initialization */ 299 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 300 "xive.tima", 4ull << TM_SHIFT); 301 302 /* Define all XIVE MMIO regions on SysBus */ 303 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 304 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 305 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 306 307 /* Map all regions */ 308 spapr_xive_map_mmio(xive); 309 310 qemu_register_reset(spapr_xive_reset, dev); 311 } 312 313 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 314 uint32_t eas_idx, XiveEAS *eas) 315 { 316 sPAPRXive *xive = SPAPR_XIVE(xrtr); 317 318 if (eas_idx >= xive->nr_irqs) { 319 return -1; 320 } 321 322 *eas = xive->eat[eas_idx]; 323 return 0; 324 } 325 326 static int spapr_xive_get_end(XiveRouter *xrtr, 327 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 328 { 329 sPAPRXive *xive = SPAPR_XIVE(xrtr); 330 331 if (end_idx >= xive->nr_ends) { 332 return -1; 333 } 334 335 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 336 return 0; 337 } 338 339 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 340 uint32_t end_idx, XiveEND *end, 341 uint8_t word_number) 342 { 343 sPAPRXive *xive = SPAPR_XIVE(xrtr); 344 345 if (end_idx >= xive->nr_ends) { 346 return -1; 347 } 348 349 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 350 return 0; 351 } 352 353 static int spapr_xive_get_nvt(XiveRouter *xrtr, 354 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 355 { 356 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 357 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 358 359 if (!cpu) { 360 /* TODO: should we assert() if we can find a NVT ? */ 361 return -1; 362 } 363 364 /* 365 * sPAPR does not maintain a NVT table. Return that the NVT is 366 * valid if we have found a matching CPU 367 */ 368 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 369 return 0; 370 } 371 372 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 373 uint32_t nvt_idx, XiveNVT *nvt, 374 uint8_t word_number) 375 { 376 /* 377 * We don't need to write back to the NVTs because the sPAPR 378 * machine should never hit a non-scheduled NVT. It should never 379 * get called. 380 */ 381 g_assert_not_reached(); 382 } 383 384 static const VMStateDescription vmstate_spapr_xive_end = { 385 .name = TYPE_SPAPR_XIVE "/end", 386 .version_id = 1, 387 .minimum_version_id = 1, 388 .fields = (VMStateField []) { 389 VMSTATE_UINT32(w0, XiveEND), 390 VMSTATE_UINT32(w1, XiveEND), 391 VMSTATE_UINT32(w2, XiveEND), 392 VMSTATE_UINT32(w3, XiveEND), 393 VMSTATE_UINT32(w4, XiveEND), 394 VMSTATE_UINT32(w5, XiveEND), 395 VMSTATE_UINT32(w6, XiveEND), 396 VMSTATE_UINT32(w7, XiveEND), 397 VMSTATE_END_OF_LIST() 398 }, 399 }; 400 401 static const VMStateDescription vmstate_spapr_xive_eas = { 402 .name = TYPE_SPAPR_XIVE "/eas", 403 .version_id = 1, 404 .minimum_version_id = 1, 405 .fields = (VMStateField []) { 406 VMSTATE_UINT64(w, XiveEAS), 407 VMSTATE_END_OF_LIST() 408 }, 409 }; 410 411 static const VMStateDescription vmstate_spapr_xive = { 412 .name = TYPE_SPAPR_XIVE, 413 .version_id = 1, 414 .minimum_version_id = 1, 415 .fields = (VMStateField[]) { 416 VMSTATE_UINT32_EQUAL(nr_irqs, sPAPRXive, NULL), 417 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, sPAPRXive, nr_irqs, 418 vmstate_spapr_xive_eas, XiveEAS), 419 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, sPAPRXive, nr_ends, 420 vmstate_spapr_xive_end, XiveEND), 421 VMSTATE_END_OF_LIST() 422 }, 423 }; 424 425 static Property spapr_xive_properties[] = { 426 DEFINE_PROP_UINT32("nr-irqs", sPAPRXive, nr_irqs, 0), 427 DEFINE_PROP_UINT32("nr-ends", sPAPRXive, nr_ends, 0), 428 DEFINE_PROP_UINT64("vc-base", sPAPRXive, vc_base, SPAPR_XIVE_VC_BASE), 429 DEFINE_PROP_UINT64("tm-base", sPAPRXive, tm_base, SPAPR_XIVE_TM_BASE), 430 DEFINE_PROP_END_OF_LIST(), 431 }; 432 433 static void spapr_xive_class_init(ObjectClass *klass, void *data) 434 { 435 DeviceClass *dc = DEVICE_CLASS(klass); 436 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 437 438 dc->desc = "sPAPR XIVE Interrupt Controller"; 439 dc->props = spapr_xive_properties; 440 dc->realize = spapr_xive_realize; 441 dc->vmsd = &vmstate_spapr_xive; 442 443 xrc->get_eas = spapr_xive_get_eas; 444 xrc->get_end = spapr_xive_get_end; 445 xrc->write_end = spapr_xive_write_end; 446 xrc->get_nvt = spapr_xive_get_nvt; 447 xrc->write_nvt = spapr_xive_write_nvt; 448 } 449 450 static const TypeInfo spapr_xive_info = { 451 .name = TYPE_SPAPR_XIVE, 452 .parent = TYPE_XIVE_ROUTER, 453 .instance_init = spapr_xive_instance_init, 454 .instance_size = sizeof(sPAPRXive), 455 .class_init = spapr_xive_class_init, 456 }; 457 458 static void spapr_xive_register_types(void) 459 { 460 type_register_static(&spapr_xive_info); 461 } 462 463 type_init(spapr_xive_register_types) 464 465 bool spapr_xive_irq_claim(sPAPRXive *xive, uint32_t lisn, bool lsi) 466 { 467 XiveSource *xsrc = &xive->source; 468 469 if (lisn >= xive->nr_irqs) { 470 return false; 471 } 472 473 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID); 474 xive_source_irq_set(xsrc, lisn, lsi); 475 return true; 476 } 477 478 bool spapr_xive_irq_free(sPAPRXive *xive, uint32_t lisn) 479 { 480 XiveSource *xsrc = &xive->source; 481 482 if (lisn >= xive->nr_irqs) { 483 return false; 484 } 485 486 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 487 xive_source_irq_set(xsrc, lisn, false); 488 return true; 489 } 490 491 qemu_irq spapr_xive_qirq(sPAPRXive *xive, uint32_t lisn) 492 { 493 XiveSource *xsrc = &xive->source; 494 495 if (lisn >= xive->nr_irqs) { 496 return NULL; 497 } 498 499 /* The sPAPR machine/device should have claimed the IRQ before */ 500 assert(xive_eas_is_valid(&xive->eat[lisn])); 501 502 return xive_source_qirq(xsrc, lisn); 503 } 504 505 /* 506 * XIVE hcalls 507 * 508 * The terminology used by the XIVE hcalls is the following : 509 * 510 * TARGET vCPU number 511 * EQ Event Queue assigned by OS to receive event data 512 * ESB page for source interrupt management 513 * LISN Logical Interrupt Source Number identifying a source in the 514 * machine 515 * EISN Effective Interrupt Source Number used by guest OS to 516 * identify source in the guest 517 * 518 * The EAS, END, NVT structures are not exposed. 519 */ 520 521 /* 522 * Linux hosts under OPAL reserve priority 7 for their own escalation 523 * interrupts (DD2.X POWER9). So we only allow the guest to use 524 * priorities [0..6]. 525 */ 526 static bool spapr_xive_priority_is_reserved(uint8_t priority) 527 { 528 switch (priority) { 529 case 0 ... 6: 530 return false; 531 case 7: /* OPAL escalation queue */ 532 default: 533 return true; 534 } 535 } 536 537 /* 538 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 539 * real address of the MMIO page through which the Event State Buffer 540 * entry associated with the value of the "lisn" parameter is managed. 541 * 542 * Parameters: 543 * Input 544 * - R4: "flags" 545 * Bits 0-63 reserved 546 * - R5: "lisn" is per "interrupts", "interrupt-map", or 547 * "ibm,xive-lisn-ranges" properties, or as returned by the 548 * ibm,query-interrupt-source-number RTAS call, or as returned 549 * by the H_ALLOCATE_VAS_WINDOW hcall 550 * 551 * Output 552 * - R4: "flags" 553 * Bits 0-59: Reserved 554 * Bit 60: H_INT_ESB must be used for Event State Buffer 555 * management 556 * Bit 61: 1 == LSI 0 == MSI 557 * Bit 62: the full function page supports trigger 558 * Bit 63: Store EOI Supported 559 * - R5: Logical Real address of full function Event State Buffer 560 * management page, -1 if H_INT_ESB hcall flag is set to 1. 561 * - R6: Logical Real Address of trigger only Event State Buffer 562 * management page or -1. 563 * - R7: Power of 2 page size for the ESB management pages returned in 564 * R5 and R6. 565 */ 566 567 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 568 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 569 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 570 on same page */ 571 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 572 573 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 574 sPAPRMachineState *spapr, 575 target_ulong opcode, 576 target_ulong *args) 577 { 578 sPAPRXive *xive = spapr->xive; 579 XiveSource *xsrc = &xive->source; 580 target_ulong flags = args[0]; 581 target_ulong lisn = args[1]; 582 583 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 584 return H_FUNCTION; 585 } 586 587 if (flags) { 588 return H_PARAMETER; 589 } 590 591 if (lisn >= xive->nr_irqs) { 592 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 593 lisn); 594 return H_P2; 595 } 596 597 if (!xive_eas_is_valid(&xive->eat[lisn])) { 598 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 599 lisn); 600 return H_P2; 601 } 602 603 /* 604 * All sources are emulated under the main XIVE object and share 605 * the same characteristics. 606 */ 607 args[0] = 0; 608 if (!xive_source_esb_has_2page(xsrc)) { 609 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 610 } 611 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 612 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 613 } 614 615 /* 616 * Force the use of the H_INT_ESB hcall in case of an LSI 617 * interrupt. This is necessary under KVM to re-trigger the 618 * interrupt if the level is still asserted 619 */ 620 if (xive_source_irq_is_lsi(xsrc, lisn)) { 621 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 622 } 623 624 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 625 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 626 } else { 627 args[1] = -1; 628 } 629 630 if (xive_source_esb_has_2page(xsrc) && 631 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 632 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 633 } else { 634 args[2] = -1; 635 } 636 637 if (xive_source_esb_has_2page(xsrc)) { 638 args[3] = xsrc->esb_shift - 1; 639 } else { 640 args[3] = xsrc->esb_shift; 641 } 642 643 return H_SUCCESS; 644 } 645 646 /* 647 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 648 * Interrupt Source to a target. The Logical Interrupt Source is 649 * designated with the "lisn" parameter and the target is designated 650 * with the "target" and "priority" parameters. Upon return from the 651 * hcall(), no additional interrupts will be directed to the old EQ. 652 * 653 * Parameters: 654 * Input: 655 * - R4: "flags" 656 * Bits 0-61: Reserved 657 * Bit 62: set the "eisn" in the EAS 658 * Bit 63: masks the interrupt source in the hardware interrupt 659 * control structure. An interrupt masked by this mechanism will 660 * be dropped, but it's source state bits will still be 661 * set. There is no race-free way of unmasking and restoring the 662 * source. Thus this should only be used in interrupts that are 663 * also masked at the source, and only in cases where the 664 * interrupt is not meant to be used for a large amount of time 665 * because no valid target exists for it for example 666 * - R5: "lisn" is per "interrupts", "interrupt-map", or 667 * "ibm,xive-lisn-ranges" properties, or as returned by the 668 * ibm,query-interrupt-source-number RTAS call, or as returned by 669 * the H_ALLOCATE_VAS_WINDOW hcall 670 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 671 * "ibm,ppc-interrupt-gserver#s" 672 * - R7: "priority" is a valid priority not in 673 * "ibm,plat-res-int-priorities" 674 * - R8: "eisn" is the guest EISN associated with the "lisn" 675 * 676 * Output: 677 * - None 678 */ 679 680 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 681 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 682 683 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 684 sPAPRMachineState *spapr, 685 target_ulong opcode, 686 target_ulong *args) 687 { 688 sPAPRXive *xive = spapr->xive; 689 XiveEAS eas, new_eas; 690 target_ulong flags = args[0]; 691 target_ulong lisn = args[1]; 692 target_ulong target = args[2]; 693 target_ulong priority = args[3]; 694 target_ulong eisn = args[4]; 695 uint8_t end_blk; 696 uint32_t end_idx; 697 698 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 699 return H_FUNCTION; 700 } 701 702 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 703 return H_PARAMETER; 704 } 705 706 if (lisn >= xive->nr_irqs) { 707 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 708 lisn); 709 return H_P2; 710 } 711 712 eas = xive->eat[lisn]; 713 if (!xive_eas_is_valid(&eas)) { 714 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 715 lisn); 716 return H_P2; 717 } 718 719 /* priority 0xff is used to reset the EAS */ 720 if (priority == 0xff) { 721 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 722 goto out; 723 } 724 725 if (flags & SPAPR_XIVE_SRC_MASK) { 726 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 727 } else { 728 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 729 } 730 731 if (spapr_xive_priority_is_reserved(priority)) { 732 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 733 " is reserved\n", priority); 734 return H_P4; 735 } 736 737 /* 738 * Validate that "target" is part of the list of threads allocated 739 * to the partition. For that, find the END corresponding to the 740 * target. 741 */ 742 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 743 return H_P3; 744 } 745 746 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 747 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 748 749 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 750 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 751 } 752 753 out: 754 xive->eat[lisn] = new_eas; 755 return H_SUCCESS; 756 } 757 758 /* 759 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 760 * target/priority pair is assigned to the specified Logical Interrupt 761 * Source. 762 * 763 * Parameters: 764 * Input: 765 * - R4: "flags" 766 * Bits 0-63 Reserved 767 * - R5: "lisn" is per "interrupts", "interrupt-map", or 768 * "ibm,xive-lisn-ranges" properties, or as returned by the 769 * ibm,query-interrupt-source-number RTAS call, or as 770 * returned by the H_ALLOCATE_VAS_WINDOW hcall 771 * 772 * Output: 773 * - R4: Target to which the specified Logical Interrupt Source is 774 * assigned 775 * - R5: Priority to which the specified Logical Interrupt Source is 776 * assigned 777 * - R6: EISN for the specified Logical Interrupt Source (this will be 778 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 779 */ 780 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 781 sPAPRMachineState *spapr, 782 target_ulong opcode, 783 target_ulong *args) 784 { 785 sPAPRXive *xive = spapr->xive; 786 target_ulong flags = args[0]; 787 target_ulong lisn = args[1]; 788 XiveEAS eas; 789 XiveEND *end; 790 uint8_t nvt_blk; 791 uint32_t end_idx, nvt_idx; 792 793 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 794 return H_FUNCTION; 795 } 796 797 if (flags) { 798 return H_PARAMETER; 799 } 800 801 if (lisn >= xive->nr_irqs) { 802 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 803 lisn); 804 return H_P2; 805 } 806 807 eas = xive->eat[lisn]; 808 if (!xive_eas_is_valid(&eas)) { 809 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 810 lisn); 811 return H_P2; 812 } 813 814 /* EAS_END_BLOCK is unused on sPAPR */ 815 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 816 817 assert(end_idx < xive->nr_ends); 818 end = &xive->endt[end_idx]; 819 820 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 821 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 822 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 823 824 if (xive_eas_is_masked(&eas)) { 825 args[1] = 0xff; 826 } else { 827 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 828 } 829 830 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 831 832 return H_SUCCESS; 833 } 834 835 /* 836 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 837 * address of the notification management page associated with the 838 * specified target and priority. 839 * 840 * Parameters: 841 * Input: 842 * - R4: "flags" 843 * Bits 0-63 Reserved 844 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 845 * "ibm,ppc-interrupt-gserver#s" 846 * - R6: "priority" is a valid priority not in 847 * "ibm,plat-res-int-priorities" 848 * 849 * Output: 850 * - R4: Logical real address of notification page 851 * - R5: Power of 2 page size of the notification page 852 */ 853 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 854 sPAPRMachineState *spapr, 855 target_ulong opcode, 856 target_ulong *args) 857 { 858 sPAPRXive *xive = spapr->xive; 859 XiveENDSource *end_xsrc = &xive->end_source; 860 target_ulong flags = args[0]; 861 target_ulong target = args[1]; 862 target_ulong priority = args[2]; 863 XiveEND *end; 864 uint8_t end_blk; 865 uint32_t end_idx; 866 867 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 868 return H_FUNCTION; 869 } 870 871 if (flags) { 872 return H_PARAMETER; 873 } 874 875 /* 876 * H_STATE should be returned if a H_INT_RESET is in progress. 877 * This is not needed when running the emulation under QEMU 878 */ 879 880 if (spapr_xive_priority_is_reserved(priority)) { 881 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 882 " is reserved\n", priority); 883 return H_P3; 884 } 885 886 /* 887 * Validate that "target" is part of the list of threads allocated 888 * to the partition. For that, find the END corresponding to the 889 * target. 890 */ 891 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 892 return H_P2; 893 } 894 895 assert(end_idx < xive->nr_ends); 896 end = &xive->endt[end_idx]; 897 898 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 899 if (xive_end_is_enqueue(end)) { 900 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 901 } else { 902 args[1] = 0; 903 } 904 905 return H_SUCCESS; 906 } 907 908 /* 909 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 910 * a given "target" and "priority". It is also used to set the 911 * notification config associated with the EQ. An EQ size of 0 is 912 * used to reset the EQ config for a given target and priority. If 913 * resetting the EQ config, the END associated with the given "target" 914 * and "priority" will be changed to disable queueing. 915 * 916 * Upon return from the hcall(), no additional interrupts will be 917 * directed to the old EQ (if one was set). The old EQ (if one was 918 * set) should be investigated for interrupts that occurred prior to 919 * or during the hcall(). 920 * 921 * Parameters: 922 * Input: 923 * - R4: "flags" 924 * Bits 0-62: Reserved 925 * Bit 63: Unconditional Notify (n) per the XIVE spec 926 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 927 * "ibm,ppc-interrupt-gserver#s" 928 * - R6: "priority" is a valid priority not in 929 * "ibm,plat-res-int-priorities" 930 * - R7: "eventQueue": The logical real address of the start of the EQ 931 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 932 * 933 * Output: 934 * - None 935 */ 936 937 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 938 939 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 940 sPAPRMachineState *spapr, 941 target_ulong opcode, 942 target_ulong *args) 943 { 944 sPAPRXive *xive = spapr->xive; 945 target_ulong flags = args[0]; 946 target_ulong target = args[1]; 947 target_ulong priority = args[2]; 948 target_ulong qpage = args[3]; 949 target_ulong qsize = args[4]; 950 XiveEND end; 951 uint8_t end_blk, nvt_blk; 952 uint32_t end_idx, nvt_idx; 953 954 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 955 return H_FUNCTION; 956 } 957 958 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 959 return H_PARAMETER; 960 } 961 962 /* 963 * H_STATE should be returned if a H_INT_RESET is in progress. 964 * This is not needed when running the emulation under QEMU 965 */ 966 967 if (spapr_xive_priority_is_reserved(priority)) { 968 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 969 " is reserved\n", priority); 970 return H_P3; 971 } 972 973 /* 974 * Validate that "target" is part of the list of threads allocated 975 * to the partition. For that, find the END corresponding to the 976 * target. 977 */ 978 979 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 980 return H_P2; 981 } 982 983 assert(end_idx < xive->nr_ends); 984 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 985 986 switch (qsize) { 987 case 12: 988 case 16: 989 case 21: 990 case 24: 991 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 992 end.w3 = cpu_to_be32(qpage & 0xffffffff); 993 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 994 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 995 break; 996 case 0: 997 /* reset queue and disable queueing */ 998 spapr_xive_end_reset(&end); 999 goto out; 1000 1001 default: 1002 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1003 qsize); 1004 return H_P5; 1005 } 1006 1007 if (qsize) { 1008 hwaddr plen = 1 << qsize; 1009 void *eq; 1010 1011 /* 1012 * Validate the guest EQ. We should also check that the queue 1013 * has been zeroed by the OS. 1014 */ 1015 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1016 MEMTXATTRS_UNSPECIFIED); 1017 if (plen != 1 << qsize) { 1018 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1019 HWADDR_PRIx "\n", qpage); 1020 return H_P4; 1021 } 1022 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1023 } 1024 1025 /* "target" should have been validated above */ 1026 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1027 g_assert_not_reached(); 1028 } 1029 1030 /* 1031 * Ensure the priority and target are correctly set (they will not 1032 * be right after allocation) 1033 */ 1034 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1035 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1036 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1037 1038 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1039 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1040 } else { 1041 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1042 } 1043 1044 /* 1045 * The generation bit for the END starts at 1 and The END page 1046 * offset counter starts at 0. 1047 */ 1048 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1049 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1050 end.w0 |= cpu_to_be32(END_W0_VALID); 1051 1052 /* 1053 * TODO: issue syncs required to ensure all in-flight interrupts 1054 * are complete on the old END 1055 */ 1056 1057 out: 1058 /* Update END */ 1059 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1060 return H_SUCCESS; 1061 } 1062 1063 /* 1064 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1065 * target and priority. 1066 * 1067 * Parameters: 1068 * Input: 1069 * - R4: "flags" 1070 * Bits 0-62: Reserved 1071 * Bit 63: Debug: Return debug data 1072 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1073 * "ibm,ppc-interrupt-gserver#s" 1074 * - R6: "priority" is a valid priority not in 1075 * "ibm,plat-res-int-priorities" 1076 * 1077 * Output: 1078 * - R4: "flags": 1079 * Bits 0-61: Reserved 1080 * Bit 62: The value of Event Queue Generation Number (g) per 1081 * the XIVE spec if "Debug" = 1 1082 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1083 * - R5: The logical real address of the start of the EQ 1084 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1085 * - R7: The value of Event Queue Offset Counter per XIVE spec 1086 * if "Debug" = 1, else 0 1087 * 1088 */ 1089 1090 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1091 1092 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1093 sPAPRMachineState *spapr, 1094 target_ulong opcode, 1095 target_ulong *args) 1096 { 1097 sPAPRXive *xive = spapr->xive; 1098 target_ulong flags = args[0]; 1099 target_ulong target = args[1]; 1100 target_ulong priority = args[2]; 1101 XiveEND *end; 1102 uint8_t end_blk; 1103 uint32_t end_idx; 1104 1105 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1106 return H_FUNCTION; 1107 } 1108 1109 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1110 return H_PARAMETER; 1111 } 1112 1113 /* 1114 * H_STATE should be returned if a H_INT_RESET is in progress. 1115 * This is not needed when running the emulation under QEMU 1116 */ 1117 1118 if (spapr_xive_priority_is_reserved(priority)) { 1119 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1120 " is reserved\n", priority); 1121 return H_P3; 1122 } 1123 1124 /* 1125 * Validate that "target" is part of the list of threads allocated 1126 * to the partition. For that, find the END corresponding to the 1127 * target. 1128 */ 1129 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1130 return H_P2; 1131 } 1132 1133 assert(end_idx < xive->nr_ends); 1134 end = &xive->endt[end_idx]; 1135 1136 args[0] = 0; 1137 if (xive_end_is_notify(end)) { 1138 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1139 } 1140 1141 if (xive_end_is_enqueue(end)) { 1142 args[1] = (uint64_t) be32_to_cpu(end->w2 & 0x0fffffff) << 32 1143 | be32_to_cpu(end->w3); 1144 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1145 } else { 1146 args[1] = 0; 1147 args[2] = 0; 1148 } 1149 1150 /* TODO: do we need any locking on the END ? */ 1151 if (flags & SPAPR_XIVE_END_DEBUG) { 1152 /* Load the event queue generation number into the return flags */ 1153 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1154 1155 /* Load R7 with the event queue offset counter */ 1156 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1157 } else { 1158 args[3] = 0; 1159 } 1160 1161 return H_SUCCESS; 1162 } 1163 1164 /* 1165 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1166 * reporting cache line pair for the calling thread. The reporting 1167 * cache lines will contain the OS interrupt context when the OS 1168 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1169 * interrupt. The reporting cache lines can be reset by inputting -1 1170 * in "reportingLine". Issuing the CI store byte without reporting 1171 * cache lines registered will result in the data not being accessible 1172 * to the OS. 1173 * 1174 * Parameters: 1175 * Input: 1176 * - R4: "flags" 1177 * Bits 0-63: Reserved 1178 * - R5: "reportingLine": The logical real address of the reporting cache 1179 * line pair 1180 * 1181 * Output: 1182 * - None 1183 */ 1184 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1185 sPAPRMachineState *spapr, 1186 target_ulong opcode, 1187 target_ulong *args) 1188 { 1189 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1190 return H_FUNCTION; 1191 } 1192 1193 /* 1194 * H_STATE should be returned if a H_INT_RESET is in progress. 1195 * This is not needed when running the emulation under QEMU 1196 */ 1197 1198 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1199 return H_FUNCTION; 1200 } 1201 1202 /* 1203 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1204 * real address of the reporting cache line pair set for the input 1205 * "target". If no reporting cache line pair has been set, -1 is 1206 * returned. 1207 * 1208 * Parameters: 1209 * Input: 1210 * - R4: "flags" 1211 * Bits 0-63: Reserved 1212 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1213 * "ibm,ppc-interrupt-gserver#s" 1214 * - R6: "reportingLine": The logical real address of the reporting 1215 * cache line pair 1216 * 1217 * Output: 1218 * - R4: The logical real address of the reporting line if set, else -1 1219 */ 1220 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1221 sPAPRMachineState *spapr, 1222 target_ulong opcode, 1223 target_ulong *args) 1224 { 1225 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1226 return H_FUNCTION; 1227 } 1228 1229 /* 1230 * H_STATE should be returned if a H_INT_RESET is in progress. 1231 * This is not needed when running the emulation under QEMU 1232 */ 1233 1234 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1235 return H_FUNCTION; 1236 } 1237 1238 /* 1239 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1240 * page for the input "lisn". This hcall is only supported for LISNs 1241 * that have the ESB hcall flag set to 1 when returned from hcall() 1242 * H_INT_GET_SOURCE_INFO. 1243 * 1244 * Parameters: 1245 * Input: 1246 * - R4: "flags" 1247 * Bits 0-62: Reserved 1248 * bit 63: Store: Store=1, store operation, else load operation 1249 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1250 * "ibm,xive-lisn-ranges" properties, or as returned by the 1251 * ibm,query-interrupt-source-number RTAS call, or as 1252 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1253 * - R6: "esbOffset" is the offset into the ESB page for the load or 1254 * store operation 1255 * - R7: "storeData" is the data to write for a store operation 1256 * 1257 * Output: 1258 * - R4: The value of the load if load operation, else -1 1259 */ 1260 1261 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1262 1263 static target_ulong h_int_esb(PowerPCCPU *cpu, 1264 sPAPRMachineState *spapr, 1265 target_ulong opcode, 1266 target_ulong *args) 1267 { 1268 sPAPRXive *xive = spapr->xive; 1269 XiveEAS eas; 1270 target_ulong flags = args[0]; 1271 target_ulong lisn = args[1]; 1272 target_ulong offset = args[2]; 1273 target_ulong data = args[3]; 1274 hwaddr mmio_addr; 1275 XiveSource *xsrc = &xive->source; 1276 1277 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1278 return H_FUNCTION; 1279 } 1280 1281 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1282 return H_PARAMETER; 1283 } 1284 1285 if (lisn >= xive->nr_irqs) { 1286 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1287 lisn); 1288 return H_P2; 1289 } 1290 1291 eas = xive->eat[lisn]; 1292 if (!xive_eas_is_valid(&eas)) { 1293 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1294 lisn); 1295 return H_P2; 1296 } 1297 1298 if (offset > (1ull << xsrc->esb_shift)) { 1299 return H_P3; 1300 } 1301 1302 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1303 1304 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1305 (flags & SPAPR_XIVE_ESB_STORE))) { 1306 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1307 HWADDR_PRIx "\n", mmio_addr); 1308 return H_HARDWARE; 1309 } 1310 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1311 return H_SUCCESS; 1312 } 1313 1314 /* 1315 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1316 * ensure any in flight events for the input lisn are in the event 1317 * queue. 1318 * 1319 * Parameters: 1320 * Input: 1321 * - R4: "flags" 1322 * Bits 0-63: Reserved 1323 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1324 * "ibm,xive-lisn-ranges" properties, or as returned by the 1325 * ibm,query-interrupt-source-number RTAS call, or as 1326 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1327 * 1328 * Output: 1329 * - None 1330 */ 1331 static target_ulong h_int_sync(PowerPCCPU *cpu, 1332 sPAPRMachineState *spapr, 1333 target_ulong opcode, 1334 target_ulong *args) 1335 { 1336 sPAPRXive *xive = spapr->xive; 1337 XiveEAS eas; 1338 target_ulong flags = args[0]; 1339 target_ulong lisn = args[1]; 1340 1341 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1342 return H_FUNCTION; 1343 } 1344 1345 if (flags) { 1346 return H_PARAMETER; 1347 } 1348 1349 if (lisn >= xive->nr_irqs) { 1350 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1351 lisn); 1352 return H_P2; 1353 } 1354 1355 eas = xive->eat[lisn]; 1356 if (!xive_eas_is_valid(&eas)) { 1357 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1358 lisn); 1359 return H_P2; 1360 } 1361 1362 /* 1363 * H_STATE should be returned if a H_INT_RESET is in progress. 1364 * This is not needed when running the emulation under QEMU 1365 */ 1366 1367 /* This is not real hardware. Nothing to be done */ 1368 return H_SUCCESS; 1369 } 1370 1371 /* 1372 * The H_INT_RESET hcall() is used to reset all of the partition's 1373 * interrupt exploitation structures to their initial state. This 1374 * means losing all previously set interrupt state set via 1375 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1376 * 1377 * Parameters: 1378 * Input: 1379 * - R4: "flags" 1380 * Bits 0-63: Reserved 1381 * 1382 * Output: 1383 * - None 1384 */ 1385 static target_ulong h_int_reset(PowerPCCPU *cpu, 1386 sPAPRMachineState *spapr, 1387 target_ulong opcode, 1388 target_ulong *args) 1389 { 1390 sPAPRXive *xive = spapr->xive; 1391 target_ulong flags = args[0]; 1392 1393 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1394 return H_FUNCTION; 1395 } 1396 1397 if (flags) { 1398 return H_PARAMETER; 1399 } 1400 1401 device_reset(DEVICE(xive)); 1402 return H_SUCCESS; 1403 } 1404 1405 void spapr_xive_hcall_init(sPAPRMachineState *spapr) 1406 { 1407 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1408 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1409 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1410 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1411 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1412 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1413 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1414 h_int_set_os_reporting_line); 1415 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1416 h_int_get_os_reporting_line); 1417 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1418 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1419 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1420 } 1421 1422 void spapr_dt_xive(sPAPRMachineState *spapr, uint32_t nr_servers, void *fdt, 1423 uint32_t phandle) 1424 { 1425 sPAPRXive *xive = spapr->xive; 1426 int node; 1427 uint64_t timas[2 * 2]; 1428 /* Interrupt number ranges for the IPIs */ 1429 uint32_t lisn_ranges[] = { 1430 cpu_to_be32(0), 1431 cpu_to_be32(nr_servers), 1432 }; 1433 /* 1434 * EQ size - the sizes of pages supported by the system 4K, 64K, 1435 * 2M, 16M. We only advertise 64K for the moment. 1436 */ 1437 uint32_t eq_sizes[] = { 1438 cpu_to_be32(16), /* 64K */ 1439 }; 1440 /* 1441 * The following array is in sync with the reserved priorities 1442 * defined by the 'spapr_xive_priority_is_reserved' routine. 1443 */ 1444 uint32_t plat_res_int_priorities[] = { 1445 cpu_to_be32(7), /* start */ 1446 cpu_to_be32(0xf8), /* count */ 1447 }; 1448 gchar *nodename; 1449 1450 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 1451 timas[0] = cpu_to_be64(xive->tm_base + 1452 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 1453 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 1454 timas[2] = cpu_to_be64(xive->tm_base + 1455 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 1456 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 1457 1458 nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 1459 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 1460 _FDT(node = fdt_add_subnode(fdt, 0, nodename)); 1461 g_free(nodename); 1462 1463 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 1464 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 1465 1466 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 1467 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 1468 sizeof(eq_sizes))); 1469 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 1470 sizeof(lisn_ranges))); 1471 1472 /* For Linux to link the LSIs to the interrupt controller. */ 1473 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 1474 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 1475 1476 /* For SLOF */ 1477 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 1478 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 1479 1480 /* 1481 * The "ibm,plat-res-int-priorities" property defines the priority 1482 * ranges reserved by the hypervisor 1483 */ 1484 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 1485 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 1486 } 1487