1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "qemu/error-report.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "monitor/monitor.h" 17 #include "hw/ppc/fdt.h" 18 #include "hw/ppc/spapr.h" 19 #include "hw/ppc/spapr_xive.h" 20 #include "hw/ppc/xive.h" 21 #include "hw/ppc/xive_regs.h" 22 23 /* 24 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 25 * use for the ESB pages and the TIMA pages 26 */ 27 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 28 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 29 30 /* 31 * The allocation of VP blocks is a complex operation in OPAL and the 32 * VP identifiers have a relation with the number of HW chips, the 33 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 34 * controller model does not have the same constraints and can use a 35 * simple mapping scheme of the CPU vcpu_id 36 * 37 * These identifiers are never returned to the OS. 38 */ 39 40 #define SPAPR_XIVE_NVT_BASE 0x400 41 42 /* 43 * The sPAPR machine has a unique XIVE IC device. Assign a fixed value 44 * to the controller block id value. It can nevertheless be changed 45 * for testing purpose. 46 */ 47 #define SPAPR_XIVE_BLOCK_ID 0x0 48 49 /* 50 * sPAPR NVT and END indexing helpers 51 */ 52 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 53 { 54 return nvt_idx - SPAPR_XIVE_NVT_BASE; 55 } 56 57 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 58 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 59 { 60 assert(cpu); 61 62 if (out_nvt_blk) { 63 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 64 } 65 66 if (out_nvt_blk) { 67 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 68 } 69 } 70 71 static int spapr_xive_target_to_nvt(uint32_t target, 72 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 73 { 74 PowerPCCPU *cpu = spapr_find_cpu(target); 75 76 if (!cpu) { 77 return -1; 78 } 79 80 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 81 return 0; 82 } 83 84 /* 85 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 86 * priorities per CPU 87 */ 88 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 89 uint8_t *out_end_blk, uint32_t *out_end_idx) 90 { 91 assert(cpu); 92 93 if (out_end_blk) { 94 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 95 } 96 97 if (out_end_idx) { 98 *out_end_idx = (cpu->vcpu_id << 3) + prio; 99 } 100 } 101 102 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 PowerPCCPU *cpu = spapr_find_cpu(target); 106 107 if (!cpu) { 108 return -1; 109 } 110 111 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 112 return 0; 113 } 114 115 /* 116 * On sPAPR machines, use a simplified output for the XIVE END 117 * structure dumping only the information related to the OS EQ. 118 */ 119 static void spapr_xive_end_pic_print_info(sPAPRXive *xive, XiveEND *end, 120 Monitor *mon) 121 { 122 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 123 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 124 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 125 uint32_t qentries = 1 << (qsize + 10); 126 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 127 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 128 129 monitor_printf(mon, "%3d/%d % 6d/%5d ^%d", 130 spapr_xive_nvt_to_target(0, nvt), 131 priority, qindex, qentries, qgen); 132 133 xive_end_queue_pic_print_info(end, 6, mon); 134 monitor_printf(mon, "]"); 135 } 136 137 void spapr_xive_pic_print_info(sPAPRXive *xive, Monitor *mon) 138 { 139 XiveSource *xsrc = &xive->source; 140 int i; 141 142 monitor_printf(mon, " LSIN PQ EISN CPU/PRIO EQ\n"); 143 144 for (i = 0; i < xive->nr_irqs; i++) { 145 uint8_t pq = xive_source_esb_get(xsrc, i); 146 XiveEAS *eas = &xive->eat[i]; 147 148 if (!xive_eas_is_valid(eas)) { 149 continue; 150 } 151 152 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 153 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 154 pq & XIVE_ESB_VAL_P ? 'P' : '-', 155 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 156 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 157 xive_eas_is_masked(eas) ? "M" : " ", 158 (int) xive_get_field64(EAS_END_DATA, eas->w)); 159 160 if (!xive_eas_is_masked(eas)) { 161 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 162 XiveEND *end; 163 164 assert(end_idx < xive->nr_ends); 165 end = &xive->endt[end_idx]; 166 167 if (xive_end_is_valid(end)) { 168 spapr_xive_end_pic_print_info(xive, end, mon); 169 } 170 } 171 monitor_printf(mon, "\n"); 172 } 173 } 174 175 static void spapr_xive_map_mmio(sPAPRXive *xive) 176 { 177 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 178 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 179 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 180 } 181 182 void spapr_xive_mmio_set_enabled(sPAPRXive *xive, bool enable) 183 { 184 memory_region_set_enabled(&xive->source.esb_mmio, enable); 185 memory_region_set_enabled(&xive->tm_mmio, enable); 186 187 /* Disable the END ESBs until a guest OS makes use of them */ 188 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 189 } 190 191 /* 192 * When a Virtual Processor is scheduled to run on a HW thread, the 193 * hypervisor pushes its identifier in the OS CAM line. Emulate the 194 * same behavior under QEMU. 195 */ 196 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 197 { 198 uint8_t nvt_blk; 199 uint32_t nvt_idx; 200 uint32_t nvt_cam; 201 202 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 203 204 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 205 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 206 } 207 208 static void spapr_xive_end_reset(XiveEND *end) 209 { 210 memset(end, 0, sizeof(*end)); 211 212 /* switch off the escalation and notification ESBs */ 213 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 214 } 215 216 static void spapr_xive_reset(void *dev) 217 { 218 sPAPRXive *xive = SPAPR_XIVE(dev); 219 int i; 220 221 /* 222 * The XiveSource has its own reset handler, which mask off all 223 * IRQs (!P|Q) 224 */ 225 226 /* Mask all valid EASs in the IRQ number space. */ 227 for (i = 0; i < xive->nr_irqs; i++) { 228 XiveEAS *eas = &xive->eat[i]; 229 if (xive_eas_is_valid(eas)) { 230 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 231 } else { 232 eas->w = 0; 233 } 234 } 235 236 /* Clear all ENDs */ 237 for (i = 0; i < xive->nr_ends; i++) { 238 spapr_xive_end_reset(&xive->endt[i]); 239 } 240 } 241 242 static void spapr_xive_instance_init(Object *obj) 243 { 244 sPAPRXive *xive = SPAPR_XIVE(obj); 245 246 object_initialize(&xive->source, sizeof(xive->source), TYPE_XIVE_SOURCE); 247 object_property_add_child(obj, "source", OBJECT(&xive->source), NULL); 248 249 object_initialize(&xive->end_source, sizeof(xive->end_source), 250 TYPE_XIVE_END_SOURCE); 251 object_property_add_child(obj, "end_source", OBJECT(&xive->end_source), 252 NULL); 253 } 254 255 static void spapr_xive_realize(DeviceState *dev, Error **errp) 256 { 257 sPAPRXive *xive = SPAPR_XIVE(dev); 258 XiveSource *xsrc = &xive->source; 259 XiveENDSource *end_xsrc = &xive->end_source; 260 Error *local_err = NULL; 261 262 if (!xive->nr_irqs) { 263 error_setg(errp, "Number of interrupt needs to be greater 0"); 264 return; 265 } 266 267 if (!xive->nr_ends) { 268 error_setg(errp, "Number of interrupt needs to be greater 0"); 269 return; 270 } 271 272 /* 273 * Initialize the internal sources, for IPIs and virtual devices. 274 */ 275 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 276 &error_fatal); 277 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 278 &error_fatal); 279 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 280 if (local_err) { 281 error_propagate(errp, local_err); 282 return; 283 } 284 285 /* 286 * Initialize the END ESB source 287 */ 288 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 289 &error_fatal); 290 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 291 &error_fatal); 292 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 293 if (local_err) { 294 error_propagate(errp, local_err); 295 return; 296 } 297 298 /* Set the mapping address of the END ESB pages after the source ESBs */ 299 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 300 301 /* 302 * Allocate the routing tables 303 */ 304 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 305 xive->endt = g_new0(XiveEND, xive->nr_ends); 306 307 /* TIMA initialization */ 308 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 309 "xive.tima", 4ull << TM_SHIFT); 310 311 /* Define all XIVE MMIO regions on SysBus */ 312 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 313 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 314 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 315 316 /* Map all regions */ 317 spapr_xive_map_mmio(xive); 318 319 qemu_register_reset(spapr_xive_reset, dev); 320 } 321 322 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 323 uint32_t eas_idx, XiveEAS *eas) 324 { 325 sPAPRXive *xive = SPAPR_XIVE(xrtr); 326 327 if (eas_idx >= xive->nr_irqs) { 328 return -1; 329 } 330 331 *eas = xive->eat[eas_idx]; 332 return 0; 333 } 334 335 static int spapr_xive_get_end(XiveRouter *xrtr, 336 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 337 { 338 sPAPRXive *xive = SPAPR_XIVE(xrtr); 339 340 if (end_idx >= xive->nr_ends) { 341 return -1; 342 } 343 344 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 345 return 0; 346 } 347 348 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 349 uint32_t end_idx, XiveEND *end, 350 uint8_t word_number) 351 { 352 sPAPRXive *xive = SPAPR_XIVE(xrtr); 353 354 if (end_idx >= xive->nr_ends) { 355 return -1; 356 } 357 358 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 359 return 0; 360 } 361 362 static int spapr_xive_get_nvt(XiveRouter *xrtr, 363 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 364 { 365 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 366 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 367 368 if (!cpu) { 369 /* TODO: should we assert() if we can find a NVT ? */ 370 return -1; 371 } 372 373 /* 374 * sPAPR does not maintain a NVT table. Return that the NVT is 375 * valid if we have found a matching CPU 376 */ 377 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 378 return 0; 379 } 380 381 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 382 uint32_t nvt_idx, XiveNVT *nvt, 383 uint8_t word_number) 384 { 385 /* 386 * We don't need to write back to the NVTs because the sPAPR 387 * machine should never hit a non-scheduled NVT. It should never 388 * get called. 389 */ 390 g_assert_not_reached(); 391 } 392 393 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 394 { 395 PowerPCCPU *cpu = POWERPC_CPU(cs); 396 397 return cpu->tctx; 398 } 399 400 static const VMStateDescription vmstate_spapr_xive_end = { 401 .name = TYPE_SPAPR_XIVE "/end", 402 .version_id = 1, 403 .minimum_version_id = 1, 404 .fields = (VMStateField []) { 405 VMSTATE_UINT32(w0, XiveEND), 406 VMSTATE_UINT32(w1, XiveEND), 407 VMSTATE_UINT32(w2, XiveEND), 408 VMSTATE_UINT32(w3, XiveEND), 409 VMSTATE_UINT32(w4, XiveEND), 410 VMSTATE_UINT32(w5, XiveEND), 411 VMSTATE_UINT32(w6, XiveEND), 412 VMSTATE_UINT32(w7, XiveEND), 413 VMSTATE_END_OF_LIST() 414 }, 415 }; 416 417 static const VMStateDescription vmstate_spapr_xive_eas = { 418 .name = TYPE_SPAPR_XIVE "/eas", 419 .version_id = 1, 420 .minimum_version_id = 1, 421 .fields = (VMStateField []) { 422 VMSTATE_UINT64(w, XiveEAS), 423 VMSTATE_END_OF_LIST() 424 }, 425 }; 426 427 static const VMStateDescription vmstate_spapr_xive = { 428 .name = TYPE_SPAPR_XIVE, 429 .version_id = 1, 430 .minimum_version_id = 1, 431 .fields = (VMStateField[]) { 432 VMSTATE_UINT32_EQUAL(nr_irqs, sPAPRXive, NULL), 433 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, sPAPRXive, nr_irqs, 434 vmstate_spapr_xive_eas, XiveEAS), 435 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, sPAPRXive, nr_ends, 436 vmstate_spapr_xive_end, XiveEND), 437 VMSTATE_END_OF_LIST() 438 }, 439 }; 440 441 static Property spapr_xive_properties[] = { 442 DEFINE_PROP_UINT32("nr-irqs", sPAPRXive, nr_irqs, 0), 443 DEFINE_PROP_UINT32("nr-ends", sPAPRXive, nr_ends, 0), 444 DEFINE_PROP_UINT64("vc-base", sPAPRXive, vc_base, SPAPR_XIVE_VC_BASE), 445 DEFINE_PROP_UINT64("tm-base", sPAPRXive, tm_base, SPAPR_XIVE_TM_BASE), 446 DEFINE_PROP_END_OF_LIST(), 447 }; 448 449 static void spapr_xive_class_init(ObjectClass *klass, void *data) 450 { 451 DeviceClass *dc = DEVICE_CLASS(klass); 452 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 453 454 dc->desc = "sPAPR XIVE Interrupt Controller"; 455 dc->props = spapr_xive_properties; 456 dc->realize = spapr_xive_realize; 457 dc->vmsd = &vmstate_spapr_xive; 458 459 xrc->get_eas = spapr_xive_get_eas; 460 xrc->get_end = spapr_xive_get_end; 461 xrc->write_end = spapr_xive_write_end; 462 xrc->get_nvt = spapr_xive_get_nvt; 463 xrc->write_nvt = spapr_xive_write_nvt; 464 xrc->get_tctx = spapr_xive_get_tctx; 465 } 466 467 static const TypeInfo spapr_xive_info = { 468 .name = TYPE_SPAPR_XIVE, 469 .parent = TYPE_XIVE_ROUTER, 470 .instance_init = spapr_xive_instance_init, 471 .instance_size = sizeof(sPAPRXive), 472 .class_init = spapr_xive_class_init, 473 }; 474 475 static void spapr_xive_register_types(void) 476 { 477 type_register_static(&spapr_xive_info); 478 } 479 480 type_init(spapr_xive_register_types) 481 482 bool spapr_xive_irq_claim(sPAPRXive *xive, uint32_t lisn, bool lsi) 483 { 484 XiveSource *xsrc = &xive->source; 485 486 if (lisn >= xive->nr_irqs) { 487 return false; 488 } 489 490 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID); 491 xive_source_irq_set(xsrc, lisn, lsi); 492 return true; 493 } 494 495 bool spapr_xive_irq_free(sPAPRXive *xive, uint32_t lisn) 496 { 497 XiveSource *xsrc = &xive->source; 498 499 if (lisn >= xive->nr_irqs) { 500 return false; 501 } 502 503 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 504 xive_source_irq_set(xsrc, lisn, false); 505 return true; 506 } 507 508 /* 509 * XIVE hcalls 510 * 511 * The terminology used by the XIVE hcalls is the following : 512 * 513 * TARGET vCPU number 514 * EQ Event Queue assigned by OS to receive event data 515 * ESB page for source interrupt management 516 * LISN Logical Interrupt Source Number identifying a source in the 517 * machine 518 * EISN Effective Interrupt Source Number used by guest OS to 519 * identify source in the guest 520 * 521 * The EAS, END, NVT structures are not exposed. 522 */ 523 524 /* 525 * Linux hosts under OPAL reserve priority 7 for their own escalation 526 * interrupts (DD2.X POWER9). So we only allow the guest to use 527 * priorities [0..6]. 528 */ 529 static bool spapr_xive_priority_is_reserved(uint8_t priority) 530 { 531 switch (priority) { 532 case 0 ... 6: 533 return false; 534 case 7: /* OPAL escalation queue */ 535 default: 536 return true; 537 } 538 } 539 540 /* 541 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 542 * real address of the MMIO page through which the Event State Buffer 543 * entry associated with the value of the "lisn" parameter is managed. 544 * 545 * Parameters: 546 * Input 547 * - R4: "flags" 548 * Bits 0-63 reserved 549 * - R5: "lisn" is per "interrupts", "interrupt-map", or 550 * "ibm,xive-lisn-ranges" properties, or as returned by the 551 * ibm,query-interrupt-source-number RTAS call, or as returned 552 * by the H_ALLOCATE_VAS_WINDOW hcall 553 * 554 * Output 555 * - R4: "flags" 556 * Bits 0-59: Reserved 557 * Bit 60: H_INT_ESB must be used for Event State Buffer 558 * management 559 * Bit 61: 1 == LSI 0 == MSI 560 * Bit 62: the full function page supports trigger 561 * Bit 63: Store EOI Supported 562 * - R5: Logical Real address of full function Event State Buffer 563 * management page, -1 if H_INT_ESB hcall flag is set to 1. 564 * - R6: Logical Real Address of trigger only Event State Buffer 565 * management page or -1. 566 * - R7: Power of 2 page size for the ESB management pages returned in 567 * R5 and R6. 568 */ 569 570 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 571 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 572 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 573 on same page */ 574 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 575 576 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 577 sPAPRMachineState *spapr, 578 target_ulong opcode, 579 target_ulong *args) 580 { 581 sPAPRXive *xive = spapr->xive; 582 XiveSource *xsrc = &xive->source; 583 target_ulong flags = args[0]; 584 target_ulong lisn = args[1]; 585 586 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 587 return H_FUNCTION; 588 } 589 590 if (flags) { 591 return H_PARAMETER; 592 } 593 594 if (lisn >= xive->nr_irqs) { 595 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 596 lisn); 597 return H_P2; 598 } 599 600 if (!xive_eas_is_valid(&xive->eat[lisn])) { 601 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 602 lisn); 603 return H_P2; 604 } 605 606 /* 607 * All sources are emulated under the main XIVE object and share 608 * the same characteristics. 609 */ 610 args[0] = 0; 611 if (!xive_source_esb_has_2page(xsrc)) { 612 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 613 } 614 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 615 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 616 } 617 618 /* 619 * Force the use of the H_INT_ESB hcall in case of an LSI 620 * interrupt. This is necessary under KVM to re-trigger the 621 * interrupt if the level is still asserted 622 */ 623 if (xive_source_irq_is_lsi(xsrc, lisn)) { 624 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 625 } 626 627 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 628 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 629 } else { 630 args[1] = -1; 631 } 632 633 if (xive_source_esb_has_2page(xsrc) && 634 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 635 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 636 } else { 637 args[2] = -1; 638 } 639 640 if (xive_source_esb_has_2page(xsrc)) { 641 args[3] = xsrc->esb_shift - 1; 642 } else { 643 args[3] = xsrc->esb_shift; 644 } 645 646 return H_SUCCESS; 647 } 648 649 /* 650 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 651 * Interrupt Source to a target. The Logical Interrupt Source is 652 * designated with the "lisn" parameter and the target is designated 653 * with the "target" and "priority" parameters. Upon return from the 654 * hcall(), no additional interrupts will be directed to the old EQ. 655 * 656 * Parameters: 657 * Input: 658 * - R4: "flags" 659 * Bits 0-61: Reserved 660 * Bit 62: set the "eisn" in the EAS 661 * Bit 63: masks the interrupt source in the hardware interrupt 662 * control structure. An interrupt masked by this mechanism will 663 * be dropped, but it's source state bits will still be 664 * set. There is no race-free way of unmasking and restoring the 665 * source. Thus this should only be used in interrupts that are 666 * also masked at the source, and only in cases where the 667 * interrupt is not meant to be used for a large amount of time 668 * because no valid target exists for it for example 669 * - R5: "lisn" is per "interrupts", "interrupt-map", or 670 * "ibm,xive-lisn-ranges" properties, or as returned by the 671 * ibm,query-interrupt-source-number RTAS call, or as returned by 672 * the H_ALLOCATE_VAS_WINDOW hcall 673 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 674 * "ibm,ppc-interrupt-gserver#s" 675 * - R7: "priority" is a valid priority not in 676 * "ibm,plat-res-int-priorities" 677 * - R8: "eisn" is the guest EISN associated with the "lisn" 678 * 679 * Output: 680 * - None 681 */ 682 683 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 684 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 685 686 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 687 sPAPRMachineState *spapr, 688 target_ulong opcode, 689 target_ulong *args) 690 { 691 sPAPRXive *xive = spapr->xive; 692 XiveEAS eas, new_eas; 693 target_ulong flags = args[0]; 694 target_ulong lisn = args[1]; 695 target_ulong target = args[2]; 696 target_ulong priority = args[3]; 697 target_ulong eisn = args[4]; 698 uint8_t end_blk; 699 uint32_t end_idx; 700 701 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 702 return H_FUNCTION; 703 } 704 705 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 706 return H_PARAMETER; 707 } 708 709 if (lisn >= xive->nr_irqs) { 710 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 711 lisn); 712 return H_P2; 713 } 714 715 eas = xive->eat[lisn]; 716 if (!xive_eas_is_valid(&eas)) { 717 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 718 lisn); 719 return H_P2; 720 } 721 722 /* priority 0xff is used to reset the EAS */ 723 if (priority == 0xff) { 724 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 725 goto out; 726 } 727 728 if (flags & SPAPR_XIVE_SRC_MASK) { 729 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 730 } else { 731 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 732 } 733 734 if (spapr_xive_priority_is_reserved(priority)) { 735 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 736 " is reserved\n", priority); 737 return H_P4; 738 } 739 740 /* 741 * Validate that "target" is part of the list of threads allocated 742 * to the partition. For that, find the END corresponding to the 743 * target. 744 */ 745 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 746 return H_P3; 747 } 748 749 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 750 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 751 752 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 753 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 754 } 755 756 out: 757 xive->eat[lisn] = new_eas; 758 return H_SUCCESS; 759 } 760 761 /* 762 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 763 * target/priority pair is assigned to the specified Logical Interrupt 764 * Source. 765 * 766 * Parameters: 767 * Input: 768 * - R4: "flags" 769 * Bits 0-63 Reserved 770 * - R5: "lisn" is per "interrupts", "interrupt-map", or 771 * "ibm,xive-lisn-ranges" properties, or as returned by the 772 * ibm,query-interrupt-source-number RTAS call, or as 773 * returned by the H_ALLOCATE_VAS_WINDOW hcall 774 * 775 * Output: 776 * - R4: Target to which the specified Logical Interrupt Source is 777 * assigned 778 * - R5: Priority to which the specified Logical Interrupt Source is 779 * assigned 780 * - R6: EISN for the specified Logical Interrupt Source (this will be 781 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 782 */ 783 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 784 sPAPRMachineState *spapr, 785 target_ulong opcode, 786 target_ulong *args) 787 { 788 sPAPRXive *xive = spapr->xive; 789 target_ulong flags = args[0]; 790 target_ulong lisn = args[1]; 791 XiveEAS eas; 792 XiveEND *end; 793 uint8_t nvt_blk; 794 uint32_t end_idx, nvt_idx; 795 796 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 797 return H_FUNCTION; 798 } 799 800 if (flags) { 801 return H_PARAMETER; 802 } 803 804 if (lisn >= xive->nr_irqs) { 805 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 806 lisn); 807 return H_P2; 808 } 809 810 eas = xive->eat[lisn]; 811 if (!xive_eas_is_valid(&eas)) { 812 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 813 lisn); 814 return H_P2; 815 } 816 817 /* EAS_END_BLOCK is unused on sPAPR */ 818 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 819 820 assert(end_idx < xive->nr_ends); 821 end = &xive->endt[end_idx]; 822 823 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 824 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 825 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 826 827 if (xive_eas_is_masked(&eas)) { 828 args[1] = 0xff; 829 } else { 830 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 831 } 832 833 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 834 835 return H_SUCCESS; 836 } 837 838 /* 839 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 840 * address of the notification management page associated with the 841 * specified target and priority. 842 * 843 * Parameters: 844 * Input: 845 * - R4: "flags" 846 * Bits 0-63 Reserved 847 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 848 * "ibm,ppc-interrupt-gserver#s" 849 * - R6: "priority" is a valid priority not in 850 * "ibm,plat-res-int-priorities" 851 * 852 * Output: 853 * - R4: Logical real address of notification page 854 * - R5: Power of 2 page size of the notification page 855 */ 856 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 857 sPAPRMachineState *spapr, 858 target_ulong opcode, 859 target_ulong *args) 860 { 861 sPAPRXive *xive = spapr->xive; 862 XiveENDSource *end_xsrc = &xive->end_source; 863 target_ulong flags = args[0]; 864 target_ulong target = args[1]; 865 target_ulong priority = args[2]; 866 XiveEND *end; 867 uint8_t end_blk; 868 uint32_t end_idx; 869 870 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 871 return H_FUNCTION; 872 } 873 874 if (flags) { 875 return H_PARAMETER; 876 } 877 878 /* 879 * H_STATE should be returned if a H_INT_RESET is in progress. 880 * This is not needed when running the emulation under QEMU 881 */ 882 883 if (spapr_xive_priority_is_reserved(priority)) { 884 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 885 " is reserved\n", priority); 886 return H_P3; 887 } 888 889 /* 890 * Validate that "target" is part of the list of threads allocated 891 * to the partition. For that, find the END corresponding to the 892 * target. 893 */ 894 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 895 return H_P2; 896 } 897 898 assert(end_idx < xive->nr_ends); 899 end = &xive->endt[end_idx]; 900 901 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 902 if (xive_end_is_enqueue(end)) { 903 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 904 } else { 905 args[1] = 0; 906 } 907 908 return H_SUCCESS; 909 } 910 911 /* 912 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 913 * a given "target" and "priority". It is also used to set the 914 * notification config associated with the EQ. An EQ size of 0 is 915 * used to reset the EQ config for a given target and priority. If 916 * resetting the EQ config, the END associated with the given "target" 917 * and "priority" will be changed to disable queueing. 918 * 919 * Upon return from the hcall(), no additional interrupts will be 920 * directed to the old EQ (if one was set). The old EQ (if one was 921 * set) should be investigated for interrupts that occurred prior to 922 * or during the hcall(). 923 * 924 * Parameters: 925 * Input: 926 * - R4: "flags" 927 * Bits 0-62: Reserved 928 * Bit 63: Unconditional Notify (n) per the XIVE spec 929 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 930 * "ibm,ppc-interrupt-gserver#s" 931 * - R6: "priority" is a valid priority not in 932 * "ibm,plat-res-int-priorities" 933 * - R7: "eventQueue": The logical real address of the start of the EQ 934 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 935 * 936 * Output: 937 * - None 938 */ 939 940 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 941 942 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 943 sPAPRMachineState *spapr, 944 target_ulong opcode, 945 target_ulong *args) 946 { 947 sPAPRXive *xive = spapr->xive; 948 target_ulong flags = args[0]; 949 target_ulong target = args[1]; 950 target_ulong priority = args[2]; 951 target_ulong qpage = args[3]; 952 target_ulong qsize = args[4]; 953 XiveEND end; 954 uint8_t end_blk, nvt_blk; 955 uint32_t end_idx, nvt_idx; 956 957 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 958 return H_FUNCTION; 959 } 960 961 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 962 return H_PARAMETER; 963 } 964 965 /* 966 * H_STATE should be returned if a H_INT_RESET is in progress. 967 * This is not needed when running the emulation under QEMU 968 */ 969 970 if (spapr_xive_priority_is_reserved(priority)) { 971 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 972 " is reserved\n", priority); 973 return H_P3; 974 } 975 976 /* 977 * Validate that "target" is part of the list of threads allocated 978 * to the partition. For that, find the END corresponding to the 979 * target. 980 */ 981 982 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 983 return H_P2; 984 } 985 986 assert(end_idx < xive->nr_ends); 987 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 988 989 switch (qsize) { 990 case 12: 991 case 16: 992 case 21: 993 case 24: 994 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 995 end.w3 = cpu_to_be32(qpage & 0xffffffff); 996 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 997 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 998 break; 999 case 0: 1000 /* reset queue and disable queueing */ 1001 spapr_xive_end_reset(&end); 1002 goto out; 1003 1004 default: 1005 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1006 qsize); 1007 return H_P5; 1008 } 1009 1010 if (qsize) { 1011 hwaddr plen = 1 << qsize; 1012 void *eq; 1013 1014 /* 1015 * Validate the guest EQ. We should also check that the queue 1016 * has been zeroed by the OS. 1017 */ 1018 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1019 MEMTXATTRS_UNSPECIFIED); 1020 if (plen != 1 << qsize) { 1021 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1022 HWADDR_PRIx "\n", qpage); 1023 return H_P4; 1024 } 1025 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1026 } 1027 1028 /* "target" should have been validated above */ 1029 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1030 g_assert_not_reached(); 1031 } 1032 1033 /* 1034 * Ensure the priority and target are correctly set (they will not 1035 * be right after allocation) 1036 */ 1037 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1038 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1039 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1040 1041 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1042 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1043 } else { 1044 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1045 } 1046 1047 /* 1048 * The generation bit for the END starts at 1 and The END page 1049 * offset counter starts at 0. 1050 */ 1051 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1052 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1053 end.w0 |= cpu_to_be32(END_W0_VALID); 1054 1055 /* 1056 * TODO: issue syncs required to ensure all in-flight interrupts 1057 * are complete on the old END 1058 */ 1059 1060 out: 1061 /* Update END */ 1062 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1063 return H_SUCCESS; 1064 } 1065 1066 /* 1067 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1068 * target and priority. 1069 * 1070 * Parameters: 1071 * Input: 1072 * - R4: "flags" 1073 * Bits 0-62: Reserved 1074 * Bit 63: Debug: Return debug data 1075 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1076 * "ibm,ppc-interrupt-gserver#s" 1077 * - R6: "priority" is a valid priority not in 1078 * "ibm,plat-res-int-priorities" 1079 * 1080 * Output: 1081 * - R4: "flags": 1082 * Bits 0-61: Reserved 1083 * Bit 62: The value of Event Queue Generation Number (g) per 1084 * the XIVE spec if "Debug" = 1 1085 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1086 * - R5: The logical real address of the start of the EQ 1087 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1088 * - R7: The value of Event Queue Offset Counter per XIVE spec 1089 * if "Debug" = 1, else 0 1090 * 1091 */ 1092 1093 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1094 1095 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1096 sPAPRMachineState *spapr, 1097 target_ulong opcode, 1098 target_ulong *args) 1099 { 1100 sPAPRXive *xive = spapr->xive; 1101 target_ulong flags = args[0]; 1102 target_ulong target = args[1]; 1103 target_ulong priority = args[2]; 1104 XiveEND *end; 1105 uint8_t end_blk; 1106 uint32_t end_idx; 1107 1108 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1109 return H_FUNCTION; 1110 } 1111 1112 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1113 return H_PARAMETER; 1114 } 1115 1116 /* 1117 * H_STATE should be returned if a H_INT_RESET is in progress. 1118 * This is not needed when running the emulation under QEMU 1119 */ 1120 1121 if (spapr_xive_priority_is_reserved(priority)) { 1122 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1123 " is reserved\n", priority); 1124 return H_P3; 1125 } 1126 1127 /* 1128 * Validate that "target" is part of the list of threads allocated 1129 * to the partition. For that, find the END corresponding to the 1130 * target. 1131 */ 1132 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1133 return H_P2; 1134 } 1135 1136 assert(end_idx < xive->nr_ends); 1137 end = &xive->endt[end_idx]; 1138 1139 args[0] = 0; 1140 if (xive_end_is_notify(end)) { 1141 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1142 } 1143 1144 if (xive_end_is_enqueue(end)) { 1145 args[1] = (uint64_t) be32_to_cpu(end->w2 & 0x0fffffff) << 32 1146 | be32_to_cpu(end->w3); 1147 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1148 } else { 1149 args[1] = 0; 1150 args[2] = 0; 1151 } 1152 1153 /* TODO: do we need any locking on the END ? */ 1154 if (flags & SPAPR_XIVE_END_DEBUG) { 1155 /* Load the event queue generation number into the return flags */ 1156 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1157 1158 /* Load R7 with the event queue offset counter */ 1159 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1160 } else { 1161 args[3] = 0; 1162 } 1163 1164 return H_SUCCESS; 1165 } 1166 1167 /* 1168 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1169 * reporting cache line pair for the calling thread. The reporting 1170 * cache lines will contain the OS interrupt context when the OS 1171 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1172 * interrupt. The reporting cache lines can be reset by inputting -1 1173 * in "reportingLine". Issuing the CI store byte without reporting 1174 * cache lines registered will result in the data not being accessible 1175 * to the OS. 1176 * 1177 * Parameters: 1178 * Input: 1179 * - R4: "flags" 1180 * Bits 0-63: Reserved 1181 * - R5: "reportingLine": The logical real address of the reporting cache 1182 * line pair 1183 * 1184 * Output: 1185 * - None 1186 */ 1187 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1188 sPAPRMachineState *spapr, 1189 target_ulong opcode, 1190 target_ulong *args) 1191 { 1192 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1193 return H_FUNCTION; 1194 } 1195 1196 /* 1197 * H_STATE should be returned if a H_INT_RESET is in progress. 1198 * This is not needed when running the emulation under QEMU 1199 */ 1200 1201 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1202 return H_FUNCTION; 1203 } 1204 1205 /* 1206 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1207 * real address of the reporting cache line pair set for the input 1208 * "target". If no reporting cache line pair has been set, -1 is 1209 * returned. 1210 * 1211 * Parameters: 1212 * Input: 1213 * - R4: "flags" 1214 * Bits 0-63: Reserved 1215 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1216 * "ibm,ppc-interrupt-gserver#s" 1217 * - R6: "reportingLine": The logical real address of the reporting 1218 * cache line pair 1219 * 1220 * Output: 1221 * - R4: The logical real address of the reporting line if set, else -1 1222 */ 1223 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1224 sPAPRMachineState *spapr, 1225 target_ulong opcode, 1226 target_ulong *args) 1227 { 1228 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1229 return H_FUNCTION; 1230 } 1231 1232 /* 1233 * H_STATE should be returned if a H_INT_RESET is in progress. 1234 * This is not needed when running the emulation under QEMU 1235 */ 1236 1237 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1238 return H_FUNCTION; 1239 } 1240 1241 /* 1242 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1243 * page for the input "lisn". This hcall is only supported for LISNs 1244 * that have the ESB hcall flag set to 1 when returned from hcall() 1245 * H_INT_GET_SOURCE_INFO. 1246 * 1247 * Parameters: 1248 * Input: 1249 * - R4: "flags" 1250 * Bits 0-62: Reserved 1251 * bit 63: Store: Store=1, store operation, else load operation 1252 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1253 * "ibm,xive-lisn-ranges" properties, or as returned by the 1254 * ibm,query-interrupt-source-number RTAS call, or as 1255 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1256 * - R6: "esbOffset" is the offset into the ESB page for the load or 1257 * store operation 1258 * - R7: "storeData" is the data to write for a store operation 1259 * 1260 * Output: 1261 * - R4: The value of the load if load operation, else -1 1262 */ 1263 1264 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1265 1266 static target_ulong h_int_esb(PowerPCCPU *cpu, 1267 sPAPRMachineState *spapr, 1268 target_ulong opcode, 1269 target_ulong *args) 1270 { 1271 sPAPRXive *xive = spapr->xive; 1272 XiveEAS eas; 1273 target_ulong flags = args[0]; 1274 target_ulong lisn = args[1]; 1275 target_ulong offset = args[2]; 1276 target_ulong data = args[3]; 1277 hwaddr mmio_addr; 1278 XiveSource *xsrc = &xive->source; 1279 1280 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1281 return H_FUNCTION; 1282 } 1283 1284 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1285 return H_PARAMETER; 1286 } 1287 1288 if (lisn >= xive->nr_irqs) { 1289 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1290 lisn); 1291 return H_P2; 1292 } 1293 1294 eas = xive->eat[lisn]; 1295 if (!xive_eas_is_valid(&eas)) { 1296 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1297 lisn); 1298 return H_P2; 1299 } 1300 1301 if (offset > (1ull << xsrc->esb_shift)) { 1302 return H_P3; 1303 } 1304 1305 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1306 1307 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1308 (flags & SPAPR_XIVE_ESB_STORE))) { 1309 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1310 HWADDR_PRIx "\n", mmio_addr); 1311 return H_HARDWARE; 1312 } 1313 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1314 return H_SUCCESS; 1315 } 1316 1317 /* 1318 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1319 * ensure any in flight events for the input lisn are in the event 1320 * queue. 1321 * 1322 * Parameters: 1323 * Input: 1324 * - R4: "flags" 1325 * Bits 0-63: Reserved 1326 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1327 * "ibm,xive-lisn-ranges" properties, or as returned by the 1328 * ibm,query-interrupt-source-number RTAS call, or as 1329 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1330 * 1331 * Output: 1332 * - None 1333 */ 1334 static target_ulong h_int_sync(PowerPCCPU *cpu, 1335 sPAPRMachineState *spapr, 1336 target_ulong opcode, 1337 target_ulong *args) 1338 { 1339 sPAPRXive *xive = spapr->xive; 1340 XiveEAS eas; 1341 target_ulong flags = args[0]; 1342 target_ulong lisn = args[1]; 1343 1344 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1345 return H_FUNCTION; 1346 } 1347 1348 if (flags) { 1349 return H_PARAMETER; 1350 } 1351 1352 if (lisn >= xive->nr_irqs) { 1353 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1354 lisn); 1355 return H_P2; 1356 } 1357 1358 eas = xive->eat[lisn]; 1359 if (!xive_eas_is_valid(&eas)) { 1360 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1361 lisn); 1362 return H_P2; 1363 } 1364 1365 /* 1366 * H_STATE should be returned if a H_INT_RESET is in progress. 1367 * This is not needed when running the emulation under QEMU 1368 */ 1369 1370 /* This is not real hardware. Nothing to be done */ 1371 return H_SUCCESS; 1372 } 1373 1374 /* 1375 * The H_INT_RESET hcall() is used to reset all of the partition's 1376 * interrupt exploitation structures to their initial state. This 1377 * means losing all previously set interrupt state set via 1378 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1379 * 1380 * Parameters: 1381 * Input: 1382 * - R4: "flags" 1383 * Bits 0-63: Reserved 1384 * 1385 * Output: 1386 * - None 1387 */ 1388 static target_ulong h_int_reset(PowerPCCPU *cpu, 1389 sPAPRMachineState *spapr, 1390 target_ulong opcode, 1391 target_ulong *args) 1392 { 1393 sPAPRXive *xive = spapr->xive; 1394 target_ulong flags = args[0]; 1395 1396 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1397 return H_FUNCTION; 1398 } 1399 1400 if (flags) { 1401 return H_PARAMETER; 1402 } 1403 1404 device_reset(DEVICE(xive)); 1405 return H_SUCCESS; 1406 } 1407 1408 void spapr_xive_hcall_init(sPAPRMachineState *spapr) 1409 { 1410 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1411 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1412 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1413 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1414 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1415 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1416 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1417 h_int_set_os_reporting_line); 1418 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1419 h_int_get_os_reporting_line); 1420 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1421 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1422 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1423 } 1424 1425 void spapr_dt_xive(sPAPRMachineState *spapr, uint32_t nr_servers, void *fdt, 1426 uint32_t phandle) 1427 { 1428 sPAPRXive *xive = spapr->xive; 1429 int node; 1430 uint64_t timas[2 * 2]; 1431 /* Interrupt number ranges for the IPIs */ 1432 uint32_t lisn_ranges[] = { 1433 cpu_to_be32(0), 1434 cpu_to_be32(nr_servers), 1435 }; 1436 /* 1437 * EQ size - the sizes of pages supported by the system 4K, 64K, 1438 * 2M, 16M. We only advertise 64K for the moment. 1439 */ 1440 uint32_t eq_sizes[] = { 1441 cpu_to_be32(16), /* 64K */ 1442 }; 1443 /* 1444 * The following array is in sync with the reserved priorities 1445 * defined by the 'spapr_xive_priority_is_reserved' routine. 1446 */ 1447 uint32_t plat_res_int_priorities[] = { 1448 cpu_to_be32(7), /* start */ 1449 cpu_to_be32(0xf8), /* count */ 1450 }; 1451 gchar *nodename; 1452 1453 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 1454 timas[0] = cpu_to_be64(xive->tm_base + 1455 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 1456 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 1457 timas[2] = cpu_to_be64(xive->tm_base + 1458 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 1459 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 1460 1461 nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 1462 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 1463 _FDT(node = fdt_add_subnode(fdt, 0, nodename)); 1464 g_free(nodename); 1465 1466 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 1467 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 1468 1469 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 1470 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 1471 sizeof(eq_sizes))); 1472 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 1473 sizeof(lisn_ranges))); 1474 1475 /* For Linux to link the LSIs to the interrupt controller. */ 1476 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 1477 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 1478 1479 /* For SLOF */ 1480 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 1481 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 1482 1483 /* 1484 * The "ibm,plat-res-int-priorities" property defines the priority 1485 * ranges reserved by the hypervisor 1486 */ 1487 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 1488 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 1489 } 1490