1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "monitor/monitor.h" 18 #include "hw/ppc/fdt.h" 19 #include "hw/ppc/spapr.h" 20 #include "hw/ppc/spapr_cpu_core.h" 21 #include "hw/ppc/spapr_xive.h" 22 #include "hw/ppc/xive.h" 23 #include "hw/ppc/xive_regs.h" 24 25 /* 26 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 27 * use for the ESB pages and the TIMA pages 28 */ 29 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 30 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 31 32 /* 33 * The allocation of VP blocks is a complex operation in OPAL and the 34 * VP identifiers have a relation with the number of HW chips, the 35 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 36 * controller model does not have the same constraints and can use a 37 * simple mapping scheme of the CPU vcpu_id 38 * 39 * These identifiers are never returned to the OS. 40 */ 41 42 #define SPAPR_XIVE_NVT_BASE 0x400 43 44 /* 45 * sPAPR NVT and END indexing helpers 46 */ 47 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 48 { 49 return nvt_idx - SPAPR_XIVE_NVT_BASE; 50 } 51 52 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 53 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 54 { 55 assert(cpu); 56 57 if (out_nvt_blk) { 58 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 59 } 60 61 if (out_nvt_blk) { 62 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 63 } 64 } 65 66 static int spapr_xive_target_to_nvt(uint32_t target, 67 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 68 { 69 PowerPCCPU *cpu = spapr_find_cpu(target); 70 71 if (!cpu) { 72 return -1; 73 } 74 75 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 76 return 0; 77 } 78 79 /* 80 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 81 * priorities per CPU 82 */ 83 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 84 uint32_t *out_server, uint8_t *out_prio) 85 { 86 87 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 88 89 if (out_server) { 90 *out_server = end_idx >> 3; 91 } 92 93 if (out_prio) { 94 *out_prio = end_idx & 0x7; 95 } 96 return 0; 97 } 98 99 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 100 uint8_t *out_end_blk, uint32_t *out_end_idx) 101 { 102 assert(cpu); 103 104 if (out_end_blk) { 105 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 106 } 107 108 if (out_end_idx) { 109 *out_end_idx = (cpu->vcpu_id << 3) + prio; 110 } 111 } 112 113 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 114 uint8_t *out_end_blk, uint32_t *out_end_idx) 115 { 116 PowerPCCPU *cpu = spapr_find_cpu(target); 117 118 if (!cpu) { 119 return -1; 120 } 121 122 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 123 return 0; 124 } 125 126 /* 127 * On sPAPR machines, use a simplified output for the XIVE END 128 * structure dumping only the information related to the OS EQ. 129 */ 130 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 131 Monitor *mon) 132 { 133 uint64_t qaddr_base = xive_end_qaddr(end); 134 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 135 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 136 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 137 uint32_t qentries = 1 << (qsize + 10); 138 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 139 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 140 141 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 142 spapr_xive_nvt_to_target(0, nvt), 143 priority, qindex, qentries, qaddr_base, qgen); 144 145 xive_end_queue_pic_print_info(end, 6, mon); 146 monitor_printf(mon, "]"); 147 } 148 149 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 150 { 151 XiveSource *xsrc = &xive->source; 152 int i; 153 154 if (kvm_irqchip_in_kernel()) { 155 Error *local_err = NULL; 156 157 kvmppc_xive_synchronize_state(xive, &local_err); 158 if (local_err) { 159 error_report_err(local_err); 160 return; 161 } 162 } 163 164 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 165 166 for (i = 0; i < xive->nr_irqs; i++) { 167 uint8_t pq = xive_source_esb_get(xsrc, i); 168 XiveEAS *eas = &xive->eat[i]; 169 170 if (!xive_eas_is_valid(eas)) { 171 continue; 172 } 173 174 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 175 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 176 pq & XIVE_ESB_VAL_P ? 'P' : '-', 177 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 178 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 179 xive_eas_is_masked(eas) ? "M" : " ", 180 (int) xive_get_field64(EAS_END_DATA, eas->w)); 181 182 if (!xive_eas_is_masked(eas)) { 183 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 184 XiveEND *end; 185 186 assert(end_idx < xive->nr_ends); 187 end = &xive->endt[end_idx]; 188 189 if (xive_end_is_valid(end)) { 190 spapr_xive_end_pic_print_info(xive, end, mon); 191 } 192 } 193 monitor_printf(mon, "\n"); 194 } 195 } 196 197 void spapr_xive_map_mmio(SpaprXive *xive) 198 { 199 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 200 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 201 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 202 } 203 204 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 205 { 206 memory_region_set_enabled(&xive->source.esb_mmio, enable); 207 memory_region_set_enabled(&xive->tm_mmio, enable); 208 209 /* Disable the END ESBs until a guest OS makes use of them */ 210 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 211 } 212 213 /* 214 * When a Virtual Processor is scheduled to run on a HW thread, the 215 * hypervisor pushes its identifier in the OS CAM line. Emulate the 216 * same behavior under QEMU. 217 */ 218 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 219 { 220 uint8_t nvt_blk; 221 uint32_t nvt_idx; 222 uint32_t nvt_cam; 223 224 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 225 226 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 227 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 228 } 229 230 static void spapr_xive_end_reset(XiveEND *end) 231 { 232 memset(end, 0, sizeof(*end)); 233 234 /* switch off the escalation and notification ESBs */ 235 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 236 } 237 238 static void spapr_xive_reset(void *dev) 239 { 240 SpaprXive *xive = SPAPR_XIVE(dev); 241 int i; 242 243 /* 244 * The XiveSource has its own reset handler, which mask off all 245 * IRQs (!P|Q) 246 */ 247 248 /* Mask all valid EASs in the IRQ number space. */ 249 for (i = 0; i < xive->nr_irqs; i++) { 250 XiveEAS *eas = &xive->eat[i]; 251 if (xive_eas_is_valid(eas)) { 252 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 253 } else { 254 eas->w = 0; 255 } 256 } 257 258 /* Clear all ENDs */ 259 for (i = 0; i < xive->nr_ends; i++) { 260 spapr_xive_end_reset(&xive->endt[i]); 261 } 262 } 263 264 static void spapr_xive_instance_init(Object *obj) 265 { 266 SpaprXive *xive = SPAPR_XIVE(obj); 267 268 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 269 TYPE_XIVE_SOURCE, &error_abort, NULL); 270 271 object_initialize_child(obj, "end_source", &xive->end_source, 272 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 273 &error_abort, NULL); 274 275 /* Not connected to the KVM XIVE device */ 276 xive->fd = -1; 277 } 278 279 static void spapr_xive_realize(DeviceState *dev, Error **errp) 280 { 281 SpaprXive *xive = SPAPR_XIVE(dev); 282 XiveSource *xsrc = &xive->source; 283 XiveENDSource *end_xsrc = &xive->end_source; 284 Error *local_err = NULL; 285 286 if (!xive->nr_irqs) { 287 error_setg(errp, "Number of interrupt needs to be greater 0"); 288 return; 289 } 290 291 if (!xive->nr_ends) { 292 error_setg(errp, "Number of interrupt needs to be greater 0"); 293 return; 294 } 295 296 /* 297 * Initialize the internal sources, for IPIs and virtual devices. 298 */ 299 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 300 &error_fatal); 301 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 302 &error_fatal); 303 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 304 if (local_err) { 305 error_propagate(errp, local_err); 306 return; 307 } 308 309 /* 310 * Initialize the END ESB source 311 */ 312 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 313 &error_fatal); 314 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 315 &error_fatal); 316 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 317 if (local_err) { 318 error_propagate(errp, local_err); 319 return; 320 } 321 322 /* Set the mapping address of the END ESB pages after the source ESBs */ 323 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 324 325 /* 326 * Allocate the routing tables 327 */ 328 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 329 xive->endt = g_new0(XiveEND, xive->nr_ends); 330 331 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 332 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 333 334 qemu_register_reset(spapr_xive_reset, dev); 335 336 /* Define all XIVE MMIO regions on SysBus */ 337 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 338 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 339 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 340 } 341 342 void spapr_xive_init(SpaprXive *xive, Error **errp) 343 { 344 XiveSource *xsrc = &xive->source; 345 346 /* 347 * The emulated XIVE device can only be initialized once. If the 348 * ESB memory region has been already mapped, it means we have been 349 * through there. 350 */ 351 if (memory_region_is_mapped(&xsrc->esb_mmio)) { 352 return; 353 } 354 355 /* TIMA initialization */ 356 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 357 "xive.tima", 4ull << TM_SHIFT); 358 359 /* Map all regions */ 360 spapr_xive_map_mmio(xive); 361 } 362 363 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 364 uint32_t eas_idx, XiveEAS *eas) 365 { 366 SpaprXive *xive = SPAPR_XIVE(xrtr); 367 368 if (eas_idx >= xive->nr_irqs) { 369 return -1; 370 } 371 372 *eas = xive->eat[eas_idx]; 373 return 0; 374 } 375 376 static int spapr_xive_get_end(XiveRouter *xrtr, 377 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 378 { 379 SpaprXive *xive = SPAPR_XIVE(xrtr); 380 381 if (end_idx >= xive->nr_ends) { 382 return -1; 383 } 384 385 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 386 return 0; 387 } 388 389 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 390 uint32_t end_idx, XiveEND *end, 391 uint8_t word_number) 392 { 393 SpaprXive *xive = SPAPR_XIVE(xrtr); 394 395 if (end_idx >= xive->nr_ends) { 396 return -1; 397 } 398 399 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 400 return 0; 401 } 402 403 static int spapr_xive_get_nvt(XiveRouter *xrtr, 404 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 405 { 406 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 407 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 408 409 if (!cpu) { 410 /* TODO: should we assert() if we can find a NVT ? */ 411 return -1; 412 } 413 414 /* 415 * sPAPR does not maintain a NVT table. Return that the NVT is 416 * valid if we have found a matching CPU 417 */ 418 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 419 return 0; 420 } 421 422 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 423 uint32_t nvt_idx, XiveNVT *nvt, 424 uint8_t word_number) 425 { 426 /* 427 * We don't need to write back to the NVTs because the sPAPR 428 * machine should never hit a non-scheduled NVT. It should never 429 * get called. 430 */ 431 g_assert_not_reached(); 432 } 433 434 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 435 { 436 PowerPCCPU *cpu = POWERPC_CPU(cs); 437 438 return spapr_cpu_state(cpu)->tctx; 439 } 440 441 static const VMStateDescription vmstate_spapr_xive_end = { 442 .name = TYPE_SPAPR_XIVE "/end", 443 .version_id = 1, 444 .minimum_version_id = 1, 445 .fields = (VMStateField []) { 446 VMSTATE_UINT32(w0, XiveEND), 447 VMSTATE_UINT32(w1, XiveEND), 448 VMSTATE_UINT32(w2, XiveEND), 449 VMSTATE_UINT32(w3, XiveEND), 450 VMSTATE_UINT32(w4, XiveEND), 451 VMSTATE_UINT32(w5, XiveEND), 452 VMSTATE_UINT32(w6, XiveEND), 453 VMSTATE_UINT32(w7, XiveEND), 454 VMSTATE_END_OF_LIST() 455 }, 456 }; 457 458 static const VMStateDescription vmstate_spapr_xive_eas = { 459 .name = TYPE_SPAPR_XIVE "/eas", 460 .version_id = 1, 461 .minimum_version_id = 1, 462 .fields = (VMStateField []) { 463 VMSTATE_UINT64(w, XiveEAS), 464 VMSTATE_END_OF_LIST() 465 }, 466 }; 467 468 static int vmstate_spapr_xive_pre_save(void *opaque) 469 { 470 if (kvm_irqchip_in_kernel()) { 471 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 472 } 473 474 return 0; 475 } 476 477 /* 478 * Called by the sPAPR IRQ backend 'post_load' method at the machine 479 * level. 480 */ 481 int spapr_xive_post_load(SpaprXive *xive, int version_id) 482 { 483 if (kvm_irqchip_in_kernel()) { 484 return kvmppc_xive_post_load(xive, version_id); 485 } 486 487 return 0; 488 } 489 490 static const VMStateDescription vmstate_spapr_xive = { 491 .name = TYPE_SPAPR_XIVE, 492 .version_id = 1, 493 .minimum_version_id = 1, 494 .pre_save = vmstate_spapr_xive_pre_save, 495 .post_load = NULL, /* handled at the machine level */ 496 .fields = (VMStateField[]) { 497 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 498 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 499 vmstate_spapr_xive_eas, XiveEAS), 500 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 501 vmstate_spapr_xive_end, XiveEND), 502 VMSTATE_END_OF_LIST() 503 }, 504 }; 505 506 static Property spapr_xive_properties[] = { 507 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 508 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 509 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 510 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 511 DEFINE_PROP_END_OF_LIST(), 512 }; 513 514 static void spapr_xive_class_init(ObjectClass *klass, void *data) 515 { 516 DeviceClass *dc = DEVICE_CLASS(klass); 517 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 518 519 dc->desc = "sPAPR XIVE Interrupt Controller"; 520 dc->props = spapr_xive_properties; 521 dc->realize = spapr_xive_realize; 522 dc->vmsd = &vmstate_spapr_xive; 523 524 xrc->get_eas = spapr_xive_get_eas; 525 xrc->get_end = spapr_xive_get_end; 526 xrc->write_end = spapr_xive_write_end; 527 xrc->get_nvt = spapr_xive_get_nvt; 528 xrc->write_nvt = spapr_xive_write_nvt; 529 xrc->get_tctx = spapr_xive_get_tctx; 530 } 531 532 static const TypeInfo spapr_xive_info = { 533 .name = TYPE_SPAPR_XIVE, 534 .parent = TYPE_XIVE_ROUTER, 535 .instance_init = spapr_xive_instance_init, 536 .instance_size = sizeof(SpaprXive), 537 .class_init = spapr_xive_class_init, 538 }; 539 540 static void spapr_xive_register_types(void) 541 { 542 type_register_static(&spapr_xive_info); 543 } 544 545 type_init(spapr_xive_register_types) 546 547 bool spapr_xive_irq_claim(SpaprXive *xive, uint32_t lisn, bool lsi) 548 { 549 XiveSource *xsrc = &xive->source; 550 551 if (lisn >= xive->nr_irqs) { 552 return false; 553 } 554 555 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID); 556 if (lsi) { 557 xive_source_irq_set_lsi(xsrc, lisn); 558 } 559 560 if (kvm_irqchip_in_kernel()) { 561 Error *local_err = NULL; 562 563 kvmppc_xive_source_reset_one(xsrc, lisn, &local_err); 564 if (local_err) { 565 error_report_err(local_err); 566 return false; 567 } 568 } 569 570 return true; 571 } 572 573 bool spapr_xive_irq_free(SpaprXive *xive, uint32_t lisn) 574 { 575 if (lisn >= xive->nr_irqs) { 576 return false; 577 } 578 579 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 580 return true; 581 } 582 583 /* 584 * XIVE hcalls 585 * 586 * The terminology used by the XIVE hcalls is the following : 587 * 588 * TARGET vCPU number 589 * EQ Event Queue assigned by OS to receive event data 590 * ESB page for source interrupt management 591 * LISN Logical Interrupt Source Number identifying a source in the 592 * machine 593 * EISN Effective Interrupt Source Number used by guest OS to 594 * identify source in the guest 595 * 596 * The EAS, END, NVT structures are not exposed. 597 */ 598 599 /* 600 * Linux hosts under OPAL reserve priority 7 for their own escalation 601 * interrupts (DD2.X POWER9). So we only allow the guest to use 602 * priorities [0..6]. 603 */ 604 static bool spapr_xive_priority_is_reserved(uint8_t priority) 605 { 606 switch (priority) { 607 case 0 ... 6: 608 return false; 609 case 7: /* OPAL escalation queue */ 610 default: 611 return true; 612 } 613 } 614 615 /* 616 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 617 * real address of the MMIO page through which the Event State Buffer 618 * entry associated with the value of the "lisn" parameter is managed. 619 * 620 * Parameters: 621 * Input 622 * - R4: "flags" 623 * Bits 0-63 reserved 624 * - R5: "lisn" is per "interrupts", "interrupt-map", or 625 * "ibm,xive-lisn-ranges" properties, or as returned by the 626 * ibm,query-interrupt-source-number RTAS call, or as returned 627 * by the H_ALLOCATE_VAS_WINDOW hcall 628 * 629 * Output 630 * - R4: "flags" 631 * Bits 0-59: Reserved 632 * Bit 60: H_INT_ESB must be used for Event State Buffer 633 * management 634 * Bit 61: 1 == LSI 0 == MSI 635 * Bit 62: the full function page supports trigger 636 * Bit 63: Store EOI Supported 637 * - R5: Logical Real address of full function Event State Buffer 638 * management page, -1 if H_INT_ESB hcall flag is set to 1. 639 * - R6: Logical Real Address of trigger only Event State Buffer 640 * management page or -1. 641 * - R7: Power of 2 page size for the ESB management pages returned in 642 * R5 and R6. 643 */ 644 645 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 646 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 647 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 648 on same page */ 649 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 650 651 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 652 SpaprMachineState *spapr, 653 target_ulong opcode, 654 target_ulong *args) 655 { 656 SpaprXive *xive = spapr->xive; 657 XiveSource *xsrc = &xive->source; 658 target_ulong flags = args[0]; 659 target_ulong lisn = args[1]; 660 661 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 662 return H_FUNCTION; 663 } 664 665 if (flags) { 666 return H_PARAMETER; 667 } 668 669 if (lisn >= xive->nr_irqs) { 670 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 671 lisn); 672 return H_P2; 673 } 674 675 if (!xive_eas_is_valid(&xive->eat[lisn])) { 676 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 677 lisn); 678 return H_P2; 679 } 680 681 /* 682 * All sources are emulated under the main XIVE object and share 683 * the same characteristics. 684 */ 685 args[0] = 0; 686 if (!xive_source_esb_has_2page(xsrc)) { 687 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 688 } 689 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 690 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 691 } 692 693 /* 694 * Force the use of the H_INT_ESB hcall in case of an LSI 695 * interrupt. This is necessary under KVM to re-trigger the 696 * interrupt if the level is still asserted 697 */ 698 if (xive_source_irq_is_lsi(xsrc, lisn)) { 699 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 700 } 701 702 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 703 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 704 } else { 705 args[1] = -1; 706 } 707 708 if (xive_source_esb_has_2page(xsrc) && 709 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 710 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 711 } else { 712 args[2] = -1; 713 } 714 715 if (xive_source_esb_has_2page(xsrc)) { 716 args[3] = xsrc->esb_shift - 1; 717 } else { 718 args[3] = xsrc->esb_shift; 719 } 720 721 return H_SUCCESS; 722 } 723 724 /* 725 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 726 * Interrupt Source to a target. The Logical Interrupt Source is 727 * designated with the "lisn" parameter and the target is designated 728 * with the "target" and "priority" parameters. Upon return from the 729 * hcall(), no additional interrupts will be directed to the old EQ. 730 * 731 * Parameters: 732 * Input: 733 * - R4: "flags" 734 * Bits 0-61: Reserved 735 * Bit 62: set the "eisn" in the EAS 736 * Bit 63: masks the interrupt source in the hardware interrupt 737 * control structure. An interrupt masked by this mechanism will 738 * be dropped, but it's source state bits will still be 739 * set. There is no race-free way of unmasking and restoring the 740 * source. Thus this should only be used in interrupts that are 741 * also masked at the source, and only in cases where the 742 * interrupt is not meant to be used for a large amount of time 743 * because no valid target exists for it for example 744 * - R5: "lisn" is per "interrupts", "interrupt-map", or 745 * "ibm,xive-lisn-ranges" properties, or as returned by the 746 * ibm,query-interrupt-source-number RTAS call, or as returned by 747 * the H_ALLOCATE_VAS_WINDOW hcall 748 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 749 * "ibm,ppc-interrupt-gserver#s" 750 * - R7: "priority" is a valid priority not in 751 * "ibm,plat-res-int-priorities" 752 * - R8: "eisn" is the guest EISN associated with the "lisn" 753 * 754 * Output: 755 * - None 756 */ 757 758 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 759 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 760 761 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 762 SpaprMachineState *spapr, 763 target_ulong opcode, 764 target_ulong *args) 765 { 766 SpaprXive *xive = spapr->xive; 767 XiveEAS eas, new_eas; 768 target_ulong flags = args[0]; 769 target_ulong lisn = args[1]; 770 target_ulong target = args[2]; 771 target_ulong priority = args[3]; 772 target_ulong eisn = args[4]; 773 uint8_t end_blk; 774 uint32_t end_idx; 775 776 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 777 return H_FUNCTION; 778 } 779 780 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 781 return H_PARAMETER; 782 } 783 784 if (lisn >= xive->nr_irqs) { 785 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 786 lisn); 787 return H_P2; 788 } 789 790 eas = xive->eat[lisn]; 791 if (!xive_eas_is_valid(&eas)) { 792 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 793 lisn); 794 return H_P2; 795 } 796 797 /* priority 0xff is used to reset the EAS */ 798 if (priority == 0xff) { 799 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 800 goto out; 801 } 802 803 if (flags & SPAPR_XIVE_SRC_MASK) { 804 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 805 } else { 806 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 807 } 808 809 if (spapr_xive_priority_is_reserved(priority)) { 810 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 811 " is reserved\n", priority); 812 return H_P4; 813 } 814 815 /* 816 * Validate that "target" is part of the list of threads allocated 817 * to the partition. For that, find the END corresponding to the 818 * target. 819 */ 820 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 821 return H_P3; 822 } 823 824 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 825 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 826 827 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 828 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 829 } 830 831 if (kvm_irqchip_in_kernel()) { 832 Error *local_err = NULL; 833 834 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 835 if (local_err) { 836 error_report_err(local_err); 837 return H_HARDWARE; 838 } 839 } 840 841 out: 842 xive->eat[lisn] = new_eas; 843 return H_SUCCESS; 844 } 845 846 /* 847 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 848 * target/priority pair is assigned to the specified Logical Interrupt 849 * Source. 850 * 851 * Parameters: 852 * Input: 853 * - R4: "flags" 854 * Bits 0-63 Reserved 855 * - R5: "lisn" is per "interrupts", "interrupt-map", or 856 * "ibm,xive-lisn-ranges" properties, or as returned by the 857 * ibm,query-interrupt-source-number RTAS call, or as 858 * returned by the H_ALLOCATE_VAS_WINDOW hcall 859 * 860 * Output: 861 * - R4: Target to which the specified Logical Interrupt Source is 862 * assigned 863 * - R5: Priority to which the specified Logical Interrupt Source is 864 * assigned 865 * - R6: EISN for the specified Logical Interrupt Source (this will be 866 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 867 */ 868 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 869 SpaprMachineState *spapr, 870 target_ulong opcode, 871 target_ulong *args) 872 { 873 SpaprXive *xive = spapr->xive; 874 target_ulong flags = args[0]; 875 target_ulong lisn = args[1]; 876 XiveEAS eas; 877 XiveEND *end; 878 uint8_t nvt_blk; 879 uint32_t end_idx, nvt_idx; 880 881 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 882 return H_FUNCTION; 883 } 884 885 if (flags) { 886 return H_PARAMETER; 887 } 888 889 if (lisn >= xive->nr_irqs) { 890 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 891 lisn); 892 return H_P2; 893 } 894 895 eas = xive->eat[lisn]; 896 if (!xive_eas_is_valid(&eas)) { 897 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 898 lisn); 899 return H_P2; 900 } 901 902 /* EAS_END_BLOCK is unused on sPAPR */ 903 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 904 905 assert(end_idx < xive->nr_ends); 906 end = &xive->endt[end_idx]; 907 908 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 909 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 910 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 911 912 if (xive_eas_is_masked(&eas)) { 913 args[1] = 0xff; 914 } else { 915 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 916 } 917 918 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 919 920 return H_SUCCESS; 921 } 922 923 /* 924 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 925 * address of the notification management page associated with the 926 * specified target and priority. 927 * 928 * Parameters: 929 * Input: 930 * - R4: "flags" 931 * Bits 0-63 Reserved 932 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 933 * "ibm,ppc-interrupt-gserver#s" 934 * - R6: "priority" is a valid priority not in 935 * "ibm,plat-res-int-priorities" 936 * 937 * Output: 938 * - R4: Logical real address of notification page 939 * - R5: Power of 2 page size of the notification page 940 */ 941 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 942 SpaprMachineState *spapr, 943 target_ulong opcode, 944 target_ulong *args) 945 { 946 SpaprXive *xive = spapr->xive; 947 XiveENDSource *end_xsrc = &xive->end_source; 948 target_ulong flags = args[0]; 949 target_ulong target = args[1]; 950 target_ulong priority = args[2]; 951 XiveEND *end; 952 uint8_t end_blk; 953 uint32_t end_idx; 954 955 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 956 return H_FUNCTION; 957 } 958 959 if (flags) { 960 return H_PARAMETER; 961 } 962 963 /* 964 * H_STATE should be returned if a H_INT_RESET is in progress. 965 * This is not needed when running the emulation under QEMU 966 */ 967 968 if (spapr_xive_priority_is_reserved(priority)) { 969 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 970 " is reserved\n", priority); 971 return H_P3; 972 } 973 974 /* 975 * Validate that "target" is part of the list of threads allocated 976 * to the partition. For that, find the END corresponding to the 977 * target. 978 */ 979 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 980 return H_P2; 981 } 982 983 assert(end_idx < xive->nr_ends); 984 end = &xive->endt[end_idx]; 985 986 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 987 if (xive_end_is_enqueue(end)) { 988 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 989 } else { 990 args[1] = 0; 991 } 992 993 return H_SUCCESS; 994 } 995 996 /* 997 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 998 * a given "target" and "priority". It is also used to set the 999 * notification config associated with the EQ. An EQ size of 0 is 1000 * used to reset the EQ config for a given target and priority. If 1001 * resetting the EQ config, the END associated with the given "target" 1002 * and "priority" will be changed to disable queueing. 1003 * 1004 * Upon return from the hcall(), no additional interrupts will be 1005 * directed to the old EQ (if one was set). The old EQ (if one was 1006 * set) should be investigated for interrupts that occurred prior to 1007 * or during the hcall(). 1008 * 1009 * Parameters: 1010 * Input: 1011 * - R4: "flags" 1012 * Bits 0-62: Reserved 1013 * Bit 63: Unconditional Notify (n) per the XIVE spec 1014 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1015 * "ibm,ppc-interrupt-gserver#s" 1016 * - R6: "priority" is a valid priority not in 1017 * "ibm,plat-res-int-priorities" 1018 * - R7: "eventQueue": The logical real address of the start of the EQ 1019 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1020 * 1021 * Output: 1022 * - None 1023 */ 1024 1025 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1026 1027 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1028 SpaprMachineState *spapr, 1029 target_ulong opcode, 1030 target_ulong *args) 1031 { 1032 SpaprXive *xive = spapr->xive; 1033 target_ulong flags = args[0]; 1034 target_ulong target = args[1]; 1035 target_ulong priority = args[2]; 1036 target_ulong qpage = args[3]; 1037 target_ulong qsize = args[4]; 1038 XiveEND end; 1039 uint8_t end_blk, nvt_blk; 1040 uint32_t end_idx, nvt_idx; 1041 1042 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1043 return H_FUNCTION; 1044 } 1045 1046 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1047 return H_PARAMETER; 1048 } 1049 1050 /* 1051 * H_STATE should be returned if a H_INT_RESET is in progress. 1052 * This is not needed when running the emulation under QEMU 1053 */ 1054 1055 if (spapr_xive_priority_is_reserved(priority)) { 1056 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1057 " is reserved\n", priority); 1058 return H_P3; 1059 } 1060 1061 /* 1062 * Validate that "target" is part of the list of threads allocated 1063 * to the partition. For that, find the END corresponding to the 1064 * target. 1065 */ 1066 1067 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1068 return H_P2; 1069 } 1070 1071 assert(end_idx < xive->nr_ends); 1072 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1073 1074 switch (qsize) { 1075 case 12: 1076 case 16: 1077 case 21: 1078 case 24: 1079 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1080 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1081 " is not naturally aligned with %" HWADDR_PRIx "\n", 1082 qpage, (hwaddr)1 << qsize); 1083 return H_P4; 1084 } 1085 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1086 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1087 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1088 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1089 break; 1090 case 0: 1091 /* reset queue and disable queueing */ 1092 spapr_xive_end_reset(&end); 1093 goto out; 1094 1095 default: 1096 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1097 qsize); 1098 return H_P5; 1099 } 1100 1101 if (qsize) { 1102 hwaddr plen = 1 << qsize; 1103 void *eq; 1104 1105 /* 1106 * Validate the guest EQ. We should also check that the queue 1107 * has been zeroed by the OS. 1108 */ 1109 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1110 MEMTXATTRS_UNSPECIFIED); 1111 if (plen != 1 << qsize) { 1112 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1113 HWADDR_PRIx "\n", qpage); 1114 return H_P4; 1115 } 1116 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1117 } 1118 1119 /* "target" should have been validated above */ 1120 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1121 g_assert_not_reached(); 1122 } 1123 1124 /* 1125 * Ensure the priority and target are correctly set (they will not 1126 * be right after allocation) 1127 */ 1128 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1129 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1130 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1131 1132 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1133 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1134 } else { 1135 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1136 } 1137 1138 /* 1139 * The generation bit for the END starts at 1 and The END page 1140 * offset counter starts at 0. 1141 */ 1142 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1143 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1144 end.w0 |= cpu_to_be32(END_W0_VALID); 1145 1146 /* 1147 * TODO: issue syncs required to ensure all in-flight interrupts 1148 * are complete on the old END 1149 */ 1150 1151 out: 1152 if (kvm_irqchip_in_kernel()) { 1153 Error *local_err = NULL; 1154 1155 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1156 if (local_err) { 1157 error_report_err(local_err); 1158 return H_HARDWARE; 1159 } 1160 } 1161 1162 /* Update END */ 1163 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1164 return H_SUCCESS; 1165 } 1166 1167 /* 1168 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1169 * target and priority. 1170 * 1171 * Parameters: 1172 * Input: 1173 * - R4: "flags" 1174 * Bits 0-62: Reserved 1175 * Bit 63: Debug: Return debug data 1176 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1177 * "ibm,ppc-interrupt-gserver#s" 1178 * - R6: "priority" is a valid priority not in 1179 * "ibm,plat-res-int-priorities" 1180 * 1181 * Output: 1182 * - R4: "flags": 1183 * Bits 0-61: Reserved 1184 * Bit 62: The value of Event Queue Generation Number (g) per 1185 * the XIVE spec if "Debug" = 1 1186 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1187 * - R5: The logical real address of the start of the EQ 1188 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1189 * - R7: The value of Event Queue Offset Counter per XIVE spec 1190 * if "Debug" = 1, else 0 1191 * 1192 */ 1193 1194 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1195 1196 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1197 SpaprMachineState *spapr, 1198 target_ulong opcode, 1199 target_ulong *args) 1200 { 1201 SpaprXive *xive = spapr->xive; 1202 target_ulong flags = args[0]; 1203 target_ulong target = args[1]; 1204 target_ulong priority = args[2]; 1205 XiveEND *end; 1206 uint8_t end_blk; 1207 uint32_t end_idx; 1208 1209 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1210 return H_FUNCTION; 1211 } 1212 1213 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1214 return H_PARAMETER; 1215 } 1216 1217 /* 1218 * H_STATE should be returned if a H_INT_RESET is in progress. 1219 * This is not needed when running the emulation under QEMU 1220 */ 1221 1222 if (spapr_xive_priority_is_reserved(priority)) { 1223 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1224 " is reserved\n", priority); 1225 return H_P3; 1226 } 1227 1228 /* 1229 * Validate that "target" is part of the list of threads allocated 1230 * to the partition. For that, find the END corresponding to the 1231 * target. 1232 */ 1233 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1234 return H_P2; 1235 } 1236 1237 assert(end_idx < xive->nr_ends); 1238 end = &xive->endt[end_idx]; 1239 1240 args[0] = 0; 1241 if (xive_end_is_notify(end)) { 1242 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1243 } 1244 1245 if (xive_end_is_enqueue(end)) { 1246 args[1] = xive_end_qaddr(end); 1247 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1248 } else { 1249 args[1] = 0; 1250 args[2] = 0; 1251 } 1252 1253 if (kvm_irqchip_in_kernel()) { 1254 Error *local_err = NULL; 1255 1256 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1257 if (local_err) { 1258 error_report_err(local_err); 1259 return H_HARDWARE; 1260 } 1261 } 1262 1263 /* TODO: do we need any locking on the END ? */ 1264 if (flags & SPAPR_XIVE_END_DEBUG) { 1265 /* Load the event queue generation number into the return flags */ 1266 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1267 1268 /* Load R7 with the event queue offset counter */ 1269 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1270 } else { 1271 args[3] = 0; 1272 } 1273 1274 return H_SUCCESS; 1275 } 1276 1277 /* 1278 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1279 * reporting cache line pair for the calling thread. The reporting 1280 * cache lines will contain the OS interrupt context when the OS 1281 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1282 * interrupt. The reporting cache lines can be reset by inputting -1 1283 * in "reportingLine". Issuing the CI store byte without reporting 1284 * cache lines registered will result in the data not being accessible 1285 * to the OS. 1286 * 1287 * Parameters: 1288 * Input: 1289 * - R4: "flags" 1290 * Bits 0-63: Reserved 1291 * - R5: "reportingLine": The logical real address of the reporting cache 1292 * line pair 1293 * 1294 * Output: 1295 * - None 1296 */ 1297 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1298 SpaprMachineState *spapr, 1299 target_ulong opcode, 1300 target_ulong *args) 1301 { 1302 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1303 return H_FUNCTION; 1304 } 1305 1306 /* 1307 * H_STATE should be returned if a H_INT_RESET is in progress. 1308 * This is not needed when running the emulation under QEMU 1309 */ 1310 1311 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1312 return H_FUNCTION; 1313 } 1314 1315 /* 1316 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1317 * real address of the reporting cache line pair set for the input 1318 * "target". If no reporting cache line pair has been set, -1 is 1319 * returned. 1320 * 1321 * Parameters: 1322 * Input: 1323 * - R4: "flags" 1324 * Bits 0-63: Reserved 1325 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1326 * "ibm,ppc-interrupt-gserver#s" 1327 * - R6: "reportingLine": The logical real address of the reporting 1328 * cache line pair 1329 * 1330 * Output: 1331 * - R4: The logical real address of the reporting line if set, else -1 1332 */ 1333 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1334 SpaprMachineState *spapr, 1335 target_ulong opcode, 1336 target_ulong *args) 1337 { 1338 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1339 return H_FUNCTION; 1340 } 1341 1342 /* 1343 * H_STATE should be returned if a H_INT_RESET is in progress. 1344 * This is not needed when running the emulation under QEMU 1345 */ 1346 1347 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1348 return H_FUNCTION; 1349 } 1350 1351 /* 1352 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1353 * page for the input "lisn". This hcall is only supported for LISNs 1354 * that have the ESB hcall flag set to 1 when returned from hcall() 1355 * H_INT_GET_SOURCE_INFO. 1356 * 1357 * Parameters: 1358 * Input: 1359 * - R4: "flags" 1360 * Bits 0-62: Reserved 1361 * bit 63: Store: Store=1, store operation, else load operation 1362 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1363 * "ibm,xive-lisn-ranges" properties, or as returned by the 1364 * ibm,query-interrupt-source-number RTAS call, or as 1365 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1366 * - R6: "esbOffset" is the offset into the ESB page for the load or 1367 * store operation 1368 * - R7: "storeData" is the data to write for a store operation 1369 * 1370 * Output: 1371 * - R4: The value of the load if load operation, else -1 1372 */ 1373 1374 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1375 1376 static target_ulong h_int_esb(PowerPCCPU *cpu, 1377 SpaprMachineState *spapr, 1378 target_ulong opcode, 1379 target_ulong *args) 1380 { 1381 SpaprXive *xive = spapr->xive; 1382 XiveEAS eas; 1383 target_ulong flags = args[0]; 1384 target_ulong lisn = args[1]; 1385 target_ulong offset = args[2]; 1386 target_ulong data = args[3]; 1387 hwaddr mmio_addr; 1388 XiveSource *xsrc = &xive->source; 1389 1390 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1391 return H_FUNCTION; 1392 } 1393 1394 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1395 return H_PARAMETER; 1396 } 1397 1398 if (lisn >= xive->nr_irqs) { 1399 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1400 lisn); 1401 return H_P2; 1402 } 1403 1404 eas = xive->eat[lisn]; 1405 if (!xive_eas_is_valid(&eas)) { 1406 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1407 lisn); 1408 return H_P2; 1409 } 1410 1411 if (offset > (1ull << xsrc->esb_shift)) { 1412 return H_P3; 1413 } 1414 1415 if (kvm_irqchip_in_kernel()) { 1416 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1417 flags & SPAPR_XIVE_ESB_STORE); 1418 } else { 1419 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1420 1421 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1422 (flags & SPAPR_XIVE_ESB_STORE))) { 1423 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1424 HWADDR_PRIx "\n", mmio_addr); 1425 return H_HARDWARE; 1426 } 1427 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1428 } 1429 return H_SUCCESS; 1430 } 1431 1432 /* 1433 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1434 * ensure any in flight events for the input lisn are in the event 1435 * queue. 1436 * 1437 * Parameters: 1438 * Input: 1439 * - R4: "flags" 1440 * Bits 0-63: Reserved 1441 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1442 * "ibm,xive-lisn-ranges" properties, or as returned by the 1443 * ibm,query-interrupt-source-number RTAS call, or as 1444 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1445 * 1446 * Output: 1447 * - None 1448 */ 1449 static target_ulong h_int_sync(PowerPCCPU *cpu, 1450 SpaprMachineState *spapr, 1451 target_ulong opcode, 1452 target_ulong *args) 1453 { 1454 SpaprXive *xive = spapr->xive; 1455 XiveEAS eas; 1456 target_ulong flags = args[0]; 1457 target_ulong lisn = args[1]; 1458 1459 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1460 return H_FUNCTION; 1461 } 1462 1463 if (flags) { 1464 return H_PARAMETER; 1465 } 1466 1467 if (lisn >= xive->nr_irqs) { 1468 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1469 lisn); 1470 return H_P2; 1471 } 1472 1473 eas = xive->eat[lisn]; 1474 if (!xive_eas_is_valid(&eas)) { 1475 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1476 lisn); 1477 return H_P2; 1478 } 1479 1480 /* 1481 * H_STATE should be returned if a H_INT_RESET is in progress. 1482 * This is not needed when running the emulation under QEMU 1483 */ 1484 1485 /* 1486 * This is not real hardware. Nothing to be done unless when 1487 * under KVM 1488 */ 1489 1490 if (kvm_irqchip_in_kernel()) { 1491 Error *local_err = NULL; 1492 1493 kvmppc_xive_sync_source(xive, lisn, &local_err); 1494 if (local_err) { 1495 error_report_err(local_err); 1496 return H_HARDWARE; 1497 } 1498 } 1499 return H_SUCCESS; 1500 } 1501 1502 /* 1503 * The H_INT_RESET hcall() is used to reset all of the partition's 1504 * interrupt exploitation structures to their initial state. This 1505 * means losing all previously set interrupt state set via 1506 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1507 * 1508 * Parameters: 1509 * Input: 1510 * - R4: "flags" 1511 * Bits 0-63: Reserved 1512 * 1513 * Output: 1514 * - None 1515 */ 1516 static target_ulong h_int_reset(PowerPCCPU *cpu, 1517 SpaprMachineState *spapr, 1518 target_ulong opcode, 1519 target_ulong *args) 1520 { 1521 SpaprXive *xive = spapr->xive; 1522 target_ulong flags = args[0]; 1523 1524 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1525 return H_FUNCTION; 1526 } 1527 1528 if (flags) { 1529 return H_PARAMETER; 1530 } 1531 1532 device_reset(DEVICE(xive)); 1533 1534 if (kvm_irqchip_in_kernel()) { 1535 Error *local_err = NULL; 1536 1537 kvmppc_xive_reset(xive, &local_err); 1538 if (local_err) { 1539 error_report_err(local_err); 1540 return H_HARDWARE; 1541 } 1542 } 1543 return H_SUCCESS; 1544 } 1545 1546 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1547 { 1548 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1549 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1550 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1551 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1552 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1553 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1554 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1555 h_int_set_os_reporting_line); 1556 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1557 h_int_get_os_reporting_line); 1558 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1559 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1560 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1561 } 1562 1563 void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, 1564 uint32_t phandle) 1565 { 1566 SpaprXive *xive = spapr->xive; 1567 int node; 1568 uint64_t timas[2 * 2]; 1569 /* Interrupt number ranges for the IPIs */ 1570 uint32_t lisn_ranges[] = { 1571 cpu_to_be32(0), 1572 cpu_to_be32(nr_servers), 1573 }; 1574 /* 1575 * EQ size - the sizes of pages supported by the system 4K, 64K, 1576 * 2M, 16M. We only advertise 64K for the moment. 1577 */ 1578 uint32_t eq_sizes[] = { 1579 cpu_to_be32(16), /* 64K */ 1580 }; 1581 /* 1582 * The following array is in sync with the reserved priorities 1583 * defined by the 'spapr_xive_priority_is_reserved' routine. 1584 */ 1585 uint32_t plat_res_int_priorities[] = { 1586 cpu_to_be32(7), /* start */ 1587 cpu_to_be32(0xf8), /* count */ 1588 }; 1589 1590 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 1591 timas[0] = cpu_to_be64(xive->tm_base + 1592 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 1593 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 1594 timas[2] = cpu_to_be64(xive->tm_base + 1595 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 1596 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 1597 1598 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 1599 1600 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 1601 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 1602 1603 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 1604 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 1605 sizeof(eq_sizes))); 1606 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 1607 sizeof(lisn_ranges))); 1608 1609 /* For Linux to link the LSIs to the interrupt controller. */ 1610 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 1611 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 1612 1613 /* For SLOF */ 1614 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 1615 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 1616 1617 /* 1618 * The "ibm,plat-res-int-priorities" property defines the priority 1619 * ranges reserved by the hypervisor 1620 */ 1621 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 1622 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 1623 } 1624