1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "qemu/error-report.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "monitor/monitor.h" 17 #include "hw/ppc/fdt.h" 18 #include "hw/ppc/spapr.h" 19 #include "hw/ppc/spapr_cpu_core.h" 20 #include "hw/ppc/spapr_xive.h" 21 #include "hw/ppc/xive.h" 22 #include "hw/ppc/xive_regs.h" 23 24 /* 25 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 26 * use for the ESB pages and the TIMA pages 27 */ 28 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 29 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 30 31 /* 32 * The allocation of VP blocks is a complex operation in OPAL and the 33 * VP identifiers have a relation with the number of HW chips, the 34 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 35 * controller model does not have the same constraints and can use a 36 * simple mapping scheme of the CPU vcpu_id 37 * 38 * These identifiers are never returned to the OS. 39 */ 40 41 #define SPAPR_XIVE_NVT_BASE 0x400 42 43 /* 44 * The sPAPR machine has a unique XIVE IC device. Assign a fixed value 45 * to the controller block id value. It can nevertheless be changed 46 * for testing purpose. 47 */ 48 #define SPAPR_XIVE_BLOCK_ID 0x0 49 50 /* 51 * sPAPR NVT and END indexing helpers 52 */ 53 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 54 { 55 return nvt_idx - SPAPR_XIVE_NVT_BASE; 56 } 57 58 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 59 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 60 { 61 assert(cpu); 62 63 if (out_nvt_blk) { 64 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 65 } 66 67 if (out_nvt_blk) { 68 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 69 } 70 } 71 72 static int spapr_xive_target_to_nvt(uint32_t target, 73 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 74 { 75 PowerPCCPU *cpu = spapr_find_cpu(target); 76 77 if (!cpu) { 78 return -1; 79 } 80 81 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 82 return 0; 83 } 84 85 /* 86 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 87 * priorities per CPU 88 */ 89 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 90 uint8_t *out_end_blk, uint32_t *out_end_idx) 91 { 92 assert(cpu); 93 94 if (out_end_blk) { 95 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 96 } 97 98 if (out_end_idx) { 99 *out_end_idx = (cpu->vcpu_id << 3) + prio; 100 } 101 } 102 103 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 104 uint8_t *out_end_blk, uint32_t *out_end_idx) 105 { 106 PowerPCCPU *cpu = spapr_find_cpu(target); 107 108 if (!cpu) { 109 return -1; 110 } 111 112 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 113 return 0; 114 } 115 116 /* 117 * On sPAPR machines, use a simplified output for the XIVE END 118 * structure dumping only the information related to the OS EQ. 119 */ 120 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 121 Monitor *mon) 122 { 123 uint64_t qaddr_base = xive_end_qaddr(end); 124 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 125 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 126 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 127 uint32_t qentries = 1 << (qsize + 10); 128 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 129 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 130 131 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 132 spapr_xive_nvt_to_target(0, nvt), 133 priority, qindex, qentries, qaddr_base, qgen); 134 135 xive_end_queue_pic_print_info(end, 6, mon); 136 monitor_printf(mon, "]"); 137 } 138 139 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 140 { 141 XiveSource *xsrc = &xive->source; 142 int i; 143 144 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 145 146 for (i = 0; i < xive->nr_irqs; i++) { 147 uint8_t pq = xive_source_esb_get(xsrc, i); 148 XiveEAS *eas = &xive->eat[i]; 149 150 if (!xive_eas_is_valid(eas)) { 151 continue; 152 } 153 154 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 155 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 156 pq & XIVE_ESB_VAL_P ? 'P' : '-', 157 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 158 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 159 xive_eas_is_masked(eas) ? "M" : " ", 160 (int) xive_get_field64(EAS_END_DATA, eas->w)); 161 162 if (!xive_eas_is_masked(eas)) { 163 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 164 XiveEND *end; 165 166 assert(end_idx < xive->nr_ends); 167 end = &xive->endt[end_idx]; 168 169 if (xive_end_is_valid(end)) { 170 spapr_xive_end_pic_print_info(xive, end, mon); 171 } 172 } 173 monitor_printf(mon, "\n"); 174 } 175 } 176 177 void spapr_xive_map_mmio(SpaprXive *xive) 178 { 179 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 180 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 181 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 182 } 183 184 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 185 { 186 memory_region_set_enabled(&xive->source.esb_mmio, enable); 187 memory_region_set_enabled(&xive->tm_mmio, enable); 188 189 /* Disable the END ESBs until a guest OS makes use of them */ 190 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 191 } 192 193 /* 194 * When a Virtual Processor is scheduled to run on a HW thread, the 195 * hypervisor pushes its identifier in the OS CAM line. Emulate the 196 * same behavior under QEMU. 197 */ 198 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 199 { 200 uint8_t nvt_blk; 201 uint32_t nvt_idx; 202 uint32_t nvt_cam; 203 204 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 205 206 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 207 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 208 } 209 210 static void spapr_xive_end_reset(XiveEND *end) 211 { 212 memset(end, 0, sizeof(*end)); 213 214 /* switch off the escalation and notification ESBs */ 215 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 216 } 217 218 static void spapr_xive_reset(void *dev) 219 { 220 SpaprXive *xive = SPAPR_XIVE(dev); 221 int i; 222 223 /* 224 * The XiveSource has its own reset handler, which mask off all 225 * IRQs (!P|Q) 226 */ 227 228 /* Mask all valid EASs in the IRQ number space. */ 229 for (i = 0; i < xive->nr_irqs; i++) { 230 XiveEAS *eas = &xive->eat[i]; 231 if (xive_eas_is_valid(eas)) { 232 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 233 } else { 234 eas->w = 0; 235 } 236 } 237 238 /* Clear all ENDs */ 239 for (i = 0; i < xive->nr_ends; i++) { 240 spapr_xive_end_reset(&xive->endt[i]); 241 } 242 } 243 244 static void spapr_xive_instance_init(Object *obj) 245 { 246 SpaprXive *xive = SPAPR_XIVE(obj); 247 248 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 249 TYPE_XIVE_SOURCE, &error_abort, NULL); 250 251 object_initialize_child(obj, "end_source", &xive->end_source, 252 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 253 &error_abort, NULL); 254 255 /* Not connected to the KVM XIVE device */ 256 xive->fd = -1; 257 } 258 259 static void spapr_xive_realize(DeviceState *dev, Error **errp) 260 { 261 SpaprXive *xive = SPAPR_XIVE(dev); 262 XiveSource *xsrc = &xive->source; 263 XiveENDSource *end_xsrc = &xive->end_source; 264 Error *local_err = NULL; 265 MachineState *machine = MACHINE(qdev_get_machine()); 266 267 if (!xive->nr_irqs) { 268 error_setg(errp, "Number of interrupt needs to be greater 0"); 269 return; 270 } 271 272 if (!xive->nr_ends) { 273 error_setg(errp, "Number of interrupt needs to be greater 0"); 274 return; 275 } 276 277 /* 278 * Initialize the internal sources, for IPIs and virtual devices. 279 */ 280 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 281 &error_fatal); 282 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 283 &error_fatal); 284 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 285 if (local_err) { 286 error_propagate(errp, local_err); 287 return; 288 } 289 290 /* 291 * Initialize the END ESB source 292 */ 293 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 294 &error_fatal); 295 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 296 &error_fatal); 297 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 298 if (local_err) { 299 error_propagate(errp, local_err); 300 return; 301 } 302 303 /* Set the mapping address of the END ESB pages after the source ESBs */ 304 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 305 306 /* 307 * Allocate the routing tables 308 */ 309 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 310 xive->endt = g_new0(XiveEND, xive->nr_ends); 311 312 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 313 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 314 315 qemu_register_reset(spapr_xive_reset, dev); 316 317 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) { 318 kvmppc_xive_connect(xive, &local_err); 319 if (local_err && machine_kernel_irqchip_required(machine)) { 320 error_prepend(&local_err, 321 "kernel_irqchip requested but unavailable: "); 322 error_propagate(errp, local_err); 323 return; 324 } 325 326 if (!local_err) { 327 return; 328 } 329 330 /* 331 * We failed to initialize the XIVE KVM device, fallback to 332 * emulated mode 333 */ 334 error_prepend(&local_err, "kernel_irqchip allowed but unavailable: "); 335 warn_report_err(local_err); 336 } 337 338 /* TIMA initialization */ 339 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 340 "xive.tima", 4ull << TM_SHIFT); 341 342 /* Define all XIVE MMIO regions on SysBus */ 343 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 344 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 345 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 346 347 /* Map all regions */ 348 spapr_xive_map_mmio(xive); 349 } 350 351 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 352 uint32_t eas_idx, XiveEAS *eas) 353 { 354 SpaprXive *xive = SPAPR_XIVE(xrtr); 355 356 if (eas_idx >= xive->nr_irqs) { 357 return -1; 358 } 359 360 *eas = xive->eat[eas_idx]; 361 return 0; 362 } 363 364 static int spapr_xive_get_end(XiveRouter *xrtr, 365 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 366 { 367 SpaprXive *xive = SPAPR_XIVE(xrtr); 368 369 if (end_idx >= xive->nr_ends) { 370 return -1; 371 } 372 373 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 374 return 0; 375 } 376 377 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 378 uint32_t end_idx, XiveEND *end, 379 uint8_t word_number) 380 { 381 SpaprXive *xive = SPAPR_XIVE(xrtr); 382 383 if (end_idx >= xive->nr_ends) { 384 return -1; 385 } 386 387 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 388 return 0; 389 } 390 391 static int spapr_xive_get_nvt(XiveRouter *xrtr, 392 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 393 { 394 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 395 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 396 397 if (!cpu) { 398 /* TODO: should we assert() if we can find a NVT ? */ 399 return -1; 400 } 401 402 /* 403 * sPAPR does not maintain a NVT table. Return that the NVT is 404 * valid if we have found a matching CPU 405 */ 406 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 407 return 0; 408 } 409 410 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 411 uint32_t nvt_idx, XiveNVT *nvt, 412 uint8_t word_number) 413 { 414 /* 415 * We don't need to write back to the NVTs because the sPAPR 416 * machine should never hit a non-scheduled NVT. It should never 417 * get called. 418 */ 419 g_assert_not_reached(); 420 } 421 422 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 423 { 424 PowerPCCPU *cpu = POWERPC_CPU(cs); 425 426 return spapr_cpu_state(cpu)->tctx; 427 } 428 429 static const VMStateDescription vmstate_spapr_xive_end = { 430 .name = TYPE_SPAPR_XIVE "/end", 431 .version_id = 1, 432 .minimum_version_id = 1, 433 .fields = (VMStateField []) { 434 VMSTATE_UINT32(w0, XiveEND), 435 VMSTATE_UINT32(w1, XiveEND), 436 VMSTATE_UINT32(w2, XiveEND), 437 VMSTATE_UINT32(w3, XiveEND), 438 VMSTATE_UINT32(w4, XiveEND), 439 VMSTATE_UINT32(w5, XiveEND), 440 VMSTATE_UINT32(w6, XiveEND), 441 VMSTATE_UINT32(w7, XiveEND), 442 VMSTATE_END_OF_LIST() 443 }, 444 }; 445 446 static const VMStateDescription vmstate_spapr_xive_eas = { 447 .name = TYPE_SPAPR_XIVE "/eas", 448 .version_id = 1, 449 .minimum_version_id = 1, 450 .fields = (VMStateField []) { 451 VMSTATE_UINT64(w, XiveEAS), 452 VMSTATE_END_OF_LIST() 453 }, 454 }; 455 456 static const VMStateDescription vmstate_spapr_xive = { 457 .name = TYPE_SPAPR_XIVE, 458 .version_id = 1, 459 .minimum_version_id = 1, 460 .fields = (VMStateField[]) { 461 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 462 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 463 vmstate_spapr_xive_eas, XiveEAS), 464 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 465 vmstate_spapr_xive_end, XiveEND), 466 VMSTATE_END_OF_LIST() 467 }, 468 }; 469 470 static Property spapr_xive_properties[] = { 471 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 472 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 473 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 474 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 475 DEFINE_PROP_END_OF_LIST(), 476 }; 477 478 static void spapr_xive_class_init(ObjectClass *klass, void *data) 479 { 480 DeviceClass *dc = DEVICE_CLASS(klass); 481 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 482 483 dc->desc = "sPAPR XIVE Interrupt Controller"; 484 dc->props = spapr_xive_properties; 485 dc->realize = spapr_xive_realize; 486 dc->vmsd = &vmstate_spapr_xive; 487 488 xrc->get_eas = spapr_xive_get_eas; 489 xrc->get_end = spapr_xive_get_end; 490 xrc->write_end = spapr_xive_write_end; 491 xrc->get_nvt = spapr_xive_get_nvt; 492 xrc->write_nvt = spapr_xive_write_nvt; 493 xrc->get_tctx = spapr_xive_get_tctx; 494 } 495 496 static const TypeInfo spapr_xive_info = { 497 .name = TYPE_SPAPR_XIVE, 498 .parent = TYPE_XIVE_ROUTER, 499 .instance_init = spapr_xive_instance_init, 500 .instance_size = sizeof(SpaprXive), 501 .class_init = spapr_xive_class_init, 502 }; 503 504 static void spapr_xive_register_types(void) 505 { 506 type_register_static(&spapr_xive_info); 507 } 508 509 type_init(spapr_xive_register_types) 510 511 bool spapr_xive_irq_claim(SpaprXive *xive, uint32_t lisn, bool lsi) 512 { 513 XiveSource *xsrc = &xive->source; 514 515 if (lisn >= xive->nr_irqs) { 516 return false; 517 } 518 519 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID); 520 if (lsi) { 521 xive_source_irq_set_lsi(xsrc, lisn); 522 } 523 524 if (kvm_irqchip_in_kernel()) { 525 Error *local_err = NULL; 526 527 kvmppc_xive_source_reset_one(xsrc, lisn, &local_err); 528 if (local_err) { 529 error_report_err(local_err); 530 return false; 531 } 532 } 533 534 return true; 535 } 536 537 bool spapr_xive_irq_free(SpaprXive *xive, uint32_t lisn) 538 { 539 if (lisn >= xive->nr_irqs) { 540 return false; 541 } 542 543 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 544 return true; 545 } 546 547 /* 548 * XIVE hcalls 549 * 550 * The terminology used by the XIVE hcalls is the following : 551 * 552 * TARGET vCPU number 553 * EQ Event Queue assigned by OS to receive event data 554 * ESB page for source interrupt management 555 * LISN Logical Interrupt Source Number identifying a source in the 556 * machine 557 * EISN Effective Interrupt Source Number used by guest OS to 558 * identify source in the guest 559 * 560 * The EAS, END, NVT structures are not exposed. 561 */ 562 563 /* 564 * Linux hosts under OPAL reserve priority 7 for their own escalation 565 * interrupts (DD2.X POWER9). So we only allow the guest to use 566 * priorities [0..6]. 567 */ 568 static bool spapr_xive_priority_is_reserved(uint8_t priority) 569 { 570 switch (priority) { 571 case 0 ... 6: 572 return false; 573 case 7: /* OPAL escalation queue */ 574 default: 575 return true; 576 } 577 } 578 579 /* 580 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 581 * real address of the MMIO page through which the Event State Buffer 582 * entry associated with the value of the "lisn" parameter is managed. 583 * 584 * Parameters: 585 * Input 586 * - R4: "flags" 587 * Bits 0-63 reserved 588 * - R5: "lisn" is per "interrupts", "interrupt-map", or 589 * "ibm,xive-lisn-ranges" properties, or as returned by the 590 * ibm,query-interrupt-source-number RTAS call, or as returned 591 * by the H_ALLOCATE_VAS_WINDOW hcall 592 * 593 * Output 594 * - R4: "flags" 595 * Bits 0-59: Reserved 596 * Bit 60: H_INT_ESB must be used for Event State Buffer 597 * management 598 * Bit 61: 1 == LSI 0 == MSI 599 * Bit 62: the full function page supports trigger 600 * Bit 63: Store EOI Supported 601 * - R5: Logical Real address of full function Event State Buffer 602 * management page, -1 if H_INT_ESB hcall flag is set to 1. 603 * - R6: Logical Real Address of trigger only Event State Buffer 604 * management page or -1. 605 * - R7: Power of 2 page size for the ESB management pages returned in 606 * R5 and R6. 607 */ 608 609 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 610 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 611 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 612 on same page */ 613 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 614 615 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 616 SpaprMachineState *spapr, 617 target_ulong opcode, 618 target_ulong *args) 619 { 620 SpaprXive *xive = spapr->xive; 621 XiveSource *xsrc = &xive->source; 622 target_ulong flags = args[0]; 623 target_ulong lisn = args[1]; 624 625 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 626 return H_FUNCTION; 627 } 628 629 if (flags) { 630 return H_PARAMETER; 631 } 632 633 if (lisn >= xive->nr_irqs) { 634 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 635 lisn); 636 return H_P2; 637 } 638 639 if (!xive_eas_is_valid(&xive->eat[lisn])) { 640 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 641 lisn); 642 return H_P2; 643 } 644 645 /* 646 * All sources are emulated under the main XIVE object and share 647 * the same characteristics. 648 */ 649 args[0] = 0; 650 if (!xive_source_esb_has_2page(xsrc)) { 651 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 652 } 653 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 654 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 655 } 656 657 /* 658 * Force the use of the H_INT_ESB hcall in case of an LSI 659 * interrupt. This is necessary under KVM to re-trigger the 660 * interrupt if the level is still asserted 661 */ 662 if (xive_source_irq_is_lsi(xsrc, lisn)) { 663 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 664 } 665 666 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 667 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 668 } else { 669 args[1] = -1; 670 } 671 672 if (xive_source_esb_has_2page(xsrc) && 673 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 674 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 675 } else { 676 args[2] = -1; 677 } 678 679 if (xive_source_esb_has_2page(xsrc)) { 680 args[3] = xsrc->esb_shift - 1; 681 } else { 682 args[3] = xsrc->esb_shift; 683 } 684 685 return H_SUCCESS; 686 } 687 688 /* 689 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 690 * Interrupt Source to a target. The Logical Interrupt Source is 691 * designated with the "lisn" parameter and the target is designated 692 * with the "target" and "priority" parameters. Upon return from the 693 * hcall(), no additional interrupts will be directed to the old EQ. 694 * 695 * Parameters: 696 * Input: 697 * - R4: "flags" 698 * Bits 0-61: Reserved 699 * Bit 62: set the "eisn" in the EAS 700 * Bit 63: masks the interrupt source in the hardware interrupt 701 * control structure. An interrupt masked by this mechanism will 702 * be dropped, but it's source state bits will still be 703 * set. There is no race-free way of unmasking and restoring the 704 * source. Thus this should only be used in interrupts that are 705 * also masked at the source, and only in cases where the 706 * interrupt is not meant to be used for a large amount of time 707 * because no valid target exists for it for example 708 * - R5: "lisn" is per "interrupts", "interrupt-map", or 709 * "ibm,xive-lisn-ranges" properties, or as returned by the 710 * ibm,query-interrupt-source-number RTAS call, or as returned by 711 * the H_ALLOCATE_VAS_WINDOW hcall 712 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 713 * "ibm,ppc-interrupt-gserver#s" 714 * - R7: "priority" is a valid priority not in 715 * "ibm,plat-res-int-priorities" 716 * - R8: "eisn" is the guest EISN associated with the "lisn" 717 * 718 * Output: 719 * - None 720 */ 721 722 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 723 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 724 725 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 726 SpaprMachineState *spapr, 727 target_ulong opcode, 728 target_ulong *args) 729 { 730 SpaprXive *xive = spapr->xive; 731 XiveEAS eas, new_eas; 732 target_ulong flags = args[0]; 733 target_ulong lisn = args[1]; 734 target_ulong target = args[2]; 735 target_ulong priority = args[3]; 736 target_ulong eisn = args[4]; 737 uint8_t end_blk; 738 uint32_t end_idx; 739 740 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 741 return H_FUNCTION; 742 } 743 744 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 745 return H_PARAMETER; 746 } 747 748 if (lisn >= xive->nr_irqs) { 749 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 750 lisn); 751 return H_P2; 752 } 753 754 eas = xive->eat[lisn]; 755 if (!xive_eas_is_valid(&eas)) { 756 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 757 lisn); 758 return H_P2; 759 } 760 761 /* priority 0xff is used to reset the EAS */ 762 if (priority == 0xff) { 763 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 764 goto out; 765 } 766 767 if (flags & SPAPR_XIVE_SRC_MASK) { 768 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 769 } else { 770 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 771 } 772 773 if (spapr_xive_priority_is_reserved(priority)) { 774 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 775 " is reserved\n", priority); 776 return H_P4; 777 } 778 779 /* 780 * Validate that "target" is part of the list of threads allocated 781 * to the partition. For that, find the END corresponding to the 782 * target. 783 */ 784 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 785 return H_P3; 786 } 787 788 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 789 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 790 791 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 792 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 793 } 794 795 out: 796 xive->eat[lisn] = new_eas; 797 return H_SUCCESS; 798 } 799 800 /* 801 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 802 * target/priority pair is assigned to the specified Logical Interrupt 803 * Source. 804 * 805 * Parameters: 806 * Input: 807 * - R4: "flags" 808 * Bits 0-63 Reserved 809 * - R5: "lisn" is per "interrupts", "interrupt-map", or 810 * "ibm,xive-lisn-ranges" properties, or as returned by the 811 * ibm,query-interrupt-source-number RTAS call, or as 812 * returned by the H_ALLOCATE_VAS_WINDOW hcall 813 * 814 * Output: 815 * - R4: Target to which the specified Logical Interrupt Source is 816 * assigned 817 * - R5: Priority to which the specified Logical Interrupt Source is 818 * assigned 819 * - R6: EISN for the specified Logical Interrupt Source (this will be 820 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 821 */ 822 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 823 SpaprMachineState *spapr, 824 target_ulong opcode, 825 target_ulong *args) 826 { 827 SpaprXive *xive = spapr->xive; 828 target_ulong flags = args[0]; 829 target_ulong lisn = args[1]; 830 XiveEAS eas; 831 XiveEND *end; 832 uint8_t nvt_blk; 833 uint32_t end_idx, nvt_idx; 834 835 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 836 return H_FUNCTION; 837 } 838 839 if (flags) { 840 return H_PARAMETER; 841 } 842 843 if (lisn >= xive->nr_irqs) { 844 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 845 lisn); 846 return H_P2; 847 } 848 849 eas = xive->eat[lisn]; 850 if (!xive_eas_is_valid(&eas)) { 851 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 852 lisn); 853 return H_P2; 854 } 855 856 /* EAS_END_BLOCK is unused on sPAPR */ 857 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 858 859 assert(end_idx < xive->nr_ends); 860 end = &xive->endt[end_idx]; 861 862 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 863 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 864 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 865 866 if (xive_eas_is_masked(&eas)) { 867 args[1] = 0xff; 868 } else { 869 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 870 } 871 872 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 873 874 return H_SUCCESS; 875 } 876 877 /* 878 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 879 * address of the notification management page associated with the 880 * specified target and priority. 881 * 882 * Parameters: 883 * Input: 884 * - R4: "flags" 885 * Bits 0-63 Reserved 886 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 887 * "ibm,ppc-interrupt-gserver#s" 888 * - R6: "priority" is a valid priority not in 889 * "ibm,plat-res-int-priorities" 890 * 891 * Output: 892 * - R4: Logical real address of notification page 893 * - R5: Power of 2 page size of the notification page 894 */ 895 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 896 SpaprMachineState *spapr, 897 target_ulong opcode, 898 target_ulong *args) 899 { 900 SpaprXive *xive = spapr->xive; 901 XiveENDSource *end_xsrc = &xive->end_source; 902 target_ulong flags = args[0]; 903 target_ulong target = args[1]; 904 target_ulong priority = args[2]; 905 XiveEND *end; 906 uint8_t end_blk; 907 uint32_t end_idx; 908 909 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 910 return H_FUNCTION; 911 } 912 913 if (flags) { 914 return H_PARAMETER; 915 } 916 917 /* 918 * H_STATE should be returned if a H_INT_RESET is in progress. 919 * This is not needed when running the emulation under QEMU 920 */ 921 922 if (spapr_xive_priority_is_reserved(priority)) { 923 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 924 " is reserved\n", priority); 925 return H_P3; 926 } 927 928 /* 929 * Validate that "target" is part of the list of threads allocated 930 * to the partition. For that, find the END corresponding to the 931 * target. 932 */ 933 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 934 return H_P2; 935 } 936 937 assert(end_idx < xive->nr_ends); 938 end = &xive->endt[end_idx]; 939 940 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 941 if (xive_end_is_enqueue(end)) { 942 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 943 } else { 944 args[1] = 0; 945 } 946 947 return H_SUCCESS; 948 } 949 950 /* 951 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 952 * a given "target" and "priority". It is also used to set the 953 * notification config associated with the EQ. An EQ size of 0 is 954 * used to reset the EQ config for a given target and priority. If 955 * resetting the EQ config, the END associated with the given "target" 956 * and "priority" will be changed to disable queueing. 957 * 958 * Upon return from the hcall(), no additional interrupts will be 959 * directed to the old EQ (if one was set). The old EQ (if one was 960 * set) should be investigated for interrupts that occurred prior to 961 * or during the hcall(). 962 * 963 * Parameters: 964 * Input: 965 * - R4: "flags" 966 * Bits 0-62: Reserved 967 * Bit 63: Unconditional Notify (n) per the XIVE spec 968 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 969 * "ibm,ppc-interrupt-gserver#s" 970 * - R6: "priority" is a valid priority not in 971 * "ibm,plat-res-int-priorities" 972 * - R7: "eventQueue": The logical real address of the start of the EQ 973 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 974 * 975 * Output: 976 * - None 977 */ 978 979 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 980 981 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 982 SpaprMachineState *spapr, 983 target_ulong opcode, 984 target_ulong *args) 985 { 986 SpaprXive *xive = spapr->xive; 987 target_ulong flags = args[0]; 988 target_ulong target = args[1]; 989 target_ulong priority = args[2]; 990 target_ulong qpage = args[3]; 991 target_ulong qsize = args[4]; 992 XiveEND end; 993 uint8_t end_blk, nvt_blk; 994 uint32_t end_idx, nvt_idx; 995 996 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 997 return H_FUNCTION; 998 } 999 1000 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1001 return H_PARAMETER; 1002 } 1003 1004 /* 1005 * H_STATE should be returned if a H_INT_RESET is in progress. 1006 * This is not needed when running the emulation under QEMU 1007 */ 1008 1009 if (spapr_xive_priority_is_reserved(priority)) { 1010 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1011 " is reserved\n", priority); 1012 return H_P3; 1013 } 1014 1015 /* 1016 * Validate that "target" is part of the list of threads allocated 1017 * to the partition. For that, find the END corresponding to the 1018 * target. 1019 */ 1020 1021 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1022 return H_P2; 1023 } 1024 1025 assert(end_idx < xive->nr_ends); 1026 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1027 1028 switch (qsize) { 1029 case 12: 1030 case 16: 1031 case 21: 1032 case 24: 1033 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1034 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1035 " is not naturally aligned with %" HWADDR_PRIx "\n", 1036 qpage, (hwaddr)1 << qsize); 1037 return H_P4; 1038 } 1039 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1040 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1041 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1042 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1043 break; 1044 case 0: 1045 /* reset queue and disable queueing */ 1046 spapr_xive_end_reset(&end); 1047 goto out; 1048 1049 default: 1050 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1051 qsize); 1052 return H_P5; 1053 } 1054 1055 if (qsize) { 1056 hwaddr plen = 1 << qsize; 1057 void *eq; 1058 1059 /* 1060 * Validate the guest EQ. We should also check that the queue 1061 * has been zeroed by the OS. 1062 */ 1063 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1064 MEMTXATTRS_UNSPECIFIED); 1065 if (plen != 1 << qsize) { 1066 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1067 HWADDR_PRIx "\n", qpage); 1068 return H_P4; 1069 } 1070 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1071 } 1072 1073 /* "target" should have been validated above */ 1074 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1075 g_assert_not_reached(); 1076 } 1077 1078 /* 1079 * Ensure the priority and target are correctly set (they will not 1080 * be right after allocation) 1081 */ 1082 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1083 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1084 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1085 1086 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1087 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1088 } else { 1089 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1090 } 1091 1092 /* 1093 * The generation bit for the END starts at 1 and The END page 1094 * offset counter starts at 0. 1095 */ 1096 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1097 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1098 end.w0 |= cpu_to_be32(END_W0_VALID); 1099 1100 /* 1101 * TODO: issue syncs required to ensure all in-flight interrupts 1102 * are complete on the old END 1103 */ 1104 1105 out: 1106 /* Update END */ 1107 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1108 return H_SUCCESS; 1109 } 1110 1111 /* 1112 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1113 * target and priority. 1114 * 1115 * Parameters: 1116 * Input: 1117 * - R4: "flags" 1118 * Bits 0-62: Reserved 1119 * Bit 63: Debug: Return debug data 1120 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1121 * "ibm,ppc-interrupt-gserver#s" 1122 * - R6: "priority" is a valid priority not in 1123 * "ibm,plat-res-int-priorities" 1124 * 1125 * Output: 1126 * - R4: "flags": 1127 * Bits 0-61: Reserved 1128 * Bit 62: The value of Event Queue Generation Number (g) per 1129 * the XIVE spec if "Debug" = 1 1130 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1131 * - R5: The logical real address of the start of the EQ 1132 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1133 * - R7: The value of Event Queue Offset Counter per XIVE spec 1134 * if "Debug" = 1, else 0 1135 * 1136 */ 1137 1138 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1139 1140 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1141 SpaprMachineState *spapr, 1142 target_ulong opcode, 1143 target_ulong *args) 1144 { 1145 SpaprXive *xive = spapr->xive; 1146 target_ulong flags = args[0]; 1147 target_ulong target = args[1]; 1148 target_ulong priority = args[2]; 1149 XiveEND *end; 1150 uint8_t end_blk; 1151 uint32_t end_idx; 1152 1153 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1154 return H_FUNCTION; 1155 } 1156 1157 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1158 return H_PARAMETER; 1159 } 1160 1161 /* 1162 * H_STATE should be returned if a H_INT_RESET is in progress. 1163 * This is not needed when running the emulation under QEMU 1164 */ 1165 1166 if (spapr_xive_priority_is_reserved(priority)) { 1167 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1168 " is reserved\n", priority); 1169 return H_P3; 1170 } 1171 1172 /* 1173 * Validate that "target" is part of the list of threads allocated 1174 * to the partition. For that, find the END corresponding to the 1175 * target. 1176 */ 1177 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1178 return H_P2; 1179 } 1180 1181 assert(end_idx < xive->nr_ends); 1182 end = &xive->endt[end_idx]; 1183 1184 args[0] = 0; 1185 if (xive_end_is_notify(end)) { 1186 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1187 } 1188 1189 if (xive_end_is_enqueue(end)) { 1190 args[1] = xive_end_qaddr(end); 1191 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1192 } else { 1193 args[1] = 0; 1194 args[2] = 0; 1195 } 1196 1197 /* TODO: do we need any locking on the END ? */ 1198 if (flags & SPAPR_XIVE_END_DEBUG) { 1199 /* Load the event queue generation number into the return flags */ 1200 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1201 1202 /* Load R7 with the event queue offset counter */ 1203 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1204 } else { 1205 args[3] = 0; 1206 } 1207 1208 return H_SUCCESS; 1209 } 1210 1211 /* 1212 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1213 * reporting cache line pair for the calling thread. The reporting 1214 * cache lines will contain the OS interrupt context when the OS 1215 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1216 * interrupt. The reporting cache lines can be reset by inputting -1 1217 * in "reportingLine". Issuing the CI store byte without reporting 1218 * cache lines registered will result in the data not being accessible 1219 * to the OS. 1220 * 1221 * Parameters: 1222 * Input: 1223 * - R4: "flags" 1224 * Bits 0-63: Reserved 1225 * - R5: "reportingLine": The logical real address of the reporting cache 1226 * line pair 1227 * 1228 * Output: 1229 * - None 1230 */ 1231 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1232 SpaprMachineState *spapr, 1233 target_ulong opcode, 1234 target_ulong *args) 1235 { 1236 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1237 return H_FUNCTION; 1238 } 1239 1240 /* 1241 * H_STATE should be returned if a H_INT_RESET is in progress. 1242 * This is not needed when running the emulation under QEMU 1243 */ 1244 1245 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1246 return H_FUNCTION; 1247 } 1248 1249 /* 1250 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1251 * real address of the reporting cache line pair set for the input 1252 * "target". If no reporting cache line pair has been set, -1 is 1253 * returned. 1254 * 1255 * Parameters: 1256 * Input: 1257 * - R4: "flags" 1258 * Bits 0-63: Reserved 1259 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1260 * "ibm,ppc-interrupt-gserver#s" 1261 * - R6: "reportingLine": The logical real address of the reporting 1262 * cache line pair 1263 * 1264 * Output: 1265 * - R4: The logical real address of the reporting line if set, else -1 1266 */ 1267 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1268 SpaprMachineState *spapr, 1269 target_ulong opcode, 1270 target_ulong *args) 1271 { 1272 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1273 return H_FUNCTION; 1274 } 1275 1276 /* 1277 * H_STATE should be returned if a H_INT_RESET is in progress. 1278 * This is not needed when running the emulation under QEMU 1279 */ 1280 1281 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1282 return H_FUNCTION; 1283 } 1284 1285 /* 1286 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1287 * page for the input "lisn". This hcall is only supported for LISNs 1288 * that have the ESB hcall flag set to 1 when returned from hcall() 1289 * H_INT_GET_SOURCE_INFO. 1290 * 1291 * Parameters: 1292 * Input: 1293 * - R4: "flags" 1294 * Bits 0-62: Reserved 1295 * bit 63: Store: Store=1, store operation, else load operation 1296 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1297 * "ibm,xive-lisn-ranges" properties, or as returned by the 1298 * ibm,query-interrupt-source-number RTAS call, or as 1299 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1300 * - R6: "esbOffset" is the offset into the ESB page for the load or 1301 * store operation 1302 * - R7: "storeData" is the data to write for a store operation 1303 * 1304 * Output: 1305 * - R4: The value of the load if load operation, else -1 1306 */ 1307 1308 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1309 1310 static target_ulong h_int_esb(PowerPCCPU *cpu, 1311 SpaprMachineState *spapr, 1312 target_ulong opcode, 1313 target_ulong *args) 1314 { 1315 SpaprXive *xive = spapr->xive; 1316 XiveEAS eas; 1317 target_ulong flags = args[0]; 1318 target_ulong lisn = args[1]; 1319 target_ulong offset = args[2]; 1320 target_ulong data = args[3]; 1321 hwaddr mmio_addr; 1322 XiveSource *xsrc = &xive->source; 1323 1324 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1325 return H_FUNCTION; 1326 } 1327 1328 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1329 return H_PARAMETER; 1330 } 1331 1332 if (lisn >= xive->nr_irqs) { 1333 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1334 lisn); 1335 return H_P2; 1336 } 1337 1338 eas = xive->eat[lisn]; 1339 if (!xive_eas_is_valid(&eas)) { 1340 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1341 lisn); 1342 return H_P2; 1343 } 1344 1345 if (offset > (1ull << xsrc->esb_shift)) { 1346 return H_P3; 1347 } 1348 1349 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1350 1351 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1352 (flags & SPAPR_XIVE_ESB_STORE))) { 1353 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1354 HWADDR_PRIx "\n", mmio_addr); 1355 return H_HARDWARE; 1356 } 1357 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1358 return H_SUCCESS; 1359 } 1360 1361 /* 1362 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1363 * ensure any in flight events for the input lisn are in the event 1364 * queue. 1365 * 1366 * Parameters: 1367 * Input: 1368 * - R4: "flags" 1369 * Bits 0-63: Reserved 1370 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1371 * "ibm,xive-lisn-ranges" properties, or as returned by the 1372 * ibm,query-interrupt-source-number RTAS call, or as 1373 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1374 * 1375 * Output: 1376 * - None 1377 */ 1378 static target_ulong h_int_sync(PowerPCCPU *cpu, 1379 SpaprMachineState *spapr, 1380 target_ulong opcode, 1381 target_ulong *args) 1382 { 1383 SpaprXive *xive = spapr->xive; 1384 XiveEAS eas; 1385 target_ulong flags = args[0]; 1386 target_ulong lisn = args[1]; 1387 1388 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1389 return H_FUNCTION; 1390 } 1391 1392 if (flags) { 1393 return H_PARAMETER; 1394 } 1395 1396 if (lisn >= xive->nr_irqs) { 1397 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1398 lisn); 1399 return H_P2; 1400 } 1401 1402 eas = xive->eat[lisn]; 1403 if (!xive_eas_is_valid(&eas)) { 1404 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1405 lisn); 1406 return H_P2; 1407 } 1408 1409 /* 1410 * H_STATE should be returned if a H_INT_RESET is in progress. 1411 * This is not needed when running the emulation under QEMU 1412 */ 1413 1414 /* This is not real hardware. Nothing to be done */ 1415 return H_SUCCESS; 1416 } 1417 1418 /* 1419 * The H_INT_RESET hcall() is used to reset all of the partition's 1420 * interrupt exploitation structures to their initial state. This 1421 * means losing all previously set interrupt state set via 1422 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1423 * 1424 * Parameters: 1425 * Input: 1426 * - R4: "flags" 1427 * Bits 0-63: Reserved 1428 * 1429 * Output: 1430 * - None 1431 */ 1432 static target_ulong h_int_reset(PowerPCCPU *cpu, 1433 SpaprMachineState *spapr, 1434 target_ulong opcode, 1435 target_ulong *args) 1436 { 1437 SpaprXive *xive = spapr->xive; 1438 target_ulong flags = args[0]; 1439 1440 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1441 return H_FUNCTION; 1442 } 1443 1444 if (flags) { 1445 return H_PARAMETER; 1446 } 1447 1448 device_reset(DEVICE(xive)); 1449 return H_SUCCESS; 1450 } 1451 1452 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1453 { 1454 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1455 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1456 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1457 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1458 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1459 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1460 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1461 h_int_set_os_reporting_line); 1462 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1463 h_int_get_os_reporting_line); 1464 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1465 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1466 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1467 } 1468 1469 void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, 1470 uint32_t phandle) 1471 { 1472 SpaprXive *xive = spapr->xive; 1473 int node; 1474 uint64_t timas[2 * 2]; 1475 /* Interrupt number ranges for the IPIs */ 1476 uint32_t lisn_ranges[] = { 1477 cpu_to_be32(0), 1478 cpu_to_be32(nr_servers), 1479 }; 1480 /* 1481 * EQ size - the sizes of pages supported by the system 4K, 64K, 1482 * 2M, 16M. We only advertise 64K for the moment. 1483 */ 1484 uint32_t eq_sizes[] = { 1485 cpu_to_be32(16), /* 64K */ 1486 }; 1487 /* 1488 * The following array is in sync with the reserved priorities 1489 * defined by the 'spapr_xive_priority_is_reserved' routine. 1490 */ 1491 uint32_t plat_res_int_priorities[] = { 1492 cpu_to_be32(7), /* start */ 1493 cpu_to_be32(0xf8), /* count */ 1494 }; 1495 1496 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 1497 timas[0] = cpu_to_be64(xive->tm_base + 1498 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 1499 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 1500 timas[2] = cpu_to_be64(xive->tm_base + 1501 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 1502 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 1503 1504 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 1505 1506 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 1507 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 1508 1509 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 1510 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 1511 sizeof(eq_sizes))); 1512 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 1513 sizeof(lisn_ranges))); 1514 1515 /* For Linux to link the LSIs to the interrupt controller. */ 1516 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 1517 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 1518 1519 /* For SLOF */ 1520 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 1521 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 1522 1523 /* 1524 * The "ibm,plat-res-int-priorities" property defines the priority 1525 * ranges reserved by the hypervisor 1526 */ 1527 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 1528 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 1529 } 1530