1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 } 150 151 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 152 { 153 XiveSource *xsrc = &xive->source; 154 int i; 155 156 if (kvm_irqchip_in_kernel()) { 157 Error *local_err = NULL; 158 159 kvmppc_xive_synchronize_state(xive, &local_err); 160 if (local_err) { 161 error_report_err(local_err); 162 return; 163 } 164 } 165 166 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 167 168 for (i = 0; i < xive->nr_irqs; i++) { 169 uint8_t pq = xive_source_esb_get(xsrc, i); 170 XiveEAS *eas = &xive->eat[i]; 171 172 if (!xive_eas_is_valid(eas)) { 173 continue; 174 } 175 176 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 177 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 178 pq & XIVE_ESB_VAL_P ? 'P' : '-', 179 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 180 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 181 xive_eas_is_masked(eas) ? "M" : " ", 182 (int) xive_get_field64(EAS_END_DATA, eas->w)); 183 184 if (!xive_eas_is_masked(eas)) { 185 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 186 XiveEND *end; 187 188 assert(end_idx < xive->nr_ends); 189 end = &xive->endt[end_idx]; 190 191 if (xive_end_is_valid(end)) { 192 spapr_xive_end_pic_print_info(xive, end, mon); 193 } 194 } 195 monitor_printf(mon, "\n"); 196 } 197 } 198 199 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 200 { 201 memory_region_set_enabled(&xive->source.esb_mmio, enable); 202 memory_region_set_enabled(&xive->tm_mmio, enable); 203 204 /* Disable the END ESBs until a guest OS makes use of them */ 205 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 206 } 207 208 static void spapr_xive_tm_write(void *opaque, hwaddr offset, 209 uint64_t value, unsigned size) 210 { 211 XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; 212 213 xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); 214 } 215 216 static uint64_t spapr_xive_tm_read(void *opaque, hwaddr offset, unsigned size) 217 { 218 XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; 219 220 return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); 221 } 222 223 const MemoryRegionOps spapr_xive_tm_ops = { 224 .read = spapr_xive_tm_read, 225 .write = spapr_xive_tm_write, 226 .endianness = DEVICE_BIG_ENDIAN, 227 .valid = { 228 .min_access_size = 1, 229 .max_access_size = 8, 230 }, 231 .impl = { 232 .min_access_size = 1, 233 .max_access_size = 8, 234 }, 235 }; 236 237 static void spapr_xive_end_reset(XiveEND *end) 238 { 239 memset(end, 0, sizeof(*end)); 240 241 /* switch off the escalation and notification ESBs */ 242 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 243 } 244 245 static void spapr_xive_reset(void *dev) 246 { 247 SpaprXive *xive = SPAPR_XIVE(dev); 248 int i; 249 250 /* 251 * The XiveSource has its own reset handler, which mask off all 252 * IRQs (!P|Q) 253 */ 254 255 /* Mask all valid EASs in the IRQ number space. */ 256 for (i = 0; i < xive->nr_irqs; i++) { 257 XiveEAS *eas = &xive->eat[i]; 258 if (xive_eas_is_valid(eas)) { 259 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 260 } else { 261 eas->w = 0; 262 } 263 } 264 265 /* Clear all ENDs */ 266 for (i = 0; i < xive->nr_ends; i++) { 267 spapr_xive_end_reset(&xive->endt[i]); 268 } 269 } 270 271 static void spapr_xive_instance_init(Object *obj) 272 { 273 SpaprXive *xive = SPAPR_XIVE(obj); 274 275 object_initialize_child(obj, "source", &xive->source, TYPE_XIVE_SOURCE); 276 277 object_initialize_child(obj, "end_source", &xive->end_source, 278 TYPE_XIVE_END_SOURCE); 279 280 /* Not connected to the KVM XIVE device */ 281 xive->fd = -1; 282 } 283 284 static void spapr_xive_realize(DeviceState *dev, Error **errp) 285 { 286 SpaprXive *xive = SPAPR_XIVE(dev); 287 SpaprXiveClass *sxc = SPAPR_XIVE_GET_CLASS(xive); 288 XiveSource *xsrc = &xive->source; 289 XiveENDSource *end_xsrc = &xive->end_source; 290 Error *local_err = NULL; 291 292 sxc->parent_realize(dev, &local_err); 293 if (local_err) { 294 error_propagate(errp, local_err); 295 return; 296 } 297 298 if (!xive->nr_irqs) { 299 error_setg(errp, "Number of interrupt needs to be greater 0"); 300 return; 301 } 302 303 if (!xive->nr_ends) { 304 error_setg(errp, "Number of interrupt needs to be greater 0"); 305 return; 306 } 307 308 /* 309 * Initialize the internal sources, for IPIs and virtual devices. 310 */ 311 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 312 &error_fatal); 313 object_property_set_link(OBJECT(xsrc), OBJECT(xive), "xive", 314 &error_abort); 315 qdev_realize(DEVICE(xsrc), NULL, &local_err); 316 if (local_err) { 317 error_propagate(errp, local_err); 318 return; 319 } 320 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 321 322 /* 323 * Initialize the END ESB source 324 */ 325 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 326 &error_fatal); 327 object_property_set_link(OBJECT(end_xsrc), OBJECT(xive), "xive", 328 &error_abort); 329 qdev_realize(DEVICE(end_xsrc), NULL, &local_err); 330 if (local_err) { 331 error_propagate(errp, local_err); 332 return; 333 } 334 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 335 336 /* Set the mapping address of the END ESB pages after the source ESBs */ 337 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 338 339 /* 340 * Allocate the routing tables 341 */ 342 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 343 xive->endt = g_new0(XiveEND, xive->nr_ends); 344 345 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 346 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 347 348 qemu_register_reset(spapr_xive_reset, dev); 349 350 /* TIMA initialization */ 351 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &spapr_xive_tm_ops, 352 xive, "xive.tima", 4ull << TM_SHIFT); 353 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 354 355 /* 356 * Map all regions. These will be enabled or disabled at reset and 357 * can also be overridden by KVM memory regions if active 358 */ 359 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 360 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 361 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 362 } 363 364 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 365 uint32_t eas_idx, XiveEAS *eas) 366 { 367 SpaprXive *xive = SPAPR_XIVE(xrtr); 368 369 if (eas_idx >= xive->nr_irqs) { 370 return -1; 371 } 372 373 *eas = xive->eat[eas_idx]; 374 return 0; 375 } 376 377 static int spapr_xive_get_end(XiveRouter *xrtr, 378 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 379 { 380 SpaprXive *xive = SPAPR_XIVE(xrtr); 381 382 if (end_idx >= xive->nr_ends) { 383 return -1; 384 } 385 386 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 387 return 0; 388 } 389 390 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 391 uint32_t end_idx, XiveEND *end, 392 uint8_t word_number) 393 { 394 SpaprXive *xive = SPAPR_XIVE(xrtr); 395 396 if (end_idx >= xive->nr_ends) { 397 return -1; 398 } 399 400 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 401 return 0; 402 } 403 404 static int spapr_xive_get_nvt(XiveRouter *xrtr, 405 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 406 { 407 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 408 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 409 410 if (!cpu) { 411 /* TODO: should we assert() if we can find a NVT ? */ 412 return -1; 413 } 414 415 /* 416 * sPAPR does not maintain a NVT table. Return that the NVT is 417 * valid if we have found a matching CPU 418 */ 419 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 420 return 0; 421 } 422 423 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 424 uint32_t nvt_idx, XiveNVT *nvt, 425 uint8_t word_number) 426 { 427 /* 428 * We don't need to write back to the NVTs because the sPAPR 429 * machine should never hit a non-scheduled NVT. It should never 430 * get called. 431 */ 432 g_assert_not_reached(); 433 } 434 435 static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, 436 uint8_t nvt_blk, uint32_t nvt_idx, 437 bool cam_ignore, uint8_t priority, 438 uint32_t logic_serv, XiveTCTXMatch *match) 439 { 440 CPUState *cs; 441 int count = 0; 442 443 CPU_FOREACH(cs) { 444 PowerPCCPU *cpu = POWERPC_CPU(cs); 445 XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx; 446 int ring; 447 448 /* 449 * Skip partially initialized vCPUs. This can happen when 450 * vCPUs are hotplugged. 451 */ 452 if (!tctx) { 453 continue; 454 } 455 456 /* 457 * Check the thread context CAM lines and record matches. 458 */ 459 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx, 460 cam_ignore, logic_serv); 461 /* 462 * Save the matching thread interrupt context and follow on to 463 * check for duplicates which are invalid. 464 */ 465 if (ring != -1) { 466 if (match->tctx) { 467 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread " 468 "context NVT %x/%x\n", nvt_blk, nvt_idx); 469 return -1; 470 } 471 472 match->ring = ring; 473 match->tctx = tctx; 474 count++; 475 } 476 } 477 478 return count; 479 } 480 481 static uint8_t spapr_xive_get_block_id(XiveRouter *xrtr) 482 { 483 return SPAPR_XIVE_BLOCK_ID; 484 } 485 486 static const VMStateDescription vmstate_spapr_xive_end = { 487 .name = TYPE_SPAPR_XIVE "/end", 488 .version_id = 1, 489 .minimum_version_id = 1, 490 .fields = (VMStateField []) { 491 VMSTATE_UINT32(w0, XiveEND), 492 VMSTATE_UINT32(w1, XiveEND), 493 VMSTATE_UINT32(w2, XiveEND), 494 VMSTATE_UINT32(w3, XiveEND), 495 VMSTATE_UINT32(w4, XiveEND), 496 VMSTATE_UINT32(w5, XiveEND), 497 VMSTATE_UINT32(w6, XiveEND), 498 VMSTATE_UINT32(w7, XiveEND), 499 VMSTATE_END_OF_LIST() 500 }, 501 }; 502 503 static const VMStateDescription vmstate_spapr_xive_eas = { 504 .name = TYPE_SPAPR_XIVE "/eas", 505 .version_id = 1, 506 .minimum_version_id = 1, 507 .fields = (VMStateField []) { 508 VMSTATE_UINT64(w, XiveEAS), 509 VMSTATE_END_OF_LIST() 510 }, 511 }; 512 513 static int vmstate_spapr_xive_pre_save(void *opaque) 514 { 515 if (kvm_irqchip_in_kernel()) { 516 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 517 } 518 519 return 0; 520 } 521 522 /* 523 * Called by the sPAPR IRQ backend 'post_load' method at the machine 524 * level. 525 */ 526 static int spapr_xive_post_load(SpaprInterruptController *intc, int version_id) 527 { 528 if (kvm_irqchip_in_kernel()) { 529 return kvmppc_xive_post_load(SPAPR_XIVE(intc), version_id); 530 } 531 532 return 0; 533 } 534 535 static const VMStateDescription vmstate_spapr_xive = { 536 .name = TYPE_SPAPR_XIVE, 537 .version_id = 1, 538 .minimum_version_id = 1, 539 .pre_save = vmstate_spapr_xive_pre_save, 540 .post_load = NULL, /* handled at the machine level */ 541 .fields = (VMStateField[]) { 542 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 543 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 544 vmstate_spapr_xive_eas, XiveEAS), 545 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 546 vmstate_spapr_xive_end, XiveEND), 547 VMSTATE_END_OF_LIST() 548 }, 549 }; 550 551 static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, 552 bool lsi, Error **errp) 553 { 554 SpaprXive *xive = SPAPR_XIVE(intc); 555 XiveSource *xsrc = &xive->source; 556 557 assert(lisn < xive->nr_irqs); 558 559 if (xive_eas_is_valid(&xive->eat[lisn])) { 560 error_setg(errp, "IRQ %d is not free", lisn); 561 return -EBUSY; 562 } 563 564 /* 565 * Set default values when allocating an IRQ number 566 */ 567 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); 568 if (lsi) { 569 xive_source_irq_set_lsi(xsrc, lisn); 570 } 571 572 if (kvm_irqchip_in_kernel()) { 573 return kvmppc_xive_source_reset_one(xsrc, lisn, errp); 574 } 575 576 return 0; 577 } 578 579 static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) 580 { 581 SpaprXive *xive = SPAPR_XIVE(intc); 582 assert(lisn < xive->nr_irqs); 583 584 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 585 } 586 587 static Property spapr_xive_properties[] = { 588 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 589 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 590 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 591 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 592 DEFINE_PROP_END_OF_LIST(), 593 }; 594 595 static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 596 PowerPCCPU *cpu, Error **errp) 597 { 598 SpaprXive *xive = SPAPR_XIVE(intc); 599 Object *obj; 600 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 601 602 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(xive), errp); 603 if (!obj) { 604 return -1; 605 } 606 607 spapr_cpu->tctx = XIVE_TCTX(obj); 608 return 0; 609 } 610 611 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t os_cam) 612 { 613 uint32_t qw1w2 = cpu_to_be32(TM_QW1W2_VO | os_cam); 614 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 615 } 616 617 static void spapr_xive_cpu_intc_reset(SpaprInterruptController *intc, 618 PowerPCCPU *cpu) 619 { 620 XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx; 621 uint8_t nvt_blk; 622 uint32_t nvt_idx; 623 624 xive_tctx_reset(tctx); 625 626 /* 627 * When a Virtual Processor is scheduled to run on a HW thread, 628 * the hypervisor pushes its identifier in the OS CAM line. 629 * Emulate the same behavior under QEMU. 630 */ 631 spapr_xive_cpu_to_nvt(cpu, &nvt_blk, &nvt_idx); 632 633 xive_tctx_set_os_cam(tctx, xive_nvt_cam_line(nvt_blk, nvt_idx)); 634 } 635 636 static void spapr_xive_cpu_intc_destroy(SpaprInterruptController *intc, 637 PowerPCCPU *cpu) 638 { 639 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 640 641 xive_tctx_destroy(spapr_cpu->tctx); 642 spapr_cpu->tctx = NULL; 643 } 644 645 static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val) 646 { 647 SpaprXive *xive = SPAPR_XIVE(intc); 648 649 if (kvm_irqchip_in_kernel()) { 650 kvmppc_xive_source_set_irq(&xive->source, irq, val); 651 } else { 652 xive_source_set_irq(&xive->source, irq, val); 653 } 654 } 655 656 static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor *mon) 657 { 658 SpaprXive *xive = SPAPR_XIVE(intc); 659 CPUState *cs; 660 661 CPU_FOREACH(cs) { 662 PowerPCCPU *cpu = POWERPC_CPU(cs); 663 664 xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); 665 } 666 667 spapr_xive_pic_print_info(xive, mon); 668 } 669 670 static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers, 671 void *fdt, uint32_t phandle) 672 { 673 SpaprXive *xive = SPAPR_XIVE(intc); 674 int node; 675 uint64_t timas[2 * 2]; 676 /* Interrupt number ranges for the IPIs */ 677 uint32_t lisn_ranges[] = { 678 cpu_to_be32(SPAPR_IRQ_IPI), 679 cpu_to_be32(SPAPR_IRQ_IPI + nr_servers), 680 }; 681 /* 682 * EQ size - the sizes of pages supported by the system 4K, 64K, 683 * 2M, 16M. We only advertise 64K for the moment. 684 */ 685 uint32_t eq_sizes[] = { 686 cpu_to_be32(16), /* 64K */ 687 }; 688 /* 689 * The following array is in sync with the reserved priorities 690 * defined by the 'spapr_xive_priority_is_reserved' routine. 691 */ 692 uint32_t plat_res_int_priorities[] = { 693 cpu_to_be32(7), /* start */ 694 cpu_to_be32(0xf8), /* count */ 695 }; 696 697 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 698 timas[0] = cpu_to_be64(xive->tm_base + 699 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 700 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 701 timas[2] = cpu_to_be64(xive->tm_base + 702 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 703 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 704 705 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 706 707 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 708 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 709 710 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 711 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 712 sizeof(eq_sizes))); 713 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 714 sizeof(lisn_ranges))); 715 716 /* For Linux to link the LSIs to the interrupt controller. */ 717 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 718 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 719 720 /* For SLOF */ 721 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 722 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 723 724 /* 725 * The "ibm,plat-res-int-priorities" property defines the priority 726 * ranges reserved by the hypervisor 727 */ 728 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 729 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 730 } 731 732 static int spapr_xive_activate(SpaprInterruptController *intc, 733 uint32_t nr_servers, Error **errp) 734 { 735 SpaprXive *xive = SPAPR_XIVE(intc); 736 737 if (kvm_enabled()) { 738 int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, nr_servers, 739 errp); 740 if (rc < 0) { 741 return rc; 742 } 743 } 744 745 /* Activate the XIVE MMIOs */ 746 spapr_xive_mmio_set_enabled(xive, true); 747 748 return 0; 749 } 750 751 static void spapr_xive_deactivate(SpaprInterruptController *intc) 752 { 753 SpaprXive *xive = SPAPR_XIVE(intc); 754 755 spapr_xive_mmio_set_enabled(xive, false); 756 757 if (kvm_irqchip_in_kernel()) { 758 kvmppc_xive_disconnect(intc); 759 } 760 } 761 762 static void spapr_xive_class_init(ObjectClass *klass, void *data) 763 { 764 DeviceClass *dc = DEVICE_CLASS(klass); 765 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 766 SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); 767 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 768 SpaprXiveClass *sxc = SPAPR_XIVE_CLASS(klass); 769 770 dc->desc = "sPAPR XIVE Interrupt Controller"; 771 device_class_set_props(dc, spapr_xive_properties); 772 device_class_set_parent_realize(dc, spapr_xive_realize, 773 &sxc->parent_realize); 774 dc->vmsd = &vmstate_spapr_xive; 775 776 xrc->get_eas = spapr_xive_get_eas; 777 xrc->get_end = spapr_xive_get_end; 778 xrc->write_end = spapr_xive_write_end; 779 xrc->get_nvt = spapr_xive_get_nvt; 780 xrc->write_nvt = spapr_xive_write_nvt; 781 xrc->get_block_id = spapr_xive_get_block_id; 782 783 sicc->activate = spapr_xive_activate; 784 sicc->deactivate = spapr_xive_deactivate; 785 sicc->cpu_intc_create = spapr_xive_cpu_intc_create; 786 sicc->cpu_intc_reset = spapr_xive_cpu_intc_reset; 787 sicc->cpu_intc_destroy = spapr_xive_cpu_intc_destroy; 788 sicc->claim_irq = spapr_xive_claim_irq; 789 sicc->free_irq = spapr_xive_free_irq; 790 sicc->set_irq = spapr_xive_set_irq; 791 sicc->print_info = spapr_xive_print_info; 792 sicc->dt = spapr_xive_dt; 793 sicc->post_load = spapr_xive_post_load; 794 795 xpc->match_nvt = spapr_xive_match_nvt; 796 } 797 798 static const TypeInfo spapr_xive_info = { 799 .name = TYPE_SPAPR_XIVE, 800 .parent = TYPE_XIVE_ROUTER, 801 .instance_init = spapr_xive_instance_init, 802 .instance_size = sizeof(SpaprXive), 803 .class_init = spapr_xive_class_init, 804 .class_size = sizeof(SpaprXiveClass), 805 .interfaces = (InterfaceInfo[]) { 806 { TYPE_SPAPR_INTC }, 807 { } 808 }, 809 }; 810 811 static void spapr_xive_register_types(void) 812 { 813 type_register_static(&spapr_xive_info); 814 } 815 816 type_init(spapr_xive_register_types) 817 818 /* 819 * XIVE hcalls 820 * 821 * The terminology used by the XIVE hcalls is the following : 822 * 823 * TARGET vCPU number 824 * EQ Event Queue assigned by OS to receive event data 825 * ESB page for source interrupt management 826 * LISN Logical Interrupt Source Number identifying a source in the 827 * machine 828 * EISN Effective Interrupt Source Number used by guest OS to 829 * identify source in the guest 830 * 831 * The EAS, END, NVT structures are not exposed. 832 */ 833 834 /* 835 * Linux hosts under OPAL reserve priority 7 for their own escalation 836 * interrupts (DD2.X POWER9). So we only allow the guest to use 837 * priorities [0..6]. 838 */ 839 static bool spapr_xive_priority_is_reserved(uint8_t priority) 840 { 841 switch (priority) { 842 case 0 ... 6: 843 return false; 844 case 7: /* OPAL escalation queue */ 845 default: 846 return true; 847 } 848 } 849 850 /* 851 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 852 * real address of the MMIO page through which the Event State Buffer 853 * entry associated with the value of the "lisn" parameter is managed. 854 * 855 * Parameters: 856 * Input 857 * - R4: "flags" 858 * Bits 0-63 reserved 859 * - R5: "lisn" is per "interrupts", "interrupt-map", or 860 * "ibm,xive-lisn-ranges" properties, or as returned by the 861 * ibm,query-interrupt-source-number RTAS call, or as returned 862 * by the H_ALLOCATE_VAS_WINDOW hcall 863 * 864 * Output 865 * - R4: "flags" 866 * Bits 0-59: Reserved 867 * Bit 60: H_INT_ESB must be used for Event State Buffer 868 * management 869 * Bit 61: 1 == LSI 0 == MSI 870 * Bit 62: the full function page supports trigger 871 * Bit 63: Store EOI Supported 872 * - R5: Logical Real address of full function Event State Buffer 873 * management page, -1 if H_INT_ESB hcall flag is set to 1. 874 * - R6: Logical Real Address of trigger only Event State Buffer 875 * management page or -1. 876 * - R7: Power of 2 page size for the ESB management pages returned in 877 * R5 and R6. 878 */ 879 880 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 881 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 882 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 883 on same page */ 884 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 885 886 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 887 SpaprMachineState *spapr, 888 target_ulong opcode, 889 target_ulong *args) 890 { 891 SpaprXive *xive = spapr->xive; 892 XiveSource *xsrc = &xive->source; 893 target_ulong flags = args[0]; 894 target_ulong lisn = args[1]; 895 896 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 897 return H_FUNCTION; 898 } 899 900 if (flags) { 901 return H_PARAMETER; 902 } 903 904 if (lisn >= xive->nr_irqs) { 905 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 906 lisn); 907 return H_P2; 908 } 909 910 if (!xive_eas_is_valid(&xive->eat[lisn])) { 911 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 912 lisn); 913 return H_P2; 914 } 915 916 /* 917 * All sources are emulated under the main XIVE object and share 918 * the same characteristics. 919 */ 920 args[0] = 0; 921 if (!xive_source_esb_has_2page(xsrc)) { 922 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 923 } 924 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 925 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 926 } 927 928 /* 929 * Force the use of the H_INT_ESB hcall in case of an LSI 930 * interrupt. This is necessary under KVM to re-trigger the 931 * interrupt if the level is still asserted 932 */ 933 if (xive_source_irq_is_lsi(xsrc, lisn)) { 934 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 935 } 936 937 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 938 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 939 } else { 940 args[1] = -1; 941 } 942 943 if (xive_source_esb_has_2page(xsrc) && 944 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 945 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 946 } else { 947 args[2] = -1; 948 } 949 950 if (xive_source_esb_has_2page(xsrc)) { 951 args[3] = xsrc->esb_shift - 1; 952 } else { 953 args[3] = xsrc->esb_shift; 954 } 955 956 return H_SUCCESS; 957 } 958 959 /* 960 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 961 * Interrupt Source to a target. The Logical Interrupt Source is 962 * designated with the "lisn" parameter and the target is designated 963 * with the "target" and "priority" parameters. Upon return from the 964 * hcall(), no additional interrupts will be directed to the old EQ. 965 * 966 * Parameters: 967 * Input: 968 * - R4: "flags" 969 * Bits 0-61: Reserved 970 * Bit 62: set the "eisn" in the EAS 971 * Bit 63: masks the interrupt source in the hardware interrupt 972 * control structure. An interrupt masked by this mechanism will 973 * be dropped, but it's source state bits will still be 974 * set. There is no race-free way of unmasking and restoring the 975 * source. Thus this should only be used in interrupts that are 976 * also masked at the source, and only in cases where the 977 * interrupt is not meant to be used for a large amount of time 978 * because no valid target exists for it for example 979 * - R5: "lisn" is per "interrupts", "interrupt-map", or 980 * "ibm,xive-lisn-ranges" properties, or as returned by the 981 * ibm,query-interrupt-source-number RTAS call, or as returned by 982 * the H_ALLOCATE_VAS_WINDOW hcall 983 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 984 * "ibm,ppc-interrupt-gserver#s" 985 * - R7: "priority" is a valid priority not in 986 * "ibm,plat-res-int-priorities" 987 * - R8: "eisn" is the guest EISN associated with the "lisn" 988 * 989 * Output: 990 * - None 991 */ 992 993 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 994 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 995 996 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 997 SpaprMachineState *spapr, 998 target_ulong opcode, 999 target_ulong *args) 1000 { 1001 SpaprXive *xive = spapr->xive; 1002 XiveEAS eas, new_eas; 1003 target_ulong flags = args[0]; 1004 target_ulong lisn = args[1]; 1005 target_ulong target = args[2]; 1006 target_ulong priority = args[3]; 1007 target_ulong eisn = args[4]; 1008 uint8_t end_blk; 1009 uint32_t end_idx; 1010 1011 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1012 return H_FUNCTION; 1013 } 1014 1015 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 1016 return H_PARAMETER; 1017 } 1018 1019 if (lisn >= xive->nr_irqs) { 1020 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1021 lisn); 1022 return H_P2; 1023 } 1024 1025 eas = xive->eat[lisn]; 1026 if (!xive_eas_is_valid(&eas)) { 1027 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1028 lisn); 1029 return H_P2; 1030 } 1031 1032 /* priority 0xff is used to reset the EAS */ 1033 if (priority == 0xff) { 1034 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 1035 goto out; 1036 } 1037 1038 if (flags & SPAPR_XIVE_SRC_MASK) { 1039 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 1040 } else { 1041 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 1042 } 1043 1044 if (spapr_xive_priority_is_reserved(priority)) { 1045 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1046 " is reserved\n", priority); 1047 return H_P4; 1048 } 1049 1050 /* 1051 * Validate that "target" is part of the list of threads allocated 1052 * to the partition. For that, find the END corresponding to the 1053 * target. 1054 */ 1055 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1056 return H_P3; 1057 } 1058 1059 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 1060 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 1061 1062 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 1063 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 1064 } 1065 1066 if (kvm_irqchip_in_kernel()) { 1067 Error *local_err = NULL; 1068 1069 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 1070 if (local_err) { 1071 error_report_err(local_err); 1072 return H_HARDWARE; 1073 } 1074 } 1075 1076 out: 1077 xive->eat[lisn] = new_eas; 1078 return H_SUCCESS; 1079 } 1080 1081 /* 1082 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 1083 * target/priority pair is assigned to the specified Logical Interrupt 1084 * Source. 1085 * 1086 * Parameters: 1087 * Input: 1088 * - R4: "flags" 1089 * Bits 0-63 Reserved 1090 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1091 * "ibm,xive-lisn-ranges" properties, or as returned by the 1092 * ibm,query-interrupt-source-number RTAS call, or as 1093 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1094 * 1095 * Output: 1096 * - R4: Target to which the specified Logical Interrupt Source is 1097 * assigned 1098 * - R5: Priority to which the specified Logical Interrupt Source is 1099 * assigned 1100 * - R6: EISN for the specified Logical Interrupt Source (this will be 1101 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 1102 */ 1103 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 1104 SpaprMachineState *spapr, 1105 target_ulong opcode, 1106 target_ulong *args) 1107 { 1108 SpaprXive *xive = spapr->xive; 1109 target_ulong flags = args[0]; 1110 target_ulong lisn = args[1]; 1111 XiveEAS eas; 1112 XiveEND *end; 1113 uint8_t nvt_blk; 1114 uint32_t end_idx, nvt_idx; 1115 1116 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1117 return H_FUNCTION; 1118 } 1119 1120 if (flags) { 1121 return H_PARAMETER; 1122 } 1123 1124 if (lisn >= xive->nr_irqs) { 1125 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1126 lisn); 1127 return H_P2; 1128 } 1129 1130 eas = xive->eat[lisn]; 1131 if (!xive_eas_is_valid(&eas)) { 1132 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1133 lisn); 1134 return H_P2; 1135 } 1136 1137 /* EAS_END_BLOCK is unused on sPAPR */ 1138 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 1139 1140 assert(end_idx < xive->nr_ends); 1141 end = &xive->endt[end_idx]; 1142 1143 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1144 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1145 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 1146 1147 if (xive_eas_is_masked(&eas)) { 1148 args[1] = 0xff; 1149 } else { 1150 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1151 } 1152 1153 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 1154 1155 return H_SUCCESS; 1156 } 1157 1158 /* 1159 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 1160 * address of the notification management page associated with the 1161 * specified target and priority. 1162 * 1163 * Parameters: 1164 * Input: 1165 * - R4: "flags" 1166 * Bits 0-63 Reserved 1167 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1168 * "ibm,ppc-interrupt-gserver#s" 1169 * - R6: "priority" is a valid priority not in 1170 * "ibm,plat-res-int-priorities" 1171 * 1172 * Output: 1173 * - R4: Logical real address of notification page 1174 * - R5: Power of 2 page size of the notification page 1175 */ 1176 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 1177 SpaprMachineState *spapr, 1178 target_ulong opcode, 1179 target_ulong *args) 1180 { 1181 SpaprXive *xive = spapr->xive; 1182 XiveENDSource *end_xsrc = &xive->end_source; 1183 target_ulong flags = args[0]; 1184 target_ulong target = args[1]; 1185 target_ulong priority = args[2]; 1186 XiveEND *end; 1187 uint8_t end_blk; 1188 uint32_t end_idx; 1189 1190 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1191 return H_FUNCTION; 1192 } 1193 1194 if (flags) { 1195 return H_PARAMETER; 1196 } 1197 1198 /* 1199 * H_STATE should be returned if a H_INT_RESET is in progress. 1200 * This is not needed when running the emulation under QEMU 1201 */ 1202 1203 if (spapr_xive_priority_is_reserved(priority)) { 1204 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1205 " is reserved\n", priority); 1206 return H_P3; 1207 } 1208 1209 /* 1210 * Validate that "target" is part of the list of threads allocated 1211 * to the partition. For that, find the END corresponding to the 1212 * target. 1213 */ 1214 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1215 return H_P2; 1216 } 1217 1218 assert(end_idx < xive->nr_ends); 1219 end = &xive->endt[end_idx]; 1220 1221 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 1222 if (xive_end_is_enqueue(end)) { 1223 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1224 } else { 1225 args[1] = 0; 1226 } 1227 1228 return H_SUCCESS; 1229 } 1230 1231 /* 1232 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 1233 * a given "target" and "priority". It is also used to set the 1234 * notification config associated with the EQ. An EQ size of 0 is 1235 * used to reset the EQ config for a given target and priority. If 1236 * resetting the EQ config, the END associated with the given "target" 1237 * and "priority" will be changed to disable queueing. 1238 * 1239 * Upon return from the hcall(), no additional interrupts will be 1240 * directed to the old EQ (if one was set). The old EQ (if one was 1241 * set) should be investigated for interrupts that occurred prior to 1242 * or during the hcall(). 1243 * 1244 * Parameters: 1245 * Input: 1246 * - R4: "flags" 1247 * Bits 0-62: Reserved 1248 * Bit 63: Unconditional Notify (n) per the XIVE spec 1249 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1250 * "ibm,ppc-interrupt-gserver#s" 1251 * - R6: "priority" is a valid priority not in 1252 * "ibm,plat-res-int-priorities" 1253 * - R7: "eventQueue": The logical real address of the start of the EQ 1254 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1255 * 1256 * Output: 1257 * - None 1258 */ 1259 1260 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1261 1262 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1263 SpaprMachineState *spapr, 1264 target_ulong opcode, 1265 target_ulong *args) 1266 { 1267 SpaprXive *xive = spapr->xive; 1268 target_ulong flags = args[0]; 1269 target_ulong target = args[1]; 1270 target_ulong priority = args[2]; 1271 target_ulong qpage = args[3]; 1272 target_ulong qsize = args[4]; 1273 XiveEND end; 1274 uint8_t end_blk, nvt_blk; 1275 uint32_t end_idx, nvt_idx; 1276 1277 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1278 return H_FUNCTION; 1279 } 1280 1281 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1282 return H_PARAMETER; 1283 } 1284 1285 /* 1286 * H_STATE should be returned if a H_INT_RESET is in progress. 1287 * This is not needed when running the emulation under QEMU 1288 */ 1289 1290 if (spapr_xive_priority_is_reserved(priority)) { 1291 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1292 " is reserved\n", priority); 1293 return H_P3; 1294 } 1295 1296 /* 1297 * Validate that "target" is part of the list of threads allocated 1298 * to the partition. For that, find the END corresponding to the 1299 * target. 1300 */ 1301 1302 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1303 return H_P2; 1304 } 1305 1306 assert(end_idx < xive->nr_ends); 1307 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1308 1309 switch (qsize) { 1310 case 12: 1311 case 16: 1312 case 21: 1313 case 24: 1314 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1315 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1316 " is not naturally aligned with %" HWADDR_PRIx "\n", 1317 qpage, (hwaddr)1 << qsize); 1318 return H_P4; 1319 } 1320 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1321 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1322 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1323 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1324 break; 1325 case 0: 1326 /* reset queue and disable queueing */ 1327 spapr_xive_end_reset(&end); 1328 goto out; 1329 1330 default: 1331 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1332 qsize); 1333 return H_P5; 1334 } 1335 1336 if (qsize) { 1337 hwaddr plen = 1 << qsize; 1338 void *eq; 1339 1340 /* 1341 * Validate the guest EQ. We should also check that the queue 1342 * has been zeroed by the OS. 1343 */ 1344 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1345 MEMTXATTRS_UNSPECIFIED); 1346 if (plen != 1 << qsize) { 1347 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1348 HWADDR_PRIx "\n", qpage); 1349 return H_P4; 1350 } 1351 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1352 } 1353 1354 /* "target" should have been validated above */ 1355 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1356 g_assert_not_reached(); 1357 } 1358 1359 /* 1360 * Ensure the priority and target are correctly set (they will not 1361 * be right after allocation) 1362 */ 1363 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1364 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1365 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1366 1367 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1368 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1369 } else { 1370 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1371 } 1372 1373 /* 1374 * The generation bit for the END starts at 1 and The END page 1375 * offset counter starts at 0. 1376 */ 1377 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1378 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1379 end.w0 |= cpu_to_be32(END_W0_VALID); 1380 1381 /* 1382 * TODO: issue syncs required to ensure all in-flight interrupts 1383 * are complete on the old END 1384 */ 1385 1386 out: 1387 if (kvm_irqchip_in_kernel()) { 1388 Error *local_err = NULL; 1389 1390 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1391 if (local_err) { 1392 error_report_err(local_err); 1393 return H_HARDWARE; 1394 } 1395 } 1396 1397 /* Update END */ 1398 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1399 return H_SUCCESS; 1400 } 1401 1402 /* 1403 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1404 * target and priority. 1405 * 1406 * Parameters: 1407 * Input: 1408 * - R4: "flags" 1409 * Bits 0-62: Reserved 1410 * Bit 63: Debug: Return debug data 1411 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1412 * "ibm,ppc-interrupt-gserver#s" 1413 * - R6: "priority" is a valid priority not in 1414 * "ibm,plat-res-int-priorities" 1415 * 1416 * Output: 1417 * - R4: "flags": 1418 * Bits 0-61: Reserved 1419 * Bit 62: The value of Event Queue Generation Number (g) per 1420 * the XIVE spec if "Debug" = 1 1421 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1422 * - R5: The logical real address of the start of the EQ 1423 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1424 * - R7: The value of Event Queue Offset Counter per XIVE spec 1425 * if "Debug" = 1, else 0 1426 * 1427 */ 1428 1429 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1430 1431 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1432 SpaprMachineState *spapr, 1433 target_ulong opcode, 1434 target_ulong *args) 1435 { 1436 SpaprXive *xive = spapr->xive; 1437 target_ulong flags = args[0]; 1438 target_ulong target = args[1]; 1439 target_ulong priority = args[2]; 1440 XiveEND *end; 1441 uint8_t end_blk; 1442 uint32_t end_idx; 1443 1444 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1445 return H_FUNCTION; 1446 } 1447 1448 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1449 return H_PARAMETER; 1450 } 1451 1452 /* 1453 * H_STATE should be returned if a H_INT_RESET is in progress. 1454 * This is not needed when running the emulation under QEMU 1455 */ 1456 1457 if (spapr_xive_priority_is_reserved(priority)) { 1458 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1459 " is reserved\n", priority); 1460 return H_P3; 1461 } 1462 1463 /* 1464 * Validate that "target" is part of the list of threads allocated 1465 * to the partition. For that, find the END corresponding to the 1466 * target. 1467 */ 1468 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1469 return H_P2; 1470 } 1471 1472 assert(end_idx < xive->nr_ends); 1473 end = &xive->endt[end_idx]; 1474 1475 args[0] = 0; 1476 if (xive_end_is_notify(end)) { 1477 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1478 } 1479 1480 if (xive_end_is_enqueue(end)) { 1481 args[1] = xive_end_qaddr(end); 1482 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1483 } else { 1484 args[1] = 0; 1485 args[2] = 0; 1486 } 1487 1488 if (kvm_irqchip_in_kernel()) { 1489 Error *local_err = NULL; 1490 1491 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1492 if (local_err) { 1493 error_report_err(local_err); 1494 return H_HARDWARE; 1495 } 1496 } 1497 1498 /* TODO: do we need any locking on the END ? */ 1499 if (flags & SPAPR_XIVE_END_DEBUG) { 1500 /* Load the event queue generation number into the return flags */ 1501 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1502 1503 /* Load R7 with the event queue offset counter */ 1504 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1505 } else { 1506 args[3] = 0; 1507 } 1508 1509 return H_SUCCESS; 1510 } 1511 1512 /* 1513 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1514 * reporting cache line pair for the calling thread. The reporting 1515 * cache lines will contain the OS interrupt context when the OS 1516 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1517 * interrupt. The reporting cache lines can be reset by inputting -1 1518 * in "reportingLine". Issuing the CI store byte without reporting 1519 * cache lines registered will result in the data not being accessible 1520 * to the OS. 1521 * 1522 * Parameters: 1523 * Input: 1524 * - R4: "flags" 1525 * Bits 0-63: Reserved 1526 * - R5: "reportingLine": The logical real address of the reporting cache 1527 * line pair 1528 * 1529 * Output: 1530 * - None 1531 */ 1532 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1533 SpaprMachineState *spapr, 1534 target_ulong opcode, 1535 target_ulong *args) 1536 { 1537 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1538 return H_FUNCTION; 1539 } 1540 1541 /* 1542 * H_STATE should be returned if a H_INT_RESET is in progress. 1543 * This is not needed when running the emulation under QEMU 1544 */ 1545 1546 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1547 return H_FUNCTION; 1548 } 1549 1550 /* 1551 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1552 * real address of the reporting cache line pair set for the input 1553 * "target". If no reporting cache line pair has been set, -1 is 1554 * returned. 1555 * 1556 * Parameters: 1557 * Input: 1558 * - R4: "flags" 1559 * Bits 0-63: Reserved 1560 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1561 * "ibm,ppc-interrupt-gserver#s" 1562 * - R6: "reportingLine": The logical real address of the reporting 1563 * cache line pair 1564 * 1565 * Output: 1566 * - R4: The logical real address of the reporting line if set, else -1 1567 */ 1568 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1569 SpaprMachineState *spapr, 1570 target_ulong opcode, 1571 target_ulong *args) 1572 { 1573 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1574 return H_FUNCTION; 1575 } 1576 1577 /* 1578 * H_STATE should be returned if a H_INT_RESET is in progress. 1579 * This is not needed when running the emulation under QEMU 1580 */ 1581 1582 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1583 return H_FUNCTION; 1584 } 1585 1586 /* 1587 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1588 * page for the input "lisn". This hcall is only supported for LISNs 1589 * that have the ESB hcall flag set to 1 when returned from hcall() 1590 * H_INT_GET_SOURCE_INFO. 1591 * 1592 * Parameters: 1593 * Input: 1594 * - R4: "flags" 1595 * Bits 0-62: Reserved 1596 * bit 63: Store: Store=1, store operation, else load operation 1597 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1598 * "ibm,xive-lisn-ranges" properties, or as returned by the 1599 * ibm,query-interrupt-source-number RTAS call, or as 1600 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1601 * - R6: "esbOffset" is the offset into the ESB page for the load or 1602 * store operation 1603 * - R7: "storeData" is the data to write for a store operation 1604 * 1605 * Output: 1606 * - R4: The value of the load if load operation, else -1 1607 */ 1608 1609 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1610 1611 static target_ulong h_int_esb(PowerPCCPU *cpu, 1612 SpaprMachineState *spapr, 1613 target_ulong opcode, 1614 target_ulong *args) 1615 { 1616 SpaprXive *xive = spapr->xive; 1617 XiveEAS eas; 1618 target_ulong flags = args[0]; 1619 target_ulong lisn = args[1]; 1620 target_ulong offset = args[2]; 1621 target_ulong data = args[3]; 1622 hwaddr mmio_addr; 1623 XiveSource *xsrc = &xive->source; 1624 1625 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1626 return H_FUNCTION; 1627 } 1628 1629 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1630 return H_PARAMETER; 1631 } 1632 1633 if (lisn >= xive->nr_irqs) { 1634 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1635 lisn); 1636 return H_P2; 1637 } 1638 1639 eas = xive->eat[lisn]; 1640 if (!xive_eas_is_valid(&eas)) { 1641 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1642 lisn); 1643 return H_P2; 1644 } 1645 1646 if (offset > (1ull << xsrc->esb_shift)) { 1647 return H_P3; 1648 } 1649 1650 if (kvm_irqchip_in_kernel()) { 1651 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1652 flags & SPAPR_XIVE_ESB_STORE); 1653 } else { 1654 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1655 1656 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1657 (flags & SPAPR_XIVE_ESB_STORE))) { 1658 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1659 HWADDR_PRIx "\n", mmio_addr); 1660 return H_HARDWARE; 1661 } 1662 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1663 } 1664 return H_SUCCESS; 1665 } 1666 1667 /* 1668 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1669 * ensure any in flight events for the input lisn are in the event 1670 * queue. 1671 * 1672 * Parameters: 1673 * Input: 1674 * - R4: "flags" 1675 * Bits 0-63: Reserved 1676 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1677 * "ibm,xive-lisn-ranges" properties, or as returned by the 1678 * ibm,query-interrupt-source-number RTAS call, or as 1679 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1680 * 1681 * Output: 1682 * - None 1683 */ 1684 static target_ulong h_int_sync(PowerPCCPU *cpu, 1685 SpaprMachineState *spapr, 1686 target_ulong opcode, 1687 target_ulong *args) 1688 { 1689 SpaprXive *xive = spapr->xive; 1690 XiveEAS eas; 1691 target_ulong flags = args[0]; 1692 target_ulong lisn = args[1]; 1693 1694 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1695 return H_FUNCTION; 1696 } 1697 1698 if (flags) { 1699 return H_PARAMETER; 1700 } 1701 1702 if (lisn >= xive->nr_irqs) { 1703 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1704 lisn); 1705 return H_P2; 1706 } 1707 1708 eas = xive->eat[lisn]; 1709 if (!xive_eas_is_valid(&eas)) { 1710 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1711 lisn); 1712 return H_P2; 1713 } 1714 1715 /* 1716 * H_STATE should be returned if a H_INT_RESET is in progress. 1717 * This is not needed when running the emulation under QEMU 1718 */ 1719 1720 /* 1721 * This is not real hardware. Nothing to be done unless when 1722 * under KVM 1723 */ 1724 1725 if (kvm_irqchip_in_kernel()) { 1726 Error *local_err = NULL; 1727 1728 kvmppc_xive_sync_source(xive, lisn, &local_err); 1729 if (local_err) { 1730 error_report_err(local_err); 1731 return H_HARDWARE; 1732 } 1733 } 1734 return H_SUCCESS; 1735 } 1736 1737 /* 1738 * The H_INT_RESET hcall() is used to reset all of the partition's 1739 * interrupt exploitation structures to their initial state. This 1740 * means losing all previously set interrupt state set via 1741 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1742 * 1743 * Parameters: 1744 * Input: 1745 * - R4: "flags" 1746 * Bits 0-63: Reserved 1747 * 1748 * Output: 1749 * - None 1750 */ 1751 static target_ulong h_int_reset(PowerPCCPU *cpu, 1752 SpaprMachineState *spapr, 1753 target_ulong opcode, 1754 target_ulong *args) 1755 { 1756 SpaprXive *xive = spapr->xive; 1757 target_ulong flags = args[0]; 1758 1759 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1760 return H_FUNCTION; 1761 } 1762 1763 if (flags) { 1764 return H_PARAMETER; 1765 } 1766 1767 device_legacy_reset(DEVICE(xive)); 1768 1769 if (kvm_irqchip_in_kernel()) { 1770 Error *local_err = NULL; 1771 1772 kvmppc_xive_reset(xive, &local_err); 1773 if (local_err) { 1774 error_report_err(local_err); 1775 return H_HARDWARE; 1776 } 1777 } 1778 return H_SUCCESS; 1779 } 1780 1781 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1782 { 1783 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1784 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1785 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1786 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1787 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1788 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1789 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1790 h_int_set_os_reporting_line); 1791 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1792 h_int_get_os_reporting_line); 1793 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1794 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1795 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1796 } 1797