1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 } 150 151 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 152 { 153 XiveSource *xsrc = &xive->source; 154 int i; 155 156 if (kvm_irqchip_in_kernel()) { 157 Error *local_err = NULL; 158 159 kvmppc_xive_synchronize_state(xive, &local_err); 160 if (local_err) { 161 error_report_err(local_err); 162 return; 163 } 164 } 165 166 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 167 168 for (i = 0; i < xive->nr_irqs; i++) { 169 uint8_t pq = xive_source_esb_get(xsrc, i); 170 XiveEAS *eas = &xive->eat[i]; 171 172 if (!xive_eas_is_valid(eas)) { 173 continue; 174 } 175 176 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 177 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 178 pq & XIVE_ESB_VAL_P ? 'P' : '-', 179 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 180 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 181 xive_eas_is_masked(eas) ? "M" : " ", 182 (int) xive_get_field64(EAS_END_DATA, eas->w)); 183 184 if (!xive_eas_is_masked(eas)) { 185 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 186 XiveEND *end; 187 188 assert(end_idx < xive->nr_ends); 189 end = &xive->endt[end_idx]; 190 191 if (xive_end_is_valid(end)) { 192 spapr_xive_end_pic_print_info(xive, end, mon); 193 } 194 } 195 monitor_printf(mon, "\n"); 196 } 197 } 198 199 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 200 { 201 memory_region_set_enabled(&xive->source.esb_mmio, enable); 202 memory_region_set_enabled(&xive->tm_mmio, enable); 203 204 /* Disable the END ESBs until a guest OS makes use of them */ 205 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 206 } 207 208 /* 209 * When a Virtual Processor is scheduled to run on a HW thread, the 210 * hypervisor pushes its identifier in the OS CAM line. Emulate the 211 * same behavior under QEMU. 212 */ 213 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 214 { 215 uint8_t nvt_blk; 216 uint32_t nvt_idx; 217 uint32_t nvt_cam; 218 219 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 220 221 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 222 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 223 } 224 225 static void spapr_xive_end_reset(XiveEND *end) 226 { 227 memset(end, 0, sizeof(*end)); 228 229 /* switch off the escalation and notification ESBs */ 230 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 231 } 232 233 static void spapr_xive_reset(void *dev) 234 { 235 SpaprXive *xive = SPAPR_XIVE(dev); 236 int i; 237 238 /* 239 * The XiveSource has its own reset handler, which mask off all 240 * IRQs (!P|Q) 241 */ 242 243 /* Mask all valid EASs in the IRQ number space. */ 244 for (i = 0; i < xive->nr_irqs; i++) { 245 XiveEAS *eas = &xive->eat[i]; 246 if (xive_eas_is_valid(eas)) { 247 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 248 } else { 249 eas->w = 0; 250 } 251 } 252 253 /* Clear all ENDs */ 254 for (i = 0; i < xive->nr_ends; i++) { 255 spapr_xive_end_reset(&xive->endt[i]); 256 } 257 } 258 259 static void spapr_xive_instance_init(Object *obj) 260 { 261 SpaprXive *xive = SPAPR_XIVE(obj); 262 263 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 264 TYPE_XIVE_SOURCE, &error_abort, NULL); 265 266 object_initialize_child(obj, "end_source", &xive->end_source, 267 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 268 &error_abort, NULL); 269 270 /* Not connected to the KVM XIVE device */ 271 xive->fd = -1; 272 } 273 274 static void spapr_xive_realize(DeviceState *dev, Error **errp) 275 { 276 SpaprXive *xive = SPAPR_XIVE(dev); 277 XiveSource *xsrc = &xive->source; 278 XiveENDSource *end_xsrc = &xive->end_source; 279 Error *local_err = NULL; 280 281 if (!xive->nr_irqs) { 282 error_setg(errp, "Number of interrupt needs to be greater 0"); 283 return; 284 } 285 286 if (!xive->nr_ends) { 287 error_setg(errp, "Number of interrupt needs to be greater 0"); 288 return; 289 } 290 291 /* 292 * Initialize the internal sources, for IPIs and virtual devices. 293 */ 294 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 295 &error_fatal); 296 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 297 &error_fatal); 298 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 299 if (local_err) { 300 error_propagate(errp, local_err); 301 return; 302 } 303 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 304 305 /* 306 * Initialize the END ESB source 307 */ 308 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 309 &error_fatal); 310 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 311 &error_fatal); 312 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 313 if (local_err) { 314 error_propagate(errp, local_err); 315 return; 316 } 317 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 318 319 /* Set the mapping address of the END ESB pages after the source ESBs */ 320 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 321 322 /* 323 * Allocate the routing tables 324 */ 325 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 326 xive->endt = g_new0(XiveEND, xive->nr_ends); 327 328 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 329 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 330 331 qemu_register_reset(spapr_xive_reset, dev); 332 333 /* TIMA initialization */ 334 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 335 "xive.tima", 4ull << TM_SHIFT); 336 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 337 338 /* 339 * Map all regions. These will be enabled or disabled at reset and 340 * can also be overridden by KVM memory regions if active 341 */ 342 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 343 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 344 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 345 } 346 347 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 348 uint32_t eas_idx, XiveEAS *eas) 349 { 350 SpaprXive *xive = SPAPR_XIVE(xrtr); 351 352 if (eas_idx >= xive->nr_irqs) { 353 return -1; 354 } 355 356 *eas = xive->eat[eas_idx]; 357 return 0; 358 } 359 360 static int spapr_xive_get_end(XiveRouter *xrtr, 361 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 362 { 363 SpaprXive *xive = SPAPR_XIVE(xrtr); 364 365 if (end_idx >= xive->nr_ends) { 366 return -1; 367 } 368 369 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 370 return 0; 371 } 372 373 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 374 uint32_t end_idx, XiveEND *end, 375 uint8_t word_number) 376 { 377 SpaprXive *xive = SPAPR_XIVE(xrtr); 378 379 if (end_idx >= xive->nr_ends) { 380 return -1; 381 } 382 383 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 384 return 0; 385 } 386 387 static int spapr_xive_get_nvt(XiveRouter *xrtr, 388 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 389 { 390 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 391 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 392 393 if (!cpu) { 394 /* TODO: should we assert() if we can find a NVT ? */ 395 return -1; 396 } 397 398 /* 399 * sPAPR does not maintain a NVT table. Return that the NVT is 400 * valid if we have found a matching CPU 401 */ 402 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 403 return 0; 404 } 405 406 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 407 uint32_t nvt_idx, XiveNVT *nvt, 408 uint8_t word_number) 409 { 410 /* 411 * We don't need to write back to the NVTs because the sPAPR 412 * machine should never hit a non-scheduled NVT. It should never 413 * get called. 414 */ 415 g_assert_not_reached(); 416 } 417 418 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 419 { 420 PowerPCCPU *cpu = POWERPC_CPU(cs); 421 422 return spapr_cpu_state(cpu)->tctx; 423 } 424 425 static const VMStateDescription vmstate_spapr_xive_end = { 426 .name = TYPE_SPAPR_XIVE "/end", 427 .version_id = 1, 428 .minimum_version_id = 1, 429 .fields = (VMStateField []) { 430 VMSTATE_UINT32(w0, XiveEND), 431 VMSTATE_UINT32(w1, XiveEND), 432 VMSTATE_UINT32(w2, XiveEND), 433 VMSTATE_UINT32(w3, XiveEND), 434 VMSTATE_UINT32(w4, XiveEND), 435 VMSTATE_UINT32(w5, XiveEND), 436 VMSTATE_UINT32(w6, XiveEND), 437 VMSTATE_UINT32(w7, XiveEND), 438 VMSTATE_END_OF_LIST() 439 }, 440 }; 441 442 static const VMStateDescription vmstate_spapr_xive_eas = { 443 .name = TYPE_SPAPR_XIVE "/eas", 444 .version_id = 1, 445 .minimum_version_id = 1, 446 .fields = (VMStateField []) { 447 VMSTATE_UINT64(w, XiveEAS), 448 VMSTATE_END_OF_LIST() 449 }, 450 }; 451 452 static int vmstate_spapr_xive_pre_save(void *opaque) 453 { 454 if (kvm_irqchip_in_kernel()) { 455 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 456 } 457 458 return 0; 459 } 460 461 /* 462 * Called by the sPAPR IRQ backend 'post_load' method at the machine 463 * level. 464 */ 465 int spapr_xive_post_load(SpaprXive *xive, int version_id) 466 { 467 if (kvm_irqchip_in_kernel()) { 468 return kvmppc_xive_post_load(xive, version_id); 469 } 470 471 return 0; 472 } 473 474 static const VMStateDescription vmstate_spapr_xive = { 475 .name = TYPE_SPAPR_XIVE, 476 .version_id = 1, 477 .minimum_version_id = 1, 478 .pre_save = vmstate_spapr_xive_pre_save, 479 .post_load = NULL, /* handled at the machine level */ 480 .fields = (VMStateField[]) { 481 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 482 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 483 vmstate_spapr_xive_eas, XiveEAS), 484 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 485 vmstate_spapr_xive_end, XiveEND), 486 VMSTATE_END_OF_LIST() 487 }, 488 }; 489 490 static Property spapr_xive_properties[] = { 491 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 492 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 493 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 494 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 495 DEFINE_PROP_END_OF_LIST(), 496 }; 497 498 static void spapr_xive_class_init(ObjectClass *klass, void *data) 499 { 500 DeviceClass *dc = DEVICE_CLASS(klass); 501 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 502 503 dc->desc = "sPAPR XIVE Interrupt Controller"; 504 dc->props = spapr_xive_properties; 505 dc->realize = spapr_xive_realize; 506 dc->vmsd = &vmstate_spapr_xive; 507 508 xrc->get_eas = spapr_xive_get_eas; 509 xrc->get_end = spapr_xive_get_end; 510 xrc->write_end = spapr_xive_write_end; 511 xrc->get_nvt = spapr_xive_get_nvt; 512 xrc->write_nvt = spapr_xive_write_nvt; 513 xrc->get_tctx = spapr_xive_get_tctx; 514 } 515 516 static const TypeInfo spapr_xive_info = { 517 .name = TYPE_SPAPR_XIVE, 518 .parent = TYPE_XIVE_ROUTER, 519 .instance_init = spapr_xive_instance_init, 520 .instance_size = sizeof(SpaprXive), 521 .class_init = spapr_xive_class_init, 522 }; 523 524 static void spapr_xive_register_types(void) 525 { 526 type_register_static(&spapr_xive_info); 527 } 528 529 type_init(spapr_xive_register_types) 530 531 bool spapr_xive_irq_claim(SpaprXive *xive, uint32_t lisn, bool lsi) 532 { 533 XiveSource *xsrc = &xive->source; 534 535 if (lisn >= xive->nr_irqs) { 536 return false; 537 } 538 539 /* 540 * Set default values when allocating an IRQ number 541 */ 542 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); 543 if (lsi) { 544 xive_source_irq_set_lsi(xsrc, lisn); 545 } 546 547 if (kvm_irqchip_in_kernel()) { 548 Error *local_err = NULL; 549 550 kvmppc_xive_source_reset_one(xsrc, lisn, &local_err); 551 if (local_err) { 552 error_report_err(local_err); 553 return false; 554 } 555 } 556 557 return true; 558 } 559 560 bool spapr_xive_irq_free(SpaprXive *xive, uint32_t lisn) 561 { 562 if (lisn >= xive->nr_irqs) { 563 return false; 564 } 565 566 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 567 return true; 568 } 569 570 /* 571 * XIVE hcalls 572 * 573 * The terminology used by the XIVE hcalls is the following : 574 * 575 * TARGET vCPU number 576 * EQ Event Queue assigned by OS to receive event data 577 * ESB page for source interrupt management 578 * LISN Logical Interrupt Source Number identifying a source in the 579 * machine 580 * EISN Effective Interrupt Source Number used by guest OS to 581 * identify source in the guest 582 * 583 * The EAS, END, NVT structures are not exposed. 584 */ 585 586 /* 587 * Linux hosts under OPAL reserve priority 7 for their own escalation 588 * interrupts (DD2.X POWER9). So we only allow the guest to use 589 * priorities [0..6]. 590 */ 591 static bool spapr_xive_priority_is_reserved(uint8_t priority) 592 { 593 switch (priority) { 594 case 0 ... 6: 595 return false; 596 case 7: /* OPAL escalation queue */ 597 default: 598 return true; 599 } 600 } 601 602 /* 603 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 604 * real address of the MMIO page through which the Event State Buffer 605 * entry associated with the value of the "lisn" parameter is managed. 606 * 607 * Parameters: 608 * Input 609 * - R4: "flags" 610 * Bits 0-63 reserved 611 * - R5: "lisn" is per "interrupts", "interrupt-map", or 612 * "ibm,xive-lisn-ranges" properties, or as returned by the 613 * ibm,query-interrupt-source-number RTAS call, or as returned 614 * by the H_ALLOCATE_VAS_WINDOW hcall 615 * 616 * Output 617 * - R4: "flags" 618 * Bits 0-59: Reserved 619 * Bit 60: H_INT_ESB must be used for Event State Buffer 620 * management 621 * Bit 61: 1 == LSI 0 == MSI 622 * Bit 62: the full function page supports trigger 623 * Bit 63: Store EOI Supported 624 * - R5: Logical Real address of full function Event State Buffer 625 * management page, -1 if H_INT_ESB hcall flag is set to 1. 626 * - R6: Logical Real Address of trigger only Event State Buffer 627 * management page or -1. 628 * - R7: Power of 2 page size for the ESB management pages returned in 629 * R5 and R6. 630 */ 631 632 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 633 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 634 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 635 on same page */ 636 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 637 638 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 639 SpaprMachineState *spapr, 640 target_ulong opcode, 641 target_ulong *args) 642 { 643 SpaprXive *xive = spapr->xive; 644 XiveSource *xsrc = &xive->source; 645 target_ulong flags = args[0]; 646 target_ulong lisn = args[1]; 647 648 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 649 return H_FUNCTION; 650 } 651 652 if (flags) { 653 return H_PARAMETER; 654 } 655 656 if (lisn >= xive->nr_irqs) { 657 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 658 lisn); 659 return H_P2; 660 } 661 662 if (!xive_eas_is_valid(&xive->eat[lisn])) { 663 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 664 lisn); 665 return H_P2; 666 } 667 668 /* 669 * All sources are emulated under the main XIVE object and share 670 * the same characteristics. 671 */ 672 args[0] = 0; 673 if (!xive_source_esb_has_2page(xsrc)) { 674 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 675 } 676 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 677 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 678 } 679 680 /* 681 * Force the use of the H_INT_ESB hcall in case of an LSI 682 * interrupt. This is necessary under KVM to re-trigger the 683 * interrupt if the level is still asserted 684 */ 685 if (xive_source_irq_is_lsi(xsrc, lisn)) { 686 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 687 } 688 689 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 690 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 691 } else { 692 args[1] = -1; 693 } 694 695 if (xive_source_esb_has_2page(xsrc) && 696 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 697 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 698 } else { 699 args[2] = -1; 700 } 701 702 if (xive_source_esb_has_2page(xsrc)) { 703 args[3] = xsrc->esb_shift - 1; 704 } else { 705 args[3] = xsrc->esb_shift; 706 } 707 708 return H_SUCCESS; 709 } 710 711 /* 712 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 713 * Interrupt Source to a target. The Logical Interrupt Source is 714 * designated with the "lisn" parameter and the target is designated 715 * with the "target" and "priority" parameters. Upon return from the 716 * hcall(), no additional interrupts will be directed to the old EQ. 717 * 718 * Parameters: 719 * Input: 720 * - R4: "flags" 721 * Bits 0-61: Reserved 722 * Bit 62: set the "eisn" in the EAS 723 * Bit 63: masks the interrupt source in the hardware interrupt 724 * control structure. An interrupt masked by this mechanism will 725 * be dropped, but it's source state bits will still be 726 * set. There is no race-free way of unmasking and restoring the 727 * source. Thus this should only be used in interrupts that are 728 * also masked at the source, and only in cases where the 729 * interrupt is not meant to be used for a large amount of time 730 * because no valid target exists for it for example 731 * - R5: "lisn" is per "interrupts", "interrupt-map", or 732 * "ibm,xive-lisn-ranges" properties, or as returned by the 733 * ibm,query-interrupt-source-number RTAS call, or as returned by 734 * the H_ALLOCATE_VAS_WINDOW hcall 735 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 736 * "ibm,ppc-interrupt-gserver#s" 737 * - R7: "priority" is a valid priority not in 738 * "ibm,plat-res-int-priorities" 739 * - R8: "eisn" is the guest EISN associated with the "lisn" 740 * 741 * Output: 742 * - None 743 */ 744 745 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 746 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 747 748 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 749 SpaprMachineState *spapr, 750 target_ulong opcode, 751 target_ulong *args) 752 { 753 SpaprXive *xive = spapr->xive; 754 XiveEAS eas, new_eas; 755 target_ulong flags = args[0]; 756 target_ulong lisn = args[1]; 757 target_ulong target = args[2]; 758 target_ulong priority = args[3]; 759 target_ulong eisn = args[4]; 760 uint8_t end_blk; 761 uint32_t end_idx; 762 763 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 764 return H_FUNCTION; 765 } 766 767 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 768 return H_PARAMETER; 769 } 770 771 if (lisn >= xive->nr_irqs) { 772 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 773 lisn); 774 return H_P2; 775 } 776 777 eas = xive->eat[lisn]; 778 if (!xive_eas_is_valid(&eas)) { 779 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 780 lisn); 781 return H_P2; 782 } 783 784 /* priority 0xff is used to reset the EAS */ 785 if (priority == 0xff) { 786 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 787 goto out; 788 } 789 790 if (flags & SPAPR_XIVE_SRC_MASK) { 791 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 792 } else { 793 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 794 } 795 796 if (spapr_xive_priority_is_reserved(priority)) { 797 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 798 " is reserved\n", priority); 799 return H_P4; 800 } 801 802 /* 803 * Validate that "target" is part of the list of threads allocated 804 * to the partition. For that, find the END corresponding to the 805 * target. 806 */ 807 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 808 return H_P3; 809 } 810 811 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 812 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 813 814 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 815 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 816 } 817 818 if (kvm_irqchip_in_kernel()) { 819 Error *local_err = NULL; 820 821 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 822 if (local_err) { 823 error_report_err(local_err); 824 return H_HARDWARE; 825 } 826 } 827 828 out: 829 xive->eat[lisn] = new_eas; 830 return H_SUCCESS; 831 } 832 833 /* 834 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 835 * target/priority pair is assigned to the specified Logical Interrupt 836 * Source. 837 * 838 * Parameters: 839 * Input: 840 * - R4: "flags" 841 * Bits 0-63 Reserved 842 * - R5: "lisn" is per "interrupts", "interrupt-map", or 843 * "ibm,xive-lisn-ranges" properties, or as returned by the 844 * ibm,query-interrupt-source-number RTAS call, or as 845 * returned by the H_ALLOCATE_VAS_WINDOW hcall 846 * 847 * Output: 848 * - R4: Target to which the specified Logical Interrupt Source is 849 * assigned 850 * - R5: Priority to which the specified Logical Interrupt Source is 851 * assigned 852 * - R6: EISN for the specified Logical Interrupt Source (this will be 853 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 854 */ 855 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 856 SpaprMachineState *spapr, 857 target_ulong opcode, 858 target_ulong *args) 859 { 860 SpaprXive *xive = spapr->xive; 861 target_ulong flags = args[0]; 862 target_ulong lisn = args[1]; 863 XiveEAS eas; 864 XiveEND *end; 865 uint8_t nvt_blk; 866 uint32_t end_idx, nvt_idx; 867 868 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 869 return H_FUNCTION; 870 } 871 872 if (flags) { 873 return H_PARAMETER; 874 } 875 876 if (lisn >= xive->nr_irqs) { 877 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 878 lisn); 879 return H_P2; 880 } 881 882 eas = xive->eat[lisn]; 883 if (!xive_eas_is_valid(&eas)) { 884 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 885 lisn); 886 return H_P2; 887 } 888 889 /* EAS_END_BLOCK is unused on sPAPR */ 890 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 891 892 assert(end_idx < xive->nr_ends); 893 end = &xive->endt[end_idx]; 894 895 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 896 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 897 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 898 899 if (xive_eas_is_masked(&eas)) { 900 args[1] = 0xff; 901 } else { 902 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 903 } 904 905 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 906 907 return H_SUCCESS; 908 } 909 910 /* 911 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 912 * address of the notification management page associated with the 913 * specified target and priority. 914 * 915 * Parameters: 916 * Input: 917 * - R4: "flags" 918 * Bits 0-63 Reserved 919 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 920 * "ibm,ppc-interrupt-gserver#s" 921 * - R6: "priority" is a valid priority not in 922 * "ibm,plat-res-int-priorities" 923 * 924 * Output: 925 * - R4: Logical real address of notification page 926 * - R5: Power of 2 page size of the notification page 927 */ 928 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 929 SpaprMachineState *spapr, 930 target_ulong opcode, 931 target_ulong *args) 932 { 933 SpaprXive *xive = spapr->xive; 934 XiveENDSource *end_xsrc = &xive->end_source; 935 target_ulong flags = args[0]; 936 target_ulong target = args[1]; 937 target_ulong priority = args[2]; 938 XiveEND *end; 939 uint8_t end_blk; 940 uint32_t end_idx; 941 942 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 943 return H_FUNCTION; 944 } 945 946 if (flags) { 947 return H_PARAMETER; 948 } 949 950 /* 951 * H_STATE should be returned if a H_INT_RESET is in progress. 952 * This is not needed when running the emulation under QEMU 953 */ 954 955 if (spapr_xive_priority_is_reserved(priority)) { 956 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 957 " is reserved\n", priority); 958 return H_P3; 959 } 960 961 /* 962 * Validate that "target" is part of the list of threads allocated 963 * to the partition. For that, find the END corresponding to the 964 * target. 965 */ 966 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 967 return H_P2; 968 } 969 970 assert(end_idx < xive->nr_ends); 971 end = &xive->endt[end_idx]; 972 973 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 974 if (xive_end_is_enqueue(end)) { 975 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 976 } else { 977 args[1] = 0; 978 } 979 980 return H_SUCCESS; 981 } 982 983 /* 984 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 985 * a given "target" and "priority". It is also used to set the 986 * notification config associated with the EQ. An EQ size of 0 is 987 * used to reset the EQ config for a given target and priority. If 988 * resetting the EQ config, the END associated with the given "target" 989 * and "priority" will be changed to disable queueing. 990 * 991 * Upon return from the hcall(), no additional interrupts will be 992 * directed to the old EQ (if one was set). The old EQ (if one was 993 * set) should be investigated for interrupts that occurred prior to 994 * or during the hcall(). 995 * 996 * Parameters: 997 * Input: 998 * - R4: "flags" 999 * Bits 0-62: Reserved 1000 * Bit 63: Unconditional Notify (n) per the XIVE spec 1001 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1002 * "ibm,ppc-interrupt-gserver#s" 1003 * - R6: "priority" is a valid priority not in 1004 * "ibm,plat-res-int-priorities" 1005 * - R7: "eventQueue": The logical real address of the start of the EQ 1006 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1007 * 1008 * Output: 1009 * - None 1010 */ 1011 1012 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1013 1014 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1015 SpaprMachineState *spapr, 1016 target_ulong opcode, 1017 target_ulong *args) 1018 { 1019 SpaprXive *xive = spapr->xive; 1020 target_ulong flags = args[0]; 1021 target_ulong target = args[1]; 1022 target_ulong priority = args[2]; 1023 target_ulong qpage = args[3]; 1024 target_ulong qsize = args[4]; 1025 XiveEND end; 1026 uint8_t end_blk, nvt_blk; 1027 uint32_t end_idx, nvt_idx; 1028 1029 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1030 return H_FUNCTION; 1031 } 1032 1033 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1034 return H_PARAMETER; 1035 } 1036 1037 /* 1038 * H_STATE should be returned if a H_INT_RESET is in progress. 1039 * This is not needed when running the emulation under QEMU 1040 */ 1041 1042 if (spapr_xive_priority_is_reserved(priority)) { 1043 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1044 " is reserved\n", priority); 1045 return H_P3; 1046 } 1047 1048 /* 1049 * Validate that "target" is part of the list of threads allocated 1050 * to the partition. For that, find the END corresponding to the 1051 * target. 1052 */ 1053 1054 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1055 return H_P2; 1056 } 1057 1058 assert(end_idx < xive->nr_ends); 1059 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1060 1061 switch (qsize) { 1062 case 12: 1063 case 16: 1064 case 21: 1065 case 24: 1066 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1067 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1068 " is not naturally aligned with %" HWADDR_PRIx "\n", 1069 qpage, (hwaddr)1 << qsize); 1070 return H_P4; 1071 } 1072 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1073 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1074 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1075 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1076 break; 1077 case 0: 1078 /* reset queue and disable queueing */ 1079 spapr_xive_end_reset(&end); 1080 goto out; 1081 1082 default: 1083 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1084 qsize); 1085 return H_P5; 1086 } 1087 1088 if (qsize) { 1089 hwaddr plen = 1 << qsize; 1090 void *eq; 1091 1092 /* 1093 * Validate the guest EQ. We should also check that the queue 1094 * has been zeroed by the OS. 1095 */ 1096 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1097 MEMTXATTRS_UNSPECIFIED); 1098 if (plen != 1 << qsize) { 1099 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1100 HWADDR_PRIx "\n", qpage); 1101 return H_P4; 1102 } 1103 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1104 } 1105 1106 /* "target" should have been validated above */ 1107 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1108 g_assert_not_reached(); 1109 } 1110 1111 /* 1112 * Ensure the priority and target are correctly set (they will not 1113 * be right after allocation) 1114 */ 1115 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1116 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1117 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1118 1119 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1120 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1121 } else { 1122 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1123 } 1124 1125 /* 1126 * The generation bit for the END starts at 1 and The END page 1127 * offset counter starts at 0. 1128 */ 1129 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1130 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1131 end.w0 |= cpu_to_be32(END_W0_VALID); 1132 1133 /* 1134 * TODO: issue syncs required to ensure all in-flight interrupts 1135 * are complete on the old END 1136 */ 1137 1138 out: 1139 if (kvm_irqchip_in_kernel()) { 1140 Error *local_err = NULL; 1141 1142 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1143 if (local_err) { 1144 error_report_err(local_err); 1145 return H_HARDWARE; 1146 } 1147 } 1148 1149 /* Update END */ 1150 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1151 return H_SUCCESS; 1152 } 1153 1154 /* 1155 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1156 * target and priority. 1157 * 1158 * Parameters: 1159 * Input: 1160 * - R4: "flags" 1161 * Bits 0-62: Reserved 1162 * Bit 63: Debug: Return debug data 1163 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1164 * "ibm,ppc-interrupt-gserver#s" 1165 * - R6: "priority" is a valid priority not in 1166 * "ibm,plat-res-int-priorities" 1167 * 1168 * Output: 1169 * - R4: "flags": 1170 * Bits 0-61: Reserved 1171 * Bit 62: The value of Event Queue Generation Number (g) per 1172 * the XIVE spec if "Debug" = 1 1173 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1174 * - R5: The logical real address of the start of the EQ 1175 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1176 * - R7: The value of Event Queue Offset Counter per XIVE spec 1177 * if "Debug" = 1, else 0 1178 * 1179 */ 1180 1181 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1182 1183 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1184 SpaprMachineState *spapr, 1185 target_ulong opcode, 1186 target_ulong *args) 1187 { 1188 SpaprXive *xive = spapr->xive; 1189 target_ulong flags = args[0]; 1190 target_ulong target = args[1]; 1191 target_ulong priority = args[2]; 1192 XiveEND *end; 1193 uint8_t end_blk; 1194 uint32_t end_idx; 1195 1196 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1197 return H_FUNCTION; 1198 } 1199 1200 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1201 return H_PARAMETER; 1202 } 1203 1204 /* 1205 * H_STATE should be returned if a H_INT_RESET is in progress. 1206 * This is not needed when running the emulation under QEMU 1207 */ 1208 1209 if (spapr_xive_priority_is_reserved(priority)) { 1210 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1211 " is reserved\n", priority); 1212 return H_P3; 1213 } 1214 1215 /* 1216 * Validate that "target" is part of the list of threads allocated 1217 * to the partition. For that, find the END corresponding to the 1218 * target. 1219 */ 1220 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1221 return H_P2; 1222 } 1223 1224 assert(end_idx < xive->nr_ends); 1225 end = &xive->endt[end_idx]; 1226 1227 args[0] = 0; 1228 if (xive_end_is_notify(end)) { 1229 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1230 } 1231 1232 if (xive_end_is_enqueue(end)) { 1233 args[1] = xive_end_qaddr(end); 1234 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1235 } else { 1236 args[1] = 0; 1237 args[2] = 0; 1238 } 1239 1240 if (kvm_irqchip_in_kernel()) { 1241 Error *local_err = NULL; 1242 1243 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1244 if (local_err) { 1245 error_report_err(local_err); 1246 return H_HARDWARE; 1247 } 1248 } 1249 1250 /* TODO: do we need any locking on the END ? */ 1251 if (flags & SPAPR_XIVE_END_DEBUG) { 1252 /* Load the event queue generation number into the return flags */ 1253 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1254 1255 /* Load R7 with the event queue offset counter */ 1256 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1257 } else { 1258 args[3] = 0; 1259 } 1260 1261 return H_SUCCESS; 1262 } 1263 1264 /* 1265 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1266 * reporting cache line pair for the calling thread. The reporting 1267 * cache lines will contain the OS interrupt context when the OS 1268 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1269 * interrupt. The reporting cache lines can be reset by inputting -1 1270 * in "reportingLine". Issuing the CI store byte without reporting 1271 * cache lines registered will result in the data not being accessible 1272 * to the OS. 1273 * 1274 * Parameters: 1275 * Input: 1276 * - R4: "flags" 1277 * Bits 0-63: Reserved 1278 * - R5: "reportingLine": The logical real address of the reporting cache 1279 * line pair 1280 * 1281 * Output: 1282 * - None 1283 */ 1284 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1285 SpaprMachineState *spapr, 1286 target_ulong opcode, 1287 target_ulong *args) 1288 { 1289 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1290 return H_FUNCTION; 1291 } 1292 1293 /* 1294 * H_STATE should be returned if a H_INT_RESET is in progress. 1295 * This is not needed when running the emulation under QEMU 1296 */ 1297 1298 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1299 return H_FUNCTION; 1300 } 1301 1302 /* 1303 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1304 * real address of the reporting cache line pair set for the input 1305 * "target". If no reporting cache line pair has been set, -1 is 1306 * returned. 1307 * 1308 * Parameters: 1309 * Input: 1310 * - R4: "flags" 1311 * Bits 0-63: Reserved 1312 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1313 * "ibm,ppc-interrupt-gserver#s" 1314 * - R6: "reportingLine": The logical real address of the reporting 1315 * cache line pair 1316 * 1317 * Output: 1318 * - R4: The logical real address of the reporting line if set, else -1 1319 */ 1320 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1321 SpaprMachineState *spapr, 1322 target_ulong opcode, 1323 target_ulong *args) 1324 { 1325 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1326 return H_FUNCTION; 1327 } 1328 1329 /* 1330 * H_STATE should be returned if a H_INT_RESET is in progress. 1331 * This is not needed when running the emulation under QEMU 1332 */ 1333 1334 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1335 return H_FUNCTION; 1336 } 1337 1338 /* 1339 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1340 * page for the input "lisn". This hcall is only supported for LISNs 1341 * that have the ESB hcall flag set to 1 when returned from hcall() 1342 * H_INT_GET_SOURCE_INFO. 1343 * 1344 * Parameters: 1345 * Input: 1346 * - R4: "flags" 1347 * Bits 0-62: Reserved 1348 * bit 63: Store: Store=1, store operation, else load operation 1349 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1350 * "ibm,xive-lisn-ranges" properties, or as returned by the 1351 * ibm,query-interrupt-source-number RTAS call, or as 1352 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1353 * - R6: "esbOffset" is the offset into the ESB page for the load or 1354 * store operation 1355 * - R7: "storeData" is the data to write for a store operation 1356 * 1357 * Output: 1358 * - R4: The value of the load if load operation, else -1 1359 */ 1360 1361 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1362 1363 static target_ulong h_int_esb(PowerPCCPU *cpu, 1364 SpaprMachineState *spapr, 1365 target_ulong opcode, 1366 target_ulong *args) 1367 { 1368 SpaprXive *xive = spapr->xive; 1369 XiveEAS eas; 1370 target_ulong flags = args[0]; 1371 target_ulong lisn = args[1]; 1372 target_ulong offset = args[2]; 1373 target_ulong data = args[3]; 1374 hwaddr mmio_addr; 1375 XiveSource *xsrc = &xive->source; 1376 1377 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1378 return H_FUNCTION; 1379 } 1380 1381 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1382 return H_PARAMETER; 1383 } 1384 1385 if (lisn >= xive->nr_irqs) { 1386 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1387 lisn); 1388 return H_P2; 1389 } 1390 1391 eas = xive->eat[lisn]; 1392 if (!xive_eas_is_valid(&eas)) { 1393 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1394 lisn); 1395 return H_P2; 1396 } 1397 1398 if (offset > (1ull << xsrc->esb_shift)) { 1399 return H_P3; 1400 } 1401 1402 if (kvm_irqchip_in_kernel()) { 1403 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1404 flags & SPAPR_XIVE_ESB_STORE); 1405 } else { 1406 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1407 1408 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1409 (flags & SPAPR_XIVE_ESB_STORE))) { 1410 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1411 HWADDR_PRIx "\n", mmio_addr); 1412 return H_HARDWARE; 1413 } 1414 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1415 } 1416 return H_SUCCESS; 1417 } 1418 1419 /* 1420 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1421 * ensure any in flight events for the input lisn are in the event 1422 * queue. 1423 * 1424 * Parameters: 1425 * Input: 1426 * - R4: "flags" 1427 * Bits 0-63: Reserved 1428 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1429 * "ibm,xive-lisn-ranges" properties, or as returned by the 1430 * ibm,query-interrupt-source-number RTAS call, or as 1431 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1432 * 1433 * Output: 1434 * - None 1435 */ 1436 static target_ulong h_int_sync(PowerPCCPU *cpu, 1437 SpaprMachineState *spapr, 1438 target_ulong opcode, 1439 target_ulong *args) 1440 { 1441 SpaprXive *xive = spapr->xive; 1442 XiveEAS eas; 1443 target_ulong flags = args[0]; 1444 target_ulong lisn = args[1]; 1445 1446 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1447 return H_FUNCTION; 1448 } 1449 1450 if (flags) { 1451 return H_PARAMETER; 1452 } 1453 1454 if (lisn >= xive->nr_irqs) { 1455 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1456 lisn); 1457 return H_P2; 1458 } 1459 1460 eas = xive->eat[lisn]; 1461 if (!xive_eas_is_valid(&eas)) { 1462 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1463 lisn); 1464 return H_P2; 1465 } 1466 1467 /* 1468 * H_STATE should be returned if a H_INT_RESET is in progress. 1469 * This is not needed when running the emulation under QEMU 1470 */ 1471 1472 /* 1473 * This is not real hardware. Nothing to be done unless when 1474 * under KVM 1475 */ 1476 1477 if (kvm_irqchip_in_kernel()) { 1478 Error *local_err = NULL; 1479 1480 kvmppc_xive_sync_source(xive, lisn, &local_err); 1481 if (local_err) { 1482 error_report_err(local_err); 1483 return H_HARDWARE; 1484 } 1485 } 1486 return H_SUCCESS; 1487 } 1488 1489 /* 1490 * The H_INT_RESET hcall() is used to reset all of the partition's 1491 * interrupt exploitation structures to their initial state. This 1492 * means losing all previously set interrupt state set via 1493 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1494 * 1495 * Parameters: 1496 * Input: 1497 * - R4: "flags" 1498 * Bits 0-63: Reserved 1499 * 1500 * Output: 1501 * - None 1502 */ 1503 static target_ulong h_int_reset(PowerPCCPU *cpu, 1504 SpaprMachineState *spapr, 1505 target_ulong opcode, 1506 target_ulong *args) 1507 { 1508 SpaprXive *xive = spapr->xive; 1509 target_ulong flags = args[0]; 1510 1511 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1512 return H_FUNCTION; 1513 } 1514 1515 if (flags) { 1516 return H_PARAMETER; 1517 } 1518 1519 device_reset(DEVICE(xive)); 1520 1521 if (kvm_irqchip_in_kernel()) { 1522 Error *local_err = NULL; 1523 1524 kvmppc_xive_reset(xive, &local_err); 1525 if (local_err) { 1526 error_report_err(local_err); 1527 return H_HARDWARE; 1528 } 1529 } 1530 return H_SUCCESS; 1531 } 1532 1533 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1534 { 1535 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1536 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1537 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1538 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1539 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1540 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1541 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1542 h_int_set_os_reporting_line); 1543 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1544 h_int_get_os_reporting_line); 1545 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1546 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1547 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1548 } 1549 1550 void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, 1551 uint32_t phandle) 1552 { 1553 SpaprXive *xive = spapr->xive; 1554 int node; 1555 uint64_t timas[2 * 2]; 1556 /* Interrupt number ranges for the IPIs */ 1557 uint32_t lisn_ranges[] = { 1558 cpu_to_be32(0), 1559 cpu_to_be32(nr_servers), 1560 }; 1561 /* 1562 * EQ size - the sizes of pages supported by the system 4K, 64K, 1563 * 2M, 16M. We only advertise 64K for the moment. 1564 */ 1565 uint32_t eq_sizes[] = { 1566 cpu_to_be32(16), /* 64K */ 1567 }; 1568 /* 1569 * The following array is in sync with the reserved priorities 1570 * defined by the 'spapr_xive_priority_is_reserved' routine. 1571 */ 1572 uint32_t plat_res_int_priorities[] = { 1573 cpu_to_be32(7), /* start */ 1574 cpu_to_be32(0xf8), /* count */ 1575 }; 1576 1577 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 1578 timas[0] = cpu_to_be64(xive->tm_base + 1579 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 1580 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 1581 timas[2] = cpu_to_be64(xive->tm_base + 1582 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 1583 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 1584 1585 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 1586 1587 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 1588 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 1589 1590 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 1591 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 1592 sizeof(eq_sizes))); 1593 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 1594 sizeof(lisn_ranges))); 1595 1596 /* For Linux to link the LSIs to the interrupt controller. */ 1597 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 1598 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 1599 1600 /* For SLOF */ 1601 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 1602 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 1603 1604 /* 1605 * The "ibm,plat-res-int-priorities" property defines the priority 1606 * ranges reserved by the hypervisor 1607 */ 1608 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 1609 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 1610 } 1611